1 /* $NetBSD: if_urlreg.h,v 1.1 2002/03/28 21:09:11 ichiro Exp $ */ 2 /* 3 * Copyright (c) 2001, 2002 4 * Shingo WATANABE <nabe@nabechan.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Shingo WATANABE. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 */ 34 35 #define URL_IFACE_INDEX 0 36 #define URL_CONFIG_NO 1 37 38 #define URL_TX_LIST_CNT 1 39 #define URL_RX_LIST_CNT 1 40 41 #define URL_TX_TIMEOUT 1000 42 #define URL_TIMEOUT 10000 43 44 #define ETHER_ALIGN 2 45 46 47 /* Packet length */ 48 #define URL_MAX_MTU 1536 49 #define URL_MIN_FRAME_LEN 60 50 #define URL_BUFSZ URL_MAX_MTU 51 52 /* Request */ 53 #define URL_REQ_MEM 0x05 54 55 #define URL_CMD_READMEM 1 56 #define URL_CMD_WRITEMEM 2 57 58 /* Registers */ 59 #define URL_IDR0 0x0120 /* Ethernet Address, load from 93C46 */ 60 #define URL_IDR1 0x0121 /* Ethernet Address, load from 93C46 */ 61 #define URL_IDR2 0x0122 /* Ethernet Address, load from 93C46 */ 62 #define URL_IDR3 0x0123 /* Ethernet Address, load from 93C46 */ 63 #define URL_IDR4 0x0124 /* Ethernet Address, load from 93C46 */ 64 #define URL_IDR5 0x0125 /* Ethernet Address, load from 93C46 */ 65 66 #define URL_MAR0 0x0126 /* Multicast register */ 67 #define URL_MAR1 0x0127 /* Multicast register */ 68 #define URL_MAR2 0x0128 /* Multicast register */ 69 #define URL_MAR3 0x0129 /* Multicast register */ 70 #define URL_MAR4 0x012a /* Multicast register */ 71 #define URL_MAR5 0x012b /* Multicast register */ 72 #define URL_MAR6 0x012c /* Multicast register */ 73 #define URL_MAR7 0x012d /* Multicast register */ 74 #define URL_MAR URL_MAR0 75 76 #define URL_CR 0x012e /* Command Register */ 77 #define URL_CR_WEPROM (1<<5) /* EEPROM Write Enable */ 78 #define URL_CR_SOFT_RST (1<<4) /* Software Reset */ 79 #define URL_CR_RE (1<<3) /* Ethernet Receive Enable */ 80 #define URL_CR_TE (1<<2) /* Ethernet Transmit Enable */ 81 #define URL_CR_EP3CLREN (1<<1) /* Enable clearing the performance counter */ 82 #define URL_CR_AUTOLOAD (1<<0) /* Auto-load the contents of 93C46 */ 83 84 #define URL_TCR 0x012f /* Transmit Control Register */ 85 #define URL_TCR_TXRR1 (1<<7) /* TX Retry Count */ 86 #define URL_TCR_TXRR0 (1<<6) /* TX Retry Count */ 87 #define URL_TCR_IFG1 (1<<4) /* Interframe Gap Time */ 88 #define URL_TCR_IFG0 (1<<4) /* Interframe Gap Time */ 89 #define URL_TCR_NOCRC (1<<0) /* no CRC Append */ 90 91 #define URL_RCR 0x0130 /* Receive Configuration Register */ 92 #define URL_RCR_TAIL (1<<7) 93 #define URL_RCR_AER (1<<6) 94 #define URL_RCR_AR (1<<5) 95 #define URL_RCR_AM (1<<4) 96 #define URL_RCR_AB (1<<3) 97 #define URL_RCR_AD (1<<2) 98 #define URL_RCR_AAM (1<<1) 99 #define URL_RCR_AAP (1<<0) 100 101 #define URL_MSR 0x137 /* Media Status Register */ 102 #define URL_MSR_TXFCE (1<<7) 103 #define URL_MSR_RXFCE (1<<6) 104 #define URL_MSR_DUPLEX (1<<4) 105 #define URL_MSR_SPEED_100 (1<<3) 106 #define URL_MSR_LINK (1<<2) 107 #define URL_MSR_TXPF (1<<1) 108 #define URL_MSR_RXPF (1<<0) 109 110 #define URL_PHYADD 0x138 /* MII PHY Address select */ 111 #define URL_PHYADD_MASK 0x1f /* MII PHY Address select */ 112 113 #define URL_PHYDAT 0x139 /* MII PHY data */ 114 115 #define URL_PHYCNT 0x13b /* MII PHY control */ 116 #define URL_PHYCNT_PHYOWN (1<<6) /* Own bit */ 117 #define URL_PHYCNT_RWCR (1<<5) /* MII management data R/W control */ 118 #define URL_PHY_PHYOFF_MASK 0x1f /* PHY register offset */ 119 120 #define URL_BMCR 0x140 /* Basic mode control register */ 121 #define URL_BMSR 0x142 /* Basic mode status register */ 122 #define URL_ANAR 0x144 /* Auto-negotiation advertisement register */ 123 #define URL_ANLP 0x146 /* Auto-negotiation link partner ability register */ 124 125 126 typedef uWord url_rxhdr_t; /* Recive Header */ 127 #define URL_RXHDR_BYTEC_MASK (0x0fff) /* RX bytes count */ 128 #define URL_RXHDR_VALID_MASK (0x1000) /* Valid packet */ 129 #define URL_RXHDR_RUNTPKT_MASK (0x2000) /* Runt packet */ 130 #define URL_RXHDR_PHYPKT_MASK (0x4000) /* Physical match packet */ 131 #define URL_RXHDR_MCASTPKT_MASK (0x8000) /* Multicast packet */ 132 133 #define GET_IFP(sc) (&(sc)->sc_ec.ec_if) 134 #define GET_MII(sc) (&(sc)->sc_mii) 135 136 struct url_chain { 137 struct url_softc *url_sc; 138 usbd_xfer_handle url_xfer; 139 char *url_buf; 140 struct mbuf *url_mbuf; 141 int url_idx; 142 }; 143 144 struct url_cdata { 145 struct url_chain url_tx_chain[URL_TX_LIST_CNT]; 146 struct url_chain url_rx_chain[URL_TX_LIST_CNT]; 147 #if 0 148 /* XXX: Intrrupt Endpoint is not yet supported! */ 149 struct url_intrpkg url_ibuf; 150 #endif 151 int url_tx_prod; 152 int url_tx_cons; 153 int url_tx_cnt; 154 int url_rx_prod; 155 }; 156 157 struct url_softc { 158 USBBASEDEVICE sc_dev; /* base device */ 159 usbd_device_handle sc_udev; 160 161 /* USB */ 162 usbd_interface_handle sc_ctl_iface; 163 /* int sc_ctl_iface_no; */ 164 int sc_bulkin_no; /* bulk in endpoint */ 165 int sc_bulkout_no; /* bulk out endpoint */ 166 int sc_intrin_no; /* intr in endpoint */ 167 usbd_pipe_handle sc_pipe_rx; 168 usbd_pipe_handle sc_pipe_tx; 169 usbd_pipe_handle sc_pipe_intr; 170 usb_callout_t sc_stat_ch; 171 u_int sc_rx_errs; 172 /* u_int sc_intr_errs; */ 173 struct timeval sc_rx_notice; 174 175 /* Ethernet */ 176 struct ethercom sc_ec; /* ethernet common */ 177 struct mii_data sc_mii; 178 struct lock sc_mii_lock; 179 int sc_link; 180 #define sc_media url_mii.mii_media 181 #if NRND > 0 182 rndsource_element_t rnd_source; 183 #endif 184 struct url_cdata sc_cdata; 185 186 int sc_attached; 187 int sc_dying; 188 int sc_refcnt; 189 190 struct usb_task sc_tick_task; 191 struct usb_task sc_stop_task; 192 193 u_int16_t sc_flags; 194 }; 195