1 /* $NetBSD: uhcireg.h,v 1.15 2002/02/11 11:41:30 augustss Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhcireg.h,v 1.12 1999/11/17 22:33:42 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart@augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 #ifndef _DEV_PCI_UHCIREG_H_ 42 #define _DEV_PCI_UHCIREG_H_ 43 44 /*** PCI config registers ***/ 45 46 #define PCI_USBREV 0x60 /* USB protocol revision */ 47 #define PCI_USBREV_MASK 0xff 48 #define PCI_USBREV_PRE_1_0 0x00 49 #define PCI_USBREV_1_0 0x10 50 #define PCI_USBREV_1_1 0x11 51 52 #define PCI_LEGSUP 0xc0 /* Legacy Support register */ 53 #define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */ 54 55 #define PCI_CBIO 0x20 /* configuration base IO */ 56 57 #define PCI_INTERFACE_UHCI 0x00 58 59 /*** UHCI registers ***/ 60 61 #define UHCI_CMD 0x00 62 #define UHCI_CMD_RS 0x0001 63 #define UHCI_CMD_HCRESET 0x0002 64 #define UHCI_CMD_GRESET 0x0004 65 #define UHCI_CMD_EGSM 0x0008 66 #define UHCI_CMD_FGR 0x0010 67 #define UHCI_CMD_SWDBG 0x0020 68 #define UHCI_CMD_CF 0x0040 69 #define UHCI_CMD_MAXP 0x0080 70 71 #define UHCI_STS 0x02 72 #define UHCI_STS_USBINT 0x0001 73 #define UHCI_STS_USBEI 0x0002 74 #define UHCI_STS_RD 0x0004 75 #define UHCI_STS_HSE 0x0008 76 #define UHCI_STS_HCPE 0x0010 77 #define UHCI_STS_HCH 0x0020 78 #define UHCI_STS_ALLINTRS 0x003f 79 80 #define UHCI_INTR 0x04 81 #define UHCI_INTR_TOCRCIE 0x0001 82 #define UHCI_INTR_RIE 0x0002 83 #define UHCI_INTR_IOCE 0x0004 84 #define UHCI_INTR_SPIE 0x0008 85 86 #define UHCI_FRNUM 0x06 87 #define UHCI_FRNUM_MASK 0x03ff 88 89 90 #define UHCI_FLBASEADDR 0x08 91 92 #define UHCI_SOF 0x0c 93 #define UHCI_SOF_MASK 0x7f 94 95 #define UHCI_PORTSC1 0x010 96 #define UHCI_PORTSC2 0x012 97 #define UHCI_PORTSC_CCS 0x0001 98 #define UHCI_PORTSC_CSC 0x0002 99 #define UHCI_PORTSC_PE 0x0004 100 #define UHCI_PORTSC_POEDC 0x0008 101 #define UHCI_PORTSC_LS 0x0030 102 #define UHCI_PORTSC_LS_SHIFT 4 103 #define UHCI_PORTSC_RD 0x0040 104 #define UHCI_PORTSC_LSDA 0x0100 105 #define UHCI_PORTSC_PR 0x0200 106 #define UHCI_PORTSC_OCI 0x0400 107 #define UHCI_PORTSC_OCIC 0x0800 108 #define UHCI_PORTSC_SUSP 0x1000 109 110 #define URWMASK(x) \ 111 ((x) & (UHCI_PORTSC_SUSP | UHCI_PORTSC_PR | UHCI_PORTSC_RD | UHCI_PORTSC_PE)) 112 113 #define UHCI_FRAMELIST_COUNT 1024 114 #define UHCI_FRAMELIST_ALIGN 4096 115 116 #define UHCI_TD_ALIGN 16 117 #define UHCI_QH_ALIGN 16 118 119 typedef u_int32_t uhci_physaddr_t; 120 #define UHCI_PTR_T 0x00000001 121 #define UHCI_PTR_TD 0x00000000 122 #define UHCI_PTR_QH 0x00000002 123 #define UHCI_PTR_VF 0x00000004 124 125 /* 126 * Wait this long after a QH has been removed. This gives that HC a 127 * chance to stop looking at it before it's recycled. 128 */ 129 #define UHCI_QH_REMOVE_DELAY 5 130 131 /* 132 * The Queue Heads and Transfer Descriptors are accessed 133 * by both the CPU and the USB controller which run 134 * concurrently. This means that they have to be accessed 135 * with great care. As long as the data structures are 136 * not linked into the controller's frame list they cannot 137 * be accessed by it and anything goes. As soon as a 138 * TD is accessible by the controller it "owns" the td_status 139 * field; it will not be written by the CPU. Similarly 140 * the controller "owns" the qh_elink field. 141 */ 142 143 typedef struct { 144 uhci_physaddr_t td_link; 145 u_int32_t td_status; 146 #define UHCI_TD_GET_ACTLEN(s) (((s) + 1) & 0x3ff) 147 #define UHCI_TD_ZERO_ACTLEN(t) ((t) | 0x3ff) 148 #define UHCI_TD_BITSTUFF 0x00020000 149 #define UHCI_TD_CRCTO 0x00040000 150 #define UHCI_TD_NAK 0x00080000 151 #define UHCI_TD_BABBLE 0x00100000 152 #define UHCI_TD_DBUFFER 0x00200000 153 #define UHCI_TD_STALLED 0x00400000 154 #define UHCI_TD_ACTIVE 0x00800000 155 #define UHCI_TD_IOC 0x01000000 156 #define UHCI_TD_IOS 0x02000000 157 #define UHCI_TD_LS 0x04000000 158 #define UHCI_TD_GET_ERRCNT(s) (((s) >> 27) & 3) 159 #define UHCI_TD_SET_ERRCNT(n) ((n) << 27) 160 #define UHCI_TD_SPD 0x20000000 161 u_int32_t td_token; 162 #define UHCI_TD_PID_IN 0x00000069 163 #define UHCI_TD_PID_OUT 0x000000e1 164 #define UHCI_TD_PID_SETUP 0x0000002d 165 #define UHCI_TD_GET_PID(s) ((s) & 0xff) 166 #define UHCI_TD_SET_DEVADDR(a) ((a) << 8) 167 #define UHCI_TD_GET_DEVADDR(s) (((s) >> 8) & 0x7f) 168 #define UHCI_TD_SET_ENDPT(e) (((e)&0xf) << 15) 169 #define UHCI_TD_GET_ENDPT(s) (((s) >> 15) & 0xf) 170 #define UHCI_TD_SET_DT(t) ((t) << 19) 171 #define UHCI_TD_GET_DT(s) (((s) >> 19) & 1) 172 #define UHCI_TD_SET_MAXLEN(l) (((l)-1) << 21) 173 #define UHCI_TD_GET_MAXLEN(s) ((((s) >> 21) + 1) & 0x7ff) 174 #define UHCI_TD_MAXLEN_MASK 0xffe00000 175 u_int32_t td_buffer; 176 } uhci_td_t; 177 178 #define UHCI_TD_ERROR (UHCI_TD_BITSTUFF|UHCI_TD_CRCTO|UHCI_TD_BABBLE|UHCI_TD_DBUFFER|UHCI_TD_STALLED) 179 180 #define UHCI_TD_SETUP(len, endp, dev) (UHCI_TD_SET_MAXLEN(len) | \ 181 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_SETUP) 182 #define UHCI_TD_OUT(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \ 183 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | \ 184 UHCI_TD_PID_OUT | UHCI_TD_SET_DT(dt)) 185 #define UHCI_TD_IN(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \ 186 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_IN | \ 187 UHCI_TD_SET_DT(dt)) 188 189 typedef struct { 190 uhci_physaddr_t qh_hlink; 191 uhci_physaddr_t qh_elink; 192 } uhci_qh_t; 193 194 #endif /* _DEV_PCI_UHCIREG_H_ */ 195