1 /* $NetBSD: ustirreg.h,v 1.1 2002/01/03 18:54:32 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Sainty <David.Sainty@dtsp.co.nz> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Registers definitions for SigmaTel STIr4200 USB/IrDA Bridge 41 * Controller. Documentation available at: 42 * http://extranet.sigmatel.com/library/infrared/stir4200/stir4200-ds.pdf 43 */ 44 45 /* Notes: 46 * 47 * The data sheet states that the TX and RX frames are prepended with 48 * BOF characters. This appears to be incorrect, the standard 0xff 49 * characters behave as expected. 50 * 51 * There does not appear to be any way to get asynchronous 52 * notifications from this device that data is waiting. You simply do 53 * have to poll continuously looking for a non-zero-length result. 54 * 55 * The SigmaTel drivers provided with the device for other operating 56 * systems poll at full USB speed (1000 per second), which has a 57 * significant impact on the system. 58 */ 59 60 /* 61 * The SigmaTel device is controlled via an array of registers, with 62 * generic register read/write commands. This is a completely 63 * different approach to that defined in the USB IrDA standard. 64 */ 65 #define STIR_REG_MODE 1 66 #define STIR_REG_BRATE 2 67 #define STIR_REG_CONTROL 3 68 #define STIR_REG_SENSITIVITY 4 69 #define STIR_REG_STATUS 5 70 #define STIR_REG_FFCNT_LSB 6 71 #define STIR_REG_FFCNT_MSB 7 72 #define STIR_REG_DPLL 8 73 #define STIR_REG_IRDIG 9 74 75 /* Register numbers range from zero to STIR_MAX_REG */ 76 #define STIR_MAX_REG 15 77 78 79 /* Mode register bits */ 80 #define STIR_RMODE_FIR 0x80 81 #define STIR_RMODE_MIR 0x40 82 #define STIR_RMODE_SIR 0x20 83 #define STIR_RMODE_ASK 0x10 84 85 /* 86 * FASTRXEN can be set to enable simultaneous reads and writes. It 87 * isn't clear that this is useful, the RX and TX data is mixed into 88 * the FIFO and the chip appears to get into a funny state. In the 89 * absence of good documentation about this bit, leave it disabled! 90 */ 91 #define STIR_RMODE_FASTRXEN 0x08 92 93 #define STIR_RMODE_FFRSTEN 0x04 94 95 /* FFSPRST must be set to enable the FIFO */ 96 #define STIR_RMODE_FFSPRST 0x02 97 98 /* 99 * High bit baud rate generator value, used in conjunction with the 100 * BRATE register. 101 */ 102 #define STIR_RMODE_PDCLK8 0x01 103 104 105 /* Status register bits */ 106 #define STIR_RSTATUS_EOFRAME 0x80 107 #define STIR_RSTATUS_FFUNDER 0x40 108 #define STIR_RSTATUS_FFOVER 0x20 109 110 /* Set in write direction, cleared in read direction */ 111 #define STIR_RSTATUS_FFDIR 0x10 112 113 /* 114 * FFCLR is write-only, and the only writable bit in the STATUS 115 * register. 116 */ 117 #define STIR_RSTATUS_FFCLR 0x08 118 119 #define STIR_RSTATUS_FFEMPTY 0x04 120 #define STIR_RSTATUS_FFRXERR 0x02 121 #define STIR_RSTATUS_FFTXERR 0x01 122 123 124 /* Extract data from portions of registers */ 125 #define STIR_GET_SENSITIVITY_CHIPREVISION(x) ((x) & 7) 126 127 /* 128 * According to the documentation, FFCNT may be off by as much as 3 129 * bytes. 130 */ 131 #define STIR_FFCNT_MARGIN 3 132 133 /* 134 * The FIFO size for the device is a fixed 4k bytes 135 */ 136 #define STIR_FIFO_SIZE 0x1000 137 138 /* 139 * Vendor specific device requests 140 */ 141 #define STIR_CMD_WRITEMULTIREG 0x00 142 #define STIR_CMD_READMULTIREG 0x01 143 #define STIR_CMD_READROM 0x02 144 #define STIR_CMD_WRITESINGLEREG 0x03 145 146 /* 147 * The MSB is the MODE register setting, the LSB is the BRATE register 148 * setting. 149 */ 150 #define STIR_BRMODE_4000000 0x8002 151 #define STIR_BRMODE_1152000 0x4001 152 #define STIR_BRMODE_576000 0x4003 153 #define STIR_BRMODE_115200 0x2009 154 #define STIR_BRMODE_57600 0x2013 155 #define STIR_BRMODE_38400 0x201d 156 #define STIR_BRMODE_19200 0x203b 157 #define STIR_BRMODE_9600 0x2077 158 #define STIR_BRMODE_2400 0x21df 159 160 /* 161 * Extract values from STIR_BRMODE values. 162 */ 163 #define STIR_BRMODE_MODEREG(x) ((x) >> 8) 164 #define STIR_BRMODE_BRATEREG(x) ((x) & 0xff) 165 166 /* 167 * Each transmit frame starts with the sequence: 168 * 169 * 0x55 0xaa LSB(Length) MSB(Length) 170 */ 171 #define STIR_OUTPUT_HEADER_SIZE 4 172 #define STIR_OUTPUT_HEADER_BYTE0 0x55 173 #define STIR_OUTPUT_HEADER_BYTE1 0xaa 174