1 /* $NetBSD: if_ie_vme.c,v 1.14 2001/11/13 06:17:07 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1995 Charles D. Cranor 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles D. Cranor. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Converted to SUN ie driver by Charles D. Cranor, 35 * October 1994, January 1995. 36 */ 37 38 /* 39 * The i82586 is a very painful chip, found in sun3's, sun-4/100's 40 * sun-4/200's, and VME based suns. The byte order is all wrong for a 41 * SUN, making life difficult. Programming this chip is mostly the same, 42 * but certain details differ from system to system. This driver is 43 * written so that different "ie" interfaces can be controled by the same 44 * driver. 45 */ 46 47 /* 48 * programming notes: 49 * 50 * the ie chip operates in a 24 bit address space. 51 * 52 * most ie interfaces appear to be divided into two parts: 53 * - generic 586 stuff 54 * - board specific 55 * 56 * generic: 57 * the generic stuff of the ie chip is all done with data structures 58 * that live in the chip's memory address space. the chip expects 59 * its main data structure (the sys conf ptr -- SCP) to be at a fixed 60 * address in its 24 bit space: 0xfffff4 61 * 62 * the SCP points to another structure called the ISCP. 63 * the ISCP points to another structure called the SCB. 64 * the SCB has a status field, a linked list of "commands", and 65 * a linked list of "receive buffers". these are data structures that 66 * live in memory, not registers. 67 * 68 * board: 69 * to get the chip to do anything, you first put a command in the 70 * command data structure list. then you have to signal "attention" 71 * to the chip to get it to look at the command. how you 72 * signal attention depends on what board you have... on PC's 73 * there is an i/o port number to do this, on sun's there is a 74 * register bit you toggle. 75 * 76 * to get data from the chip you program it to interrupt... 77 * 78 * 79 * sun issues: 80 * 81 * there are 3 kinds of sun "ie" interfaces: 82 * 1 - a VME/multibus card 83 * 2 - an on-board interface (sun3's, sun-4/100's, and sun-4/200's) 84 * 3 - another VME board called the 3E 85 * 86 * the VME boards lives in vme16 space. only 16 and 8 bit accesses 87 * are allowed, so functions that copy data must be aware of this. 88 * 89 * the chip is an intel chip. this means that the byte order 90 * on all the "short"s in the chip's data structures is wrong. 91 * so, constants described in the intel docs are swapped for the sun. 92 * that means that any buffer pointers you give the chip must be 93 * swapped to intel format. yuck. 94 * 95 * VME/multibus interface: 96 * for the multibus interface the board ignores the top 4 bits 97 * of the chip address. the multibus interface has its own 98 * MMU like page map (without protections or valid bits, etc). 99 * there are 256 pages of physical memory on the board (each page 100 * is 1024 bytes). There are 1024 slots in the page map. so, 101 * a 1024 byte page takes up 10 bits of address for the offset, 102 * and if there are 1024 slots in the page that is another 10 bits 103 * of the address. That makes a 20 bit address, and as stated 104 * earlier the board ignores the top 4 bits, so that accounts 105 * for all 24 bits of address. 106 * 107 * Note that the last entry of the page map maps the top of the 108 * 24 bit address space and that the SCP is supposed to be at 109 * 0xfffff4 (taking into account allignment). so, 110 * for multibus, that entry in the page map has to be used for the SCP. 111 * 112 * The page map effects BOTH how the ie chip sees the 113 * memory, and how the host sees it. 114 * 115 * The page map is part of the "register" area of the board 116 * 117 * The page map to control where ram appears in the address space. 118 * We choose to have RAM start at 0 in the 24 bit address space. 119 * 120 * to get the phyiscal address of the board's RAM you must take the 121 * top 12 bits of the physical address of the register address and 122 * or in the 4 bits from the status word as bits 17-20 (remember that 123 * the board ignores the chip's top 4 address lines). For example: 124 * if the register is @ 0xffe88000, then the top 12 bits are 0xffe00000. 125 * to get the 4 bits from the status word just do status & IEVME_HADDR. 126 * suppose the value is "4". Then just shift it left 16 bits to get 127 * it into bits 17-20 (e.g. 0x40000). Then or it to get the 128 * address of RAM (in our example: 0xffe40000). see the attach routine! 129 * 130 * 131 * on-board interface: 132 * 133 * on the onboard ie interface the 24 bit address space is hardwired 134 * to be 0xff000000 -> 0xffffffff of KVA. this means that sc_iobase 135 * will be 0xff000000. sc_maddr will be where ever we allocate RAM 136 * in KVA. note that since the SCP is at a fixed address it means 137 * that we have to allocate a fixed KVA for the SCP. 138 * <fill in useful info later> 139 * 140 * 141 * VME3E interface: 142 * 143 * <fill in useful info later> 144 * 145 */ 146 147 #include <sys/cdefs.h> 148 __KERNEL_RCSID(0, "$NetBSD: if_ie_vme.c,v 1.14 2001/11/13 06:17:07 lukem Exp $"); 149 150 #include <sys/param.h> 151 #include <sys/systm.h> 152 #include <sys/errno.h> 153 #include <sys/device.h> 154 #include <sys/protosw.h> 155 #include <sys/socket.h> 156 157 #include <net/if.h> 158 #include <net/if_types.h> 159 #include <net/if_dl.h> 160 #include <net/if_media.h> 161 #include <net/if_ether.h> 162 163 #include <machine/bus.h> 164 #include <machine/intr.h> 165 #include <dev/vme/vmevar.h> 166 167 #include <dev/ic/i82586reg.h> 168 #include <dev/ic/i82586var.h> 169 170 #include "locators.h" 171 172 /* 173 * VME/multibus definitions 174 */ 175 #define IEVME_PAGESIZE 1024 /* bytes */ 176 #define IEVME_PAGSHIFT 10 /* bits */ 177 #define IEVME_NPAGES 256 /* number of pages on chip */ 178 #define IEVME_MAPSZ 1024 /* number of entries in the map */ 179 180 /* 181 * PTE for the page map 182 */ 183 #define IEVME_SBORDR 0x8000 /* sun byte order */ 184 #define IEVME_IBORDR 0x0000 /* intel byte ordr */ 185 186 #define IEVME_P2MEM 0x2000 /* memory is on P2 */ 187 #define IEVME_OBMEM 0x0000 /* memory is on board */ 188 189 #define IEVME_PGMASK 0x0fff /* gives the physical page frame number */ 190 191 struct ievme { 192 u_int16_t pgmap[IEVME_MAPSZ]; 193 u_int16_t xxx[32]; /* prom */ 194 u_int16_t status; /* see below for bits */ 195 u_int16_t xxx2; /* filler */ 196 u_int16_t pectrl; /* parity control (see below) */ 197 u_int16_t peaddr; /* low 16 bits of address */ 198 }; 199 200 /* 201 * status bits 202 */ 203 #define IEVME_RESET 0x8000 /* reset board */ 204 #define IEVME_ONAIR 0x4000 /* go out of loopback 'on-air' */ 205 #define IEVME_ATTEN 0x2000 /* attention */ 206 #define IEVME_IENAB 0x1000 /* interrupt enable */ 207 #define IEVME_PEINT 0x0800 /* parity error interrupt enable */ 208 #define IEVME_PERR 0x0200 /* parity error flag */ 209 #define IEVME_INT 0x0100 /* interrupt flag */ 210 #define IEVME_P2EN 0x0020 /* enable p2 bus */ 211 #define IEVME_256K 0x0010 /* 256kb rams */ 212 #define IEVME_HADDR 0x000f /* mask for bits 17-20 of address */ 213 214 /* 215 * parity control 216 */ 217 #define IEVME_PARACK 0x0100 /* parity error ack */ 218 #define IEVME_PARSRC 0x0080 /* parity error source */ 219 #define IEVME_PAREND 0x0040 /* which end of the data got the error */ 220 #define IEVME_PARADR 0x000f /* mask to get bits 17-20 of parity address */ 221 222 /* Supported media */ 223 static int media[] = { 224 IFM_ETHER | IFM_10_2, 225 }; 226 #define NMEDIA (sizeof(media) / sizeof(media[0])) 227 228 /* 229 * the 3E board not supported (yet?) 230 */ 231 232 233 static void ie_vmereset __P((struct ie_softc *, int)); 234 static void ie_vmeattend __P((struct ie_softc *, int)); 235 static void ie_vmerun __P((struct ie_softc *)); 236 static int ie_vmeintr __P((struct ie_softc *, int)); 237 238 int ie_vme_match __P((struct device *, struct cfdata *, void *)); 239 void ie_vme_attach __P((struct device *, struct device *, void *)); 240 241 struct ie_vme_softc { 242 struct ie_softc ie; 243 bus_space_tag_t ievt; 244 bus_space_handle_t ievh; 245 }; 246 247 struct cfattach ie_vme_ca = { 248 sizeof(struct ie_vme_softc), ie_vme_match, ie_vme_attach 249 }; 250 251 #define read_iev(sc, reg) \ 252 bus_space_read_2(sc->ievt, sc->ievh, offsetof(struct ievme, reg)) 253 #define write_iev(sc, reg, val) \ 254 bus_space_write_2(sc->ievt, sc->ievh, offsetof(struct ievme, reg), val) 255 256 /* 257 * MULTIBUS/VME support routines 258 */ 259 void 260 ie_vmereset(sc, what) 261 struct ie_softc *sc; 262 int what; 263 { 264 struct ie_vme_softc *vsc = (struct ie_vme_softc *)sc; 265 write_iev(vsc, status, IEVME_RESET); 266 delay(100); /* XXX could be shorter? */ 267 write_iev(vsc, status, 0); 268 } 269 270 void 271 ie_vmeattend(sc, why) 272 struct ie_softc *sc; 273 int why; 274 { 275 struct ie_vme_softc *vsc = (struct ie_vme_softc *)sc; 276 277 /* flag! */ 278 write_iev(vsc, status, read_iev(vsc, status) | IEVME_ATTEN); 279 /* down. */ 280 write_iev(vsc, status, read_iev(vsc, status) & ~IEVME_ATTEN); 281 } 282 283 void 284 ie_vmerun(sc) 285 struct ie_softc *sc; 286 { 287 struct ie_vme_softc *vsc = (struct ie_vme_softc *)sc; 288 289 write_iev(vsc, status, read_iev(vsc, status) 290 | IEVME_ONAIR | IEVME_IENAB | IEVME_PEINT); 291 } 292 293 int 294 ie_vmeintr(sc, where) 295 struct ie_softc *sc; 296 int where; 297 { 298 struct ie_vme_softc *vsc = (struct ie_vme_softc *)sc; 299 300 if (where != INTR_ENTER) 301 return (0); 302 303 /* 304 * check for parity error 305 */ 306 if (read_iev(vsc, status) & IEVME_PERR) { 307 printf("%s: parity error (ctrl 0x%x @ 0x%02x%04x)\n", 308 sc->sc_dev.dv_xname, read_iev(vsc, pectrl), 309 read_iev(vsc, pectrl) & IEVME_HADDR, 310 read_iev(vsc, peaddr)); 311 write_iev(vsc, pectrl, read_iev(vsc, pectrl) | IEVME_PARACK); 312 } 313 return (0); 314 } 315 316 void ie_memcopyin __P((struct ie_softc *, void *, int, size_t)); 317 void ie_memcopyout __P((struct ie_softc *, const void *, int, size_t)); 318 319 /* 320 * Copy board memory to kernel. 321 */ 322 void 323 ie_memcopyin(sc, p, offset, size) 324 struct ie_softc *sc; 325 void *p; 326 int offset; 327 size_t size; 328 { 329 size_t help; 330 331 if ((offset & 1) && ((u_long)p & 1) && size > 0) { 332 *(u_int8_t *)p = bus_space_read_1(sc->bt, sc->bh, offset); 333 offset++; 334 p = (u_int8_t *)p + 1; 335 size--; 336 } 337 338 if ((offset & 1) || ((u_long)p & 1)) { 339 bus_space_read_region_1(sc->bt, sc->bh, offset, p, size); 340 return; 341 } 342 343 help = size / 2; 344 bus_space_read_region_2(sc->bt, sc->bh, offset, p, help); 345 if (2 * help == size) 346 return; 347 348 offset += 2 * help; 349 p = (u_int16_t *)p + help; 350 *(u_int8_t *)p = bus_space_read_1(sc->bt, sc->bh, offset); 351 } 352 353 /* 354 * Copy from kernel space to board memory. 355 */ 356 void 357 ie_memcopyout(sc, p, offset, size) 358 struct ie_softc *sc; 359 const void *p; 360 int offset; 361 size_t size; 362 { 363 size_t help; 364 365 if ((offset & 1) && ((u_long)p & 1) && size > 0) { 366 bus_space_write_1(sc->bt, sc->bh, offset, *(u_int8_t *)p); 367 offset++; 368 p = (u_int8_t *)p + 1; 369 size--; 370 } 371 372 if ((offset & 1) || ((u_long)p & 1)) { 373 bus_space_write_region_1(sc->bt, sc->bh, offset, p, size); 374 return; 375 } 376 377 help = size / 2; 378 bus_space_write_region_2(sc->bt, sc->bh, offset, p, help); 379 if (2 * help == size) 380 return; 381 382 offset += 2 * help; 383 p = (u_int16_t *)p + help; 384 bus_space_write_1(sc->bt, sc->bh, offset, *(u_int8_t *)p); 385 } 386 387 /* read a 16-bit value at BH offset */ 388 u_int16_t ie_vme_read16 __P((struct ie_softc *, int offset)); 389 /* write a 16-bit value at BH offset */ 390 void ie_vme_write16 __P((struct ie_softc *, int offset, u_int16_t value)); 391 void ie_vme_write24 __P((struct ie_softc *, int offset, int addr)); 392 393 u_int16_t 394 ie_vme_read16(sc, offset) 395 struct ie_softc *sc; 396 int offset; 397 { 398 u_int16_t v; 399 400 bus_space_barrier(sc->bt, sc->bh, offset, 2, BUS_SPACE_BARRIER_READ); 401 v = bus_space_read_2(sc->bt, sc->bh, offset); 402 return (((v&0xff)<<8) | ((v>>8)&0xff)); 403 } 404 405 void 406 ie_vme_write16(sc, offset, v) 407 struct ie_softc *sc; 408 int offset; 409 u_int16_t v; 410 { 411 int v0 = ((((v)&0xff)<<8) | (((v)>>8)&0xff)); 412 bus_space_write_2(sc->bt, sc->bh, offset, v0); 413 bus_space_barrier(sc->bt, sc->bh, offset, 2, BUS_SPACE_BARRIER_WRITE); 414 } 415 416 void 417 ie_vme_write24(sc, offset, addr) 418 struct ie_softc *sc; 419 int offset; 420 int addr; 421 { 422 u_char *f = (u_char *)&addr; 423 u_int16_t v0, v1; 424 u_char *t; 425 426 t = (u_char *)&v0; 427 t[0] = f[3]; t[1] = f[2]; 428 bus_space_write_2(sc->bt, sc->bh, offset, v0); 429 430 t = (u_char *)&v1; 431 t[0] = f[1]; t[1] = 0; 432 bus_space_write_2(sc->bt, sc->bh, offset+2, v1); 433 434 bus_space_barrier(sc->bt, sc->bh, offset, 4, BUS_SPACE_BARRIER_WRITE); 435 } 436 437 int 438 ie_vme_match(parent, cf, aux) 439 struct device *parent; 440 struct cfdata *cf; 441 void *aux; 442 { 443 struct vme_attach_args *va = aux; 444 vme_chipset_tag_t ct = va->va_vct; 445 vme_am_t mod; 446 int error; 447 448 if (va->numcfranges < 2) { 449 printf("ie_vme_match: need 2 ranges\n"); 450 return (0); 451 } 452 if ((va->r[1].offset & 0xff0fffff) || 453 ((va->r[0].offset & 0xfff00000) 454 != (va->r[1].offset & 0xfff00000))) { 455 printf("ie_vme_match: base address mismatch\n"); 456 return (0); 457 } 458 if (va->r[0].size != VMECF_LEN_DEFAULT && 459 va->r[0].size != sizeof(sizeof(struct ievme))) { 460 printf("ie_vme_match: bad csr size\n"); 461 return (0); 462 } 463 if (va->r[1].size == VMECF_LEN_DEFAULT) { 464 printf("ie_vme_match: must specify memory size\n"); 465 return (0); 466 } 467 468 mod = 0x3d; /* VME_AM_A24|VME_AM_MBO|VME_AM_SUPER|VME_AM_DATA */ 469 470 if (va->r[0].am != VMECF_AM_DEFAULT && 471 va->r[0].am != mod) 472 return (0); 473 474 if (vme_space_alloc(va->va_vct, va->r[0].offset, 475 sizeof(struct ievme), mod)) 476 return (0); 477 if (vme_space_alloc(va->va_vct, va->r[1].offset, 478 va->r[1].size, mod)) { 479 vme_space_free(va->va_vct, va->r[0].offset, 480 sizeof(struct ievme), mod); 481 return (0); 482 } 483 error = vme_probe(ct, va->r[0].offset, 2, mod, VME_D16, 0, 0); 484 vme_space_free(va->va_vct, va->r[0].offset, sizeof(struct ievme), mod); 485 vme_space_free(va->va_vct, va->r[1].offset, va->r[1].size, mod); 486 487 return (error == 0); 488 } 489 490 void 491 ie_vme_attach(parent, self, aux) 492 struct device *parent; 493 struct device *self; 494 void *aux; 495 { 496 u_int8_t myaddr[ETHER_ADDR_LEN]; 497 #ifdef __sparc__ 498 extern void myetheraddr(u_char *); /* should be elsewhere */ 499 #endif 500 struct ie_vme_softc *vsc = (void *) self; 501 struct vme_attach_args *va = aux; 502 vme_chipset_tag_t ct = va->va_vct; 503 struct ie_softc *sc; 504 vme_intr_handle_t ih; 505 vme_addr_t rampaddr; 506 vme_size_t memsize; 507 vme_mapresc_t resc; 508 int lcv; 509 510 vme_am_t mod; 511 512 /* 513 * *note*: we don't detect the difference between a VME3E and 514 * a multibus/vme card. if you want to use a 3E you'll have 515 * to fix this. 516 */ 517 mod = 0x3d; /* VME_AM_A24|VME_AM_MBO|VME_AM_SUPER|VME_AM_DATA */ 518 if (vme_space_alloc(va->va_vct, va->r[0].offset, 519 sizeof(struct ievme), mod) || 520 vme_space_alloc(va->va_vct, va->r[1].offset, 521 va->r[1].size, mod)) 522 panic("if_ie: vme alloc"); 523 524 sc = &vsc->ie; 525 526 sc->hwreset = ie_vmereset; 527 sc->hwinit = ie_vmerun; 528 sc->chan_attn = ie_vmeattend; 529 sc->intrhook = ie_vmeintr; 530 sc->memcopyout = ie_memcopyout; 531 sc->memcopyin = ie_memcopyin; 532 533 sc->ie_bus_barrier = NULL; 534 sc->ie_bus_read16 = ie_vme_read16; 535 sc->ie_bus_write16 = ie_vme_write16; 536 sc->ie_bus_write24 = ie_vme_write24; 537 538 memsize = va->r[1].size; 539 540 if (vme_space_map(ct, va->r[0].offset, sizeof(struct ievme), mod, 541 VME_D16 | VME_D8, 0, 542 &vsc->ievt, &vsc->ievh, &resc) != 0) 543 panic("if_ie: vme map csr"); 544 545 rampaddr = va->r[1].offset; 546 547 /* 4 more */ 548 rampaddr = rampaddr | ((read_iev(vsc, status) & IEVME_HADDR) << 16); 549 if (vme_space_map(ct, rampaddr, memsize, mod, VME_D16 | VME_D8, 0, 550 &sc->bt, &sc->bh, &resc) != 0) 551 panic("if_ie: vme map mem"); 552 553 write_iev(vsc, pectrl, read_iev(vsc, pectrl) | IEVME_PARACK); 554 555 /* 556 * Set up mappings, direct map except for last page 557 * which is mapped at zero and at high address (for scp) 558 */ 559 for (lcv = 0; lcv < IEVME_MAPSZ - 1; lcv++) 560 write_iev(vsc, pgmap[lcv], IEVME_SBORDR | IEVME_OBMEM | lcv); 561 write_iev(vsc, pgmap[IEVME_MAPSZ - 1], IEVME_SBORDR | IEVME_OBMEM | 0); 562 563 /* Clear all ram */ 564 bus_space_set_region_2(sc->bt, sc->bh, 0, 0, memsize/2); 565 566 /* 567 * We use the first page to set up SCP, ICSP and SCB data 568 * structures. The remaining pages become the buffer area 569 * (managed in i82586.c). 570 * SCP is in double-mapped page, so the 586 can see it at 571 * the mandatory magic address (IE_SCP_ADDR). 572 */ 573 sc->scp = (IE_SCP_ADDR & (IEVME_PAGESIZE - 1)); 574 575 /* iscp at location zero */ 576 sc->iscp = 0; 577 578 /* scb follows iscp */ 579 sc->scb = IE_ISCP_SZ; 580 581 ie_vme_write16(sc, IE_ISCP_SCB((long)sc->iscp), sc->scb); 582 ie_vme_write16(sc, IE_ISCP_BASE((u_long)sc->iscp), 0); 583 ie_vme_write24(sc, IE_SCP_ISCP((u_long)sc->scp), 0); 584 585 if (i82586_proberam(sc) == 0) { 586 printf(": memory probe failed\n"); 587 return; 588 } 589 590 /* 591 * Rest of first page is unused; rest of ram for buffers. 592 */ 593 sc->buf_area = IEVME_PAGESIZE; 594 sc->buf_area_sz = memsize - IEVME_PAGESIZE; 595 596 sc->do_xmitnopchain = 0; 597 598 printf("\n%s:", self->dv_xname); 599 600 #ifdef __sparc__ 601 myetheraddr(myaddr); 602 #endif 603 i82586_attach(sc, "multibus/vme", myaddr, media, NMEDIA, media[0]); 604 605 vme_intr_map(ct, va->ilevel, va->ivector, &ih); 606 vme_intr_establish(ct, ih, IPL_NET, i82586_intr, sc); 607 } 608