1 /*-
2  * Copyright 2009 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *     Alex Deucher <alexander.deucher@amd.com>
25  */
26 
27 #include <sys/cdefs.h>
28 /*__FBSDID("$FreeBSD: src/sys/dev/drm/r600_blit.c,v 1.5 2009/10/30 18:08:46 rnoland Exp $");*/
29 
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_drv.h"
34 
35 static u32 r6xx_default_state[] =
36 {
37 	0xc0002400,
38 	0x00000000,
39 	0xc0012800,
40 	0x80000000,
41 	0x80000000,
42 	0xc0004600,
43 	0x00000016,
44 	0xc0016800,
45 	0x00000010,
46 	0x00028000,
47 	0xc0016800,
48 	0x00000010,
49 	0x00008000,
50 	0xc0016800,
51 	0x00000542,
52 	0x07000003,
53 	0xc0016800,
54 	0x000005c5,
55 	0x00000000,
56 	0xc0016800,
57 	0x00000363,
58 	0x00000000,
59 	0xc0016800,
60 	0x0000060c,
61 	0x82000000,
62 	0xc0016800,
63 	0x0000060e,
64 	0x01020204,
65 	0xc0016f00,
66 	0x00000000,
67 	0x00000000,
68 	0xc0016f00,
69 	0x00000001,
70 	0x00000000,
71 	0xc0096900,
72 	0x0000022a,
73 	0x00000000,
74 	0x00000000,
75 	0x00000000,
76 	0x00000000,
77 	0x00000000,
78 	0x00000000,
79 	0x00000000,
80 	0x00000000,
81 	0x00000000,
82 	0xc0016900,
83 	0x00000004,
84 	0x00000000,
85 	0xc0016900,
86 	0x0000000a,
87 	0x00000000,
88 	0xc0016900,
89 	0x0000000b,
90 	0x00000000,
91 	0xc0016900,
92 	0x0000010c,
93 	0x00000000,
94 	0xc0016900,
95 	0x0000010d,
96 	0x00000000,
97 	0xc0016900,
98 	0x00000200,
99 	0x00000000,
100 	0xc0016900,
101 	0x00000343,
102 	0x00000060,
103 	0xc0016900,
104 	0x00000344,
105 	0x00000040,
106 	0xc0016900,
107 	0x00000351,
108 	0x0000aa00,
109 	0xc0016900,
110 	0x00000104,
111 	0x00000000,
112 	0xc0016900,
113 	0x0000010e,
114 	0x00000000,
115 	0xc0046900,
116 	0x00000105,
117 	0x00000000,
118 	0x00000000,
119 	0x00000000,
120 	0x00000000,
121 	0xc0036900,
122 	0x00000109,
123 	0x00000000,
124 	0x00000000,
125 	0x00000000,
126 	0xc0046900,
127 	0x0000030c,
128 	0x01000000,
129 	0x00000000,
130 	0x00000000,
131 	0x00000000,
132 	0xc0046900,
133 	0x00000048,
134 	0x3f800000,
135 	0x00000000,
136 	0x3f800000,
137 	0x3f800000,
138 	0xc0016900,
139 	0x0000008e,
140 	0x0000000f,
141 	0xc0016900,
142 	0x00000080,
143 	0x00000000,
144 	0xc0016900,
145 	0x00000083,
146 	0x0000ffff,
147 	0xc0016900,
148 	0x00000084,
149 	0x00000000,
150 	0xc0016900,
151 	0x00000085,
152 	0x20002000,
153 	0xc0016900,
154 	0x00000086,
155 	0x00000000,
156 	0xc0016900,
157 	0x00000087,
158 	0x20002000,
159 	0xc0016900,
160 	0x00000088,
161 	0x00000000,
162 	0xc0016900,
163 	0x00000089,
164 	0x20002000,
165 	0xc0016900,
166 	0x0000008a,
167 	0x00000000,
168 	0xc0016900,
169 	0x0000008b,
170 	0x20002000,
171 	0xc0016900,
172 	0x0000008c,
173 	0x00000000,
174 	0xc0016900,
175 	0x00000094,
176 	0x80000000,
177 	0xc0016900,
178 	0x00000095,
179 	0x20002000,
180 	0xc0026900,
181 	0x000000b4,
182 	0x00000000,
183 	0x3f800000,
184 	0xc0016900,
185 	0x00000096,
186 	0x80000000,
187 	0xc0016900,
188 	0x00000097,
189 	0x20002000,
190 	0xc0026900,
191 	0x000000b6,
192 	0x00000000,
193 	0x3f800000,
194 	0xc0016900,
195 	0x00000098,
196 	0x80000000,
197 	0xc0016900,
198 	0x00000099,
199 	0x20002000,
200 	0xc0026900,
201 	0x000000b8,
202 	0x00000000,
203 	0x3f800000,
204 	0xc0016900,
205 	0x0000009a,
206 	0x80000000,
207 	0xc0016900,
208 	0x0000009b,
209 	0x20002000,
210 	0xc0026900,
211 	0x000000ba,
212 	0x00000000,
213 	0x3f800000,
214 	0xc0016900,
215 	0x0000009c,
216 	0x80000000,
217 	0xc0016900,
218 	0x0000009d,
219 	0x20002000,
220 	0xc0026900,
221 	0x000000bc,
222 	0x00000000,
223 	0x3f800000,
224 	0xc0016900,
225 	0x0000009e,
226 	0x80000000,
227 	0xc0016900,
228 	0x0000009f,
229 	0x20002000,
230 	0xc0026900,
231 	0x000000be,
232 	0x00000000,
233 	0x3f800000,
234 	0xc0016900,
235 	0x000000a0,
236 	0x80000000,
237 	0xc0016900,
238 	0x000000a1,
239 	0x20002000,
240 	0xc0026900,
241 	0x000000c0,
242 	0x00000000,
243 	0x3f800000,
244 	0xc0016900,
245 	0x000000a2,
246 	0x80000000,
247 	0xc0016900,
248 	0x000000a3,
249 	0x20002000,
250 	0xc0026900,
251 	0x000000c2,
252 	0x00000000,
253 	0x3f800000,
254 	0xc0016900,
255 	0x000000a4,
256 	0x80000000,
257 	0xc0016900,
258 	0x000000a5,
259 	0x20002000,
260 	0xc0026900,
261 	0x000000c4,
262 	0x00000000,
263 	0x3f800000,
264 	0xc0016900,
265 	0x000000a6,
266 	0x80000000,
267 	0xc0016900,
268 	0x000000a7,
269 	0x20002000,
270 	0xc0026900,
271 	0x000000c6,
272 	0x00000000,
273 	0x3f800000,
274 	0xc0016900,
275 	0x000000a8,
276 	0x80000000,
277 	0xc0016900,
278 	0x000000a9,
279 	0x20002000,
280 	0xc0026900,
281 	0x000000c8,
282 	0x00000000,
283 	0x3f800000,
284 	0xc0016900,
285 	0x000000aa,
286 	0x80000000,
287 	0xc0016900,
288 	0x000000ab,
289 	0x20002000,
290 	0xc0026900,
291 	0x000000ca,
292 	0x00000000,
293 	0x3f800000,
294 	0xc0016900,
295 	0x000000ac,
296 	0x80000000,
297 	0xc0016900,
298 	0x000000ad,
299 	0x20002000,
300 	0xc0026900,
301 	0x000000cc,
302 	0x00000000,
303 	0x3f800000,
304 	0xc0016900,
305 	0x000000ae,
306 	0x80000000,
307 	0xc0016900,
308 	0x000000af,
309 	0x20002000,
310 	0xc0026900,
311 	0x000000ce,
312 	0x00000000,
313 	0x3f800000,
314 	0xc0016900,
315 	0x000000b0,
316 	0x80000000,
317 	0xc0016900,
318 	0x000000b1,
319 	0x20002000,
320 	0xc0026900,
321 	0x000000d0,
322 	0x00000000,
323 	0x3f800000,
324 	0xc0016900,
325 	0x000000b2,
326 	0x80000000,
327 	0xc0016900,
328 	0x000000b3,
329 	0x20002000,
330 	0xc0026900,
331 	0x000000d2,
332 	0x00000000,
333 	0x3f800000,
334 	0xc0016900,
335 	0x00000293,
336 	0x00004010,
337 	0xc0016900,
338 	0x00000300,
339 	0x00000000,
340 	0xc0016900,
341 	0x00000301,
342 	0x00000000,
343 	0xc0016900,
344 	0x00000312,
345 	0xffffffff,
346 	0xc0016900,
347 	0x00000307,
348 	0x00000000,
349 	0xc0016900,
350 	0x00000308,
351 	0x00000000,
352 	0xc0016900,
353 	0x00000283,
354 	0x00000000,
355 	0xc0016900,
356 	0x00000292,
357 	0x00000000,
358 	0xc0066900,
359 	0x0000010f,
360 	0x00000000,
361 	0x00000000,
362 	0x00000000,
363 	0x00000000,
364 	0x00000000,
365 	0x00000000,
366 	0xc0016900,
367 	0x00000206,
368 	0x00000000,
369 	0xc0016900,
370 	0x00000207,
371 	0x00000000,
372 	0xc0016900,
373 	0x00000208,
374 	0x00000000,
375 	0xc0046900,
376 	0x00000303,
377 	0x3f800000,
378 	0x3f800000,
379 	0x3f800000,
380 	0x3f800000,
381 	0xc0016900,
382 	0x00000205,
383 	0x00000004,
384 	0xc0016900,
385 	0x00000280,
386 	0x00000000,
387 	0xc0016900,
388 	0x00000281,
389 	0x00000000,
390 	0xc0016900,
391 	0x0000037e,
392 	0x00000000,
393 	0xc0016900,
394 	0x00000382,
395 	0x00000000,
396 	0xc0016900,
397 	0x00000380,
398 	0x00000000,
399 	0xc0016900,
400 	0x00000383,
401 	0x00000000,
402 	0xc0016900,
403 	0x00000381,
404 	0x00000000,
405 	0xc0016900,
406 	0x00000282,
407 	0x00000008,
408 	0xc0016900,
409 	0x00000302,
410 	0x0000002d,
411 	0xc0016900,
412 	0x0000037f,
413 	0x00000000,
414 	0xc0016900,
415 	0x000001b2,
416 	0x00000000,
417 	0xc0016900,
418 	0x000001b6,
419 	0x00000000,
420 	0xc0016900,
421 	0x000001b7,
422 	0x00000000,
423 	0xc0016900,
424 	0x000001b8,
425 	0x00000000,
426 	0xc0016900,
427 	0x000001b9,
428 	0x00000000,
429 	0xc0016900,
430 	0x00000225,
431 	0x00000000,
432 	0xc0016900,
433 	0x00000229,
434 	0x00000000,
435 	0xc0016900,
436 	0x00000237,
437 	0x00000000,
438 	0xc0016900,
439 	0x00000100,
440 	0x00000800,
441 	0xc0016900,
442 	0x00000101,
443 	0x00000000,
444 	0xc0016900,
445 	0x00000102,
446 	0x00000000,
447 	0xc0016900,
448 	0x000002a8,
449 	0x00000000,
450 	0xc0016900,
451 	0x000002a9,
452 	0x00000000,
453 	0xc0016900,
454 	0x00000103,
455 	0x00000000,
456 	0xc0016900,
457 	0x00000284,
458 	0x00000000,
459 	0xc0016900,
460 	0x00000290,
461 	0x00000000,
462 	0xc0016900,
463 	0x00000285,
464 	0x00000000,
465 	0xc0016900,
466 	0x00000286,
467 	0x00000000,
468 	0xc0016900,
469 	0x00000287,
470 	0x00000000,
471 	0xc0016900,
472 	0x00000288,
473 	0x00000000,
474 	0xc0016900,
475 	0x00000289,
476 	0x00000000,
477 	0xc0016900,
478 	0x0000028a,
479 	0x00000000,
480 	0xc0016900,
481 	0x0000028b,
482 	0x00000000,
483 	0xc0016900,
484 	0x0000028c,
485 	0x00000000,
486 	0xc0016900,
487 	0x0000028d,
488 	0x00000000,
489 	0xc0016900,
490 	0x0000028e,
491 	0x00000000,
492 	0xc0016900,
493 	0x0000028f,
494 	0x00000000,
495 	0xc0016900,
496 	0x000002a1,
497 	0x00000000,
498 	0xc0016900,
499 	0x000002a5,
500 	0x00000000,
501 	0xc0016900,
502 	0x000002ac,
503 	0x00000000,
504 	0xc0016900,
505 	0x000002ad,
506 	0x00000000,
507 	0xc0016900,
508 	0x000002ae,
509 	0x00000000,
510 	0xc0016900,
511 	0x000002c8,
512 	0x00000000,
513 	0xc0016900,
514 	0x00000206,
515 	0x00000100,
516 	0xc0016900,
517 	0x00000204,
518 	0x00010000,
519 	0xc0036e00,
520 	0x00000000,
521 	0x00000012,
522 	0x00000000,
523 	0x00000000,
524 	0xc0016900,
525 	0x0000008f,
526 	0x0000000f,
527 	0xc0016900,
528 	0x000001e8,
529 	0x00000001,
530 	0xc0016900,
531 	0x00000202,
532 	0x00cc0000,
533 	0xc0016900,
534 	0x00000205,
535 	0x00000244,
536 	0xc0016900,
537 	0x00000203,
538 	0x00000210,
539 	0xc0016900,
540 	0x000001b1,
541 	0x00000000,
542 	0xc0016900,
543 	0x00000185,
544 	0x00000000,
545 	0xc0016900,
546 	0x000001b3,
547 	0x00000001,
548 	0xc0016900,
549 	0x000001b4,
550 	0x00000000,
551 	0xc0016900,
552 	0x00000191,
553 	0x00000b00,
554 	0xc0016900,
555 	0x000001b5,
556 	0x00000000,
557 };
558 
559 static u32 r7xx_default_state[] =
560 {
561 	0xc0012800,
562 	0x80000000,
563 	0x80000000,
564 	0xc0004600,
565 	0x00000016,
566 	0xc0016800,
567 	0x00000010,
568 	0x00028000,
569 	0xc0016800,
570 	0x00000010,
571 	0x00008000,
572 	0xc0016800,
573 	0x00000542,
574 	0x07000002,
575 	0xc0016800,
576 	0x000005c5,
577 	0x00000000,
578 	0xc0016800,
579 	0x00000363,
580 	0x00004000,
581 	0xc0016800,
582 	0x0000060c,
583 	0x00000000,
584 	0xc0016800,
585 	0x0000060e,
586 	0x00420204,
587 	0xc0016f00,
588 	0x00000000,
589 	0x00000000,
590 	0xc0016f00,
591 	0x00000001,
592 	0x00000000,
593 	0xc0096900,
594 	0x0000022a,
595 	0x00000000,
596 	0x00000000,
597 	0x00000000,
598 	0x00000000,
599 	0x00000000,
600 	0x00000000,
601 	0x00000000,
602 	0x00000000,
603 	0x00000000,
604 	0xc0016900,
605 	0x00000004,
606 	0x00000000,
607 	0xc0016900,
608 	0x0000000a,
609 	0x00000000,
610 	0xc0016900,
611 	0x0000000b,
612 	0x00000000,
613 	0xc0016900,
614 	0x0000010c,
615 	0x00000000,
616 	0xc0016900,
617 	0x0000010d,
618 	0x00000000,
619 	0xc0016900,
620 	0x00000200,
621 	0x00000000,
622 	0xc0016900,
623 	0x00000343,
624 	0x00000060,
625 	0xc0016900,
626 	0x00000344,
627 	0x00000000,
628 	0xc0016900,
629 	0x00000351,
630 	0x0000aa00,
631 	0xc0016900,
632 	0x00000104,
633 	0x00000000,
634 	0xc0016900,
635 	0x0000010e,
636 	0x00000000,
637 	0xc0046900,
638 	0x00000105,
639 	0x00000000,
640 	0x00000000,
641 	0x00000000,
642 	0x00000000,
643 	0xc0046900,
644 	0x0000030c,
645 	0x01000000,
646 	0x00000000,
647 	0x00000000,
648 	0x00000000,
649 	0xc0016900,
650 	0x0000008e,
651 	0x0000000f,
652 	0xc0016900,
653 	0x00000080,
654 	0x00000000,
655 	0xc0016900,
656 	0x00000083,
657 	0x0000ffff,
658 	0xc0016900,
659 	0x00000084,
660 	0x00000000,
661 	0xc0016900,
662 	0x00000085,
663 	0x20002000,
664 	0xc0016900,
665 	0x00000086,
666 	0x00000000,
667 	0xc0016900,
668 	0x00000087,
669 	0x20002000,
670 	0xc0016900,
671 	0x00000088,
672 	0x00000000,
673 	0xc0016900,
674 	0x00000089,
675 	0x20002000,
676 	0xc0016900,
677 	0x0000008a,
678 	0x00000000,
679 	0xc0016900,
680 	0x0000008b,
681 	0x20002000,
682 	0xc0016900,
683 	0x0000008c,
684 	0xaaaaaaaa,
685 	0xc0016900,
686 	0x00000094,
687 	0x80000000,
688 	0xc0016900,
689 	0x00000095,
690 	0x20002000,
691 	0xc0026900,
692 	0x000000b4,
693 	0x00000000,
694 	0x3f800000,
695 	0xc0016900,
696 	0x00000096,
697 	0x80000000,
698 	0xc0016900,
699 	0x00000097,
700 	0x20002000,
701 	0xc0026900,
702 	0x000000b6,
703 	0x00000000,
704 	0x3f800000,
705 	0xc0016900,
706 	0x00000098,
707 	0x80000000,
708 	0xc0016900,
709 	0x00000099,
710 	0x20002000,
711 	0xc0026900,
712 	0x000000b8,
713 	0x00000000,
714 	0x3f800000,
715 	0xc0016900,
716 	0x0000009a,
717 	0x80000000,
718 	0xc0016900,
719 	0x0000009b,
720 	0x20002000,
721 	0xc0026900,
722 	0x000000ba,
723 	0x00000000,
724 	0x3f800000,
725 	0xc0016900,
726 	0x0000009c,
727 	0x80000000,
728 	0xc0016900,
729 	0x0000009d,
730 	0x20002000,
731 	0xc0026900,
732 	0x000000bc,
733 	0x00000000,
734 	0x3f800000,
735 	0xc0016900,
736 	0x0000009e,
737 	0x80000000,
738 	0xc0016900,
739 	0x0000009f,
740 	0x20002000,
741 	0xc0026900,
742 	0x000000be,
743 	0x00000000,
744 	0x3f800000,
745 	0xc0016900,
746 	0x000000a0,
747 	0x80000000,
748 	0xc0016900,
749 	0x000000a1,
750 	0x20002000,
751 	0xc0026900,
752 	0x000000c0,
753 	0x00000000,
754 	0x3f800000,
755 	0xc0016900,
756 	0x000000a2,
757 	0x80000000,
758 	0xc0016900,
759 	0x000000a3,
760 	0x20002000,
761 	0xc0026900,
762 	0x000000c2,
763 	0x00000000,
764 	0x3f800000,
765 	0xc0016900,
766 	0x000000a4,
767 	0x80000000,
768 	0xc0016900,
769 	0x000000a5,
770 	0x20002000,
771 	0xc0026900,
772 	0x000000c4,
773 	0x00000000,
774 	0x3f800000,
775 	0xc0016900,
776 	0x000000a6,
777 	0x80000000,
778 	0xc0016900,
779 	0x000000a7,
780 	0x20002000,
781 	0xc0026900,
782 	0x000000c6,
783 	0x00000000,
784 	0x3f800000,
785 	0xc0016900,
786 	0x000000a8,
787 	0x80000000,
788 	0xc0016900,
789 	0x000000a9,
790 	0x20002000,
791 	0xc0026900,
792 	0x000000c8,
793 	0x00000000,
794 	0x3f800000,
795 	0xc0016900,
796 	0x000000aa,
797 	0x80000000,
798 	0xc0016900,
799 	0x000000ab,
800 	0x20002000,
801 	0xc0026900,
802 	0x000000ca,
803 	0x00000000,
804 	0x3f800000,
805 	0xc0016900,
806 	0x000000ac,
807 	0x80000000,
808 	0xc0016900,
809 	0x000000ad,
810 	0x20002000,
811 	0xc0026900,
812 	0x000000cc,
813 	0x00000000,
814 	0x3f800000,
815 	0xc0016900,
816 	0x000000ae,
817 	0x80000000,
818 	0xc0016900,
819 	0x000000af,
820 	0x20002000,
821 	0xc0026900,
822 	0x000000ce,
823 	0x00000000,
824 	0x3f800000,
825 	0xc0016900,
826 	0x000000b0,
827 	0x80000000,
828 	0xc0016900,
829 	0x000000b1,
830 	0x20002000,
831 	0xc0026900,
832 	0x000000d0,
833 	0x00000000,
834 	0x3f800000,
835 	0xc0016900,
836 	0x000000b2,
837 	0x80000000,
838 	0xc0016900,
839 	0x000000b3,
840 	0x20002000,
841 	0xc0026900,
842 	0x000000d2,
843 	0x00000000,
844 	0x3f800000,
845 	0xc0016900,
846 	0x00000293,
847 	0x00514000,
848 	0xc0016900,
849 	0x00000300,
850 	0x00000000,
851 	0xc0016900,
852 	0x00000301,
853 	0x00000000,
854 	0xc0016900,
855 	0x00000312,
856 	0xffffffff,
857 	0xc0016900,
858 	0x00000307,
859 	0x00000000,
860 	0xc0016900,
861 	0x00000308,
862 	0x00000000,
863 	0xc0016900,
864 	0x00000283,
865 	0x00000000,
866 	0xc0016900,
867 	0x00000292,
868 	0x00000000,
869 	0xc0066900,
870 	0x0000010f,
871 	0x00000000,
872 	0x00000000,
873 	0x00000000,
874 	0x00000000,
875 	0x00000000,
876 	0x00000000,
877 	0xc0016900,
878 	0x00000206,
879 	0x00000000,
880 	0xc0016900,
881 	0x00000207,
882 	0x00000000,
883 	0xc0016900,
884 	0x00000208,
885 	0x00000000,
886 	0xc0046900,
887 	0x00000303,
888 	0x3f800000,
889 	0x3f800000,
890 	0x3f800000,
891 	0x3f800000,
892 	0xc0016900,
893 	0x00000205,
894 	0x00000004,
895 	0xc0016900,
896 	0x00000280,
897 	0x00000000,
898 	0xc0016900,
899 	0x00000281,
900 	0x00000000,
901 	0xc0016900,
902 	0x0000037e,
903 	0x00000000,
904 	0xc0016900,
905 	0x00000382,
906 	0x00000000,
907 	0xc0016900,
908 	0x00000380,
909 	0x00000000,
910 	0xc0016900,
911 	0x00000383,
912 	0x00000000,
913 	0xc0016900,
914 	0x00000381,
915 	0x00000000,
916 	0xc0016900,
917 	0x00000282,
918 	0x00000008,
919 	0xc0016900,
920 	0x00000302,
921 	0x0000002d,
922 	0xc0016900,
923 	0x0000037f,
924 	0x00000000,
925 	0xc0016900,
926 	0x000001b2,
927 	0x00000001,
928 	0xc0016900,
929 	0x000001b6,
930 	0x00000000,
931 	0xc0016900,
932 	0x000001b7,
933 	0x00000000,
934 	0xc0016900,
935 	0x000001b8,
936 	0x00000000,
937 	0xc0016900,
938 	0x000001b9,
939 	0x00000000,
940 	0xc0016900,
941 	0x00000225,
942 	0x00000000,
943 	0xc0016900,
944 	0x00000229,
945 	0x00000000,
946 	0xc0016900,
947 	0x00000237,
948 	0x00000000,
949 	0xc0016900,
950 	0x00000100,
951 	0x00000800,
952 	0xc0016900,
953 	0x00000101,
954 	0x00000000,
955 	0xc0016900,
956 	0x00000102,
957 	0x00000000,
958 	0xc0016900,
959 	0x000002a8,
960 	0x00000000,
961 	0xc0016900,
962 	0x000002a9,
963 	0x00000000,
964 	0xc0016900,
965 	0x00000103,
966 	0x00000000,
967 	0xc0016900,
968 	0x00000284,
969 	0x00000000,
970 	0xc0016900,
971 	0x00000290,
972 	0x00000000,
973 	0xc0016900,
974 	0x00000285,
975 	0x00000000,
976 	0xc0016900,
977 	0x00000286,
978 	0x00000000,
979 	0xc0016900,
980 	0x00000287,
981 	0x00000000,
982 	0xc0016900,
983 	0x00000288,
984 	0x00000000,
985 	0xc0016900,
986 	0x00000289,
987 	0x00000000,
988 	0xc0016900,
989 	0x0000028a,
990 	0x00000000,
991 	0xc0016900,
992 	0x0000028b,
993 	0x00000000,
994 	0xc0016900,
995 	0x0000028c,
996 	0x00000000,
997 	0xc0016900,
998 	0x0000028d,
999 	0x00000000,
1000 	0xc0016900,
1001 	0x0000028e,
1002 	0x00000000,
1003 	0xc0016900,
1004 	0x0000028f,
1005 	0x00000000,
1006 	0xc0016900,
1007 	0x000002a1,
1008 	0x00000000,
1009 	0xc0016900,
1010 	0x000002a5,
1011 	0x00000000,
1012 	0xc0016900,
1013 	0x000002ac,
1014 	0x00000000,
1015 	0xc0016900,
1016 	0x000002ad,
1017 	0x00000000,
1018 	0xc0016900,
1019 	0x000002ae,
1020 	0x00000000,
1021 	0xc0016900,
1022 	0x000002c8,
1023 	0x00000000,
1024 	0xc0016900,
1025 	0x00000206,
1026 	0x00000100,
1027 	0xc0016900,
1028 	0x00000204,
1029 	0x00010000,
1030 	0xc0036e00,
1031 	0x00000000,
1032 	0x00000012,
1033 	0x00000000,
1034 	0x00000000,
1035 	0xc0016900,
1036 	0x0000008f,
1037 	0x0000000f,
1038 	0xc0016900,
1039 	0x000001e8,
1040 	0x00000001,
1041 	0xc0016900,
1042 	0x00000202,
1043 	0x00cc0000,
1044 	0xc0016900,
1045 	0x00000205,
1046 	0x00000244,
1047 	0xc0016900,
1048 	0x00000203,
1049 	0x00000210,
1050 	0xc0016900,
1051 	0x000001b1,
1052 	0x00000000,
1053 	0xc0016900,
1054 	0x00000185,
1055 	0x00000000,
1056 	0xc0016900,
1057 	0x000001b3,
1058 	0x00000001,
1059 	0xc0016900,
1060 	0x000001b4,
1061 	0x00000000,
1062 	0xc0016900,
1063 	0x00000191,
1064 	0x00000b00,
1065 	0xc0016900,
1066 	0x000001b5,
1067 	0x00000000,
1068 };
1069 
1070 /* same for r6xx/r7xx */
1071 static u32 r6xx_vs[] =
1072 {
1073 	0x00000004,
1074 	0x81000000,
1075 	0x0000203c,
1076 	0x94000b08,
1077 	0x00004000,
1078 	0x14200b1a,
1079 	0x00000000,
1080 	0x00000000,
1081 	0x3c000000,
1082 	0x68cd1000,
1083 	0x00080000,
1084 	0x00000000,
1085 };
1086 
1087 static u32 r6xx_ps[] =
1088 {
1089 	0x00000002,
1090 	0x80800000,
1091 	0x00000000,
1092 	0x94200688,
1093 	0x00000010,
1094 	0x000d1000,
1095 	0xb0800000,
1096 	0x00000000,
1097 };
1098 
1099 #define DI_PT_RECTLIST 0x11
1100 #define DI_INDEX_SIZE_16_BIT 0x0
1101 #define DI_SRC_SEL_AUTO_INDEX 0x2
1102 
1103 #define FMT_8 1
1104 #define FMT_5_6_5 8
1105 #define FMT_8_8_8_8 0x1a
1106 #define COLOR_8 1
1107 #define COLOR_5_6_5 8
1108 #define COLOR_8_8_8_8 0x1a
1109 
1110 #define R600_CB0_DEST_BASE_ENA (1 << 6)
1111 #define R600_TC_ACTION_ENA (1 << 23)
1112 #define R600_VC_ACTION_ENA (1 << 24)
1113 #define R600_CB_ACTION_ENA (1 << 25)
1114 #define R600_DB_ACTION_ENA (1 << 26)
1115 #define R600_SH_ACTION_ENA (1 << 27)
1116 #define R600_SMX_ACTION_ENA (1 << 28)
1117 
1118 #define R600_CB_COLOR0_SIZE 0x28060
1119 #define R600_CB_COLOR0_VIEW 0x28080
1120 #define R600_CB_COLOR0_INFO 0x280a0
1121 #define R600_CB_COLOR0_TILE 0x280c0
1122 #define R600_CB_COLOR0_FRAG 0x280e0
1123 #define R600_CB_COLOR0_MASK 0x28100
1124 
1125 #define R600_SQ_PGM_START_VS                                   0x28858
1126 #define R600_SQ_PGM_RESOURCES_VS 0x28868
1127 #define R600_SQ_PGM_CF_OFFSET_VS 0x288d0
1128 #define R600_SQ_PGM_START_PS                                   0x28840
1129 #define R600_SQ_PGM_RESOURCES_PS 0x28850
1130 #define R600_SQ_PGM_EXPORTS_PS 0x28854
1131 #define R600_SQ_PGM_CF_OFFSET_PS 0x288cc
1132 
1133 #define R600_VGT_PRIMITIVE_TYPE 0x8958
1134 
1135 #define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030
1136 #define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240
1137 #define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204
1138 
1139 #define R600_SQ_TEX_VTX_INVALID_TEXTURE                        0x0
1140 #define R600_SQ_TEX_VTX_INVALID_BUFFER                         0x1
1141 #define R600_SQ_TEX_VTX_VALID_TEXTURE                          0x2
1142 #define R600_SQ_TEX_VTX_VALID_BUFFER                           0x3
1143 
1144 /* packet 3 type offsets */
1145 #define R600_SET_CONFIG_REG_OFFSET                             0x00008000
1146 #define R600_SET_CONFIG_REG_END                                0x0000ac00
1147 #define R600_SET_CONTEXT_REG_OFFSET                            0x00028000
1148 #define R600_SET_CONTEXT_REG_END                               0x00029000
1149 #define R600_SET_ALU_CONST_OFFSET                              0x00030000
1150 #define R600_SET_ALU_CONST_END                                 0x00032000
1151 #define R600_SET_RESOURCE_OFFSET                               0x00038000
1152 #define R600_SET_RESOURCE_END                                  0x0003c000
1153 #define R600_SET_SAMPLER_OFFSET                                0x0003c000
1154 #define R600_SET_SAMPLER_END                                   0x0003cff0
1155 #define R600_SET_CTL_CONST_OFFSET                              0x0003cff0
1156 #define R600_SET_CTL_CONST_END                                 0x0003e200
1157 #define R600_SET_LOOP_CONST_OFFSET                             0x0003e200
1158 #define R600_SET_LOOP_CONST_END                                0x0003e380
1159 #define R600_SET_BOOL_CONST_OFFSET                             0x0003e380
1160 #define R600_SET_BOOL_CONST_END                                0x00040000
1161 
1162 /* Packet 3 types */
1163 #define R600_IT_INDIRECT_BUFFER_END               0x00001700
1164 #define R600_IT_SET_PREDICATION                   0x00002000
1165 #define R600_IT_REG_RMW                           0x00002100
1166 #define R600_IT_COND_EXEC                         0x00002200
1167 #define R600_IT_PRED_EXEC                         0x00002300
1168 #define R600_IT_START_3D_CMDBUF                   0x00002400
1169 #define R600_IT_DRAW_INDEX_2                      0x00002700
1170 #define R600_IT_CONTEXT_CONTROL                   0x00002800
1171 #define R600_IT_DRAW_INDEX_IMMD_BE                0x00002900
1172 #define R600_IT_INDEX_TYPE                        0x00002A00
1173 #define R600_IT_DRAW_INDEX                        0x00002B00
1174 #define R600_IT_DRAW_INDEX_AUTO                   0x00002D00
1175 #define R600_IT_DRAW_INDEX_IMMD                   0x00002E00
1176 #define R600_IT_NUM_INSTANCES                     0x00002F00
1177 #define R600_IT_STRMOUT_BUFFER_UPDATE             0x00003400
1178 #define R600_IT_INDIRECT_BUFFER_MP                0x00003800
1179 #define R600_IT_MEM_SEMAPHORE                     0x00003900
1180 #define R600_IT_MPEG_INDEX                        0x00003A00
1181 #define R600_IT_WAIT_REG_MEM                      0x00003C00
1182 #define R600_IT_MEM_WRITE                         0x00003D00
1183 #define R600_IT_INDIRECT_BUFFER                   0x00003200
1184 #define R600_IT_CP_INTERRUPT                      0x00004000
1185 #define R600_IT_SURFACE_SYNC                      0x00004300
1186 #define R600_IT_ME_INITIALIZE                     0x00004400
1187 #define R600_IT_COND_WRITE                        0x00004500
1188 #define R600_IT_EVENT_WRITE                       0x00004600
1189 #define R600_IT_EVENT_WRITE_EOP                   0x00004700
1190 #define R600_IT_ONE_REG_WRITE                     0x00005700
1191 #define R600_IT_SET_CONFIG_REG                    0x00006800
1192 #define R600_IT_SET_CONTEXT_REG                   0x00006900
1193 #define R600_IT_SET_ALU_CONST                     0x00006A00
1194 #define R600_IT_SET_BOOL_CONST                    0x00006B00
1195 #define R600_IT_SET_LOOP_CONST                    0x00006C00
1196 #define R600_IT_SET_RESOURCE                      0x00006D00
1197 #define R600_IT_SET_SAMPLER                       0x00006E00
1198 #define R600_IT_SET_CTL_CONST                     0x00006F00
1199 #define R600_IT_SURFACE_BASE_UPDATE               0x00007300
1200 
1201 static inline void
1202 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
1203 {
1204 	u32 cb_color_info;
1205 	int pitch, slice;
1206 	RING_LOCALS;
1207 	DRM_DEBUG("\n");
1208 
1209 	h = (h + 7) & ~7;
1210 	if (h < 8)
1211 		h = 8;
1212 
1213 	cb_color_info = ((format << 2) | (1 << 27));
1214 	pitch = (w / 8) - 1;
1215 	slice = ((w * h) / 64) - 1;
1216 
1217 	if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) &&
1218 	    ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) {
1219 		BEGIN_RING(21 + 2);
1220 		OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1221 		OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1222 		OUT_RING(gpu_addr >> 8);
1223 		OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
1224 		OUT_RING(2 << 0);
1225 	} else {
1226 		BEGIN_RING(21);
1227 		OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1228 		OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1229 		OUT_RING(gpu_addr >> 8);
1230 	}
1231 
1232 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1233         OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1234 	OUT_RING((pitch << 0) | (slice << 10));
1235 
1236 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1237         OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1238 	OUT_RING(0);
1239 
1240 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1241         OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1242 	OUT_RING(cb_color_info);
1243 
1244 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1245         OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1246 	OUT_RING(0);
1247 
1248 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1249         OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1250 	OUT_RING(0);
1251 
1252 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1253         OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1254 	OUT_RING(0);
1255 
1256 	ADVANCE_RING();
1257 }
1258 
1259 static inline void
1260 cp_set_surface_sync(drm_radeon_private_t *dev_priv,
1261 		    u32 sync_type, u32 size, u64 mc_addr)
1262 {
1263 	u32 cp_coher_size;
1264 	RING_LOCALS;
1265 	DRM_DEBUG("\n");
1266 
1267 	if (size == 0xffffffff)
1268 		cp_coher_size = 0xffffffff;
1269 	else
1270 		cp_coher_size = ((size + 255) >> 8);
1271 
1272 	BEGIN_RING(5);
1273 	OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
1274 	OUT_RING(sync_type);
1275 	OUT_RING(cp_coher_size);
1276 	OUT_RING((mc_addr >> 8));
1277 	OUT_RING(10); /* poll interval */
1278 	ADVANCE_RING();
1279 }
1280 
1281 static inline void
1282 set_shaders(struct drm_device *dev)
1283 {
1284 	drm_radeon_private_t *dev_priv = dev->dev_private;
1285 	u64 gpu_addr;
1286 	int shader_size, i;
1287 	u32 *vs, *ps;
1288 	uint32_t sq_pgm_resources;
1289 	RING_LOCALS;
1290 	DRM_DEBUG("\n");
1291 
1292 	/* load shaders */
1293 	vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
1294 	ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
1295 
1296 	shader_size = sizeof(r6xx_vs) / 4;
1297 	for (i= 0; i < shader_size; i++)
1298 		vs[i] = r6xx_vs[i];
1299 	shader_size = sizeof(r6xx_ps) / 4;
1300 	for (i= 0; i < shader_size; i++)
1301 		ps[i] = r6xx_ps[i];
1302 
1303 	dev_priv->blit_vb->used = 512;
1304 
1305 	gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
1306 
1307 	/* setup shader regs */
1308 	sq_pgm_resources = (1 << 0);
1309 
1310 	BEGIN_RING(9 + 12);
1311 	/* VS */
1312 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1313         OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1314 	OUT_RING(gpu_addr >> 8);
1315 
1316 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1317         OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1318 	OUT_RING(sq_pgm_resources);
1319 
1320 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1321         OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1322 	OUT_RING(0);
1323 
1324 	/* PS */
1325 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1326         OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1327 	OUT_RING((gpu_addr + 256) >> 8);
1328 
1329 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1330         OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1331 	OUT_RING(sq_pgm_resources | (1 << 28));
1332 
1333 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1334         OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1335 	OUT_RING(2);
1336 
1337 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1338         OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1339 	OUT_RING(0);
1340 	ADVANCE_RING();
1341 
1342 	cp_set_surface_sync(dev_priv,
1343 			    R600_SH_ACTION_ENA, 512, gpu_addr);
1344 }
1345 
1346 static inline void
1347 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
1348 {
1349 	uint32_t sq_vtx_constant_word2;
1350 	RING_LOCALS;
1351 	DRM_DEBUG("\n");
1352 
1353 	sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
1354 
1355 	BEGIN_RING(9);
1356 	OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
1357 	OUT_RING(0x460);
1358 	OUT_RING(gpu_addr & 0xffffffff);
1359 	OUT_RING(48 - 1);
1360 	OUT_RING(sq_vtx_constant_word2);
1361 	OUT_RING(1 << 0);
1362 	OUT_RING(0);
1363 	OUT_RING(0);
1364 	OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30);
1365 	ADVANCE_RING();
1366 
1367 	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1368 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1369 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1370 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
1371 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
1372 		cp_set_surface_sync(dev_priv,
1373 				    R600_TC_ACTION_ENA, 48, gpu_addr);
1374 	else
1375 		cp_set_surface_sync(dev_priv,
1376 				    R600_VC_ACTION_ENA, 48, gpu_addr);
1377 }
1378 
1379 static inline void
1380 set_tex_resource(drm_radeon_private_t *dev_priv,
1381 		 int format, int w, int h, int pitch, u64 gpu_addr)
1382 {
1383 	uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
1384 	RING_LOCALS;
1385 	DRM_DEBUG("\n");
1386 
1387 	if (h < 1)
1388 		h = 1;
1389 
1390 	sq_tex_resource_word0 = (1 << 0);
1391 	sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
1392 				  ((w - 1) << 19));
1393 
1394 	sq_tex_resource_word1 = (format << 26);
1395 	sq_tex_resource_word1 |= ((h - 1) << 0);
1396 
1397 	sq_tex_resource_word4 = ((1 << 14) |
1398 				 (0 << 16) |
1399 				 (1 << 19) |
1400 				 (2 << 22) |
1401 				 (3 << 25));
1402 
1403 	BEGIN_RING(9);
1404 	OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
1405 	OUT_RING(0);
1406 	OUT_RING(sq_tex_resource_word0);
1407 	OUT_RING(sq_tex_resource_word1);
1408 	OUT_RING(gpu_addr >> 8);
1409 	OUT_RING(gpu_addr >> 8);
1410 	OUT_RING(sq_tex_resource_word4);
1411 	OUT_RING(0);
1412 	OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);
1413 	ADVANCE_RING();
1414 
1415 }
1416 
1417 static inline void
1418 set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
1419 {
1420 	RING_LOCALS;
1421 	DRM_DEBUG("\n");
1422 
1423 	BEGIN_RING(12);
1424 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
1425         OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1426 	OUT_RING((x1 << 0) | (y1 << 16));
1427 	OUT_RING((x2 << 0) | (y2 << 16));
1428 
1429 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
1430         OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1431 	OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
1432 	OUT_RING((x2 << 0) | (y2 << 16));
1433 
1434 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
1435         OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1436 	OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
1437 	OUT_RING((x2 << 0) | (y2 << 16));
1438 	ADVANCE_RING();
1439 }
1440 
1441 static inline void
1442 draw_auto(drm_radeon_private_t *dev_priv)
1443 {
1444 	RING_LOCALS;
1445 	DRM_DEBUG("\n");
1446 
1447 	BEGIN_RING(10);
1448 	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
1449         OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);
1450 	OUT_RING(DI_PT_RECTLIST);
1451 
1452 	OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
1453 	OUT_RING(DI_INDEX_SIZE_16_BIT);
1454 
1455 	OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
1456 	OUT_RING(1);
1457 
1458 	OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
1459 	OUT_RING(3);
1460 	OUT_RING(DI_SRC_SEL_AUTO_INDEX);
1461 
1462 	ADVANCE_RING();
1463 	COMMIT_RING();
1464 }
1465 
1466 static inline void
1467 set_default_state(drm_radeon_private_t *dev_priv)
1468 {
1469 	int default_state_dw, i;
1470 	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
1471 	u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
1472 	int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
1473 	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
1474 	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
1475 	RING_LOCALS;
1476 
1477 	switch ((dev_priv->flags & RADEON_FAMILY_MASK)) {
1478 	case CHIP_R600:
1479 		num_ps_gprs = 192;
1480 		num_vs_gprs = 56;
1481 		num_temp_gprs = 4;
1482 		num_gs_gprs = 0;
1483 		num_es_gprs = 0;
1484 		num_ps_threads = 136;
1485 		num_vs_threads = 48;
1486 		num_gs_threads = 4;
1487 		num_es_threads = 4;
1488 		num_ps_stack_entries = 128;
1489 		num_vs_stack_entries = 128;
1490 		num_gs_stack_entries = 0;
1491 		num_es_stack_entries = 0;
1492 		break;
1493 	case CHIP_RV630:
1494 	case CHIP_RV635:
1495 		num_ps_gprs = 84;
1496 		num_vs_gprs = 36;
1497 		num_temp_gprs = 4;
1498 		num_gs_gprs = 0;
1499 		num_es_gprs = 0;
1500 		num_ps_threads = 144;
1501 		num_vs_threads = 40;
1502 		num_gs_threads = 4;
1503 		num_es_threads = 4;
1504 		num_ps_stack_entries = 40;
1505 		num_vs_stack_entries = 40;
1506 		num_gs_stack_entries = 32;
1507 		num_es_stack_entries = 16;
1508 		break;
1509 	case CHIP_RV610:
1510 	case CHIP_RV620:
1511 	case CHIP_RS780:
1512 	case CHIP_RS880:
1513 	default:
1514 		num_ps_gprs = 84;
1515 		num_vs_gprs = 36;
1516 		num_temp_gprs = 4;
1517 		num_gs_gprs = 0;
1518 		num_es_gprs = 0;
1519 		num_ps_threads = 136;
1520 		num_vs_threads = 48;
1521 		num_gs_threads = 4;
1522 		num_es_threads = 4;
1523 		num_ps_stack_entries = 40;
1524 		num_vs_stack_entries = 40;
1525 		num_gs_stack_entries = 32;
1526 		num_es_stack_entries = 16;
1527 		break;
1528 	case CHIP_RV670:
1529 		num_ps_gprs = 144;
1530 		num_vs_gprs = 40;
1531 		num_temp_gprs = 4;
1532 		num_gs_gprs = 0;
1533 		num_es_gprs = 0;
1534 		num_ps_threads = 136;
1535 		num_vs_threads = 48;
1536 		num_gs_threads = 4;
1537 		num_es_threads = 4;
1538 		num_ps_stack_entries = 40;
1539 		num_vs_stack_entries = 40;
1540 		num_gs_stack_entries = 32;
1541 		num_es_stack_entries = 16;
1542 		break;
1543 	case CHIP_RV770:
1544 		num_ps_gprs = 192;
1545 		num_vs_gprs = 56;
1546 		num_temp_gprs = 4;
1547 		num_gs_gprs = 0;
1548 		num_es_gprs = 0;
1549 		num_ps_threads = 188;
1550 		num_vs_threads = 60;
1551 		num_gs_threads = 0;
1552 		num_es_threads = 0;
1553 		num_ps_stack_entries = 256;
1554 		num_vs_stack_entries = 256;
1555 		num_gs_stack_entries = 0;
1556 		num_es_stack_entries = 0;
1557 		break;
1558 	case CHIP_RV730:
1559 	case CHIP_RV740:
1560 		num_ps_gprs = 84;
1561 		num_vs_gprs = 36;
1562 		num_temp_gprs = 4;
1563 		num_gs_gprs = 0;
1564 		num_es_gprs = 0;
1565 		num_ps_threads = 188;
1566 		num_vs_threads = 60;
1567 		num_gs_threads = 0;
1568 		num_es_threads = 0;
1569 		num_ps_stack_entries = 128;
1570 		num_vs_stack_entries = 128;
1571 		num_gs_stack_entries = 0;
1572 		num_es_stack_entries = 0;
1573 		break;
1574 	case CHIP_RV710:
1575 		num_ps_gprs = 192;
1576 		num_vs_gprs = 56;
1577 		num_temp_gprs = 4;
1578 		num_gs_gprs = 0;
1579 		num_es_gprs = 0;
1580 		num_ps_threads = 144;
1581 		num_vs_threads = 48;
1582 		num_gs_threads = 0;
1583 		num_es_threads = 0;
1584 		num_ps_stack_entries = 128;
1585 		num_vs_stack_entries = 128;
1586 		num_gs_stack_entries = 0;
1587 		num_es_stack_entries = 0;
1588 		break;
1589 	}
1590 
1591 	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1592 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1593 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1594 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
1595 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
1596 		sq_config = 0;
1597 	else
1598 		sq_config = R600_VC_ENABLE;
1599 
1600 	sq_config |= (R600_DX9_CONSTS |
1601 		      R600_ALU_INST_PREFER_VECTOR |
1602 		      R600_PS_PRIO(0) |
1603 		      R600_VS_PRIO(1) |
1604 		      R600_GS_PRIO(2) |
1605 		      R600_ES_PRIO(3));
1606 
1607 	sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) |
1608 				  R600_NUM_VS_GPRS(num_vs_gprs) |
1609 				  R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
1610 	sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) |
1611 				  R600_NUM_ES_GPRS(num_es_gprs));
1612 	sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) |
1613 				   R600_NUM_VS_THREADS(num_vs_threads) |
1614 				   R600_NUM_GS_THREADS(num_gs_threads) |
1615 				   R600_NUM_ES_THREADS(num_es_threads));
1616 	sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
1617 				    R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
1618 	sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
1619 				    R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
1620 
1621 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
1622 		default_state_dw = sizeof(r7xx_default_state) / 4;
1623 		BEGIN_RING(default_state_dw + 10);
1624 		for (i = 0; i < default_state_dw; i++)
1625 			OUT_RING(r7xx_default_state[i]);
1626 	} else {
1627 		default_state_dw = sizeof(r6xx_default_state) / 4;
1628 		BEGIN_RING(default_state_dw + 10);
1629 		for (i = 0; i < default_state_dw; i++)
1630 			OUT_RING(r6xx_default_state[i]);
1631 	}
1632 	OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
1633 	OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
1634 	/* SQ config */
1635 	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));
1636         OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);
1637 	OUT_RING(sq_config);
1638 	OUT_RING(sq_gpr_resource_mgmt_1);
1639 	OUT_RING(sq_gpr_resource_mgmt_2);
1640 	OUT_RING(sq_thread_resource_mgmt);
1641 	OUT_RING(sq_stack_resource_mgmt_1);
1642 	OUT_RING(sq_stack_resource_mgmt_2);
1643 	ADVANCE_RING();
1644 }
1645 
1646 static inline uint32_t i2f(uint32_t input)
1647 {
1648 	u32 result, i, exponent, fraction;
1649 
1650 	if ((input & 0x3fff) == 0)
1651 		result = 0; /* 0 is a special case */
1652 	else {
1653 		exponent = 140; /* exponent biased by 127; */
1654 		fraction = (input & 0x3fff) << 10; /* cheat and only
1655 						      handle numbers below 2^^15 */
1656 		for (i = 0; i < 14; i++) {
1657 			if (fraction & 0x800000)
1658 				break;
1659 			else {
1660 				fraction = fraction << 1; /* keep
1661 							     shifting left until top bit = 1 */
1662 				exponent = exponent -1;
1663 			}
1664 		}
1665 		result = exponent << 23 | (fraction & 0x7fffff); /* mask
1666 								    off top bit; assumed 1 */
1667 	}
1668 	return result;
1669 }
1670 
1671 int
1672 r600_prepare_blit_copy(struct drm_device *dev)
1673 {
1674 	drm_radeon_private_t *dev_priv = dev->dev_private;
1675 	DRM_DEBUG("\n");
1676 
1677 	dev_priv->blit_vb = radeon_freelist_get(dev);
1678 	if (!dev_priv->blit_vb) {
1679 		DRM_ERROR("Unable to allocate vertex buffer for blit\n");
1680 		return -EAGAIN;
1681 	}
1682 
1683 	set_default_state(dev_priv);
1684 	set_shaders(dev);
1685 
1686 	return 0;
1687 }
1688 
1689 void
1690 r600_done_blit_copy(struct drm_device *dev)
1691 {
1692 	drm_radeon_private_t *dev_priv = dev->dev_private;
1693 	RING_LOCALS;
1694 	DRM_DEBUG("\n");
1695 
1696 	BEGIN_RING(5);
1697 	OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
1698 	OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
1699 	/* wait for 3D idle clean */
1700 	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
1701 	OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
1702 	OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
1703 
1704 	ADVANCE_RING();
1705 	COMMIT_RING();
1706 
1707 	dev_priv->blit_vb->used = 0;
1708 	radeon_cp_discard_buffer(dev, dev_priv->blit_vb);
1709 }
1710 
1711 void
1712 r600_blit_copy(struct drm_device *dev,
1713 	       uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
1714 	       int size_bytes)
1715 {
1716 	drm_radeon_private_t *dev_priv = dev->dev_private;
1717 	int max_bytes;
1718 	u64 vb_addr;
1719 	u32 *vb;
1720 
1721 	vb = (u32 *) ((char *)dev->agp_buffer_map->handle +
1722 	    dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
1723 	DRM_DEBUG("src=0x%016llx, dst=0x%016llx, size=%d\n",
1724 	    (unsigned long long)src_gpu_addr,
1725 	    (unsigned long long)dst_gpu_addr, size_bytes);
1726 
1727 	if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
1728 		max_bytes = 8192;
1729 
1730 		while (size_bytes) {
1731 			int cur_size = size_bytes;
1732 			int src_x = src_gpu_addr & 255;
1733 			int dst_x = dst_gpu_addr & 255;
1734 			int h = 1;
1735 			src_gpu_addr = src_gpu_addr & ~255;
1736 			dst_gpu_addr = dst_gpu_addr & ~255;
1737 
1738 			if (!src_x && !dst_x) {
1739 				h = (cur_size / max_bytes);
1740 				if (h > 8192)
1741 					h = 8192;
1742 				if (h == 0)
1743 					h = 1;
1744 				else
1745 					cur_size = max_bytes;
1746 			} else {
1747 				if (cur_size > max_bytes)
1748 					cur_size = max_bytes;
1749 				if (cur_size > (max_bytes - dst_x))
1750 					cur_size = (max_bytes - dst_x);
1751 				if (cur_size > (max_bytes - src_x))
1752 					cur_size = (max_bytes - src_x);
1753 			}
1754 
1755 			if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
1756 				dev_priv->blit_vb->used = 0;
1757 				radeon_cp_discard_buffer(dev, dev_priv->blit_vb);
1758 				dev_priv->blit_vb = radeon_freelist_get(dev);
1759 				if (!dev_priv->blit_vb)
1760 					return;
1761 				set_shaders(dev);
1762 				vb = (u32 *) ((char *)dev->agp_buffer_map->handle +
1763 				    dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
1764 			}
1765 
1766 			vb[0] = i2f(dst_x);
1767 			vb[1] = 0;
1768 			vb[2] = i2f(src_x);
1769 			vb[3] = 0;
1770 
1771 			vb[4] = i2f(dst_x);
1772 			vb[5] = i2f(h);
1773 			vb[6] = i2f(src_x);
1774 			vb[7] = i2f(h);
1775 
1776 			vb[8] = i2f(dst_x + cur_size);
1777 			vb[9] = i2f(h);
1778 			vb[10] = i2f(src_x + cur_size);
1779 			vb[11] = i2f(h);
1780 
1781 			/* src */
1782 			set_tex_resource(dev_priv, FMT_8,
1783 					 src_x + cur_size, h, src_x + cur_size,
1784 					 src_gpu_addr);
1785 
1786 			cp_set_surface_sync(dev_priv,
1787 					    R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
1788 
1789 			/* dst */
1790 			set_render_target(dev_priv, COLOR_8,
1791 					  dst_x + cur_size, h,
1792 					  dst_gpu_addr);
1793 
1794 			/* scissors */
1795 			set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h);
1796 
1797 			/* Vertex buffer setup */
1798 			vb_addr = dev_priv->gart_buffers_offset +
1799                                 dev_priv->blit_vb->offset +
1800 				dev_priv->blit_vb->used;
1801 			set_vtx_resource(dev_priv, vb_addr);
1802 
1803 			/* draw */
1804 			draw_auto(dev_priv);
1805 
1806 			cp_set_surface_sync(dev_priv,
1807 					    R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
1808 					    cur_size * h, dst_gpu_addr);
1809 
1810 			vb += 12;
1811 			dev_priv->blit_vb->used += 12 * 4;
1812 
1813 			src_gpu_addr += cur_size * h;
1814 			dst_gpu_addr += cur_size * h;
1815 			size_bytes -= cur_size * h;
1816 		}
1817 	} else {
1818 		max_bytes = 8192 * 4;
1819 
1820 		while (size_bytes) {
1821 			int cur_size = size_bytes;
1822 			int src_x = (src_gpu_addr & 255);
1823 			int dst_x = (dst_gpu_addr & 255);
1824 			int h = 1;
1825 			src_gpu_addr = src_gpu_addr & ~255;
1826 			dst_gpu_addr = dst_gpu_addr & ~255;
1827 
1828 			if (!src_x && !dst_x) {
1829 				h = (cur_size / max_bytes);
1830 				if (h > 8192)
1831 					h = 8192;
1832 				if (h == 0)
1833 					h = 1;
1834 				else
1835 					cur_size = max_bytes;
1836 			} else {
1837 				if (cur_size > max_bytes)
1838 				    cur_size = max_bytes;
1839 				if (cur_size > (max_bytes - dst_x))
1840 					cur_size = (max_bytes - dst_x);
1841 				if (cur_size > (max_bytes - src_x))
1842 					cur_size = (max_bytes - src_x);
1843 			}
1844 
1845 			if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
1846 				dev_priv->blit_vb->used = 0;
1847 				radeon_cp_discard_buffer(dev, dev_priv->blit_vb);
1848 				dev_priv->blit_vb = radeon_freelist_get(dev);
1849 				if (!dev_priv->blit_vb)
1850 					return;
1851 				set_shaders(dev);
1852 				vb = (u32 *) ((char *)dev->agp_buffer_map->handle +
1853 				    dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
1854 			}
1855 
1856 			vb[0] = i2f(dst_x / 4);
1857 			vb[1] = 0;
1858 			vb[2] = i2f(src_x / 4);
1859 			vb[3] = 0;
1860 
1861 			vb[4] = i2f(dst_x / 4);
1862 			vb[5] = i2f(h);
1863 			vb[6] = i2f(src_x / 4);
1864 			vb[7] = i2f(h);
1865 
1866 			vb[8] = i2f((dst_x + cur_size) / 4);
1867 			vb[9] = i2f(h);
1868 			vb[10] = i2f((src_x + cur_size) / 4);
1869 			vb[11] = i2f(h);
1870 
1871 			/* src */
1872 			set_tex_resource(dev_priv, FMT_8_8_8_8,
1873 					 (src_x + cur_size) / 4,
1874 					 h, (src_x + cur_size) / 4,
1875 					 src_gpu_addr);
1876 
1877 			cp_set_surface_sync(dev_priv,
1878 					    R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
1879 
1880 			/* dst */
1881 			set_render_target(dev_priv, COLOR_8_8_8_8,
1882 					  (dst_x + cur_size) / 4, h,
1883 					  dst_gpu_addr);
1884 
1885 			/* scissors */
1886 			set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
1887 
1888 			/* Vertex buffer setup */
1889 			vb_addr = dev_priv->gart_buffers_offset +
1890                                 dev_priv->blit_vb->offset +
1891 				dev_priv->blit_vb->used;
1892 			set_vtx_resource(dev_priv, vb_addr);
1893 
1894 			/* draw */
1895 			draw_auto(dev_priv);
1896 
1897 			cp_set_surface_sync(dev_priv,
1898 					    R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
1899 					    cur_size * h, dst_gpu_addr);
1900 
1901 			vb += 12;
1902 			dev_priv->blit_vb->used += 12 * 4;
1903 
1904 			src_gpu_addr += cur_size * h;
1905 			dst_gpu_addr += cur_size * h;
1906 			size_bytes -= cur_size * h;
1907 		}
1908 	}
1909 }
1910 
1911 void
1912 r600_blit_swap(struct drm_device *dev,
1913 	       uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
1914 	       int sx, int sy, int dx, int dy,
1915 	       int w, int h, int src_pitch, int dst_pitch, int cpp)
1916 {
1917 	drm_radeon_private_t *dev_priv = dev->dev_private;
1918 	int cb_format, tex_format;
1919 	int sx2, sy2, dx2, dy2;
1920 	u64 vb_addr;
1921 	u32 *vb;
1922 
1923 	if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
1924 		dev_priv->blit_vb->used = 0;
1925 		radeon_cp_discard_buffer(dev, dev_priv->blit_vb);
1926 		dev_priv->blit_vb = radeon_freelist_get(dev);
1927 		if (!dev_priv->blit_vb)
1928 			return;
1929 		set_shaders(dev);
1930 	}
1931 	vb = (u32 *) ((char *)dev->agp_buffer_map->handle +
1932 	    dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
1933 
1934 	sx2 = sx + w;
1935 	sy2 = sy + h;
1936 	dx2 = dx + w;
1937 	dy2 = dy + h;
1938 
1939 	vb[0] = i2f(dx);
1940 	vb[1] = i2f(dy);
1941 	vb[2] = i2f(sx);
1942 	vb[3] = i2f(sy);
1943 
1944 	vb[4] = i2f(dx);
1945 	vb[5] = i2f(dy2);
1946 	vb[6] = i2f(sx);
1947 	vb[7] = i2f(sy2);
1948 
1949 	vb[8] = i2f(dx2);
1950 	vb[9] = i2f(dy2);
1951 	vb[10] = i2f(sx2);
1952 	vb[11] = i2f(sy2);
1953 
1954 	switch(cpp) {
1955 	case 4:
1956 		cb_format = COLOR_8_8_8_8;
1957 		tex_format = FMT_8_8_8_8;
1958 		break;
1959 	case 2:
1960 		cb_format = COLOR_5_6_5;
1961 		tex_format = FMT_5_6_5;
1962 		break;
1963 	default:
1964 		cb_format = COLOR_8;
1965 		tex_format = FMT_8;
1966 		break;
1967 	}
1968 
1969 	/* src */
1970 	set_tex_resource(dev_priv, tex_format,
1971 			 src_pitch / cpp,
1972 			 sy2, src_pitch / cpp,
1973 			 src_gpu_addr);
1974 
1975 	cp_set_surface_sync(dev_priv,
1976 			    R600_TC_ACTION_ENA, src_pitch * sy2, src_gpu_addr);
1977 
1978 	/* dst */
1979 	set_render_target(dev_priv, cb_format,
1980 			  dst_pitch / cpp, dy2,
1981 			  dst_gpu_addr);
1982 
1983 	/* scissors */
1984 	set_scissors(dev_priv, dx, dy, dx2, dy2);
1985 
1986 	/* Vertex buffer setup */
1987 	vb_addr = dev_priv->gart_buffers_offset +
1988 		dev_priv->blit_vb->offset +
1989 		dev_priv->blit_vb->used;
1990 	set_vtx_resource(dev_priv, vb_addr);
1991 
1992 	/* draw */
1993 	draw_auto(dev_priv);
1994 
1995 	cp_set_surface_sync(dev_priv,
1996 			    R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
1997 			    dst_pitch * dy2, dst_gpu_addr);
1998 
1999 	dev_priv->blit_vb->used += 12 * 4;
2000 }
2001