1*677dec6eSriastradh /* $NetBSD: amdgpu_doorbell.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */ 21571a7a1Sriastradh 31571a7a1Sriastradh /* 41571a7a1Sriastradh * Copyright 2018 Advanced Micro Devices, Inc. 51571a7a1Sriastradh * 61571a7a1Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 71571a7a1Sriastradh * copy of this software and associated documentation files (the "Software"), 81571a7a1Sriastradh * to deal in the Software without restriction, including without limitation 91571a7a1Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 101571a7a1Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 111571a7a1Sriastradh * Software is furnished to do so, subject to the following conditions: 121571a7a1Sriastradh * 131571a7a1Sriastradh * The above copyright notice and this permission notice shall be included in 141571a7a1Sriastradh * all copies or substantial portions of the Software. 151571a7a1Sriastradh * 161571a7a1Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 171571a7a1Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 181571a7a1Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 191571a7a1Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 201571a7a1Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 211571a7a1Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 221571a7a1Sriastradh * OTHER DEALINGS IN THE SOFTWARE. 231571a7a1Sriastradh * 241571a7a1Sriastradh */ 251571a7a1Sriastradh 261571a7a1Sriastradh /* 271571a7a1Sriastradh * GPU doorbell structures, functions & helpers 281571a7a1Sriastradh */ 291571a7a1Sriastradh struct amdgpu_doorbell { 301571a7a1Sriastradh /* doorbell mmio */ 311571a7a1Sriastradh resource_size_t base; 321571a7a1Sriastradh resource_size_t size; 33*677dec6eSriastradh #ifdef __NetBSD__ 34*677dec6eSriastradh bus_space_tag_t bst; 35*677dec6eSriastradh bus_space_handle_t bsh; 36*677dec6eSriastradh #else 371571a7a1Sriastradh u32 __iomem *ptr; 38*677dec6eSriastradh #endif 391571a7a1Sriastradh u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 401571a7a1Sriastradh }; 411571a7a1Sriastradh 421571a7a1Sriastradh /* Reserved doorbells for amdgpu (including multimedia). 431571a7a1Sriastradh * KFD can use all the rest in the 2M doorbell bar. 441571a7a1Sriastradh * For asic before vega10, doorbell is 32-bit, so the 451571a7a1Sriastradh * index/offset is in dword. For vega10 and after, doorbell 461571a7a1Sriastradh * can be 64-bit, so the index defined is in qword. 471571a7a1Sriastradh */ 481571a7a1Sriastradh struct amdgpu_doorbell_index { 491571a7a1Sriastradh uint32_t kiq; 501571a7a1Sriastradh uint32_t mec_ring0; 511571a7a1Sriastradh uint32_t mec_ring1; 521571a7a1Sriastradh uint32_t mec_ring2; 531571a7a1Sriastradh uint32_t mec_ring3; 541571a7a1Sriastradh uint32_t mec_ring4; 551571a7a1Sriastradh uint32_t mec_ring5; 561571a7a1Sriastradh uint32_t mec_ring6; 571571a7a1Sriastradh uint32_t mec_ring7; 581571a7a1Sriastradh uint32_t userqueue_start; 591571a7a1Sriastradh uint32_t userqueue_end; 601571a7a1Sriastradh uint32_t gfx_ring0; 611571a7a1Sriastradh uint32_t gfx_ring1; 621571a7a1Sriastradh uint32_t sdma_engine[8]; 631571a7a1Sriastradh uint32_t ih; 641571a7a1Sriastradh union { 651571a7a1Sriastradh struct { 661571a7a1Sriastradh uint32_t vcn_ring0_1; 671571a7a1Sriastradh uint32_t vcn_ring2_3; 681571a7a1Sriastradh uint32_t vcn_ring4_5; 691571a7a1Sriastradh uint32_t vcn_ring6_7; 701571a7a1Sriastradh } vcn; 711571a7a1Sriastradh struct { 721571a7a1Sriastradh uint32_t uvd_ring0_1; 731571a7a1Sriastradh uint32_t uvd_ring2_3; 741571a7a1Sriastradh uint32_t uvd_ring4_5; 751571a7a1Sriastradh uint32_t uvd_ring6_7; 761571a7a1Sriastradh uint32_t vce_ring0_1; 771571a7a1Sriastradh uint32_t vce_ring2_3; 781571a7a1Sriastradh uint32_t vce_ring4_5; 791571a7a1Sriastradh uint32_t vce_ring6_7; 801571a7a1Sriastradh } uvd_vce; 811571a7a1Sriastradh }; 821571a7a1Sriastradh uint32_t first_non_cp; 831571a7a1Sriastradh uint32_t last_non_cp; 841571a7a1Sriastradh uint32_t max_assignment; 851571a7a1Sriastradh /* Per engine SDMA doorbell size in dword */ 861571a7a1Sriastradh uint32_t sdma_doorbell_range; 871571a7a1Sriastradh }; 881571a7a1Sriastradh 891571a7a1Sriastradh typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 901571a7a1Sriastradh { 911571a7a1Sriastradh AMDGPU_DOORBELL_KIQ = 0x000, 921571a7a1Sriastradh AMDGPU_DOORBELL_HIQ = 0x001, 931571a7a1Sriastradh AMDGPU_DOORBELL_DIQ = 0x002, 941571a7a1Sriastradh AMDGPU_DOORBELL_MEC_RING0 = 0x010, 951571a7a1Sriastradh AMDGPU_DOORBELL_MEC_RING1 = 0x011, 961571a7a1Sriastradh AMDGPU_DOORBELL_MEC_RING2 = 0x012, 971571a7a1Sriastradh AMDGPU_DOORBELL_MEC_RING3 = 0x013, 981571a7a1Sriastradh AMDGPU_DOORBELL_MEC_RING4 = 0x014, 991571a7a1Sriastradh AMDGPU_DOORBELL_MEC_RING5 = 0x015, 1001571a7a1Sriastradh AMDGPU_DOORBELL_MEC_RING6 = 0x016, 1011571a7a1Sriastradh AMDGPU_DOORBELL_MEC_RING7 = 0x017, 1021571a7a1Sriastradh AMDGPU_DOORBELL_GFX_RING0 = 0x020, 1031571a7a1Sriastradh AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 1041571a7a1Sriastradh AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 1051571a7a1Sriastradh AMDGPU_DOORBELL_IH = 0x1E8, 1061571a7a1Sriastradh AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 1071571a7a1Sriastradh AMDGPU_DOORBELL_INVALID = 0xFFFF 1081571a7a1Sriastradh } AMDGPU_DOORBELL_ASSIGNMENT; 1091571a7a1Sriastradh 1101571a7a1Sriastradh typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT 1111571a7a1Sriastradh { 1121571a7a1Sriastradh /* Compute + GFX: 0~255 */ 1131571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, 1141571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, 1151571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, 1161571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, 1171571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, 1181571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, 1191571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, 1201571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, 1211571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, 1221571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, 1231571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, 1241571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, 1251571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, 1261571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, 1271571a7a1Sriastradh /* SDMA:256~335*/ 1281571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, 1291571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, 1301571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, 1311571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, 1321571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, 1331571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, 1341571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, 1351571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, 1361571a7a1Sriastradh /* IH: 376~391 */ 1371571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_IH = 0x178, 1381571a7a1Sriastradh /* MMSCH: 392~407 1391571a7a1Sriastradh * overlap the doorbell assignment with VCN as they are mutually exclusive 1401571a7a1Sriastradh * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD 1411571a7a1Sriastradh */ 1421571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ 1431571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, 1441571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, 1451571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, 1461571a7a1Sriastradh 1471571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ 1481571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, 1491571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, 1501571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, 1511571a7a1Sriastradh 1521571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, 1531571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, 1541571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, 1551571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, 1561571a7a1Sriastradh 1571571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, 1581571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, 1591571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, 1601571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, 1611571a7a1Sriastradh 1621571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, 1631571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, 1641571a7a1Sriastradh 1651571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F, 1661571a7a1Sriastradh AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF 1671571a7a1Sriastradh } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT; 1681571a7a1Sriastradh 1691571a7a1Sriastradh typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT 1701571a7a1Sriastradh { 1711571a7a1Sriastradh /* Compute + GFX: 0~255 */ 1721571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_KIQ = 0x000, 1731571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_HIQ = 0x001, 1741571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_DIQ = 0x002, 1751571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003, 1761571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004, 1771571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005, 1781571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006, 1791571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007, 1801571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008, 1811571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009, 1821571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A, 1831571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00B, 1841571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A, 1851571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B, 1861571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C, 1871571a7a1Sriastradh /* SDMA:256~335*/ 1881571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100, 1891571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A, 1901571a7a1Sriastradh /* IH: 376~391 */ 1911571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_IH = 0x178, 1921571a7a1Sriastradh /* MMSCH: 392~407 1931571a7a1Sriastradh * overlap the doorbell assignment with VCN as they are mutually exclusive 1941571a7a1Sriastradh * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 1951571a7a1Sriastradh */ 1961571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 1971571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189, 1981571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A, 1991571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B, 2001571a7a1Sriastradh 2011571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0, 2021571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCN6_7, 2031571a7a1Sriastradh 2041571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F, 2051571a7a1Sriastradh AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF 2061571a7a1Sriastradh } AMDGPU_NAVI10_DOORBELL_ASSIGNMENT; 2071571a7a1Sriastradh 2081571a7a1Sriastradh /* 2091571a7a1Sriastradh * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 2101571a7a1Sriastradh */ 2111571a7a1Sriastradh typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 2121571a7a1Sriastradh { 2131571a7a1Sriastradh /* 2141571a7a1Sriastradh * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 2151571a7a1Sriastradh * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 2161571a7a1Sriastradh * Compute related doorbells are allocated from 0x00 to 0x8a 2171571a7a1Sriastradh */ 2181571a7a1Sriastradh 2191571a7a1Sriastradh 2201571a7a1Sriastradh /* kernel scheduling */ 2211571a7a1Sriastradh AMDGPU_DOORBELL64_KIQ = 0x00, 2221571a7a1Sriastradh 2231571a7a1Sriastradh /* HSA interface queue and debug queue */ 2241571a7a1Sriastradh AMDGPU_DOORBELL64_HIQ = 0x01, 2251571a7a1Sriastradh AMDGPU_DOORBELL64_DIQ = 0x02, 2261571a7a1Sriastradh 2271571a7a1Sriastradh /* Compute engines */ 2281571a7a1Sriastradh AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 2291571a7a1Sriastradh AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 2301571a7a1Sriastradh AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 2311571a7a1Sriastradh AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 2321571a7a1Sriastradh AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 2331571a7a1Sriastradh AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 2341571a7a1Sriastradh AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 2351571a7a1Sriastradh AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 2361571a7a1Sriastradh 2371571a7a1Sriastradh /* User queue doorbell range (128 doorbells) */ 2381571a7a1Sriastradh AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 2391571a7a1Sriastradh AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 2401571a7a1Sriastradh 2411571a7a1Sriastradh /* Graphics engine */ 2421571a7a1Sriastradh AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 2431571a7a1Sriastradh 2441571a7a1Sriastradh /* 2451571a7a1Sriastradh * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 2461571a7a1Sriastradh * Graphics voltage island aperture 1 2471571a7a1Sriastradh * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 2481571a7a1Sriastradh */ 2491571a7a1Sriastradh 2501571a7a1Sriastradh /* For vega10 sriov, the sdma doorbell must be fixed as follow 2511571a7a1Sriastradh * to keep the same setting with host driver, or it will 2521571a7a1Sriastradh * happen conflicts 2531571a7a1Sriastradh */ 2541571a7a1Sriastradh AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 2551571a7a1Sriastradh AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 2561571a7a1Sriastradh AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 2571571a7a1Sriastradh AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 2581571a7a1Sriastradh 2591571a7a1Sriastradh /* Interrupt handler */ 2601571a7a1Sriastradh AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 2611571a7a1Sriastradh AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 2621571a7a1Sriastradh AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 2631571a7a1Sriastradh 2641571a7a1Sriastradh /* VCN engine use 32 bits doorbell */ 2651571a7a1Sriastradh AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 2661571a7a1Sriastradh AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 2671571a7a1Sriastradh AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 2681571a7a1Sriastradh AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 2691571a7a1Sriastradh 2701571a7a1Sriastradh /* overlap the doorbell assignment with VCN as they are mutually exclusive 2711571a7a1Sriastradh * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 2721571a7a1Sriastradh */ 2731571a7a1Sriastradh AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 2741571a7a1Sriastradh AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 2751571a7a1Sriastradh AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 2761571a7a1Sriastradh AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 2771571a7a1Sriastradh 2781571a7a1Sriastradh AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 2791571a7a1Sriastradh AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 2801571a7a1Sriastradh AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 2811571a7a1Sriastradh AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 2821571a7a1Sriastradh 2831571a7a1Sriastradh AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, 2841571a7a1Sriastradh AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, 2851571a7a1Sriastradh 2861571a7a1Sriastradh AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 2871571a7a1Sriastradh AMDGPU_DOORBELL64_INVALID = 0xFFFF 2881571a7a1Sriastradh } AMDGPU_DOORBELL64_ASSIGNMENT; 2891571a7a1Sriastradh 2901571a7a1Sriastradh u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2911571a7a1Sriastradh void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2921571a7a1Sriastradh u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 2931571a7a1Sriastradh void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 2941571a7a1Sriastradh 2951571a7a1Sriastradh #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2961571a7a1Sriastradh #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2971571a7a1Sriastradh #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 2981571a7a1Sriastradh #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 2991571a7a1Sriastradh 300