1*b45c3ff5Sriastradh /* $NetBSD: amdgpu_gfx_v8_0.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $ */
2a30d5d3aSriastradh
3a30d5d3aSriastradh /*
4a30d5d3aSriastradh * Copyright 2014 Advanced Micro Devices, Inc.
5a30d5d3aSriastradh *
6a30d5d3aSriastradh * Permission is hereby granted, free of charge, to any person obtaining a
7a30d5d3aSriastradh * copy of this software and associated documentation files (the "Software"),
8a30d5d3aSriastradh * to deal in the Software without restriction, including without limitation
9a30d5d3aSriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10a30d5d3aSriastradh * and/or sell copies of the Software, and to permit persons to whom the
11a30d5d3aSriastradh * Software is furnished to do so, subject to the following conditions:
12a30d5d3aSriastradh *
13a30d5d3aSriastradh * The above copyright notice and this permission notice shall be included in
14a30d5d3aSriastradh * all copies or substantial portions of the Software.
15a30d5d3aSriastradh *
16a30d5d3aSriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17a30d5d3aSriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18a30d5d3aSriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19a30d5d3aSriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20a30d5d3aSriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21a30d5d3aSriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22a30d5d3aSriastradh * OTHER DEALINGS IN THE SOFTWARE.
23a30d5d3aSriastradh *
24a30d5d3aSriastradh */
25a30d5d3aSriastradh
26677dec6eSriastradh #include <sys/cdefs.h>
27*b45c3ff5Sriastradh __KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v8_0.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $");
28677dec6eSriastradh
29677dec6eSriastradh #include <linux/delay.h>
30677dec6eSriastradh #include <linux/kernel.h>
31a30d5d3aSriastradh #include <linux/firmware.h>
32677dec6eSriastradh #include <linux/module.h>
33677dec6eSriastradh #include <linux/pci.h>
34677dec6eSriastradh
35a30d5d3aSriastradh #include "amdgpu.h"
36a30d5d3aSriastradh #include "amdgpu_gfx.h"
37a30d5d3aSriastradh #include "vi.h"
38677dec6eSriastradh #include "vi_structs.h"
39a30d5d3aSriastradh #include "vid.h"
40a30d5d3aSriastradh #include "amdgpu_ucode.h"
41677dec6eSriastradh #include "amdgpu_atombios.h"
42677dec6eSriastradh #include "atombios_i2c.h"
43a30d5d3aSriastradh #include "clearstate_vi.h"
44a30d5d3aSriastradh #include "gfx_v8_0.h"
45a30d5d3aSriastradh
46a30d5d3aSriastradh #include "gmc/gmc_8_2_d.h"
47a30d5d3aSriastradh #include "gmc/gmc_8_2_sh_mask.h"
48a30d5d3aSriastradh
49a30d5d3aSriastradh #include "oss/oss_3_0_d.h"
50a30d5d3aSriastradh #include "oss/oss_3_0_sh_mask.h"
51a30d5d3aSriastradh
52a30d5d3aSriastradh #include "bif/bif_5_0_d.h"
53a30d5d3aSriastradh #include "bif/bif_5_0_sh_mask.h"
54a30d5d3aSriastradh #include "gca/gfx_8_0_d.h"
55a30d5d3aSriastradh #include "gca/gfx_8_0_enum.h"
56a30d5d3aSriastradh #include "gca/gfx_8_0_sh_mask.h"
57a30d5d3aSriastradh
58a30d5d3aSriastradh #include "dce/dce_10_0_d.h"
59a30d5d3aSriastradh #include "dce/dce_10_0_sh_mask.h"
60a30d5d3aSriastradh
61677dec6eSriastradh #include "smu/smu_7_1_3_d.h"
62677dec6eSriastradh
63677dec6eSriastradh #include "ivsrcid/ivsrcid_vislands30.h"
64677dec6eSriastradh
651cb26435Sriastradh #include <linux/nbsd-namespace.h>
661cb26435Sriastradh
67a30d5d3aSriastradh #define GFX8_NUM_GFX_RINGS 1
68677dec6eSriastradh #define GFX8_MEC_HPD_SIZE 4096
69a30d5d3aSriastradh
70a30d5d3aSriastradh #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
71a30d5d3aSriastradh #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
72677dec6eSriastradh #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
73a30d5d3aSriastradh #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
74a30d5d3aSriastradh
75a30d5d3aSriastradh #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
76a30d5d3aSriastradh #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
77a30d5d3aSriastradh #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
78a30d5d3aSriastradh #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
79a30d5d3aSriastradh #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
80a30d5d3aSriastradh #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
81a30d5d3aSriastradh #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
82a30d5d3aSriastradh #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
83a30d5d3aSriastradh #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
84a30d5d3aSriastradh
85677dec6eSriastradh #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
86677dec6eSriastradh #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
87677dec6eSriastradh #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
88677dec6eSriastradh #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
89677dec6eSriastradh #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
90677dec6eSriastradh #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
91677dec6eSriastradh
92677dec6eSriastradh /* BPM SERDES CMD */
93677dec6eSriastradh #define SET_BPM_SERDES_CMD 1
94677dec6eSriastradh #define CLE_BPM_SERDES_CMD 0
95677dec6eSriastradh
96677dec6eSriastradh /* BPM Register Address*/
97677dec6eSriastradh enum {
98677dec6eSriastradh BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
99677dec6eSriastradh BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
100677dec6eSriastradh BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
101677dec6eSriastradh BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
102677dec6eSriastradh BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
103677dec6eSriastradh BPM_REG_FGCG_MAX
104677dec6eSriastradh };
105677dec6eSriastradh
106677dec6eSriastradh #define RLC_FormatDirectRegListLength 14
107677dec6eSriastradh
108a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
109a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
110a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
111a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
112a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
113a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
114a30d5d3aSriastradh
115a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
116a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
117a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/stoney_me.bin");
118a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
119a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
120a30d5d3aSriastradh
121a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
122a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
123a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/tonga_me.bin");
124a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
125a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
126a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
127a30d5d3aSriastradh
128a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
129a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
130a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/topaz_me.bin");
131a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
132a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
133a30d5d3aSriastradh
134a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
135a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
136a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/fiji_me.bin");
137a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
138a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
139a30d5d3aSriastradh MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
140a30d5d3aSriastradh
141677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
142677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
143677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
144677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
145677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
146677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
147677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
148677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
149677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
150677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
151677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
152677dec6eSriastradh
153677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
154677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
155677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
156677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
157677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
158677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
159677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
160677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
161677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
162677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
163677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
164677dec6eSriastradh
165677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
166677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
167677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
168677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
169677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
170677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
171677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
172677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
173677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
174677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
175677dec6eSriastradh MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
176677dec6eSriastradh
177677dec6eSriastradh MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
178677dec6eSriastradh MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
179677dec6eSriastradh MODULE_FIRMWARE("amdgpu/vegam_me.bin");
180677dec6eSriastradh MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
181677dec6eSriastradh MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
182677dec6eSriastradh MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
183677dec6eSriastradh
184a30d5d3aSriastradh static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
185a30d5d3aSriastradh {
186a30d5d3aSriastradh {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
187a30d5d3aSriastradh {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
188a30d5d3aSriastradh {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
189a30d5d3aSriastradh {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
190a30d5d3aSriastradh {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
191a30d5d3aSriastradh {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
192a30d5d3aSriastradh {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
193a30d5d3aSriastradh {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
194a30d5d3aSriastradh {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
195a30d5d3aSriastradh {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
196a30d5d3aSriastradh {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
197a30d5d3aSriastradh {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
198a30d5d3aSriastradh {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
199a30d5d3aSriastradh {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
200a30d5d3aSriastradh {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
201a30d5d3aSriastradh {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
202a30d5d3aSriastradh };
203a30d5d3aSriastradh
204a30d5d3aSriastradh static const u32 golden_settings_tonga_a11[] =
205a30d5d3aSriastradh {
206a30d5d3aSriastradh mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
207a30d5d3aSriastradh mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
208a30d5d3aSriastradh mmDB_DEBUG2, 0xf00fffff, 0x00000400,
209a30d5d3aSriastradh mmGB_GPU_ID, 0x0000000f, 0x00000000,
210a30d5d3aSriastradh mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
211a30d5d3aSriastradh mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
212a30d5d3aSriastradh mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
213677dec6eSriastradh mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
214a30d5d3aSriastradh mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
215a30d5d3aSriastradh mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
216a30d5d3aSriastradh mmTCC_CTRL, 0x00100000, 0xf31fff7f,
217a30d5d3aSriastradh mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
218a30d5d3aSriastradh mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
219a30d5d3aSriastradh mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
220a30d5d3aSriastradh mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
221a30d5d3aSriastradh mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
222a30d5d3aSriastradh };
223a30d5d3aSriastradh
224a30d5d3aSriastradh static const u32 tonga_golden_common_all[] =
225a30d5d3aSriastradh {
226a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
227a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
228a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
229a30d5d3aSriastradh mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
230a30d5d3aSriastradh mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
231a30d5d3aSriastradh mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
232677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
233677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
234a30d5d3aSriastradh };
235a30d5d3aSriastradh
236a30d5d3aSriastradh static const u32 tonga_mgcg_cgcg_init[] =
237a30d5d3aSriastradh {
238a30d5d3aSriastradh mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
239a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
240a30d5d3aSriastradh mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
241a30d5d3aSriastradh mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
242a30d5d3aSriastradh mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
243a30d5d3aSriastradh mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
244a30d5d3aSriastradh mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
245a30d5d3aSriastradh mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
246a30d5d3aSriastradh mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
247a30d5d3aSriastradh mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
248a30d5d3aSriastradh mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
249a30d5d3aSriastradh mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
250a30d5d3aSriastradh mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
251a30d5d3aSriastradh mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
252a30d5d3aSriastradh mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
253a30d5d3aSriastradh mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
254a30d5d3aSriastradh mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
255a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
256a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
257a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
258a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
259a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
260a30d5d3aSriastradh mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
261a30d5d3aSriastradh mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
262a30d5d3aSriastradh mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
263a30d5d3aSriastradh mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
264a30d5d3aSriastradh mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
265a30d5d3aSriastradh mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
266a30d5d3aSriastradh mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
267a30d5d3aSriastradh mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
268a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
269a30d5d3aSriastradh mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
270a30d5d3aSriastradh mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
271a30d5d3aSriastradh mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
272a30d5d3aSriastradh mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
273a30d5d3aSriastradh mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
274a30d5d3aSriastradh mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
275a30d5d3aSriastradh mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
276a30d5d3aSriastradh mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
277a30d5d3aSriastradh mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
278a30d5d3aSriastradh mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
279a30d5d3aSriastradh mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
280a30d5d3aSriastradh mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
281a30d5d3aSriastradh mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
282a30d5d3aSriastradh mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
283a30d5d3aSriastradh mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
284a30d5d3aSriastradh mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
285a30d5d3aSriastradh mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
286a30d5d3aSriastradh mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
287a30d5d3aSriastradh mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
288a30d5d3aSriastradh mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
289a30d5d3aSriastradh mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
290a30d5d3aSriastradh mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
291a30d5d3aSriastradh mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
292a30d5d3aSriastradh mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
293a30d5d3aSriastradh mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
294a30d5d3aSriastradh mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
295a30d5d3aSriastradh mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
296a30d5d3aSriastradh mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
297a30d5d3aSriastradh mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
298a30d5d3aSriastradh mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
299a30d5d3aSriastradh mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
300a30d5d3aSriastradh mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
301a30d5d3aSriastradh mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
302a30d5d3aSriastradh mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
303a30d5d3aSriastradh mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
304a30d5d3aSriastradh mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
305a30d5d3aSriastradh mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
306a30d5d3aSriastradh mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
307a30d5d3aSriastradh mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
308a30d5d3aSriastradh mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
309a30d5d3aSriastradh mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
310a30d5d3aSriastradh mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
311a30d5d3aSriastradh mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
312a30d5d3aSriastradh mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
313a30d5d3aSriastradh };
314a30d5d3aSriastradh
315677dec6eSriastradh static const u32 golden_settings_vegam_a11[] =
316677dec6eSriastradh {
317677dec6eSriastradh mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
318677dec6eSriastradh mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
319677dec6eSriastradh mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
320677dec6eSriastradh mmDB_DEBUG2, 0xf00fffff, 0x00000400,
321677dec6eSriastradh mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
322677dec6eSriastradh mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
323677dec6eSriastradh mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
324677dec6eSriastradh mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
325677dec6eSriastradh mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
326677dec6eSriastradh mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
327677dec6eSriastradh mmSQ_CONFIG, 0x07f80000, 0x01180000,
328677dec6eSriastradh mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
329677dec6eSriastradh mmTCC_CTRL, 0x00100000, 0xf31fff7f,
330677dec6eSriastradh mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
331677dec6eSriastradh mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
332677dec6eSriastradh mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
333677dec6eSriastradh mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
334677dec6eSriastradh };
335677dec6eSriastradh
336677dec6eSriastradh static const u32 vegam_golden_common_all[] =
337677dec6eSriastradh {
338677dec6eSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
339677dec6eSriastradh mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
340677dec6eSriastradh mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
341677dec6eSriastradh mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
342677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
343677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
344677dec6eSriastradh };
345677dec6eSriastradh
346677dec6eSriastradh static const u32 golden_settings_polaris11_a11[] =
347677dec6eSriastradh {
348677dec6eSriastradh mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
349677dec6eSriastradh mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
350677dec6eSriastradh mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
351677dec6eSriastradh mmDB_DEBUG2, 0xf00fffff, 0x00000400,
352677dec6eSriastradh mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
353677dec6eSriastradh mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
354677dec6eSriastradh mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
355677dec6eSriastradh mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
356677dec6eSriastradh mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
357677dec6eSriastradh mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
358677dec6eSriastradh mmSQ_CONFIG, 0x07f80000, 0x01180000,
359677dec6eSriastradh mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
360677dec6eSriastradh mmTCC_CTRL, 0x00100000, 0xf31fff7f,
361677dec6eSriastradh mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
362677dec6eSriastradh mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
363677dec6eSriastradh mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
364677dec6eSriastradh mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
365677dec6eSriastradh };
366677dec6eSriastradh
367677dec6eSriastradh static const u32 polaris11_golden_common_all[] =
368677dec6eSriastradh {
369677dec6eSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
370677dec6eSriastradh mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
371677dec6eSriastradh mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
372677dec6eSriastradh mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
373677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
374677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
375677dec6eSriastradh };
376677dec6eSriastradh
377677dec6eSriastradh static const u32 golden_settings_polaris10_a11[] =
378677dec6eSriastradh {
379677dec6eSriastradh mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
380677dec6eSriastradh mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
381677dec6eSriastradh mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
382677dec6eSriastradh mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
383677dec6eSriastradh mmDB_DEBUG2, 0xf00fffff, 0x00000400,
384677dec6eSriastradh mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
385677dec6eSriastradh mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
386677dec6eSriastradh mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
387677dec6eSriastradh mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
388677dec6eSriastradh mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
389677dec6eSriastradh mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
390677dec6eSriastradh mmSQ_CONFIG, 0x07f80000, 0x07180000,
391677dec6eSriastradh mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
392677dec6eSriastradh mmTCC_CTRL, 0x00100000, 0xf31fff7f,
393677dec6eSriastradh mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
394677dec6eSriastradh mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
395677dec6eSriastradh mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
396677dec6eSriastradh };
397677dec6eSriastradh
398677dec6eSriastradh static const u32 polaris10_golden_common_all[] =
399677dec6eSriastradh {
400677dec6eSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
401677dec6eSriastradh mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
402677dec6eSriastradh mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
403677dec6eSriastradh mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
404677dec6eSriastradh mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
405677dec6eSriastradh mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
406677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
407677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
408677dec6eSriastradh };
409677dec6eSriastradh
410a30d5d3aSriastradh static const u32 fiji_golden_common_all[] =
411a30d5d3aSriastradh {
412a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
413a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
414a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
415a30d5d3aSriastradh mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
416a30d5d3aSriastradh mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
417a30d5d3aSriastradh mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
418677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
419677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
420a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
421a30d5d3aSriastradh mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
422a30d5d3aSriastradh };
423a30d5d3aSriastradh
424a30d5d3aSriastradh static const u32 golden_settings_fiji_a10[] =
425a30d5d3aSriastradh {
426a30d5d3aSriastradh mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
427a30d5d3aSriastradh mmDB_DEBUG2, 0xf00fffff, 0x00000400,
428a30d5d3aSriastradh mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
429a30d5d3aSriastradh mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
430a30d5d3aSriastradh mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
431a30d5d3aSriastradh mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
432a30d5d3aSriastradh mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
433a30d5d3aSriastradh mmTCC_CTRL, 0x00100000, 0xf31fff7f,
434a30d5d3aSriastradh mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
435a30d5d3aSriastradh mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
436a30d5d3aSriastradh mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
437a30d5d3aSriastradh };
438a30d5d3aSriastradh
439a30d5d3aSriastradh static const u32 fiji_mgcg_cgcg_init[] =
440a30d5d3aSriastradh {
441a30d5d3aSriastradh mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
442a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
443a30d5d3aSriastradh mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
444a30d5d3aSriastradh mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
445a30d5d3aSriastradh mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
446a30d5d3aSriastradh mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
447a30d5d3aSriastradh mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
448a30d5d3aSriastradh mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
449a30d5d3aSriastradh mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
450a30d5d3aSriastradh mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
451a30d5d3aSriastradh mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
452a30d5d3aSriastradh mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
453a30d5d3aSriastradh mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
454a30d5d3aSriastradh mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
455a30d5d3aSriastradh mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
456a30d5d3aSriastradh mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
457a30d5d3aSriastradh mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
458a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
459a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
460a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
461a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
462a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
463a30d5d3aSriastradh mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
464a30d5d3aSriastradh mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
465a30d5d3aSriastradh mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
466a30d5d3aSriastradh mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
467a30d5d3aSriastradh mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
468a30d5d3aSriastradh mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
469a30d5d3aSriastradh mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
470a30d5d3aSriastradh mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
471a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
472a30d5d3aSriastradh mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
473a30d5d3aSriastradh mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
474a30d5d3aSriastradh mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
475a30d5d3aSriastradh mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
476a30d5d3aSriastradh };
477a30d5d3aSriastradh
478a30d5d3aSriastradh static const u32 golden_settings_iceland_a11[] =
479a30d5d3aSriastradh {
480a30d5d3aSriastradh mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
481a30d5d3aSriastradh mmDB_DEBUG2, 0xf00fffff, 0x00000400,
482a30d5d3aSriastradh mmDB_DEBUG3, 0xc0000000, 0xc0000000,
483a30d5d3aSriastradh mmGB_GPU_ID, 0x0000000f, 0x00000000,
484a30d5d3aSriastradh mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
485a30d5d3aSriastradh mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
486a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
487a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
488677dec6eSriastradh mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
489a30d5d3aSriastradh mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
490a30d5d3aSriastradh mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
491a30d5d3aSriastradh mmTCC_CTRL, 0x00100000, 0xf31fff7f,
492a30d5d3aSriastradh mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
493a30d5d3aSriastradh mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
494a30d5d3aSriastradh mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
495a30d5d3aSriastradh mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
496a30d5d3aSriastradh };
497a30d5d3aSriastradh
498a30d5d3aSriastradh static const u32 iceland_golden_common_all[] =
499a30d5d3aSriastradh {
500a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
501a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
502a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
503a30d5d3aSriastradh mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
504a30d5d3aSriastradh mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
505a30d5d3aSriastradh mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
506677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
507677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
508a30d5d3aSriastradh };
509a30d5d3aSriastradh
510a30d5d3aSriastradh static const u32 iceland_mgcg_cgcg_init[] =
511a30d5d3aSriastradh {
512a30d5d3aSriastradh mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
513a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
514a30d5d3aSriastradh mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
515a30d5d3aSriastradh mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
516a30d5d3aSriastradh mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
517a30d5d3aSriastradh mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
518a30d5d3aSriastradh mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
519a30d5d3aSriastradh mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
520a30d5d3aSriastradh mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
521a30d5d3aSriastradh mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
522a30d5d3aSriastradh mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
523a30d5d3aSriastradh mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
524a30d5d3aSriastradh mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
525a30d5d3aSriastradh mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
526a30d5d3aSriastradh mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
527a30d5d3aSriastradh mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
528a30d5d3aSriastradh mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
529a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
530a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
531a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
532a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
533a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
534a30d5d3aSriastradh mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
535a30d5d3aSriastradh mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
536a30d5d3aSriastradh mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
537a30d5d3aSriastradh mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
538a30d5d3aSriastradh mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
539a30d5d3aSriastradh mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
540a30d5d3aSriastradh mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
541a30d5d3aSriastradh mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
542a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
543a30d5d3aSriastradh mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
544a30d5d3aSriastradh mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
545a30d5d3aSriastradh mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
546a30d5d3aSriastradh mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
547a30d5d3aSriastradh mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
548a30d5d3aSriastradh mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
549a30d5d3aSriastradh mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
550a30d5d3aSriastradh mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
551a30d5d3aSriastradh mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
552a30d5d3aSriastradh mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
553a30d5d3aSriastradh mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
554a30d5d3aSriastradh mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
555a30d5d3aSriastradh mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
556a30d5d3aSriastradh mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
557a30d5d3aSriastradh mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
558a30d5d3aSriastradh mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
559a30d5d3aSriastradh mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
560a30d5d3aSriastradh mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
561a30d5d3aSriastradh mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
562a30d5d3aSriastradh mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
563a30d5d3aSriastradh mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
564a30d5d3aSriastradh mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
565a30d5d3aSriastradh mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
566a30d5d3aSriastradh mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
567a30d5d3aSriastradh mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
568a30d5d3aSriastradh mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
569a30d5d3aSriastradh mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
570a30d5d3aSriastradh mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
571a30d5d3aSriastradh mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
572a30d5d3aSriastradh mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
573a30d5d3aSriastradh mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
574a30d5d3aSriastradh mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
575a30d5d3aSriastradh mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
576a30d5d3aSriastradh };
577a30d5d3aSriastradh
578a30d5d3aSriastradh static const u32 cz_golden_settings_a11[] =
579a30d5d3aSriastradh {
580a30d5d3aSriastradh mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
581a30d5d3aSriastradh mmDB_DEBUG2, 0xf00fffff, 0x00000400,
582a30d5d3aSriastradh mmGB_GPU_ID, 0x0000000f, 0x00000000,
583a30d5d3aSriastradh mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
584a30d5d3aSriastradh mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
585677dec6eSriastradh mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
586a30d5d3aSriastradh mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
587a30d5d3aSriastradh mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
588677dec6eSriastradh mmTCC_CTRL, 0x00100000, 0xf31fff7f,
589a30d5d3aSriastradh mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
590a30d5d3aSriastradh mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
591a30d5d3aSriastradh mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
592a30d5d3aSriastradh };
593a30d5d3aSriastradh
594a30d5d3aSriastradh static const u32 cz_golden_common_all[] =
595a30d5d3aSriastradh {
596a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
597a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
598a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
599a30d5d3aSriastradh mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
600a30d5d3aSriastradh mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
601a30d5d3aSriastradh mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
602677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
603677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
604a30d5d3aSriastradh };
605a30d5d3aSriastradh
606a30d5d3aSriastradh static const u32 cz_mgcg_cgcg_init[] =
607a30d5d3aSriastradh {
608a30d5d3aSriastradh mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
609a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
610a30d5d3aSriastradh mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
611a30d5d3aSriastradh mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
612a30d5d3aSriastradh mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
613a30d5d3aSriastradh mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
614a30d5d3aSriastradh mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
615a30d5d3aSriastradh mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
616a30d5d3aSriastradh mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
617a30d5d3aSriastradh mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
618a30d5d3aSriastradh mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
619a30d5d3aSriastradh mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
620a30d5d3aSriastradh mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
621a30d5d3aSriastradh mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
622a30d5d3aSriastradh mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
623a30d5d3aSriastradh mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
624a30d5d3aSriastradh mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
625a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
626a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
627a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
628a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
629a30d5d3aSriastradh mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
630a30d5d3aSriastradh mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
631a30d5d3aSriastradh mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
632a30d5d3aSriastradh mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
633a30d5d3aSriastradh mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
634a30d5d3aSriastradh mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
635a30d5d3aSriastradh mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
636a30d5d3aSriastradh mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
637a30d5d3aSriastradh mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
638a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
639a30d5d3aSriastradh mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
640a30d5d3aSriastradh mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
641a30d5d3aSriastradh mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
642a30d5d3aSriastradh mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
643a30d5d3aSriastradh mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
644a30d5d3aSriastradh mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
645a30d5d3aSriastradh mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
646a30d5d3aSriastradh mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
647a30d5d3aSriastradh mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
648a30d5d3aSriastradh mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
649a30d5d3aSriastradh mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
650a30d5d3aSriastradh mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
651a30d5d3aSriastradh mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
652a30d5d3aSriastradh mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
653a30d5d3aSriastradh mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
654a30d5d3aSriastradh mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
655a30d5d3aSriastradh mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
656a30d5d3aSriastradh mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
657a30d5d3aSriastradh mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
658a30d5d3aSriastradh mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
659a30d5d3aSriastradh mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
660a30d5d3aSriastradh mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
661a30d5d3aSriastradh mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
662a30d5d3aSriastradh mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
663a30d5d3aSriastradh mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
664a30d5d3aSriastradh mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
665a30d5d3aSriastradh mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
666a30d5d3aSriastradh mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
667a30d5d3aSriastradh mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
668a30d5d3aSriastradh mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
669a30d5d3aSriastradh mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
670a30d5d3aSriastradh mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
671a30d5d3aSriastradh mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
672a30d5d3aSriastradh mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
673a30d5d3aSriastradh mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
674a30d5d3aSriastradh mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
675a30d5d3aSriastradh mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
676a30d5d3aSriastradh mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
677a30d5d3aSriastradh mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
678a30d5d3aSriastradh mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
679a30d5d3aSriastradh mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
680a30d5d3aSriastradh mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
681a30d5d3aSriastradh mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
682a30d5d3aSriastradh mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
683a30d5d3aSriastradh };
684a30d5d3aSriastradh
685a30d5d3aSriastradh static const u32 stoney_golden_settings_a11[] =
686a30d5d3aSriastradh {
687a30d5d3aSriastradh mmDB_DEBUG2, 0xf00fffff, 0x00000400,
688a30d5d3aSriastradh mmGB_GPU_ID, 0x0000000f, 0x00000000,
689a30d5d3aSriastradh mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
690a30d5d3aSriastradh mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
691a30d5d3aSriastradh mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
692a30d5d3aSriastradh mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
693a30d5d3aSriastradh mmTCC_CTRL, 0x00100000, 0xf31fff7f,
694a30d5d3aSriastradh mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
695a30d5d3aSriastradh mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
696a30d5d3aSriastradh mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
697a30d5d3aSriastradh };
698a30d5d3aSriastradh
699a30d5d3aSriastradh static const u32 stoney_golden_common_all[] =
700a30d5d3aSriastradh {
701a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
702a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
703a30d5d3aSriastradh mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
704a30d5d3aSriastradh mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
705a30d5d3aSriastradh mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
706a30d5d3aSriastradh mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
707677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
708677dec6eSriastradh mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
709a30d5d3aSriastradh };
710a30d5d3aSriastradh
711a30d5d3aSriastradh static const u32 stoney_mgcg_cgcg_init[] =
712a30d5d3aSriastradh {
713a30d5d3aSriastradh mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
714a30d5d3aSriastradh mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
715a30d5d3aSriastradh mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
716a30d5d3aSriastradh mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
717a30d5d3aSriastradh mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
718677dec6eSriastradh };
719677dec6eSriastradh
720677dec6eSriastradh
721677dec6eSriastradh static const char * const sq_edc_source_names[] = {
722677dec6eSriastradh "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
723677dec6eSriastradh "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
724677dec6eSriastradh "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
725677dec6eSriastradh "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
726677dec6eSriastradh "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
727677dec6eSriastradh "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
728677dec6eSriastradh "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
729a30d5d3aSriastradh };
730a30d5d3aSriastradh
731a30d5d3aSriastradh static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
732a30d5d3aSriastradh static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
733a30d5d3aSriastradh static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
734677dec6eSriastradh static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
735677dec6eSriastradh static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
736677dec6eSriastradh static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
737677dec6eSriastradh static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
738677dec6eSriastradh static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
739a30d5d3aSriastradh
gfx_v8_0_init_golden_registers(struct amdgpu_device * adev)740a30d5d3aSriastradh static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
741a30d5d3aSriastradh {
742a30d5d3aSriastradh switch (adev->asic_type) {
743a30d5d3aSriastradh case CHIP_TOPAZ:
744677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
745a30d5d3aSriastradh iceland_mgcg_cgcg_init,
746677dec6eSriastradh ARRAY_SIZE(iceland_mgcg_cgcg_init));
747677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
748a30d5d3aSriastradh golden_settings_iceland_a11,
749677dec6eSriastradh ARRAY_SIZE(golden_settings_iceland_a11));
750677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
751a30d5d3aSriastradh iceland_golden_common_all,
752677dec6eSriastradh ARRAY_SIZE(iceland_golden_common_all));
753a30d5d3aSriastradh break;
754a30d5d3aSriastradh case CHIP_FIJI:
755677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
756a30d5d3aSriastradh fiji_mgcg_cgcg_init,
757677dec6eSriastradh ARRAY_SIZE(fiji_mgcg_cgcg_init));
758677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
759a30d5d3aSriastradh golden_settings_fiji_a10,
760677dec6eSriastradh ARRAY_SIZE(golden_settings_fiji_a10));
761677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
762a30d5d3aSriastradh fiji_golden_common_all,
763677dec6eSriastradh ARRAY_SIZE(fiji_golden_common_all));
764a30d5d3aSriastradh break;
765a30d5d3aSriastradh
766a30d5d3aSriastradh case CHIP_TONGA:
767677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
768a30d5d3aSriastradh tonga_mgcg_cgcg_init,
769677dec6eSriastradh ARRAY_SIZE(tonga_mgcg_cgcg_init));
770677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
771a30d5d3aSriastradh golden_settings_tonga_a11,
772677dec6eSriastradh ARRAY_SIZE(golden_settings_tonga_a11));
773677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
774a30d5d3aSriastradh tonga_golden_common_all,
775677dec6eSriastradh ARRAY_SIZE(tonga_golden_common_all));
776677dec6eSriastradh break;
777677dec6eSriastradh case CHIP_VEGAM:
778677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
779677dec6eSriastradh golden_settings_vegam_a11,
780677dec6eSriastradh ARRAY_SIZE(golden_settings_vegam_a11));
781677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
782677dec6eSriastradh vegam_golden_common_all,
783677dec6eSriastradh ARRAY_SIZE(vegam_golden_common_all));
784677dec6eSriastradh break;
785677dec6eSriastradh case CHIP_POLARIS11:
786677dec6eSriastradh case CHIP_POLARIS12:
787677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
788677dec6eSriastradh golden_settings_polaris11_a11,
789677dec6eSriastradh ARRAY_SIZE(golden_settings_polaris11_a11));
790677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
791677dec6eSriastradh polaris11_golden_common_all,
792677dec6eSriastradh ARRAY_SIZE(polaris11_golden_common_all));
793677dec6eSriastradh break;
794677dec6eSriastradh case CHIP_POLARIS10:
795677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
796677dec6eSriastradh golden_settings_polaris10_a11,
797677dec6eSriastradh ARRAY_SIZE(golden_settings_polaris10_a11));
798677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
799677dec6eSriastradh polaris10_golden_common_all,
800677dec6eSriastradh ARRAY_SIZE(polaris10_golden_common_all));
801677dec6eSriastradh WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
802677dec6eSriastradh if (adev->pdev->revision == 0xc7 &&
803677dec6eSriastradh ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
804677dec6eSriastradh (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
805677dec6eSriastradh (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) {
806677dec6eSriastradh amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
807677dec6eSriastradh amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
808677dec6eSriastradh }
809a30d5d3aSriastradh break;
810a30d5d3aSriastradh case CHIP_CARRIZO:
811677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
812a30d5d3aSriastradh cz_mgcg_cgcg_init,
813677dec6eSriastradh ARRAY_SIZE(cz_mgcg_cgcg_init));
814677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
815a30d5d3aSriastradh cz_golden_settings_a11,
816677dec6eSriastradh ARRAY_SIZE(cz_golden_settings_a11));
817677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
818a30d5d3aSriastradh cz_golden_common_all,
819677dec6eSriastradh ARRAY_SIZE(cz_golden_common_all));
820a30d5d3aSriastradh break;
821a30d5d3aSriastradh case CHIP_STONEY:
822677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
823a30d5d3aSriastradh stoney_mgcg_cgcg_init,
824677dec6eSriastradh ARRAY_SIZE(stoney_mgcg_cgcg_init));
825677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
826a30d5d3aSriastradh stoney_golden_settings_a11,
827677dec6eSriastradh ARRAY_SIZE(stoney_golden_settings_a11));
828677dec6eSriastradh amdgpu_device_program_register_sequence(adev,
829a30d5d3aSriastradh stoney_golden_common_all,
830677dec6eSriastradh ARRAY_SIZE(stoney_golden_common_all));
831a30d5d3aSriastradh break;
832a30d5d3aSriastradh default:
833a30d5d3aSriastradh break;
834a30d5d3aSriastradh }
835a30d5d3aSriastradh }
836a30d5d3aSriastradh
gfx_v8_0_scratch_init(struct amdgpu_device * adev)837a30d5d3aSriastradh static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
838a30d5d3aSriastradh {
839677dec6eSriastradh adev->gfx.scratch.num_reg = 8;
840a30d5d3aSriastradh adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
841677dec6eSriastradh adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
842a30d5d3aSriastradh }
843a30d5d3aSriastradh
gfx_v8_0_ring_test_ring(struct amdgpu_ring * ring)844a30d5d3aSriastradh static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
845a30d5d3aSriastradh {
846a30d5d3aSriastradh struct amdgpu_device *adev = ring->adev;
847a30d5d3aSriastradh uint32_t scratch;
848a30d5d3aSriastradh uint32_t tmp = 0;
849a30d5d3aSriastradh unsigned i;
850a30d5d3aSriastradh int r;
851a30d5d3aSriastradh
852a30d5d3aSriastradh r = amdgpu_gfx_scratch_get(adev, &scratch);
853677dec6eSriastradh if (r)
854a30d5d3aSriastradh return r;
855677dec6eSriastradh
856a30d5d3aSriastradh WREG32(scratch, 0xCAFEDEAD);
857677dec6eSriastradh r = amdgpu_ring_alloc(ring, 3);
858677dec6eSriastradh if (r)
859677dec6eSriastradh goto error_free_scratch;
860677dec6eSriastradh
861a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
862a30d5d3aSriastradh amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
863a30d5d3aSriastradh amdgpu_ring_write(ring, 0xDEADBEEF);
864677dec6eSriastradh amdgpu_ring_commit(ring);
865a30d5d3aSriastradh
866a30d5d3aSriastradh for (i = 0; i < adev->usec_timeout; i++) {
867a30d5d3aSriastradh tmp = RREG32(scratch);
868a30d5d3aSriastradh if (tmp == 0xDEADBEEF)
869a30d5d3aSriastradh break;
870677dec6eSriastradh udelay(1);
871a30d5d3aSriastradh }
872677dec6eSriastradh
873677dec6eSriastradh if (i >= adev->usec_timeout)
874677dec6eSriastradh r = -ETIMEDOUT;
875677dec6eSriastradh
876677dec6eSriastradh error_free_scratch:
877a30d5d3aSriastradh amdgpu_gfx_scratch_free(adev, scratch);
878a30d5d3aSriastradh return r;
879a30d5d3aSriastradh }
880a30d5d3aSriastradh
gfx_v8_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)881677dec6eSriastradh static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
882a30d5d3aSriastradh {
883a30d5d3aSriastradh struct amdgpu_device *adev = ring->adev;
884a30d5d3aSriastradh struct amdgpu_ib ib;
885677dec6eSriastradh struct dma_fence *f = NULL;
886a30d5d3aSriastradh
887677dec6eSriastradh unsigned int index;
888677dec6eSriastradh uint64_t gpu_addr;
889677dec6eSriastradh uint32_t tmp;
890677dec6eSriastradh long r;
891677dec6eSriastradh
892677dec6eSriastradh r = amdgpu_device_wb_get(adev, &index);
893677dec6eSriastradh if (r)
894a30d5d3aSriastradh return r;
895a30d5d3aSriastradh
896677dec6eSriastradh gpu_addr = adev->wb.gpu_addr + (index * 4);
897677dec6eSriastradh adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
898677dec6eSriastradh memset(&ib, 0, sizeof(ib));
899677dec6eSriastradh r = amdgpu_ib_get(adev, NULL, 16, &ib);
900677dec6eSriastradh if (r)
901677dec6eSriastradh goto err1;
902677dec6eSriastradh
903677dec6eSriastradh ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
904677dec6eSriastradh ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
905677dec6eSriastradh ib.ptr[2] = lower_32_bits(gpu_addr);
906677dec6eSriastradh ib.ptr[3] = upper_32_bits(gpu_addr);
907677dec6eSriastradh ib.ptr[4] = 0xDEADBEEF;
908677dec6eSriastradh ib.length_dw = 5;
909677dec6eSriastradh
910677dec6eSriastradh r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
911a30d5d3aSriastradh if (r)
912a30d5d3aSriastradh goto err2;
913a30d5d3aSriastradh
914677dec6eSriastradh r = dma_fence_wait_timeout(f, false, timeout);
915677dec6eSriastradh if (r == 0) {
916677dec6eSriastradh r = -ETIMEDOUT;
917677dec6eSriastradh goto err2;
918677dec6eSriastradh } else if (r < 0) {
919a30d5d3aSriastradh goto err2;
920a30d5d3aSriastradh }
921677dec6eSriastradh
922677dec6eSriastradh tmp = adev->wb.wb[index];
923a30d5d3aSriastradh if (tmp == 0xDEADBEEF)
924677dec6eSriastradh r = 0;
925677dec6eSriastradh else
926a30d5d3aSriastradh r = -EINVAL;
927677dec6eSriastradh
928a30d5d3aSriastradh err2:
929677dec6eSriastradh amdgpu_ib_free(adev, &ib, NULL);
930677dec6eSriastradh dma_fence_put(f);
931a30d5d3aSriastradh err1:
932677dec6eSriastradh amdgpu_device_wb_free(adev, index);
933a30d5d3aSriastradh return r;
934a30d5d3aSriastradh }
935a30d5d3aSriastradh
936677dec6eSriastradh
gfx_v8_0_free_microcode(struct amdgpu_device * adev)937677dec6eSriastradh static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
938677dec6eSriastradh {
939677dec6eSriastradh release_firmware(adev->gfx.pfp_fw);
940677dec6eSriastradh adev->gfx.pfp_fw = NULL;
941677dec6eSriastradh release_firmware(adev->gfx.me_fw);
942677dec6eSriastradh adev->gfx.me_fw = NULL;
943677dec6eSriastradh release_firmware(adev->gfx.ce_fw);
944677dec6eSriastradh adev->gfx.ce_fw = NULL;
945677dec6eSriastradh release_firmware(adev->gfx.rlc_fw);
946677dec6eSriastradh adev->gfx.rlc_fw = NULL;
947677dec6eSriastradh release_firmware(adev->gfx.mec_fw);
948677dec6eSriastradh adev->gfx.mec_fw = NULL;
949677dec6eSriastradh if ((adev->asic_type != CHIP_STONEY) &&
950677dec6eSriastradh (adev->asic_type != CHIP_TOPAZ))
951677dec6eSriastradh release_firmware(adev->gfx.mec2_fw);
952677dec6eSriastradh adev->gfx.mec2_fw = NULL;
953677dec6eSriastradh
954677dec6eSriastradh kfree(adev->gfx.rlc.register_list_format);
955677dec6eSriastradh }
956677dec6eSriastradh
gfx_v8_0_init_microcode(struct amdgpu_device * adev)957a30d5d3aSriastradh static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
958a30d5d3aSriastradh {
959a30d5d3aSriastradh const char *chip_name;
960a30d5d3aSriastradh char fw_name[30];
961a30d5d3aSriastradh int err;
962a30d5d3aSriastradh struct amdgpu_firmware_info *info = NULL;
963a30d5d3aSriastradh const struct common_firmware_header *header = NULL;
964a30d5d3aSriastradh const struct gfx_firmware_header_v1_0 *cp_hdr;
965677dec6eSriastradh const struct rlc_firmware_header_v2_0 *rlc_hdr;
966677dec6eSriastradh unsigned int *tmp = NULL, i;
967a30d5d3aSriastradh
968a30d5d3aSriastradh DRM_DEBUG("\n");
969a30d5d3aSriastradh
970a30d5d3aSriastradh switch (adev->asic_type) {
971a30d5d3aSriastradh case CHIP_TOPAZ:
972a30d5d3aSriastradh chip_name = "topaz";
973a30d5d3aSriastradh break;
974a30d5d3aSriastradh case CHIP_TONGA:
975a30d5d3aSriastradh chip_name = "tonga";
976a30d5d3aSriastradh break;
977a30d5d3aSriastradh case CHIP_CARRIZO:
978a30d5d3aSriastradh chip_name = "carrizo";
979a30d5d3aSriastradh break;
980a30d5d3aSriastradh case CHIP_FIJI:
981a30d5d3aSriastradh chip_name = "fiji";
982a30d5d3aSriastradh break;
983a30d5d3aSriastradh case CHIP_STONEY:
984a30d5d3aSriastradh chip_name = "stoney";
985a30d5d3aSriastradh break;
986677dec6eSriastradh case CHIP_POLARIS10:
987677dec6eSriastradh chip_name = "polaris10";
988677dec6eSriastradh break;
989677dec6eSriastradh case CHIP_POLARIS11:
990677dec6eSriastradh chip_name = "polaris11";
991677dec6eSriastradh break;
992677dec6eSriastradh case CHIP_POLARIS12:
993677dec6eSriastradh chip_name = "polaris12";
994677dec6eSriastradh break;
995677dec6eSriastradh case CHIP_VEGAM:
996677dec6eSriastradh chip_name = "vegam";
997677dec6eSriastradh break;
998a30d5d3aSriastradh default:
999a30d5d3aSriastradh BUG();
1000a30d5d3aSriastradh }
1001a30d5d3aSriastradh
1002677dec6eSriastradh if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1003677dec6eSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
1004677dec6eSriastradh err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1005677dec6eSriastradh if (err == -ENOENT) {
1006a30d5d3aSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1007a30d5d3aSriastradh err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1008677dec6eSriastradh }
1009677dec6eSriastradh } else {
1010677dec6eSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1011677dec6eSriastradh err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1012677dec6eSriastradh }
1013a30d5d3aSriastradh if (err)
1014a30d5d3aSriastradh goto out;
1015a30d5d3aSriastradh err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1016a30d5d3aSriastradh if (err)
1017a30d5d3aSriastradh goto out;
1018a30d5d3aSriastradh cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1019a30d5d3aSriastradh adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1020a30d5d3aSriastradh adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1021a30d5d3aSriastradh
1022677dec6eSriastradh if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1023677dec6eSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
1024677dec6eSriastradh err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1025677dec6eSriastradh if (err == -ENOENT) {
1026a30d5d3aSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1027a30d5d3aSriastradh err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1028677dec6eSriastradh }
1029677dec6eSriastradh } else {
1030677dec6eSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1031677dec6eSriastradh err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1032677dec6eSriastradh }
1033a30d5d3aSriastradh if (err)
1034a30d5d3aSriastradh goto out;
1035a30d5d3aSriastradh err = amdgpu_ucode_validate(adev->gfx.me_fw);
1036a30d5d3aSriastradh if (err)
1037a30d5d3aSriastradh goto out;
1038a30d5d3aSriastradh cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1039a30d5d3aSriastradh adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1040677dec6eSriastradh
1041a30d5d3aSriastradh adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1042a30d5d3aSriastradh
1043677dec6eSriastradh if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1044677dec6eSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
1045677dec6eSriastradh err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1046677dec6eSriastradh if (err == -ENOENT) {
1047a30d5d3aSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1048a30d5d3aSriastradh err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1049677dec6eSriastradh }
1050677dec6eSriastradh } else {
1051677dec6eSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1052677dec6eSriastradh err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1053677dec6eSriastradh }
1054a30d5d3aSriastradh if (err)
1055a30d5d3aSriastradh goto out;
1056a30d5d3aSriastradh err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1057a30d5d3aSriastradh if (err)
1058a30d5d3aSriastradh goto out;
1059a30d5d3aSriastradh cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1060a30d5d3aSriastradh adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1061a30d5d3aSriastradh adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1062a30d5d3aSriastradh
1063677dec6eSriastradh /*
1064677dec6eSriastradh * Support for MCBP/Virtualization in combination with chained IBs is
1065677dec6eSriastradh * formal released on feature version #46
1066677dec6eSriastradh */
1067677dec6eSriastradh if (adev->gfx.ce_feature_version >= 46 &&
1068677dec6eSriastradh adev->gfx.pfp_feature_version >= 46) {
1069677dec6eSriastradh adev->virt.chained_ib_support = true;
1070677dec6eSriastradh DRM_INFO("Chained IB support enabled!\n");
1071677dec6eSriastradh } else
1072677dec6eSriastradh adev->virt.chained_ib_support = false;
1073677dec6eSriastradh
1074a30d5d3aSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1075a30d5d3aSriastradh err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1076a30d5d3aSriastradh if (err)
1077a30d5d3aSriastradh goto out;
1078a30d5d3aSriastradh err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1079677dec6eSriastradh rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1080677dec6eSriastradh adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1081677dec6eSriastradh adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1082a30d5d3aSriastradh
1083677dec6eSriastradh adev->gfx.rlc.save_and_restore_offset =
1084677dec6eSriastradh le32_to_cpu(rlc_hdr->save_and_restore_offset);
1085677dec6eSriastradh adev->gfx.rlc.clear_state_descriptor_offset =
1086677dec6eSriastradh le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1087677dec6eSriastradh adev->gfx.rlc.avail_scratch_ram_locations =
1088677dec6eSriastradh le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1089677dec6eSriastradh adev->gfx.rlc.reg_restore_list_size =
1090677dec6eSriastradh le32_to_cpu(rlc_hdr->reg_restore_list_size);
1091677dec6eSriastradh adev->gfx.rlc.reg_list_format_start =
1092677dec6eSriastradh le32_to_cpu(rlc_hdr->reg_list_format_start);
1093677dec6eSriastradh adev->gfx.rlc.reg_list_format_separate_start =
1094677dec6eSriastradh le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1095677dec6eSriastradh adev->gfx.rlc.starting_offsets_start =
1096677dec6eSriastradh le32_to_cpu(rlc_hdr->starting_offsets_start);
1097677dec6eSriastradh adev->gfx.rlc.reg_list_format_size_bytes =
1098677dec6eSriastradh le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1099677dec6eSriastradh adev->gfx.rlc.reg_list_size_bytes =
1100677dec6eSriastradh le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1101677dec6eSriastradh
1102677dec6eSriastradh adev->gfx.rlc.register_list_format =
1103677dec6eSriastradh kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1104677dec6eSriastradh adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1105677dec6eSriastradh
1106677dec6eSriastradh if (!adev->gfx.rlc.register_list_format) {
1107677dec6eSriastradh err = -ENOMEM;
1108677dec6eSriastradh goto out;
1109677dec6eSriastradh }
1110677dec6eSriastradh
1111677dec6eSriastradh tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1112677dec6eSriastradh le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1113677dec6eSriastradh for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1114677dec6eSriastradh adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1115677dec6eSriastradh
1116677dec6eSriastradh adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1117677dec6eSriastradh
1118677dec6eSriastradh tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1119677dec6eSriastradh le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1120677dec6eSriastradh for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1121677dec6eSriastradh adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1122677dec6eSriastradh
1123677dec6eSriastradh if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1124677dec6eSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1125677dec6eSriastradh err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1126677dec6eSriastradh if (err == -ENOENT) {
1127a30d5d3aSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1128a30d5d3aSriastradh err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1129677dec6eSriastradh }
1130677dec6eSriastradh } else {
1131677dec6eSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1132677dec6eSriastradh err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1133677dec6eSriastradh }
1134a30d5d3aSriastradh if (err)
1135a30d5d3aSriastradh goto out;
1136a30d5d3aSriastradh err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1137a30d5d3aSriastradh if (err)
1138a30d5d3aSriastradh goto out;
1139a30d5d3aSriastradh cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1140a30d5d3aSriastradh adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1141a30d5d3aSriastradh adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1142a30d5d3aSriastradh
1143a30d5d3aSriastradh if ((adev->asic_type != CHIP_STONEY) &&
1144a30d5d3aSriastradh (adev->asic_type != CHIP_TOPAZ)) {
1145677dec6eSriastradh if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1146677dec6eSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1147677dec6eSriastradh err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1148677dec6eSriastradh if (err == -ENOENT) {
1149a30d5d3aSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1150a30d5d3aSriastradh err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1151677dec6eSriastradh }
1152677dec6eSriastradh } else {
1153677dec6eSriastradh snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1154677dec6eSriastradh err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1155677dec6eSriastradh }
1156a30d5d3aSriastradh if (!err) {
1157a30d5d3aSriastradh err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1158a30d5d3aSriastradh if (err)
1159a30d5d3aSriastradh goto out;
1160a30d5d3aSriastradh cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1161a30d5d3aSriastradh adev->gfx.mec2_fw->data;
1162a30d5d3aSriastradh adev->gfx.mec2_fw_version =
1163a30d5d3aSriastradh le32_to_cpu(cp_hdr->header.ucode_version);
1164a30d5d3aSriastradh adev->gfx.mec2_feature_version =
1165a30d5d3aSriastradh le32_to_cpu(cp_hdr->ucode_feature_version);
1166a30d5d3aSriastradh } else {
1167a30d5d3aSriastradh err = 0;
1168a30d5d3aSriastradh adev->gfx.mec2_fw = NULL;
1169a30d5d3aSriastradh }
1170a30d5d3aSriastradh }
1171a30d5d3aSriastradh
1172a30d5d3aSriastradh info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1173a30d5d3aSriastradh info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1174a30d5d3aSriastradh info->fw = adev->gfx.pfp_fw;
1175a30d5d3aSriastradh header = (const struct common_firmware_header *)info->fw->data;
1176a30d5d3aSriastradh adev->firmware.fw_size +=
1177a30d5d3aSriastradh ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1178a30d5d3aSriastradh
1179a30d5d3aSriastradh info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1180a30d5d3aSriastradh info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1181a30d5d3aSriastradh info->fw = adev->gfx.me_fw;
1182a30d5d3aSriastradh header = (const struct common_firmware_header *)info->fw->data;
1183a30d5d3aSriastradh adev->firmware.fw_size +=
1184a30d5d3aSriastradh ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1185a30d5d3aSriastradh
1186a30d5d3aSriastradh info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1187a30d5d3aSriastradh info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1188a30d5d3aSriastradh info->fw = adev->gfx.ce_fw;
1189a30d5d3aSriastradh header = (const struct common_firmware_header *)info->fw->data;
1190a30d5d3aSriastradh adev->firmware.fw_size +=
1191a30d5d3aSriastradh ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1192a30d5d3aSriastradh
1193a30d5d3aSriastradh info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1194a30d5d3aSriastradh info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1195a30d5d3aSriastradh info->fw = adev->gfx.rlc_fw;
1196a30d5d3aSriastradh header = (const struct common_firmware_header *)info->fw->data;
1197a30d5d3aSriastradh adev->firmware.fw_size +=
1198a30d5d3aSriastradh ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1199a30d5d3aSriastradh
1200a30d5d3aSriastradh info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1201a30d5d3aSriastradh info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1202a30d5d3aSriastradh info->fw = adev->gfx.mec_fw;
1203a30d5d3aSriastradh header = (const struct common_firmware_header *)info->fw->data;
1204a30d5d3aSriastradh adev->firmware.fw_size +=
1205a30d5d3aSriastradh ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1206a30d5d3aSriastradh
1207677dec6eSriastradh /* we need account JT in */
1208677dec6eSriastradh cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1209677dec6eSriastradh adev->firmware.fw_size +=
1210677dec6eSriastradh ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1211677dec6eSriastradh
1212677dec6eSriastradh if (amdgpu_sriov_vf(adev)) {
1213677dec6eSriastradh info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1214677dec6eSriastradh info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1215677dec6eSriastradh info->fw = adev->gfx.mec_fw;
1216677dec6eSriastradh adev->firmware.fw_size +=
1217677dec6eSriastradh ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1218677dec6eSriastradh }
1219677dec6eSriastradh
1220a30d5d3aSriastradh if (adev->gfx.mec2_fw) {
1221a30d5d3aSriastradh info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1222a30d5d3aSriastradh info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1223a30d5d3aSriastradh info->fw = adev->gfx.mec2_fw;
1224a30d5d3aSriastradh header = (const struct common_firmware_header *)info->fw->data;
1225a30d5d3aSriastradh adev->firmware.fw_size +=
1226a30d5d3aSriastradh ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1227a30d5d3aSriastradh }
1228a30d5d3aSriastradh
1229a30d5d3aSriastradh out:
1230a30d5d3aSriastradh if (err) {
1231a30d5d3aSriastradh dev_err(adev->dev,
1232a30d5d3aSriastradh "gfx8: Failed to load firmware \"%s\"\n",
1233a30d5d3aSriastradh fw_name);
1234a30d5d3aSriastradh release_firmware(adev->gfx.pfp_fw);
1235a30d5d3aSriastradh adev->gfx.pfp_fw = NULL;
1236a30d5d3aSriastradh release_firmware(adev->gfx.me_fw);
1237a30d5d3aSriastradh adev->gfx.me_fw = NULL;
1238a30d5d3aSriastradh release_firmware(adev->gfx.ce_fw);
1239a30d5d3aSriastradh adev->gfx.ce_fw = NULL;
1240a30d5d3aSriastradh release_firmware(adev->gfx.rlc_fw);
1241a30d5d3aSriastradh adev->gfx.rlc_fw = NULL;
1242a30d5d3aSriastradh release_firmware(adev->gfx.mec_fw);
1243a30d5d3aSriastradh adev->gfx.mec_fw = NULL;
1244a30d5d3aSriastradh release_firmware(adev->gfx.mec2_fw);
1245a30d5d3aSriastradh adev->gfx.mec2_fw = NULL;
1246a30d5d3aSriastradh }
1247a30d5d3aSriastradh return err;
1248a30d5d3aSriastradh }
1249a30d5d3aSriastradh
gfx_v8_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)1250677dec6eSriastradh static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1251677dec6eSriastradh volatile u32 *buffer)
1252a30d5d3aSriastradh {
1253677dec6eSriastradh u32 count = 0, i;
1254677dec6eSriastradh const struct cs_section_def *sect = NULL;
1255677dec6eSriastradh const struct cs_extent_def *ext = NULL;
1256677dec6eSriastradh
1257677dec6eSriastradh if (adev->gfx.rlc.cs_data == NULL)
1258677dec6eSriastradh return;
1259677dec6eSriastradh if (buffer == NULL)
1260677dec6eSriastradh return;
1261677dec6eSriastradh
1262677dec6eSriastradh buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1263677dec6eSriastradh buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1264677dec6eSriastradh
1265677dec6eSriastradh buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1266677dec6eSriastradh buffer[count++] = cpu_to_le32(0x80000000);
1267677dec6eSriastradh buffer[count++] = cpu_to_le32(0x80000000);
1268677dec6eSriastradh
1269677dec6eSriastradh for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1270677dec6eSriastradh for (ext = sect->section; ext->extent != NULL; ++ext) {
1271677dec6eSriastradh if (sect->id == SECT_CONTEXT) {
1272677dec6eSriastradh buffer[count++] =
1273677dec6eSriastradh cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1274677dec6eSriastradh buffer[count++] = cpu_to_le32(ext->reg_index -
1275677dec6eSriastradh PACKET3_SET_CONTEXT_REG_START);
1276677dec6eSriastradh for (i = 0; i < ext->reg_count; i++)
1277677dec6eSriastradh buffer[count++] = cpu_to_le32(ext->extent[i]);
1278677dec6eSriastradh } else {
1279677dec6eSriastradh return;
1280677dec6eSriastradh }
1281677dec6eSriastradh }
1282677dec6eSriastradh }
1283677dec6eSriastradh
1284677dec6eSriastradh buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1285677dec6eSriastradh buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1286677dec6eSriastradh PACKET3_SET_CONTEXT_REG_START);
1287677dec6eSriastradh buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1288677dec6eSriastradh buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1289677dec6eSriastradh
1290677dec6eSriastradh buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1291677dec6eSriastradh buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1292677dec6eSriastradh
1293677dec6eSriastradh buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1294677dec6eSriastradh buffer[count++] = cpu_to_le32(0);
1295677dec6eSriastradh }
1296677dec6eSriastradh
gfx_v8_0_cp_jump_table_num(struct amdgpu_device * adev)1297677dec6eSriastradh static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)
1298677dec6eSriastradh {
1299677dec6eSriastradh if (adev->asic_type == CHIP_CARRIZO)
1300677dec6eSriastradh return 5;
1301677dec6eSriastradh else
1302677dec6eSriastradh return 4;
1303677dec6eSriastradh }
1304677dec6eSriastradh
gfx_v8_0_rlc_init(struct amdgpu_device * adev)1305677dec6eSriastradh static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1306677dec6eSriastradh {
1307677dec6eSriastradh const struct cs_section_def *cs_data;
1308a30d5d3aSriastradh int r;
1309a30d5d3aSriastradh
1310677dec6eSriastradh adev->gfx.rlc.cs_data = vi_cs_data;
1311a30d5d3aSriastradh
1312677dec6eSriastradh cs_data = adev->gfx.rlc.cs_data;
1313677dec6eSriastradh
1314677dec6eSriastradh if (cs_data) {
1315677dec6eSriastradh /* init clear state block */
1316677dec6eSriastradh r = amdgpu_gfx_rlc_init_csb(adev);
1317677dec6eSriastradh if (r)
1318677dec6eSriastradh return r;
1319a30d5d3aSriastradh }
1320a30d5d3aSriastradh
1321677dec6eSriastradh if ((adev->asic_type == CHIP_CARRIZO) ||
1322677dec6eSriastradh (adev->asic_type == CHIP_STONEY)) {
1323677dec6eSriastradh adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1324677dec6eSriastradh r = amdgpu_gfx_rlc_init_cpt(adev);
1325677dec6eSriastradh if (r)
1326677dec6eSriastradh return r;
1327677dec6eSriastradh }
1328677dec6eSriastradh
1329677dec6eSriastradh return 0;
1330677dec6eSriastradh }
1331677dec6eSriastradh
gfx_v8_0_mec_fini(struct amdgpu_device * adev)1332677dec6eSriastradh static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1333677dec6eSriastradh {
1334677dec6eSriastradh amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1335677dec6eSriastradh }
1336a30d5d3aSriastradh
gfx_v8_0_mec_init(struct amdgpu_device * adev)1337a30d5d3aSriastradh static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1338a30d5d3aSriastradh {
1339a30d5d3aSriastradh int r;
1340a30d5d3aSriastradh u32 *hpd;
1341677dec6eSriastradh size_t mec_hpd_size;
1342a30d5d3aSriastradh
1343677dec6eSriastradh bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1344a30d5d3aSriastradh
1345677dec6eSriastradh /* take ownership of the relevant compute queues */
1346677dec6eSriastradh amdgpu_gfx_compute_queue_acquire(adev);
1347677dec6eSriastradh
1348677dec6eSriastradh mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1349677dec6eSriastradh
1350677dec6eSriastradh r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1351677dec6eSriastradh AMDGPU_GEM_DOMAIN_VRAM,
1352677dec6eSriastradh &adev->gfx.mec.hpd_eop_obj,
1353677dec6eSriastradh &adev->gfx.mec.hpd_eop_gpu_addr,
1354677dec6eSriastradh (void **)&hpd);
1355a30d5d3aSriastradh if (r) {
1356a30d5d3aSriastradh dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1357a30d5d3aSriastradh return r;
1358a30d5d3aSriastradh }
1359a30d5d3aSriastradh
1360677dec6eSriastradh memset(hpd, 0, mec_hpd_size);
1361a30d5d3aSriastradh
1362a30d5d3aSriastradh amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1363a30d5d3aSriastradh amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1364a30d5d3aSriastradh
1365a30d5d3aSriastradh return 0;
1366a30d5d3aSriastradh }
1367a30d5d3aSriastradh
1368677dec6eSriastradh static const u32 vgpr_init_compute_shader[] =
1369677dec6eSriastradh {
1370677dec6eSriastradh 0x7e000209, 0x7e020208,
1371677dec6eSriastradh 0x7e040207, 0x7e060206,
1372677dec6eSriastradh 0x7e080205, 0x7e0a0204,
1373677dec6eSriastradh 0x7e0c0203, 0x7e0e0202,
1374677dec6eSriastradh 0x7e100201, 0x7e120200,
1375677dec6eSriastradh 0x7e140209, 0x7e160208,
1376677dec6eSriastradh 0x7e180207, 0x7e1a0206,
1377677dec6eSriastradh 0x7e1c0205, 0x7e1e0204,
1378677dec6eSriastradh 0x7e200203, 0x7e220202,
1379677dec6eSriastradh 0x7e240201, 0x7e260200,
1380677dec6eSriastradh 0x7e280209, 0x7e2a0208,
1381677dec6eSriastradh 0x7e2c0207, 0x7e2e0206,
1382677dec6eSriastradh 0x7e300205, 0x7e320204,
1383677dec6eSriastradh 0x7e340203, 0x7e360202,
1384677dec6eSriastradh 0x7e380201, 0x7e3a0200,
1385677dec6eSriastradh 0x7e3c0209, 0x7e3e0208,
1386677dec6eSriastradh 0x7e400207, 0x7e420206,
1387677dec6eSriastradh 0x7e440205, 0x7e460204,
1388677dec6eSriastradh 0x7e480203, 0x7e4a0202,
1389677dec6eSriastradh 0x7e4c0201, 0x7e4e0200,
1390677dec6eSriastradh 0x7e500209, 0x7e520208,
1391677dec6eSriastradh 0x7e540207, 0x7e560206,
1392677dec6eSriastradh 0x7e580205, 0x7e5a0204,
1393677dec6eSriastradh 0x7e5c0203, 0x7e5e0202,
1394677dec6eSriastradh 0x7e600201, 0x7e620200,
1395677dec6eSriastradh 0x7e640209, 0x7e660208,
1396677dec6eSriastradh 0x7e680207, 0x7e6a0206,
1397677dec6eSriastradh 0x7e6c0205, 0x7e6e0204,
1398677dec6eSriastradh 0x7e700203, 0x7e720202,
1399677dec6eSriastradh 0x7e740201, 0x7e760200,
1400677dec6eSriastradh 0x7e780209, 0x7e7a0208,
1401677dec6eSriastradh 0x7e7c0207, 0x7e7e0206,
1402677dec6eSriastradh 0xbf8a0000, 0xbf810000,
1403677dec6eSriastradh };
1404677dec6eSriastradh
1405677dec6eSriastradh static const u32 sgpr_init_compute_shader[] =
1406677dec6eSriastradh {
1407677dec6eSriastradh 0xbe8a0100, 0xbe8c0102,
1408677dec6eSriastradh 0xbe8e0104, 0xbe900106,
1409677dec6eSriastradh 0xbe920108, 0xbe940100,
1410677dec6eSriastradh 0xbe960102, 0xbe980104,
1411677dec6eSriastradh 0xbe9a0106, 0xbe9c0108,
1412677dec6eSriastradh 0xbe9e0100, 0xbea00102,
1413677dec6eSriastradh 0xbea20104, 0xbea40106,
1414677dec6eSriastradh 0xbea60108, 0xbea80100,
1415677dec6eSriastradh 0xbeaa0102, 0xbeac0104,
1416677dec6eSriastradh 0xbeae0106, 0xbeb00108,
1417677dec6eSriastradh 0xbeb20100, 0xbeb40102,
1418677dec6eSriastradh 0xbeb60104, 0xbeb80106,
1419677dec6eSriastradh 0xbeba0108, 0xbebc0100,
1420677dec6eSriastradh 0xbebe0102, 0xbec00104,
1421677dec6eSriastradh 0xbec20106, 0xbec40108,
1422677dec6eSriastradh 0xbec60100, 0xbec80102,
1423677dec6eSriastradh 0xbee60004, 0xbee70005,
1424677dec6eSriastradh 0xbeea0006, 0xbeeb0007,
1425677dec6eSriastradh 0xbee80008, 0xbee90009,
1426677dec6eSriastradh 0xbefc0000, 0xbf8a0000,
1427677dec6eSriastradh 0xbf810000, 0x00000000,
1428677dec6eSriastradh };
1429677dec6eSriastradh
1430677dec6eSriastradh static const u32 vgpr_init_regs[] =
1431677dec6eSriastradh {
1432677dec6eSriastradh mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1433677dec6eSriastradh mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1434677dec6eSriastradh mmCOMPUTE_NUM_THREAD_X, 256*4,
1435677dec6eSriastradh mmCOMPUTE_NUM_THREAD_Y, 1,
1436677dec6eSriastradh mmCOMPUTE_NUM_THREAD_Z, 1,
1437677dec6eSriastradh mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1438677dec6eSriastradh mmCOMPUTE_PGM_RSRC2, 20,
1439677dec6eSriastradh mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1440677dec6eSriastradh mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1441677dec6eSriastradh mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1442677dec6eSriastradh mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1443677dec6eSriastradh mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1444677dec6eSriastradh mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1445677dec6eSriastradh mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1446677dec6eSriastradh mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1447677dec6eSriastradh mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1448677dec6eSriastradh mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1449677dec6eSriastradh };
1450677dec6eSriastradh
1451677dec6eSriastradh static const u32 sgpr1_init_regs[] =
1452677dec6eSriastradh {
1453677dec6eSriastradh mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1454677dec6eSriastradh mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1455677dec6eSriastradh mmCOMPUTE_NUM_THREAD_X, 256*5,
1456677dec6eSriastradh mmCOMPUTE_NUM_THREAD_Y, 1,
1457677dec6eSriastradh mmCOMPUTE_NUM_THREAD_Z, 1,
1458677dec6eSriastradh mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1459677dec6eSriastradh mmCOMPUTE_PGM_RSRC2, 20,
1460677dec6eSriastradh mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1461677dec6eSriastradh mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1462677dec6eSriastradh mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1463677dec6eSriastradh mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1464677dec6eSriastradh mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1465677dec6eSriastradh mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1466677dec6eSriastradh mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1467677dec6eSriastradh mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1468677dec6eSriastradh mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1469677dec6eSriastradh mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1470677dec6eSriastradh };
1471677dec6eSriastradh
1472677dec6eSriastradh static const u32 sgpr2_init_regs[] =
1473677dec6eSriastradh {
1474677dec6eSriastradh mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1475677dec6eSriastradh mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1476677dec6eSriastradh mmCOMPUTE_NUM_THREAD_X, 256*5,
1477677dec6eSriastradh mmCOMPUTE_NUM_THREAD_Y, 1,
1478677dec6eSriastradh mmCOMPUTE_NUM_THREAD_Z, 1,
1479677dec6eSriastradh mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1480677dec6eSriastradh mmCOMPUTE_PGM_RSRC2, 20,
1481677dec6eSriastradh mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1482677dec6eSriastradh mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1483677dec6eSriastradh mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1484677dec6eSriastradh mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1485677dec6eSriastradh mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1486677dec6eSriastradh mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1487677dec6eSriastradh mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1488677dec6eSriastradh mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1489677dec6eSriastradh mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1490677dec6eSriastradh mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1491677dec6eSriastradh };
1492677dec6eSriastradh
1493677dec6eSriastradh static const u32 sec_ded_counter_registers[] =
1494677dec6eSriastradh {
1495677dec6eSriastradh mmCPC_EDC_ATC_CNT,
1496677dec6eSriastradh mmCPC_EDC_SCRATCH_CNT,
1497677dec6eSriastradh mmCPC_EDC_UCODE_CNT,
1498677dec6eSriastradh mmCPF_EDC_ATC_CNT,
1499677dec6eSriastradh mmCPF_EDC_ROQ_CNT,
1500677dec6eSriastradh mmCPF_EDC_TAG_CNT,
1501677dec6eSriastradh mmCPG_EDC_ATC_CNT,
1502677dec6eSriastradh mmCPG_EDC_DMA_CNT,
1503677dec6eSriastradh mmCPG_EDC_TAG_CNT,
1504677dec6eSriastradh mmDC_EDC_CSINVOC_CNT,
1505677dec6eSriastradh mmDC_EDC_RESTORE_CNT,
1506677dec6eSriastradh mmDC_EDC_STATE_CNT,
1507677dec6eSriastradh mmGDS_EDC_CNT,
1508677dec6eSriastradh mmGDS_EDC_GRBM_CNT,
1509677dec6eSriastradh mmGDS_EDC_OA_DED,
1510677dec6eSriastradh mmSPI_EDC_CNT,
1511677dec6eSriastradh mmSQC_ATC_EDC_GATCL1_CNT,
1512677dec6eSriastradh mmSQC_EDC_CNT,
1513677dec6eSriastradh mmSQ_EDC_DED_CNT,
1514677dec6eSriastradh mmSQ_EDC_INFO,
1515677dec6eSriastradh mmSQ_EDC_SEC_CNT,
1516677dec6eSriastradh mmTCC_EDC_CNT,
1517677dec6eSriastradh mmTCP_ATC_EDC_GATCL1_CNT,
1518677dec6eSriastradh mmTCP_EDC_CNT,
1519677dec6eSriastradh mmTD_EDC_CNT
1520677dec6eSriastradh };
1521677dec6eSriastradh
gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device * adev)1522677dec6eSriastradh static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1523677dec6eSriastradh {
1524677dec6eSriastradh struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1525677dec6eSriastradh struct amdgpu_ib ib;
1526677dec6eSriastradh struct dma_fence *f = NULL;
1527677dec6eSriastradh int r, i;
1528677dec6eSriastradh u32 tmp;
1529677dec6eSriastradh unsigned total_size, vgpr_offset, sgpr_offset;
1530677dec6eSriastradh u64 gpu_addr;
1531677dec6eSriastradh
1532677dec6eSriastradh /* only supported on CZ */
1533677dec6eSriastradh if (adev->asic_type != CHIP_CARRIZO)
1534677dec6eSriastradh return 0;
1535677dec6eSriastradh
1536677dec6eSriastradh /* bail if the compute ring is not ready */
1537677dec6eSriastradh if (!ring->sched.ready)
1538677dec6eSriastradh return 0;
1539677dec6eSriastradh
1540677dec6eSriastradh tmp = RREG32(mmGB_EDC_MODE);
1541677dec6eSriastradh WREG32(mmGB_EDC_MODE, 0);
1542677dec6eSriastradh
1543677dec6eSriastradh total_size =
1544677dec6eSriastradh (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1545677dec6eSriastradh total_size +=
1546677dec6eSriastradh (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1547677dec6eSriastradh total_size +=
1548677dec6eSriastradh (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1549677dec6eSriastradh total_size = ALIGN(total_size, 256);
1550677dec6eSriastradh vgpr_offset = total_size;
1551677dec6eSriastradh total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1552677dec6eSriastradh sgpr_offset = total_size;
1553677dec6eSriastradh total_size += sizeof(sgpr_init_compute_shader);
1554677dec6eSriastradh
1555677dec6eSriastradh /* allocate an indirect buffer to put the commands in */
1556677dec6eSriastradh memset(&ib, 0, sizeof(ib));
1557677dec6eSriastradh r = amdgpu_ib_get(adev, NULL, total_size, &ib);
1558677dec6eSriastradh if (r) {
1559677dec6eSriastradh DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1560677dec6eSriastradh return r;
1561677dec6eSriastradh }
1562677dec6eSriastradh
1563677dec6eSriastradh /* load the compute shaders */
1564677dec6eSriastradh for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1565677dec6eSriastradh ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1566677dec6eSriastradh
1567677dec6eSriastradh for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1568677dec6eSriastradh ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1569677dec6eSriastradh
1570677dec6eSriastradh /* init the ib length to 0 */
1571677dec6eSriastradh ib.length_dw = 0;
1572677dec6eSriastradh
1573677dec6eSriastradh /* VGPR */
1574677dec6eSriastradh /* write the register state for the compute dispatch */
1575677dec6eSriastradh for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1576677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1577677dec6eSriastradh ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1578677dec6eSriastradh ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1579677dec6eSriastradh }
1580677dec6eSriastradh /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1581677dec6eSriastradh gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1582677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1583677dec6eSriastradh ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1584677dec6eSriastradh ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1585677dec6eSriastradh ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1586677dec6eSriastradh
1587677dec6eSriastradh /* write dispatch packet */
1588677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1589677dec6eSriastradh ib.ptr[ib.length_dw++] = 8; /* x */
1590677dec6eSriastradh ib.ptr[ib.length_dw++] = 1; /* y */
1591677dec6eSriastradh ib.ptr[ib.length_dw++] = 1; /* z */
1592677dec6eSriastradh ib.ptr[ib.length_dw++] =
1593677dec6eSriastradh REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1594677dec6eSriastradh
1595677dec6eSriastradh /* write CS partial flush packet */
1596677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1597677dec6eSriastradh ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1598677dec6eSriastradh
1599677dec6eSriastradh /* SGPR1 */
1600677dec6eSriastradh /* write the register state for the compute dispatch */
1601677dec6eSriastradh for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1602677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1603677dec6eSriastradh ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1604677dec6eSriastradh ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1605677dec6eSriastradh }
1606677dec6eSriastradh /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1607677dec6eSriastradh gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1608677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1609677dec6eSriastradh ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1610677dec6eSriastradh ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1611677dec6eSriastradh ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1612677dec6eSriastradh
1613677dec6eSriastradh /* write dispatch packet */
1614677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1615677dec6eSriastradh ib.ptr[ib.length_dw++] = 8; /* x */
1616677dec6eSriastradh ib.ptr[ib.length_dw++] = 1; /* y */
1617677dec6eSriastradh ib.ptr[ib.length_dw++] = 1; /* z */
1618677dec6eSriastradh ib.ptr[ib.length_dw++] =
1619677dec6eSriastradh REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1620677dec6eSriastradh
1621677dec6eSriastradh /* write CS partial flush packet */
1622677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1623677dec6eSriastradh ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1624677dec6eSriastradh
1625677dec6eSriastradh /* SGPR2 */
1626677dec6eSriastradh /* write the register state for the compute dispatch */
1627677dec6eSriastradh for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1628677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1629677dec6eSriastradh ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1630677dec6eSriastradh ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1631677dec6eSriastradh }
1632677dec6eSriastradh /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1633677dec6eSriastradh gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1634677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1635677dec6eSriastradh ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1636677dec6eSriastradh ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1637677dec6eSriastradh ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1638677dec6eSriastradh
1639677dec6eSriastradh /* write dispatch packet */
1640677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1641677dec6eSriastradh ib.ptr[ib.length_dw++] = 8; /* x */
1642677dec6eSriastradh ib.ptr[ib.length_dw++] = 1; /* y */
1643677dec6eSriastradh ib.ptr[ib.length_dw++] = 1; /* z */
1644677dec6eSriastradh ib.ptr[ib.length_dw++] =
1645677dec6eSriastradh REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1646677dec6eSriastradh
1647677dec6eSriastradh /* write CS partial flush packet */
1648677dec6eSriastradh ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1649677dec6eSriastradh ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1650677dec6eSriastradh
1651677dec6eSriastradh /* shedule the ib on the ring */
1652677dec6eSriastradh r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1653677dec6eSriastradh if (r) {
1654677dec6eSriastradh DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1655677dec6eSriastradh goto fail;
1656677dec6eSriastradh }
1657677dec6eSriastradh
1658677dec6eSriastradh /* wait for the GPU to finish processing the IB */
1659677dec6eSriastradh r = dma_fence_wait(f, false);
1660677dec6eSriastradh if (r) {
1661677dec6eSriastradh DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1662677dec6eSriastradh goto fail;
1663677dec6eSriastradh }
1664677dec6eSriastradh
1665677dec6eSriastradh tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1666677dec6eSriastradh tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1667677dec6eSriastradh WREG32(mmGB_EDC_MODE, tmp);
1668677dec6eSriastradh
1669677dec6eSriastradh tmp = RREG32(mmCC_GC_EDC_CONFIG);
1670677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1671677dec6eSriastradh WREG32(mmCC_GC_EDC_CONFIG, tmp);
1672677dec6eSriastradh
1673677dec6eSriastradh
1674677dec6eSriastradh /* read back registers to clear the counters */
1675677dec6eSriastradh for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1676677dec6eSriastradh RREG32(sec_ded_counter_registers[i]);
1677677dec6eSriastradh
1678677dec6eSriastradh fail:
1679677dec6eSriastradh amdgpu_ib_free(adev, &ib, NULL);
1680677dec6eSriastradh dma_fence_put(f);
1681677dec6eSriastradh
1682677dec6eSriastradh return r;
1683677dec6eSriastradh }
1684677dec6eSriastradh
gfx_v8_0_gpu_early_init(struct amdgpu_device * adev)1685677dec6eSriastradh static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1686a30d5d3aSriastradh {
1687a30d5d3aSriastradh u32 gb_addr_config;
1688677dec6eSriastradh u32 mc_arb_ramcfg;
1689a30d5d3aSriastradh u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1690a30d5d3aSriastradh u32 tmp;
1691677dec6eSriastradh int ret;
1692a30d5d3aSriastradh
1693a30d5d3aSriastradh switch (adev->asic_type) {
1694a30d5d3aSriastradh case CHIP_TOPAZ:
1695a30d5d3aSriastradh adev->gfx.config.max_shader_engines = 1;
1696a30d5d3aSriastradh adev->gfx.config.max_tile_pipes = 2;
1697a30d5d3aSriastradh adev->gfx.config.max_cu_per_sh = 6;
1698a30d5d3aSriastradh adev->gfx.config.max_sh_per_se = 1;
1699a30d5d3aSriastradh adev->gfx.config.max_backends_per_se = 2;
1700a30d5d3aSriastradh adev->gfx.config.max_texture_channel_caches = 2;
1701a30d5d3aSriastradh adev->gfx.config.max_gprs = 256;
1702a30d5d3aSriastradh adev->gfx.config.max_gs_threads = 32;
1703a30d5d3aSriastradh adev->gfx.config.max_hw_contexts = 8;
1704a30d5d3aSriastradh
1705a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1706a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1707a30d5d3aSriastradh adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1708a30d5d3aSriastradh adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1709a30d5d3aSriastradh gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1710a30d5d3aSriastradh break;
1711a30d5d3aSriastradh case CHIP_FIJI:
1712a30d5d3aSriastradh adev->gfx.config.max_shader_engines = 4;
1713a30d5d3aSriastradh adev->gfx.config.max_tile_pipes = 16;
1714a30d5d3aSriastradh adev->gfx.config.max_cu_per_sh = 16;
1715a30d5d3aSriastradh adev->gfx.config.max_sh_per_se = 1;
1716a30d5d3aSriastradh adev->gfx.config.max_backends_per_se = 4;
1717a30d5d3aSriastradh adev->gfx.config.max_texture_channel_caches = 16;
1718a30d5d3aSriastradh adev->gfx.config.max_gprs = 256;
1719a30d5d3aSriastradh adev->gfx.config.max_gs_threads = 32;
1720a30d5d3aSriastradh adev->gfx.config.max_hw_contexts = 8;
1721a30d5d3aSriastradh
1722a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1723a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1724a30d5d3aSriastradh adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1725a30d5d3aSriastradh adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1726a30d5d3aSriastradh gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1727a30d5d3aSriastradh break;
1728677dec6eSriastradh case CHIP_POLARIS11:
1729677dec6eSriastradh case CHIP_POLARIS12:
1730677dec6eSriastradh ret = amdgpu_atombios_get_gfx_info(adev);
1731677dec6eSriastradh if (ret)
1732677dec6eSriastradh return ret;
1733677dec6eSriastradh adev->gfx.config.max_gprs = 256;
1734677dec6eSriastradh adev->gfx.config.max_gs_threads = 32;
1735677dec6eSriastradh adev->gfx.config.max_hw_contexts = 8;
1736677dec6eSriastradh
1737677dec6eSriastradh adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1738677dec6eSriastradh adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1739677dec6eSriastradh adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1740677dec6eSriastradh adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1741677dec6eSriastradh gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1742677dec6eSriastradh break;
1743677dec6eSriastradh case CHIP_POLARIS10:
1744677dec6eSriastradh case CHIP_VEGAM:
1745677dec6eSriastradh ret = amdgpu_atombios_get_gfx_info(adev);
1746677dec6eSriastradh if (ret)
1747677dec6eSriastradh return ret;
1748677dec6eSriastradh adev->gfx.config.max_gprs = 256;
1749677dec6eSriastradh adev->gfx.config.max_gs_threads = 32;
1750677dec6eSriastradh adev->gfx.config.max_hw_contexts = 8;
1751677dec6eSriastradh
1752677dec6eSriastradh adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1753677dec6eSriastradh adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1754677dec6eSriastradh adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1755677dec6eSriastradh adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1756677dec6eSriastradh gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1757677dec6eSriastradh break;
1758a30d5d3aSriastradh case CHIP_TONGA:
1759a30d5d3aSriastradh adev->gfx.config.max_shader_engines = 4;
1760a30d5d3aSriastradh adev->gfx.config.max_tile_pipes = 8;
1761a30d5d3aSriastradh adev->gfx.config.max_cu_per_sh = 8;
1762a30d5d3aSriastradh adev->gfx.config.max_sh_per_se = 1;
1763a30d5d3aSriastradh adev->gfx.config.max_backends_per_se = 2;
1764a30d5d3aSriastradh adev->gfx.config.max_texture_channel_caches = 8;
1765a30d5d3aSriastradh adev->gfx.config.max_gprs = 256;
1766a30d5d3aSriastradh adev->gfx.config.max_gs_threads = 32;
1767a30d5d3aSriastradh adev->gfx.config.max_hw_contexts = 8;
1768a30d5d3aSriastradh
1769a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1770a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1771a30d5d3aSriastradh adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1772a30d5d3aSriastradh adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1773a30d5d3aSriastradh gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1774a30d5d3aSriastradh break;
1775a30d5d3aSriastradh case CHIP_CARRIZO:
1776a30d5d3aSriastradh adev->gfx.config.max_shader_engines = 1;
1777a30d5d3aSriastradh adev->gfx.config.max_tile_pipes = 2;
1778a30d5d3aSriastradh adev->gfx.config.max_sh_per_se = 1;
1779a30d5d3aSriastradh adev->gfx.config.max_backends_per_se = 2;
1780a30d5d3aSriastradh adev->gfx.config.max_cu_per_sh = 8;
1781a30d5d3aSriastradh adev->gfx.config.max_texture_channel_caches = 2;
1782a30d5d3aSriastradh adev->gfx.config.max_gprs = 256;
1783a30d5d3aSriastradh adev->gfx.config.max_gs_threads = 32;
1784a30d5d3aSriastradh adev->gfx.config.max_hw_contexts = 8;
1785a30d5d3aSriastradh
1786a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1787a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1788a30d5d3aSriastradh adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1789a30d5d3aSriastradh adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1790a30d5d3aSriastradh gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1791a30d5d3aSriastradh break;
1792a30d5d3aSriastradh case CHIP_STONEY:
1793a30d5d3aSriastradh adev->gfx.config.max_shader_engines = 1;
1794a30d5d3aSriastradh adev->gfx.config.max_tile_pipes = 2;
1795a30d5d3aSriastradh adev->gfx.config.max_sh_per_se = 1;
1796a30d5d3aSriastradh adev->gfx.config.max_backends_per_se = 1;
1797a30d5d3aSriastradh adev->gfx.config.max_cu_per_sh = 3;
1798a30d5d3aSriastradh adev->gfx.config.max_texture_channel_caches = 2;
1799a30d5d3aSriastradh adev->gfx.config.max_gprs = 256;
1800a30d5d3aSriastradh adev->gfx.config.max_gs_threads = 16;
1801a30d5d3aSriastradh adev->gfx.config.max_hw_contexts = 8;
1802a30d5d3aSriastradh
1803a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1804a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1805a30d5d3aSriastradh adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1806a30d5d3aSriastradh adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1807a30d5d3aSriastradh gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1808a30d5d3aSriastradh break;
1809a30d5d3aSriastradh default:
1810a30d5d3aSriastradh adev->gfx.config.max_shader_engines = 2;
1811a30d5d3aSriastradh adev->gfx.config.max_tile_pipes = 4;
1812a30d5d3aSriastradh adev->gfx.config.max_cu_per_sh = 2;
1813a30d5d3aSriastradh adev->gfx.config.max_sh_per_se = 1;
1814a30d5d3aSriastradh adev->gfx.config.max_backends_per_se = 2;
1815a30d5d3aSriastradh adev->gfx.config.max_texture_channel_caches = 4;
1816a30d5d3aSriastradh adev->gfx.config.max_gprs = 256;
1817a30d5d3aSriastradh adev->gfx.config.max_gs_threads = 32;
1818a30d5d3aSriastradh adev->gfx.config.max_hw_contexts = 8;
1819a30d5d3aSriastradh
1820a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1821a30d5d3aSriastradh adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1822a30d5d3aSriastradh adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1823a30d5d3aSriastradh adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1824a30d5d3aSriastradh gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1825a30d5d3aSriastradh break;
1826a30d5d3aSriastradh }
1827a30d5d3aSriastradh
1828a30d5d3aSriastradh adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1829a30d5d3aSriastradh mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1830a30d5d3aSriastradh
1831a30d5d3aSriastradh adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1832a30d5d3aSriastradh adev->gfx.config.mem_max_burst_length_bytes = 256;
1833a30d5d3aSriastradh if (adev->flags & AMD_IS_APU) {
1834a30d5d3aSriastradh /* Get memory bank mapping mode. */
1835a30d5d3aSriastradh tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1836a30d5d3aSriastradh dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1837a30d5d3aSriastradh dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1838a30d5d3aSriastradh
1839a30d5d3aSriastradh tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1840a30d5d3aSriastradh dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1841a30d5d3aSriastradh dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1842a30d5d3aSriastradh
1843a30d5d3aSriastradh /* Validate settings in case only one DIMM installed. */
1844a30d5d3aSriastradh if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1845a30d5d3aSriastradh dimm00_addr_map = 0;
1846a30d5d3aSriastradh if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1847a30d5d3aSriastradh dimm01_addr_map = 0;
1848a30d5d3aSriastradh if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1849a30d5d3aSriastradh dimm10_addr_map = 0;
1850a30d5d3aSriastradh if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1851a30d5d3aSriastradh dimm11_addr_map = 0;
1852a30d5d3aSriastradh
1853a30d5d3aSriastradh /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1854a30d5d3aSriastradh /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1855a30d5d3aSriastradh if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1856a30d5d3aSriastradh adev->gfx.config.mem_row_size_in_kb = 2;
1857a30d5d3aSriastradh else
1858a30d5d3aSriastradh adev->gfx.config.mem_row_size_in_kb = 1;
1859a30d5d3aSriastradh } else {
1860a30d5d3aSriastradh tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1861a30d5d3aSriastradh adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1862a30d5d3aSriastradh if (adev->gfx.config.mem_row_size_in_kb > 4)
1863a30d5d3aSriastradh adev->gfx.config.mem_row_size_in_kb = 4;
1864a30d5d3aSriastradh }
1865a30d5d3aSriastradh
1866a30d5d3aSriastradh adev->gfx.config.shader_engine_tile_size = 32;
1867a30d5d3aSriastradh adev->gfx.config.num_gpus = 1;
1868a30d5d3aSriastradh adev->gfx.config.multi_gpu_tile_size = 64;
1869a30d5d3aSriastradh
1870a30d5d3aSriastradh /* fix up row size */
1871a30d5d3aSriastradh switch (adev->gfx.config.mem_row_size_in_kb) {
1872a30d5d3aSriastradh case 1:
1873a30d5d3aSriastradh default:
1874a30d5d3aSriastradh gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1875a30d5d3aSriastradh break;
1876a30d5d3aSriastradh case 2:
1877a30d5d3aSriastradh gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1878a30d5d3aSriastradh break;
1879a30d5d3aSriastradh case 4:
1880a30d5d3aSriastradh gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1881a30d5d3aSriastradh break;
1882a30d5d3aSriastradh }
1883a30d5d3aSriastradh adev->gfx.config.gb_addr_config = gb_addr_config;
1884677dec6eSriastradh
1885677dec6eSriastradh return 0;
1886a30d5d3aSriastradh }
1887a30d5d3aSriastradh
gfx_v8_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)1888677dec6eSriastradh static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1889677dec6eSriastradh int mec, int pipe, int queue)
1890677dec6eSriastradh {
1891677dec6eSriastradh int r;
1892677dec6eSriastradh unsigned irq_type;
1893677dec6eSriastradh struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1894677dec6eSriastradh
1895677dec6eSriastradh ring = &adev->gfx.compute_ring[ring_id];
1896677dec6eSriastradh
1897677dec6eSriastradh /* mec0 is me1 */
1898677dec6eSriastradh ring->me = mec + 1;
1899677dec6eSriastradh ring->pipe = pipe;
1900677dec6eSriastradh ring->queue = queue;
1901677dec6eSriastradh
1902677dec6eSriastradh ring->ring_obj = NULL;
1903677dec6eSriastradh ring->use_doorbell = true;
1904677dec6eSriastradh ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
1905677dec6eSriastradh ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1906677dec6eSriastradh + (ring_id * GFX8_MEC_HPD_SIZE);
1907677dec6eSriastradh snprintf(ring->name, sizeof ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1908677dec6eSriastradh
1909677dec6eSriastradh irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1910677dec6eSriastradh + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1911677dec6eSriastradh + ring->pipe;
1912677dec6eSriastradh
1913677dec6eSriastradh /* type-2 packets are deprecated on MEC, use type-3 instead */
1914677dec6eSriastradh r = amdgpu_ring_init(adev, ring, 1024,
1915677dec6eSriastradh &adev->gfx.eop_irq, irq_type);
1916677dec6eSriastradh if (r)
1917677dec6eSriastradh return r;
1918677dec6eSriastradh
1919677dec6eSriastradh
1920677dec6eSriastradh return 0;
1921677dec6eSriastradh }
1922677dec6eSriastradh
1923677dec6eSriastradh static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
1924677dec6eSriastradh
gfx_v8_0_sw_init(void * handle)1925a30d5d3aSriastradh static int gfx_v8_0_sw_init(void *handle)
1926a30d5d3aSriastradh {
1927677dec6eSriastradh int i, j, k, r, ring_id;
1928a30d5d3aSriastradh struct amdgpu_ring *ring;
1929677dec6eSriastradh struct amdgpu_kiq *kiq;
1930a30d5d3aSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1931a30d5d3aSriastradh
1932677dec6eSriastradh switch (adev->asic_type) {
1933677dec6eSriastradh case CHIP_TONGA:
1934677dec6eSriastradh case CHIP_CARRIZO:
1935677dec6eSriastradh case CHIP_FIJI:
1936677dec6eSriastradh case CHIP_POLARIS10:
1937677dec6eSriastradh case CHIP_POLARIS11:
1938677dec6eSriastradh case CHIP_POLARIS12:
1939677dec6eSriastradh case CHIP_VEGAM:
1940677dec6eSriastradh adev->gfx.mec.num_mec = 2;
1941677dec6eSriastradh break;
1942677dec6eSriastradh case CHIP_TOPAZ:
1943677dec6eSriastradh case CHIP_STONEY:
1944677dec6eSriastradh default:
1945677dec6eSriastradh adev->gfx.mec.num_mec = 1;
1946677dec6eSriastradh break;
1947677dec6eSriastradh }
1948677dec6eSriastradh
1949677dec6eSriastradh adev->gfx.mec.num_pipe_per_mec = 4;
1950677dec6eSriastradh adev->gfx.mec.num_queue_per_pipe = 8;
1951677dec6eSriastradh
1952a30d5d3aSriastradh /* EOP Event */
1953677dec6eSriastradh r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
1954a30d5d3aSriastradh if (r)
1955a30d5d3aSriastradh return r;
1956a30d5d3aSriastradh
1957a30d5d3aSriastradh /* Privileged reg */
1958677dec6eSriastradh r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
1959677dec6eSriastradh &adev->gfx.priv_reg_irq);
1960a30d5d3aSriastradh if (r)
1961a30d5d3aSriastradh return r;
1962a30d5d3aSriastradh
1963a30d5d3aSriastradh /* Privileged inst */
1964677dec6eSriastradh r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
1965677dec6eSriastradh &adev->gfx.priv_inst_irq);
1966a30d5d3aSriastradh if (r)
1967a30d5d3aSriastradh return r;
1968a30d5d3aSriastradh
1969677dec6eSriastradh /* Add CP EDC/ECC irq */
1970677dec6eSriastradh r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
1971677dec6eSriastradh &adev->gfx.cp_ecc_error_irq);
1972677dec6eSriastradh if (r)
1973677dec6eSriastradh return r;
1974677dec6eSriastradh
1975677dec6eSriastradh /* SQ interrupts. */
1976677dec6eSriastradh r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
1977677dec6eSriastradh &adev->gfx.sq_irq);
1978677dec6eSriastradh if (r) {
1979677dec6eSriastradh DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
1980677dec6eSriastradh return r;
1981677dec6eSriastradh }
1982677dec6eSriastradh
1983677dec6eSriastradh INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
1984677dec6eSriastradh
1985a30d5d3aSriastradh adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1986a30d5d3aSriastradh
1987a30d5d3aSriastradh gfx_v8_0_scratch_init(adev);
1988a30d5d3aSriastradh
1989a30d5d3aSriastradh r = gfx_v8_0_init_microcode(adev);
1990a30d5d3aSriastradh if (r) {
1991a30d5d3aSriastradh DRM_ERROR("Failed to load gfx firmware!\n");
1992a30d5d3aSriastradh return r;
1993a30d5d3aSriastradh }
1994a30d5d3aSriastradh
1995677dec6eSriastradh r = adev->gfx.rlc.funcs->init(adev);
1996677dec6eSriastradh if (r) {
1997677dec6eSriastradh DRM_ERROR("Failed to init rlc BOs!\n");
1998677dec6eSriastradh return r;
1999677dec6eSriastradh }
2000677dec6eSriastradh
2001a30d5d3aSriastradh r = gfx_v8_0_mec_init(adev);
2002a30d5d3aSriastradh if (r) {
2003a30d5d3aSriastradh DRM_ERROR("Failed to init MEC BOs!\n");
2004a30d5d3aSriastradh return r;
2005a30d5d3aSriastradh }
2006a30d5d3aSriastradh
2007a30d5d3aSriastradh /* set up the gfx ring */
2008a30d5d3aSriastradh for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2009a30d5d3aSriastradh ring = &adev->gfx.gfx_ring[i];
2010a30d5d3aSriastradh ring->ring_obj = NULL;
2011a30d5d3aSriastradh snprintf(ring->name, sizeof ring->name, "gfx");
2012a30d5d3aSriastradh /* no gfx doorbells on iceland */
2013a30d5d3aSriastradh if (adev->asic_type != CHIP_TOPAZ) {
2014a30d5d3aSriastradh ring->use_doorbell = true;
2015677dec6eSriastradh ring->doorbell_index = adev->doorbell_index.gfx_ring0;
2016a30d5d3aSriastradh }
2017a30d5d3aSriastradh
2018677dec6eSriastradh r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2019677dec6eSriastradh AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
2020a30d5d3aSriastradh if (r)
2021a30d5d3aSriastradh return r;
2022a30d5d3aSriastradh }
2023a30d5d3aSriastradh
2024a30d5d3aSriastradh
2025677dec6eSriastradh /* set up the compute queues - allocate horizontally across pipes */
2026677dec6eSriastradh ring_id = 0;
2027677dec6eSriastradh for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2028677dec6eSriastradh for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2029677dec6eSriastradh for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2030677dec6eSriastradh if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2031677dec6eSriastradh continue;
2032677dec6eSriastradh
2033677dec6eSriastradh r = gfx_v8_0_compute_ring_init(adev,
2034677dec6eSriastradh ring_id,
2035677dec6eSriastradh i, k, j);
2036a30d5d3aSriastradh if (r)
2037a30d5d3aSriastradh return r;
2038677dec6eSriastradh
2039677dec6eSriastradh ring_id++;
2040677dec6eSriastradh }
2041677dec6eSriastradh }
2042677dec6eSriastradh }
2043677dec6eSriastradh
2044677dec6eSriastradh r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE);
2045677dec6eSriastradh if (r) {
2046677dec6eSriastradh DRM_ERROR("Failed to init KIQ BOs!\n");
2047677dec6eSriastradh return r;
2048a30d5d3aSriastradh }
2049a30d5d3aSriastradh
2050677dec6eSriastradh kiq = &adev->gfx.kiq;
2051677dec6eSriastradh r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2052a30d5d3aSriastradh if (r)
2053a30d5d3aSriastradh return r;
2054a30d5d3aSriastradh
2055677dec6eSriastradh /* create MQD for all compute queues as well as KIQ for SRIOV case */
2056677dec6eSriastradh r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
2057a30d5d3aSriastradh if (r)
2058a30d5d3aSriastradh return r;
2059a30d5d3aSriastradh
2060a30d5d3aSriastradh adev->gfx.ce_ram_size = 0x8000;
2061a30d5d3aSriastradh
2062677dec6eSriastradh r = gfx_v8_0_gpu_early_init(adev);
2063677dec6eSriastradh if (r)
2064677dec6eSriastradh return r;
2065a30d5d3aSriastradh
2066a30d5d3aSriastradh return 0;
2067a30d5d3aSriastradh }
2068a30d5d3aSriastradh
gfx_v8_0_sw_fini(void * handle)2069a30d5d3aSriastradh static int gfx_v8_0_sw_fini(void *handle)
2070a30d5d3aSriastradh {
2071a30d5d3aSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2072677dec6eSriastradh int i;
2073a30d5d3aSriastradh
2074a30d5d3aSriastradh for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2075a30d5d3aSriastradh amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2076a30d5d3aSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++)
2077a30d5d3aSriastradh amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2078a30d5d3aSriastradh
2079677dec6eSriastradh amdgpu_gfx_mqd_sw_fini(adev);
2080677dec6eSriastradh amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
2081677dec6eSriastradh amdgpu_gfx_kiq_fini(adev);
2082677dec6eSriastradh
2083a30d5d3aSriastradh gfx_v8_0_mec_fini(adev);
2084677dec6eSriastradh amdgpu_gfx_rlc_fini(adev);
2085677dec6eSriastradh amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2086677dec6eSriastradh &adev->gfx.rlc.clear_state_gpu_addr,
2087*b45c3ff5Sriastradh (void **)__UNVOLATILE(&adev->gfx.rlc.cs_ptr));
2088677dec6eSriastradh if ((adev->asic_type == CHIP_CARRIZO) ||
2089677dec6eSriastradh (adev->asic_type == CHIP_STONEY)) {
2090677dec6eSriastradh amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2091677dec6eSriastradh &adev->gfx.rlc.cp_table_gpu_addr,
2092*b45c3ff5Sriastradh (void **)__UNVOLATILE(&adev->gfx.rlc.cp_table_ptr));
2093677dec6eSriastradh }
2094677dec6eSriastradh gfx_v8_0_free_microcode(adev);
2095a30d5d3aSriastradh
2096a30d5d3aSriastradh return 0;
2097a30d5d3aSriastradh }
2098a30d5d3aSriastradh
gfx_v8_0_tiling_mode_table_init(struct amdgpu_device * adev)2099a30d5d3aSriastradh static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2100a30d5d3aSriastradh {
2101677dec6eSriastradh uint32_t *modearray, *mod2array;
2102677dec6eSriastradh const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2103677dec6eSriastradh const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2104677dec6eSriastradh u32 reg_offset;
2105a30d5d3aSriastradh
2106677dec6eSriastradh modearray = adev->gfx.config.tile_mode_array;
2107677dec6eSriastradh mod2array = adev->gfx.config.macrotile_mode_array;
2108677dec6eSriastradh
2109677dec6eSriastradh for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2110677dec6eSriastradh modearray[reg_offset] = 0;
2111677dec6eSriastradh
2112677dec6eSriastradh for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2113677dec6eSriastradh mod2array[reg_offset] = 0;
2114a30d5d3aSriastradh
2115a30d5d3aSriastradh switch (adev->asic_type) {
2116a30d5d3aSriastradh case CHIP_TOPAZ:
2117677dec6eSriastradh modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2118a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2119a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2120a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2121677dec6eSriastradh modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2122a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2123a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2124a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2125677dec6eSriastradh modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2126a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2127a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2128a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2129677dec6eSriastradh modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2130a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2131a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2132a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2133677dec6eSriastradh modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2134a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2135a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2136a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2137677dec6eSriastradh modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2138a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2139a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2140a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2141677dec6eSriastradh modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2142a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2143a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2144a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2145677dec6eSriastradh modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2146a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2));
2147677dec6eSriastradh modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2148a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2149a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2150a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2151677dec6eSriastradh modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2152a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2153a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2154a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2155677dec6eSriastradh modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2156a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2157a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2158a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2159677dec6eSriastradh modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2160a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2161a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2162a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2163677dec6eSriastradh modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2164a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2165a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2166a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2167677dec6eSriastradh modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2168a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2169a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2170a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2171677dec6eSriastradh modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2172a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2173a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2174a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2175677dec6eSriastradh modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2176a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2177a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2178a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2179677dec6eSriastradh modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2180a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2181a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2182a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2183677dec6eSriastradh modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2184a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2185a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2186a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2187677dec6eSriastradh modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2188a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2189a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2190a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2191677dec6eSriastradh modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2192a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2193a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2194a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2195677dec6eSriastradh modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2196a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2197a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2198a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2199677dec6eSriastradh modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2200a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2201a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2202a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2203677dec6eSriastradh modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2204a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2205a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2206a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2207677dec6eSriastradh modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2208a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2209a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2210a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2211677dec6eSriastradh modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2212a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2213a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2214a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2215677dec6eSriastradh modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2216a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
2217a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2218a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2219677dec6eSriastradh
2220677dec6eSriastradh mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2221a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2222a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2223a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2224677dec6eSriastradh mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2225a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2226a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2227a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2228677dec6eSriastradh mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2229a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2230a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2231a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2232677dec6eSriastradh mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2233a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2234a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2235a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2236677dec6eSriastradh mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2237a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2238a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2239a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2240677dec6eSriastradh mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2241a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2242a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2243a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2244677dec6eSriastradh mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2245a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2246a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2247a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2248677dec6eSriastradh mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2249a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2250a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2251a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2252677dec6eSriastradh mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2253a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2254a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2255a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2256677dec6eSriastradh mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2257a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2258a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2259a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2260677dec6eSriastradh mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2261a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2262a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2263a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2264677dec6eSriastradh mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2265a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2266a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2267a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2268677dec6eSriastradh mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2269a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2270a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2271a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2272677dec6eSriastradh mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2273a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2274a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2275a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2276677dec6eSriastradh
2277677dec6eSriastradh for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2278677dec6eSriastradh if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2279677dec6eSriastradh reg_offset != 23)
2280677dec6eSriastradh WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2281677dec6eSriastradh
2282677dec6eSriastradh for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2283677dec6eSriastradh if (reg_offset != 7)
2284677dec6eSriastradh WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2285677dec6eSriastradh
22867760eedaSkamil break;
2287a30d5d3aSriastradh case CHIP_FIJI:
2288677dec6eSriastradh case CHIP_VEGAM:
2289677dec6eSriastradh modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2290a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2291a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2292a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2293677dec6eSriastradh modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2294a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2295a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2296a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2297677dec6eSriastradh modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2298a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2299a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2300a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2301677dec6eSriastradh modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2302a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2303a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2304a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2305677dec6eSriastradh modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2306a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2307a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2308a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2309677dec6eSriastradh modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2310a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2311a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2312a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2313677dec6eSriastradh modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2314a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2315a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2316a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2317677dec6eSriastradh modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2318a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2319a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2320a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2321677dec6eSriastradh modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2322a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2323677dec6eSriastradh modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2324a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2325a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2326a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2327677dec6eSriastradh modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2328a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2329a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2330a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2331677dec6eSriastradh modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2332a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2333a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2334a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2335677dec6eSriastradh modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2336a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2337a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2338a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2339677dec6eSriastradh modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2340a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2341a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2342a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2343677dec6eSriastradh modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2344a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2345a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2346a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2347677dec6eSriastradh modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2348a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2349a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2350a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2351677dec6eSriastradh modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2352a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2353a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2354a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2355677dec6eSriastradh modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2356a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2357a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2358a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2359677dec6eSriastradh modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2360a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2361a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2362a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2363677dec6eSriastradh modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2364a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2365a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2366a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2367677dec6eSriastradh modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2368a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2369a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2370a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2371677dec6eSriastradh modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2372a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2373a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2374a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2375677dec6eSriastradh modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2376a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2377a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2378a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2379677dec6eSriastradh modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2380a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2381a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2382a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2383677dec6eSriastradh modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2384a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2385a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2386a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2387677dec6eSriastradh modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2388a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2389a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2390a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2391677dec6eSriastradh modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2392a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2393a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2394a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2395677dec6eSriastradh modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2396a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2397a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2398a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2399677dec6eSriastradh modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2400a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2401a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2402a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2403677dec6eSriastradh modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2404a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2405a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2406a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2407677dec6eSriastradh modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2408a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2409a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2410a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2411677dec6eSriastradh
2412677dec6eSriastradh mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2413a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2414a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2415a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2416677dec6eSriastradh mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2417a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2418a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2419a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2420677dec6eSriastradh mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2421a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2422a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2423a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2424677dec6eSriastradh mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2425a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2426a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2427a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2428677dec6eSriastradh mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2429a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2430a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2431a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2432677dec6eSriastradh mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2433a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2434a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2435a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2436677dec6eSriastradh mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2437a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2438a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2439a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2440677dec6eSriastradh mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2441a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2442a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2443a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2444677dec6eSriastradh mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2445a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2446a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2447a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2448677dec6eSriastradh mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2449a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2450a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2451a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2452677dec6eSriastradh mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2453a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2454a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2455a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2456677dec6eSriastradh mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2457a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2458a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2459a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2460677dec6eSriastradh mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2461a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2462a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2463a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2464677dec6eSriastradh mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2465a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2466a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2467a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_4_BANK));
2468677dec6eSriastradh
2469677dec6eSriastradh for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2470677dec6eSriastradh WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2471677dec6eSriastradh
2472677dec6eSriastradh for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2473677dec6eSriastradh if (reg_offset != 7)
2474677dec6eSriastradh WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2475677dec6eSriastradh
2476a30d5d3aSriastradh break;
2477a30d5d3aSriastradh case CHIP_TONGA:
2478677dec6eSriastradh modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2479a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2480a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2481a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2482677dec6eSriastradh modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2483a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2484a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2485a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2486677dec6eSriastradh modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2487a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2488a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2489a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2490677dec6eSriastradh modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2491a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2492a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2493a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2494677dec6eSriastradh modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2495a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2496a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2497a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2498677dec6eSriastradh modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2499a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2500a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2501a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2502677dec6eSriastradh modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2503a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2504a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2505a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2506677dec6eSriastradh modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2507a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2508a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2509a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2510677dec6eSriastradh modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2511a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2512677dec6eSriastradh modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2513a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2514a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2515a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2516677dec6eSriastradh modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2517a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2518a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2519a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2520677dec6eSriastradh modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2521a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2522a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2523a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2524677dec6eSriastradh modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2525a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2526a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2527a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2528677dec6eSriastradh modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2529a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2530a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2531a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2532677dec6eSriastradh modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2533a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2534a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2535a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2536677dec6eSriastradh modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2537a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2538a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2539a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2540677dec6eSriastradh modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2541a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2542a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2543a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2544677dec6eSriastradh modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2545a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2546a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2547a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2548677dec6eSriastradh modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2549a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2550a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2551a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2552677dec6eSriastradh modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2553a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2554a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2555a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2556677dec6eSriastradh modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2557a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2558a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2559a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2560677dec6eSriastradh modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2561a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2562a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2563a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2564677dec6eSriastradh modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2565a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2566a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2567a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2568677dec6eSriastradh modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2569a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2570a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2571a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2572677dec6eSriastradh modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2573a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2574a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2575a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2576677dec6eSriastradh modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2577a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2578a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2579a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2580677dec6eSriastradh modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2581a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2582a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2583a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2584677dec6eSriastradh modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2585a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2586a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2587a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2588677dec6eSriastradh modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2589a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2590a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2591a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2592677dec6eSriastradh modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2593a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2594a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2595a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2596677dec6eSriastradh modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2597a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2598a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2599a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2600677dec6eSriastradh
2601677dec6eSriastradh mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2602a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2603a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2604a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2605677dec6eSriastradh mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2606a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2607a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2608a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2609677dec6eSriastradh mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2610a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2611a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2612a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2613677dec6eSriastradh mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2614a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2615a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2616a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2617677dec6eSriastradh mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2618a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2619a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2620a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2621677dec6eSriastradh mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2622a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2623a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2624a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2625677dec6eSriastradh mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2626a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2627a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2628a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2629677dec6eSriastradh mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2630a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2631a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2632a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2633677dec6eSriastradh mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2634a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2635a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2636a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2637677dec6eSriastradh mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2638a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2639a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2640a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2641677dec6eSriastradh mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2642a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2643a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2644a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2645677dec6eSriastradh mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2646a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2647a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2648a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2649677dec6eSriastradh mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2650a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2651a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2652a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_4_BANK));
2653677dec6eSriastradh mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2654a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2655a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2656a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_4_BANK));
2657677dec6eSriastradh
2658677dec6eSriastradh for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2659677dec6eSriastradh WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2660677dec6eSriastradh
2661677dec6eSriastradh for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2662677dec6eSriastradh if (reg_offset != 7)
2663677dec6eSriastradh WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2664677dec6eSriastradh
2665a30d5d3aSriastradh break;
2666677dec6eSriastradh case CHIP_POLARIS11:
2667677dec6eSriastradh case CHIP_POLARIS12:
2668677dec6eSriastradh modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2669677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2670677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2671677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2672677dec6eSriastradh modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2673677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2674677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2675677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2676677dec6eSriastradh modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2677677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2678677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2679677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2680677dec6eSriastradh modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2681677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2682677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2683677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2684677dec6eSriastradh modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2685677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2686677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2687677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2688677dec6eSriastradh modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2689677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2690677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2691677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2692677dec6eSriastradh modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2693677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2694677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2695677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2696677dec6eSriastradh modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2697677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2698677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2699677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2700677dec6eSriastradh modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2701677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16));
2702677dec6eSriastradh modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2703677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2704677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2705677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2706677dec6eSriastradh modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2707677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2708677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2709677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2710677dec6eSriastradh modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2711677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2712677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2713677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2714677dec6eSriastradh modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2715677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2716677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2717677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2718677dec6eSriastradh modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2719677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2720677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2721677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2722677dec6eSriastradh modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2723677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2724677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2725677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2726677dec6eSriastradh modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2727677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2728677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2729677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2730677dec6eSriastradh modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2731677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2732677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2733677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2734677dec6eSriastradh modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2735677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2736677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2737677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2738677dec6eSriastradh modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2739677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2740677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2741677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2742677dec6eSriastradh modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2743677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2744677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2745677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2746677dec6eSriastradh modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2747677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2748677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2749677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2750677dec6eSriastradh modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2751677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2752677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2753677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2754677dec6eSriastradh modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2755677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2756677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2757677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2758677dec6eSriastradh modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2759677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2760677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2761677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2762677dec6eSriastradh modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2763677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2764677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2765677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2766677dec6eSriastradh modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2767677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2768677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2769677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2770677dec6eSriastradh modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2771677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2772677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2773677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2774677dec6eSriastradh modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2775677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2776677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2777677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2778677dec6eSriastradh modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2779677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2780677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2781677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2782677dec6eSriastradh modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2783677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2784677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2785677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2786677dec6eSriastradh modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2787677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2788677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2789677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2790677dec6eSriastradh
2791677dec6eSriastradh mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2792677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2793677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2794677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2795677dec6eSriastradh
2796677dec6eSriastradh mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2797677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2798677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2799677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2800677dec6eSriastradh
2801677dec6eSriastradh mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2802677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2803677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2804677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2805677dec6eSriastradh
2806677dec6eSriastradh mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2807677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2808677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2809677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2810677dec6eSriastradh
2811677dec6eSriastradh mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2812677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2813677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2814677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2815677dec6eSriastradh
2816677dec6eSriastradh mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2817677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2818677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2819677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2820677dec6eSriastradh
2821677dec6eSriastradh mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2822677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2823677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2824677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2825677dec6eSriastradh
2826677dec6eSriastradh mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2827677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2828677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2829677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2830677dec6eSriastradh
2831677dec6eSriastradh mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2832677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2833677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2834677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2835677dec6eSriastradh
2836677dec6eSriastradh mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2837677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2838677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2839677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2840677dec6eSriastradh
2841677dec6eSriastradh mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2842677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2843677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2844677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2845677dec6eSriastradh
2846677dec6eSriastradh mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2847677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2848677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2849677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2850677dec6eSriastradh
2851677dec6eSriastradh mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2852677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2853677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2854677dec6eSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
2855677dec6eSriastradh
2856677dec6eSriastradh mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2857677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2858677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2859677dec6eSriastradh NUM_BANKS(ADDR_SURF_4_BANK));
2860677dec6eSriastradh
2861677dec6eSriastradh for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2862677dec6eSriastradh WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2863677dec6eSriastradh
2864677dec6eSriastradh for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2865677dec6eSriastradh if (reg_offset != 7)
2866677dec6eSriastradh WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2867677dec6eSriastradh
2868a30d5d3aSriastradh break;
2869677dec6eSriastradh case CHIP_POLARIS10:
2870677dec6eSriastradh modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2871677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2872677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2873677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2874677dec6eSriastradh modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2875677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2876677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2877677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2878677dec6eSriastradh modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2879677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2880677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2881677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2882677dec6eSriastradh modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2883677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2884677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2885677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2886677dec6eSriastradh modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2887677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2888677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2889677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2890677dec6eSriastradh modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2891677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2892677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2893677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2894677dec6eSriastradh modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2895677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2896677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2897677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2898677dec6eSriastradh modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2899677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2900677dec6eSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2901677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2902677dec6eSriastradh modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2903677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2904677dec6eSriastradh modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2905677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2906677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2907677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2908677dec6eSriastradh modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2909677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2910677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2911677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2912677dec6eSriastradh modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2913677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2914677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2915677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2916677dec6eSriastradh modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2917677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2918677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2919677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2920677dec6eSriastradh modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2921677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2922677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2923677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2924677dec6eSriastradh modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2925677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2926677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2927677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2928677dec6eSriastradh modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2929677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2930677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2931677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2932677dec6eSriastradh modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2933677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2934677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2935677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2936677dec6eSriastradh modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2937677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2938677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2939677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2940677dec6eSriastradh modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2941677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2942677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2943677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2944677dec6eSriastradh modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2945677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2946677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2947677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2948677dec6eSriastradh modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2949677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2950677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2951677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2952677dec6eSriastradh modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2953677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2954677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2955677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2956677dec6eSriastradh modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2957677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2958677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2959677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2960677dec6eSriastradh modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2961677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2962677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2963677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2964677dec6eSriastradh modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2965677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2966677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2967677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2968677dec6eSriastradh modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2969677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2970677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2971677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2972677dec6eSriastradh modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2973677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2974677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2975677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2976677dec6eSriastradh modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2977677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2978677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2979677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2980677dec6eSriastradh modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2981677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2982677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2983677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2984677dec6eSriastradh modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2985677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2986677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2987677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2988677dec6eSriastradh modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2989677dec6eSriastradh PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2990677dec6eSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2991677dec6eSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2992677dec6eSriastradh
2993677dec6eSriastradh mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2994677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2995677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2996677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
2997677dec6eSriastradh
2998677dec6eSriastradh mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2999677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3000677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3001677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3002677dec6eSriastradh
3003677dec6eSriastradh mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3004677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3005677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3006677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3007677dec6eSriastradh
3008677dec6eSriastradh mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3009677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3010677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3011677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3012677dec6eSriastradh
3013677dec6eSriastradh mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3014677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3015677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3016677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3017677dec6eSriastradh
3018677dec6eSriastradh mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3019677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3020677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3021677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3022677dec6eSriastradh
3023677dec6eSriastradh mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3024677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3025677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3026677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3027677dec6eSriastradh
3028677dec6eSriastradh mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3029677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3030677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3031677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3032677dec6eSriastradh
3033677dec6eSriastradh mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3034677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3035677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3036677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3037677dec6eSriastradh
3038677dec6eSriastradh mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3039677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3040677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3041677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3042677dec6eSriastradh
3043677dec6eSriastradh mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3044677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3045677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3046677dec6eSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3047677dec6eSriastradh
3048677dec6eSriastradh mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3049677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3050677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3051677dec6eSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3052677dec6eSriastradh
3053677dec6eSriastradh mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3054677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3055677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3056677dec6eSriastradh NUM_BANKS(ADDR_SURF_4_BANK));
3057677dec6eSriastradh
3058677dec6eSriastradh mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3059677dec6eSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3060677dec6eSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3061677dec6eSriastradh NUM_BANKS(ADDR_SURF_4_BANK));
3062677dec6eSriastradh
3063677dec6eSriastradh for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3064677dec6eSriastradh WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3065677dec6eSriastradh
3066677dec6eSriastradh for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3067677dec6eSriastradh if (reg_offset != 7)
3068677dec6eSriastradh WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3069677dec6eSriastradh
3070a30d5d3aSriastradh break;
3071a30d5d3aSriastradh case CHIP_STONEY:
3072677dec6eSriastradh modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3073a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3074a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3075a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3076677dec6eSriastradh modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3077a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3078a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3079a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3080677dec6eSriastradh modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3081a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3082a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3083a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3084677dec6eSriastradh modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3085a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3086a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3087a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3088677dec6eSriastradh modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3089a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3090a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3091a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3092677dec6eSriastradh modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3093a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3094a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3095a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3096677dec6eSriastradh modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3097a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3098a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3099a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3100677dec6eSriastradh modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3101a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2));
3102677dec6eSriastradh modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3103a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3104a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3105a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3106677dec6eSriastradh modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3107a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3108a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3109a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3110677dec6eSriastradh modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3111a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3112a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3113a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3114677dec6eSriastradh modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3115a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3116a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3117a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3118677dec6eSriastradh modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3119a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3120a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3121a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3122677dec6eSriastradh modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3123a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3124a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3125a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3126677dec6eSriastradh modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3127a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3128a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3129a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3130677dec6eSriastradh modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3131a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3132a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3133a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3134677dec6eSriastradh modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3135a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3136a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3137a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3138677dec6eSriastradh modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3139a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3140a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3141a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3142677dec6eSriastradh modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3143a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3144a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3145a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3146677dec6eSriastradh modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3147a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3148a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3149a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3150677dec6eSriastradh modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3151a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3152a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3153a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3154677dec6eSriastradh modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3155a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3156a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3157a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3158677dec6eSriastradh modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3159a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3160a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3161a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3162677dec6eSriastradh modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3163a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3164a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3165a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3166677dec6eSriastradh modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3167a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3168a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3169a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3170677dec6eSriastradh modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3171a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3172a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3173a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3174677dec6eSriastradh
3175677dec6eSriastradh mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3176a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3177a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3178a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3179677dec6eSriastradh mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3180a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3181a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3182a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3183677dec6eSriastradh mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3184a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3185a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3186a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3187677dec6eSriastradh mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3188a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3189a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3190a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3191677dec6eSriastradh mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3192a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3193a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3194a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3195677dec6eSriastradh mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3196a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3197a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3198a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3199677dec6eSriastradh mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3200a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3201a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3202a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3203677dec6eSriastradh mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3204a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3205a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3206a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3207677dec6eSriastradh mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3208a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3209a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3210a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3211677dec6eSriastradh mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3212a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3213a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3214a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3215677dec6eSriastradh mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3216a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3217a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3218a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3219677dec6eSriastradh mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3220a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3221a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3222a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3223677dec6eSriastradh mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3224a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3225a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3226a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3227677dec6eSriastradh mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3228a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3229a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3230a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3231677dec6eSriastradh
3232677dec6eSriastradh for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3233677dec6eSriastradh if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3234677dec6eSriastradh reg_offset != 23)
3235677dec6eSriastradh WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3236677dec6eSriastradh
3237677dec6eSriastradh for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3238677dec6eSriastradh if (reg_offset != 7)
3239677dec6eSriastradh WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3240677dec6eSriastradh
3241a30d5d3aSriastradh break;
3242a30d5d3aSriastradh default:
3243677dec6eSriastradh dev_warn(adev->dev,
3244677dec6eSriastradh "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3245677dec6eSriastradh adev->asic_type);
3246677dec6eSriastradh /* fall through */
3247677dec6eSriastradh
3248a30d5d3aSriastradh case CHIP_CARRIZO:
3249677dec6eSriastradh modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3250a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3251a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3252a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3253677dec6eSriastradh modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3254a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3255a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3256a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3257677dec6eSriastradh modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3258a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3259a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3260a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3261677dec6eSriastradh modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3262a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3263a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3264a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3265677dec6eSriastradh modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3266a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3267a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3268a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3269677dec6eSriastradh modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3270a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3271a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3272a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3273677dec6eSriastradh modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3274a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3275a30d5d3aSriastradh TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3276a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3277677dec6eSriastradh modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3278a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2));
3279677dec6eSriastradh modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3280a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3281a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3282a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3283677dec6eSriastradh modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3284a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3285a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3286a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3287677dec6eSriastradh modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3288a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3289a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3290a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3291677dec6eSriastradh modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3292a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3293a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3294a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3295677dec6eSriastradh modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3296a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3297a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3298a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3299677dec6eSriastradh modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3300a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3301a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3302a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3303677dec6eSriastradh modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3304a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3305a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3306a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3307677dec6eSriastradh modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3308a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3309a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3310a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3311677dec6eSriastradh modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3312a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3313a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3314a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3315677dec6eSriastradh modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3316a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3317a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3318a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3319677dec6eSriastradh modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3320a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3321a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3322a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3323677dec6eSriastradh modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3324a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3325a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3326a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3327677dec6eSriastradh modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3328a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3329a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3330a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3331677dec6eSriastradh modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3332a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3333a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3334a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3335677dec6eSriastradh modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3336a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3337a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3338a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3339677dec6eSriastradh modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3340a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3341a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3342a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3343677dec6eSriastradh modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3344a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3345a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3346a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3347677dec6eSriastradh modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3348a30d5d3aSriastradh PIPE_CONFIG(ADDR_SURF_P2) |
3349a30d5d3aSriastradh MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3350a30d5d3aSriastradh SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3351677dec6eSriastradh
3352677dec6eSriastradh mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3353a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3354a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3355a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3356677dec6eSriastradh mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3357a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3358a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3359a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3360677dec6eSriastradh mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3361a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3362a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3363a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3364677dec6eSriastradh mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3365a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3366a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3367a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3368677dec6eSriastradh mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3369a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3370a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3371a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3372677dec6eSriastradh mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3373a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3374a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3375a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3376677dec6eSriastradh mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3377a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3378a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3379a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3380677dec6eSriastradh mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3381a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3382a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3383a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3384677dec6eSriastradh mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3385a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3386a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3387a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3388677dec6eSriastradh mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3389a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3390a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3391a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3392677dec6eSriastradh mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3393a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3394a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3395a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3396677dec6eSriastradh mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3397a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3398a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3399a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3400677dec6eSriastradh mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3401a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3402a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3403a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_16_BANK));
3404677dec6eSriastradh mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3405a30d5d3aSriastradh BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3406a30d5d3aSriastradh MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3407a30d5d3aSriastradh NUM_BANKS(ADDR_SURF_8_BANK));
3408677dec6eSriastradh
3409677dec6eSriastradh for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3410677dec6eSriastradh if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3411677dec6eSriastradh reg_offset != 23)
3412677dec6eSriastradh WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3413677dec6eSriastradh
3414677dec6eSriastradh for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3415677dec6eSriastradh if (reg_offset != 7)
3416677dec6eSriastradh WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3417677dec6eSriastradh
3418a30d5d3aSriastradh break;
3419a30d5d3aSriastradh }
3420a30d5d3aSriastradh }
3421a30d5d3aSriastradh
gfx_v8_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance)3422677dec6eSriastradh static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
3423677dec6eSriastradh u32 se_num, u32 sh_num, u32 instance)
3424a30d5d3aSriastradh {
3425677dec6eSriastradh u32 data;
3426a30d5d3aSriastradh
3427677dec6eSriastradh if (instance == 0xffffffff)
3428677dec6eSriastradh data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3429677dec6eSriastradh else
3430677dec6eSriastradh data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
3431a30d5d3aSriastradh
3432677dec6eSriastradh if (se_num == 0xffffffff)
3433a30d5d3aSriastradh data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3434677dec6eSriastradh else
3435677dec6eSriastradh data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3436677dec6eSriastradh
3437677dec6eSriastradh if (sh_num == 0xffffffff)
3438a30d5d3aSriastradh data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3439677dec6eSriastradh else
3440a30d5d3aSriastradh data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3441677dec6eSriastradh
3442a30d5d3aSriastradh WREG32(mmGRBM_GFX_INDEX, data);
3443a30d5d3aSriastradh }
3444a30d5d3aSriastradh
gfx_v8_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm)3445677dec6eSriastradh static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3446677dec6eSriastradh u32 me, u32 pipe, u32 q, u32 vm)
3447677dec6eSriastradh {
3448677dec6eSriastradh vi_srbm_select(adev, me, pipe, q, vm);
3449677dec6eSriastradh }
3450677dec6eSriastradh
gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device * adev)3451677dec6eSriastradh static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
3452a30d5d3aSriastradh {
3453a30d5d3aSriastradh u32 data, mask;
3454a30d5d3aSriastradh
3455677dec6eSriastradh data = RREG32(mmCC_RB_BACKEND_DISABLE) |
3456677dec6eSriastradh RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3457a30d5d3aSriastradh
3458677dec6eSriastradh data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
3459a30d5d3aSriastradh
3460677dec6eSriastradh mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
3461677dec6eSriastradh adev->gfx.config.max_sh_per_se);
3462a30d5d3aSriastradh
3463677dec6eSriastradh return (~data) & mask;
3464a30d5d3aSriastradh }
3465a30d5d3aSriastradh
3466677dec6eSriastradh static void
gfx_v8_0_raster_config(struct amdgpu_device * adev,u32 * rconf,u32 * rconf1)3467677dec6eSriastradh gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
3468677dec6eSriastradh {
3469677dec6eSriastradh switch (adev->asic_type) {
3470677dec6eSriastradh case CHIP_FIJI:
3471677dec6eSriastradh case CHIP_VEGAM:
3472677dec6eSriastradh *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
3473677dec6eSriastradh RB_XSEL2(1) | PKR_MAP(2) |
3474677dec6eSriastradh PKR_XSEL(1) | PKR_YSEL(1) |
3475677dec6eSriastradh SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
3476677dec6eSriastradh *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
3477677dec6eSriastradh SE_PAIR_YSEL(2);
3478677dec6eSriastradh break;
3479677dec6eSriastradh case CHIP_TONGA:
3480677dec6eSriastradh case CHIP_POLARIS10:
3481677dec6eSriastradh *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3482677dec6eSriastradh SE_XSEL(1) | SE_YSEL(1);
3483677dec6eSriastradh *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
3484677dec6eSriastradh SE_PAIR_YSEL(2);
3485677dec6eSriastradh break;
3486677dec6eSriastradh case CHIP_TOPAZ:
3487677dec6eSriastradh case CHIP_CARRIZO:
3488677dec6eSriastradh *rconf |= RB_MAP_PKR0(2);
3489677dec6eSriastradh *rconf1 |= 0x0;
3490677dec6eSriastradh break;
3491677dec6eSriastradh case CHIP_POLARIS11:
3492677dec6eSriastradh case CHIP_POLARIS12:
3493677dec6eSriastradh *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3494677dec6eSriastradh SE_XSEL(1) | SE_YSEL(1);
3495677dec6eSriastradh *rconf1 |= 0x0;
3496677dec6eSriastradh break;
3497677dec6eSriastradh case CHIP_STONEY:
3498677dec6eSriastradh *rconf |= 0x0;
3499677dec6eSriastradh *rconf1 |= 0x0;
3500677dec6eSriastradh break;
3501677dec6eSriastradh default:
3502677dec6eSriastradh DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
3503677dec6eSriastradh break;
3504677dec6eSriastradh }
3505677dec6eSriastradh }
3506677dec6eSriastradh
3507677dec6eSriastradh static void
gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device * adev,u32 raster_config,u32 raster_config_1,unsigned rb_mask,unsigned num_rb)3508677dec6eSriastradh gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
3509677dec6eSriastradh u32 raster_config, u32 raster_config_1,
3510677dec6eSriastradh unsigned rb_mask, unsigned num_rb)
3511677dec6eSriastradh {
3512677dec6eSriastradh unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
3513677dec6eSriastradh unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
3514677dec6eSriastradh unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
3515677dec6eSriastradh unsigned rb_per_se = num_rb / num_se;
3516677dec6eSriastradh unsigned se_mask[4];
3517677dec6eSriastradh unsigned se;
3518677dec6eSriastradh
3519677dec6eSriastradh se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3520677dec6eSriastradh se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3521677dec6eSriastradh se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3522677dec6eSriastradh se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3523677dec6eSriastradh
3524677dec6eSriastradh WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
3525677dec6eSriastradh WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
3526677dec6eSriastradh WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
3527677dec6eSriastradh
3528677dec6eSriastradh if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3529677dec6eSriastradh (!se_mask[2] && !se_mask[3]))) {
3530677dec6eSriastradh raster_config_1 &= ~SE_PAIR_MAP_MASK;
3531677dec6eSriastradh
3532677dec6eSriastradh if (!se_mask[0] && !se_mask[1]) {
3533677dec6eSriastradh raster_config_1 |=
3534677dec6eSriastradh SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
3535677dec6eSriastradh } else {
3536677dec6eSriastradh raster_config_1 |=
3537677dec6eSriastradh SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
3538677dec6eSriastradh }
3539677dec6eSriastradh }
3540677dec6eSriastradh
3541677dec6eSriastradh for (se = 0; se < num_se; se++) {
3542677dec6eSriastradh unsigned raster_config_se = raster_config;
3543677dec6eSriastradh unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3544677dec6eSriastradh unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3545677dec6eSriastradh int idx = (se / 2) * 2;
3546677dec6eSriastradh
3547677dec6eSriastradh if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3548677dec6eSriastradh raster_config_se &= ~SE_MAP_MASK;
3549677dec6eSriastradh
3550677dec6eSriastradh if (!se_mask[idx]) {
3551677dec6eSriastradh raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
3552677dec6eSriastradh } else {
3553677dec6eSriastradh raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
3554677dec6eSriastradh }
3555677dec6eSriastradh }
3556677dec6eSriastradh
3557677dec6eSriastradh pkr0_mask &= rb_mask;
3558677dec6eSriastradh pkr1_mask &= rb_mask;
3559677dec6eSriastradh if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3560677dec6eSriastradh raster_config_se &= ~PKR_MAP_MASK;
3561677dec6eSriastradh
3562677dec6eSriastradh if (!pkr0_mask) {
3563677dec6eSriastradh raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
3564677dec6eSriastradh } else {
3565677dec6eSriastradh raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
3566677dec6eSriastradh }
3567677dec6eSriastradh }
3568677dec6eSriastradh
3569677dec6eSriastradh if (rb_per_se >= 2) {
3570677dec6eSriastradh unsigned rb0_mask = 1 << (se * rb_per_se);
3571677dec6eSriastradh unsigned rb1_mask = rb0_mask << 1;
3572677dec6eSriastradh
3573677dec6eSriastradh rb0_mask &= rb_mask;
3574677dec6eSriastradh rb1_mask &= rb_mask;
3575677dec6eSriastradh if (!rb0_mask || !rb1_mask) {
3576677dec6eSriastradh raster_config_se &= ~RB_MAP_PKR0_MASK;
3577677dec6eSriastradh
3578677dec6eSriastradh if (!rb0_mask) {
3579677dec6eSriastradh raster_config_se |=
3580677dec6eSriastradh RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
3581677dec6eSriastradh } else {
3582677dec6eSriastradh raster_config_se |=
3583677dec6eSriastradh RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
3584677dec6eSriastradh }
3585677dec6eSriastradh }
3586677dec6eSriastradh
3587677dec6eSriastradh if (rb_per_se > 2) {
3588677dec6eSriastradh rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3589677dec6eSriastradh rb1_mask = rb0_mask << 1;
3590677dec6eSriastradh rb0_mask &= rb_mask;
3591677dec6eSriastradh rb1_mask &= rb_mask;
3592677dec6eSriastradh if (!rb0_mask || !rb1_mask) {
3593677dec6eSriastradh raster_config_se &= ~RB_MAP_PKR1_MASK;
3594677dec6eSriastradh
3595677dec6eSriastradh if (!rb0_mask) {
3596677dec6eSriastradh raster_config_se |=
3597677dec6eSriastradh RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
3598677dec6eSriastradh } else {
3599677dec6eSriastradh raster_config_se |=
3600677dec6eSriastradh RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
3601677dec6eSriastradh }
3602677dec6eSriastradh }
3603677dec6eSriastradh }
3604677dec6eSriastradh }
3605677dec6eSriastradh
3606677dec6eSriastradh /* GRBM_GFX_INDEX has a different offset on VI */
3607677dec6eSriastradh gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
3608677dec6eSriastradh WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
3609677dec6eSriastradh WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3610677dec6eSriastradh }
3611677dec6eSriastradh
3612677dec6eSriastradh /* GRBM_GFX_INDEX has a different offset on VI */
3613677dec6eSriastradh gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3614677dec6eSriastradh }
3615677dec6eSriastradh
gfx_v8_0_setup_rb(struct amdgpu_device * adev)3616677dec6eSriastradh static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
3617a30d5d3aSriastradh {
3618a30d5d3aSriastradh int i, j;
3619677dec6eSriastradh u32 data;
3620677dec6eSriastradh u32 raster_config = 0, raster_config_1 = 0;
3621677dec6eSriastradh u32 active_rbs = 0;
3622677dec6eSriastradh u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3623677dec6eSriastradh adev->gfx.config.max_sh_per_se;
3624677dec6eSriastradh unsigned num_rb_pipes;
3625a30d5d3aSriastradh
3626a30d5d3aSriastradh mutex_lock(&adev->grbm_idx_mutex);
3627677dec6eSriastradh for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3628677dec6eSriastradh for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3629677dec6eSriastradh gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3630677dec6eSriastradh data = gfx_v8_0_get_rb_active_bitmap(adev);
3631677dec6eSriastradh active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
3632677dec6eSriastradh rb_bitmap_width_per_sh);
3633a30d5d3aSriastradh }
3634a30d5d3aSriastradh }
3635677dec6eSriastradh gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3636a30d5d3aSriastradh
3637677dec6eSriastradh adev->gfx.config.backend_enable_mask = active_rbs;
3638677dec6eSriastradh adev->gfx.config.num_rbs = hweight32(active_rbs);
3639677dec6eSriastradh
3640677dec6eSriastradh num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
3641677dec6eSriastradh adev->gfx.config.max_shader_engines, 16);
3642677dec6eSriastradh
3643677dec6eSriastradh gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
3644677dec6eSriastradh
3645677dec6eSriastradh if (!adev->gfx.config.backend_enable_mask ||
3646677dec6eSriastradh adev->gfx.config.num_rbs >= num_rb_pipes) {
3647677dec6eSriastradh WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
3648677dec6eSriastradh WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3649677dec6eSriastradh } else {
3650677dec6eSriastradh gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
3651677dec6eSriastradh adev->gfx.config.backend_enable_mask,
3652677dec6eSriastradh num_rb_pipes);
3653a30d5d3aSriastradh }
3654a30d5d3aSriastradh
3655677dec6eSriastradh /* cache the values for userspace */
3656677dec6eSriastradh for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3657677dec6eSriastradh for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3658677dec6eSriastradh gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3659677dec6eSriastradh adev->gfx.config.rb_config[i][j].rb_backend_disable =
3660677dec6eSriastradh RREG32(mmCC_RB_BACKEND_DISABLE);
3661677dec6eSriastradh adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
3662677dec6eSriastradh RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3663677dec6eSriastradh adev->gfx.config.rb_config[i][j].raster_config =
3664677dec6eSriastradh RREG32(mmPA_SC_RASTER_CONFIG);
3665677dec6eSriastradh adev->gfx.config.rb_config[i][j].raster_config_1 =
3666677dec6eSriastradh RREG32(mmPA_SC_RASTER_CONFIG_1);
3667a30d5d3aSriastradh }
3668a30d5d3aSriastradh }
3669677dec6eSriastradh gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3670a30d5d3aSriastradh mutex_unlock(&adev->grbm_idx_mutex);
3671a30d5d3aSriastradh }
3672a30d5d3aSriastradh
3673a30d5d3aSriastradh /**
3674a30d5d3aSriastradh * gfx_v8_0_init_compute_vmid - gart enable
3675a30d5d3aSriastradh *
3676677dec6eSriastradh * @adev: amdgpu_device pointer
3677a30d5d3aSriastradh *
3678a30d5d3aSriastradh * Initialize compute vmid sh_mem registers
3679a30d5d3aSriastradh *
3680a30d5d3aSriastradh */
3681a30d5d3aSriastradh #define DEFAULT_SH_MEM_BASES (0x6000)
3682a30d5d3aSriastradh #define FIRST_COMPUTE_VMID (8)
3683a30d5d3aSriastradh #define LAST_COMPUTE_VMID (16)
gfx_v8_0_init_compute_vmid(struct amdgpu_device * adev)3684a30d5d3aSriastradh static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
3685a30d5d3aSriastradh {
3686a30d5d3aSriastradh int i;
3687a30d5d3aSriastradh uint32_t sh_mem_config;
3688a30d5d3aSriastradh uint32_t sh_mem_bases;
3689a30d5d3aSriastradh
3690a30d5d3aSriastradh /*
3691a30d5d3aSriastradh * Configure apertures:
3692a30d5d3aSriastradh * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3693a30d5d3aSriastradh * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3694a30d5d3aSriastradh * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3695a30d5d3aSriastradh */
3696a30d5d3aSriastradh sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3697a30d5d3aSriastradh
3698a30d5d3aSriastradh sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3699a30d5d3aSriastradh SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3700a30d5d3aSriastradh SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3701a30d5d3aSriastradh SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3702a30d5d3aSriastradh MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3703a30d5d3aSriastradh SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3704a30d5d3aSriastradh
3705a30d5d3aSriastradh mutex_lock(&adev->srbm_mutex);
3706a30d5d3aSriastradh for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
3707a30d5d3aSriastradh vi_srbm_select(adev, 0, 0, 0, i);
3708a30d5d3aSriastradh /* CP and shaders */
3709a30d5d3aSriastradh WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3710a30d5d3aSriastradh WREG32(mmSH_MEM_APE1_BASE, 1);
3711a30d5d3aSriastradh WREG32(mmSH_MEM_APE1_LIMIT, 0);
3712a30d5d3aSriastradh WREG32(mmSH_MEM_BASES, sh_mem_bases);
3713a30d5d3aSriastradh }
3714a30d5d3aSriastradh vi_srbm_select(adev, 0, 0, 0, 0);
3715a30d5d3aSriastradh mutex_unlock(&adev->srbm_mutex);
3716677dec6eSriastradh
3717677dec6eSriastradh /* Initialize all compute VMIDs to have no GDS, GWS, or OA
3718677dec6eSriastradh acccess. These should be enabled by FW for target VMIDs. */
3719677dec6eSriastradh for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
3720677dec6eSriastradh WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
3721677dec6eSriastradh WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
3722677dec6eSriastradh WREG32(amdgpu_gds_reg_offset[i].gws, 0);
3723677dec6eSriastradh WREG32(amdgpu_gds_reg_offset[i].oa, 0);
3724677dec6eSriastradh }
3725a30d5d3aSriastradh }
3726a30d5d3aSriastradh
gfx_v8_0_init_gds_vmid(struct amdgpu_device * adev)3727677dec6eSriastradh static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
3728a30d5d3aSriastradh {
3729677dec6eSriastradh int vmid;
3730677dec6eSriastradh
3731677dec6eSriastradh /*
3732677dec6eSriastradh * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
3733677dec6eSriastradh * access. Compute VMIDs should be enabled by FW for target VMIDs,
3734677dec6eSriastradh * the driver can enable them for graphics. VMID0 should maintain
3735677dec6eSriastradh * access so that HWS firmware can save/restore entries.
3736677dec6eSriastradh */
3737677dec6eSriastradh for (vmid = 1; vmid < 16; vmid++) {
3738677dec6eSriastradh WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
3739677dec6eSriastradh WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
3740677dec6eSriastradh WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
3741677dec6eSriastradh WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
3742677dec6eSriastradh }
3743677dec6eSriastradh }
3744677dec6eSriastradh
gfx_v8_0_config_init(struct amdgpu_device * adev)3745677dec6eSriastradh static void gfx_v8_0_config_init(struct amdgpu_device *adev)
3746677dec6eSriastradh {
3747677dec6eSriastradh switch (adev->asic_type) {
3748677dec6eSriastradh default:
3749677dec6eSriastradh adev->gfx.config.double_offchip_lds_buf = 1;
3750677dec6eSriastradh break;
3751677dec6eSriastradh case CHIP_CARRIZO:
3752677dec6eSriastradh case CHIP_STONEY:
3753677dec6eSriastradh adev->gfx.config.double_offchip_lds_buf = 0;
3754677dec6eSriastradh break;
3755677dec6eSriastradh }
3756677dec6eSriastradh }
3757677dec6eSriastradh
gfx_v8_0_constants_init(struct amdgpu_device * adev)3758677dec6eSriastradh static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
3759677dec6eSriastradh {
3760677dec6eSriastradh u32 tmp, sh_static_mem_cfg;
3761a30d5d3aSriastradh int i;
3762a30d5d3aSriastradh
3763677dec6eSriastradh WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
3764a30d5d3aSriastradh WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3765a30d5d3aSriastradh WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3766a30d5d3aSriastradh WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
3767a30d5d3aSriastradh
3768a30d5d3aSriastradh gfx_v8_0_tiling_mode_table_init(adev);
3769677dec6eSriastradh gfx_v8_0_setup_rb(adev);
3770677dec6eSriastradh gfx_v8_0_get_cu_info(adev);
3771677dec6eSriastradh gfx_v8_0_config_init(adev);
3772a30d5d3aSriastradh
3773a30d5d3aSriastradh /* XXX SH_MEM regs */
3774a30d5d3aSriastradh /* where to put LDS, scratch, GPUVM in FSA64 space */
3775677dec6eSriastradh sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
3776677dec6eSriastradh SWIZZLE_ENABLE, 1);
3777677dec6eSriastradh sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3778677dec6eSriastradh ELEMENT_SIZE, 1);
3779677dec6eSriastradh sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3780677dec6eSriastradh INDEX_STRIDE, 3);
3781677dec6eSriastradh WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
3782677dec6eSriastradh
3783a30d5d3aSriastradh mutex_lock(&adev->srbm_mutex);
3784677dec6eSriastradh for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
3785a30d5d3aSriastradh vi_srbm_select(adev, 0, 0, 0, i);
3786a30d5d3aSriastradh /* CP and shaders */
3787a30d5d3aSriastradh if (i == 0) {
3788a30d5d3aSriastradh tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3789a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3790a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3791a30d5d3aSriastradh SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3792a30d5d3aSriastradh WREG32(mmSH_MEM_CONFIG, tmp);
3793677dec6eSriastradh WREG32(mmSH_MEM_BASES, 0);
3794a30d5d3aSriastradh } else {
3795a30d5d3aSriastradh tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3796677dec6eSriastradh tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3797a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3798a30d5d3aSriastradh SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3799a30d5d3aSriastradh WREG32(mmSH_MEM_CONFIG, tmp);
3800677dec6eSriastradh tmp = adev->gmc.shared_aperture_start >> 48;
3801677dec6eSriastradh WREG32(mmSH_MEM_BASES, tmp);
3802a30d5d3aSriastradh }
3803a30d5d3aSriastradh
3804a30d5d3aSriastradh WREG32(mmSH_MEM_APE1_BASE, 1);
3805a30d5d3aSriastradh WREG32(mmSH_MEM_APE1_LIMIT, 0);
3806a30d5d3aSriastradh }
3807a30d5d3aSriastradh vi_srbm_select(adev, 0, 0, 0, 0);
3808a30d5d3aSriastradh mutex_unlock(&adev->srbm_mutex);
3809a30d5d3aSriastradh
3810a30d5d3aSriastradh gfx_v8_0_init_compute_vmid(adev);
3811677dec6eSriastradh gfx_v8_0_init_gds_vmid(adev);
3812a30d5d3aSriastradh
3813a30d5d3aSriastradh mutex_lock(&adev->grbm_idx_mutex);
3814a30d5d3aSriastradh /*
3815a30d5d3aSriastradh * making sure that the following register writes will be broadcasted
3816a30d5d3aSriastradh * to all the shaders
3817a30d5d3aSriastradh */
3818677dec6eSriastradh gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3819a30d5d3aSriastradh
3820a30d5d3aSriastradh WREG32(mmPA_SC_FIFO_SIZE,
3821a30d5d3aSriastradh (adev->gfx.config.sc_prim_fifo_size_frontend <<
3822a30d5d3aSriastradh PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3823a30d5d3aSriastradh (adev->gfx.config.sc_prim_fifo_size_backend <<
3824a30d5d3aSriastradh PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3825a30d5d3aSriastradh (adev->gfx.config.sc_hiz_tile_fifo_size <<
3826a30d5d3aSriastradh PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3827a30d5d3aSriastradh (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3828a30d5d3aSriastradh PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3829677dec6eSriastradh
3830677dec6eSriastradh tmp = RREG32(mmSPI_ARB_PRIORITY);
3831677dec6eSriastradh tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
3832677dec6eSriastradh tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
3833677dec6eSriastradh tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
3834677dec6eSriastradh tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
3835677dec6eSriastradh WREG32(mmSPI_ARB_PRIORITY, tmp);
3836677dec6eSriastradh
3837a30d5d3aSriastradh mutex_unlock(&adev->grbm_idx_mutex);
3838a30d5d3aSriastradh
3839a30d5d3aSriastradh }
3840a30d5d3aSriastradh
gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device * adev)3841a30d5d3aSriastradh static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3842a30d5d3aSriastradh {
3843a30d5d3aSriastradh u32 i, j, k;
3844a30d5d3aSriastradh u32 mask;
3845a30d5d3aSriastradh
3846a30d5d3aSriastradh mutex_lock(&adev->grbm_idx_mutex);
3847a30d5d3aSriastradh for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3848a30d5d3aSriastradh for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3849677dec6eSriastradh gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3850a30d5d3aSriastradh for (k = 0; k < adev->usec_timeout; k++) {
3851a30d5d3aSriastradh if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3852a30d5d3aSriastradh break;
3853a30d5d3aSriastradh udelay(1);
3854a30d5d3aSriastradh }
3855677dec6eSriastradh if (k == adev->usec_timeout) {
3856677dec6eSriastradh gfx_v8_0_select_se_sh(adev, 0xffffffff,
3857677dec6eSriastradh 0xffffffff, 0xffffffff);
3858677dec6eSriastradh mutex_unlock(&adev->grbm_idx_mutex);
3859677dec6eSriastradh DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
3860677dec6eSriastradh i, j);
3861677dec6eSriastradh return;
3862a30d5d3aSriastradh }
3863a30d5d3aSriastradh }
3864677dec6eSriastradh }
3865677dec6eSriastradh gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3866a30d5d3aSriastradh mutex_unlock(&adev->grbm_idx_mutex);
3867a30d5d3aSriastradh
3868a30d5d3aSriastradh mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3869a30d5d3aSriastradh RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3870a30d5d3aSriastradh RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3871a30d5d3aSriastradh RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3872a30d5d3aSriastradh for (k = 0; k < adev->usec_timeout; k++) {
3873a30d5d3aSriastradh if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3874a30d5d3aSriastradh break;
3875a30d5d3aSriastradh udelay(1);
3876a30d5d3aSriastradh }
3877a30d5d3aSriastradh }
3878a30d5d3aSriastradh
gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)3879a30d5d3aSriastradh static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3880a30d5d3aSriastradh bool enable)
3881a30d5d3aSriastradh {
3882a30d5d3aSriastradh u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3883a30d5d3aSriastradh
3884677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3885677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3886677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3887677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3888677dec6eSriastradh
3889a30d5d3aSriastradh WREG32(mmCP_INT_CNTL_RING0, tmp);
3890a30d5d3aSriastradh }
3891a30d5d3aSriastradh
gfx_v8_0_init_csb(struct amdgpu_device * adev)3892677dec6eSriastradh static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3893a30d5d3aSriastradh {
3894677dec6eSriastradh adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
3895677dec6eSriastradh /* csib */
3896677dec6eSriastradh WREG32(mmRLC_CSIB_ADDR_HI,
3897677dec6eSriastradh adev->gfx.rlc.clear_state_gpu_addr >> 32);
3898677dec6eSriastradh WREG32(mmRLC_CSIB_ADDR_LO,
3899677dec6eSriastradh adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3900677dec6eSriastradh WREG32(mmRLC_CSIB_LENGTH,
3901677dec6eSriastradh adev->gfx.rlc.clear_state_size);
3902677dec6eSriastradh }
3903a30d5d3aSriastradh
gfx_v8_0_parse_ind_reg_list(int * register_list_format,int ind_offset,int list_size,int * unique_indices,int * indices_count,int max_indices,int * ind_start_offsets,int * offset_count,int max_offset)3904677dec6eSriastradh static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3905677dec6eSriastradh int ind_offset,
3906677dec6eSriastradh int list_size,
3907677dec6eSriastradh int *unique_indices,
3908677dec6eSriastradh int *indices_count,
3909677dec6eSriastradh int max_indices,
3910677dec6eSriastradh int *ind_start_offsets,
3911677dec6eSriastradh int *offset_count,
3912677dec6eSriastradh int max_offset)
3913677dec6eSriastradh {
3914677dec6eSriastradh int indices;
3915677dec6eSriastradh bool new_entry = true;
3916677dec6eSriastradh
3917677dec6eSriastradh for (; ind_offset < list_size; ind_offset++) {
3918677dec6eSriastradh
3919677dec6eSriastradh if (new_entry) {
3920677dec6eSriastradh new_entry = false;
3921677dec6eSriastradh ind_start_offsets[*offset_count] = ind_offset;
3922677dec6eSriastradh *offset_count = *offset_count + 1;
3923677dec6eSriastradh BUG_ON(*offset_count >= max_offset);
3924677dec6eSriastradh }
3925677dec6eSriastradh
3926677dec6eSriastradh if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3927677dec6eSriastradh new_entry = true;
3928677dec6eSriastradh continue;
3929677dec6eSriastradh }
3930677dec6eSriastradh
3931677dec6eSriastradh ind_offset += 2;
3932677dec6eSriastradh
3933677dec6eSriastradh /* look for the matching indice */
3934677dec6eSriastradh for (indices = 0;
3935677dec6eSriastradh indices < *indices_count;
3936677dec6eSriastradh indices++) {
3937677dec6eSriastradh if (unique_indices[indices] ==
3938677dec6eSriastradh register_list_format[ind_offset])
3939677dec6eSriastradh break;
3940677dec6eSriastradh }
3941677dec6eSriastradh
3942677dec6eSriastradh if (indices >= *indices_count) {
3943677dec6eSriastradh unique_indices[*indices_count] =
3944677dec6eSriastradh register_list_format[ind_offset];
3945677dec6eSriastradh indices = *indices_count;
3946677dec6eSriastradh *indices_count = *indices_count + 1;
3947677dec6eSriastradh BUG_ON(*indices_count >= max_indices);
3948677dec6eSriastradh }
3949677dec6eSriastradh
3950677dec6eSriastradh register_list_format[ind_offset] = indices;
3951677dec6eSriastradh }
3952677dec6eSriastradh }
3953677dec6eSriastradh
gfx_v8_0_init_save_restore_list(struct amdgpu_device * adev)3954677dec6eSriastradh static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3955677dec6eSriastradh {
3956677dec6eSriastradh int i, temp, data;
3957677dec6eSriastradh int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3958677dec6eSriastradh int indices_count = 0;
3959677dec6eSriastradh int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3960677dec6eSriastradh int offset_count = 0;
3961677dec6eSriastradh
3962677dec6eSriastradh int list_size;
3963677dec6eSriastradh unsigned int *register_list_format =
3964677dec6eSriastradh kmemdup(adev->gfx.rlc.register_list_format,
3965677dec6eSriastradh adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3966677dec6eSriastradh if (!register_list_format)
3967677dec6eSriastradh return -ENOMEM;
3968677dec6eSriastradh
3969677dec6eSriastradh gfx_v8_0_parse_ind_reg_list(register_list_format,
3970677dec6eSriastradh RLC_FormatDirectRegListLength,
3971677dec6eSriastradh adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3972677dec6eSriastradh unique_indices,
3973677dec6eSriastradh &indices_count,
3974677dec6eSriastradh ARRAY_SIZE(unique_indices),
3975677dec6eSriastradh indirect_start_offsets,
3976677dec6eSriastradh &offset_count,
3977677dec6eSriastradh ARRAY_SIZE(indirect_start_offsets));
3978677dec6eSriastradh
3979677dec6eSriastradh /* save and restore list */
3980677dec6eSriastradh WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
3981677dec6eSriastradh
3982677dec6eSriastradh WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3983677dec6eSriastradh for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3984677dec6eSriastradh WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
3985677dec6eSriastradh
3986677dec6eSriastradh /* indirect list */
3987677dec6eSriastradh WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
3988677dec6eSriastradh for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
3989677dec6eSriastradh WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3990677dec6eSriastradh
3991677dec6eSriastradh list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
3992677dec6eSriastradh list_size = list_size >> 1;
3993677dec6eSriastradh WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
3994677dec6eSriastradh WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
3995677dec6eSriastradh
3996677dec6eSriastradh /* starting offsets starts */
3997677dec6eSriastradh WREG32(mmRLC_GPM_SCRATCH_ADDR,
3998677dec6eSriastradh adev->gfx.rlc.starting_offsets_start);
3999677dec6eSriastradh for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
4000677dec6eSriastradh WREG32(mmRLC_GPM_SCRATCH_DATA,
4001677dec6eSriastradh indirect_start_offsets[i]);
4002677dec6eSriastradh
4003677dec6eSriastradh /* unique indices */
4004677dec6eSriastradh temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
4005677dec6eSriastradh data = mmRLC_SRM_INDEX_CNTL_DATA_0;
4006677dec6eSriastradh for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
4007677dec6eSriastradh if (unique_indices[i] != 0) {
4008677dec6eSriastradh WREG32(temp + i, unique_indices[i] & 0x3FFFF);
4009677dec6eSriastradh WREG32(data + i, unique_indices[i] >> 20);
4010677dec6eSriastradh }
4011677dec6eSriastradh }
4012677dec6eSriastradh kfree(register_list_format);
4013677dec6eSriastradh
4014677dec6eSriastradh return 0;
4015677dec6eSriastradh }
4016677dec6eSriastradh
gfx_v8_0_enable_save_restore_machine(struct amdgpu_device * adev)4017677dec6eSriastradh static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
4018677dec6eSriastradh {
4019677dec6eSriastradh WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
4020677dec6eSriastradh }
4021677dec6eSriastradh
gfx_v8_0_init_power_gating(struct amdgpu_device * adev)4022677dec6eSriastradh static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
4023677dec6eSriastradh {
4024677dec6eSriastradh uint32_t data;
4025677dec6eSriastradh
4026677dec6eSriastradh WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
4027677dec6eSriastradh
4028677dec6eSriastradh data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
4029677dec6eSriastradh data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
4030677dec6eSriastradh data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
4031677dec6eSriastradh data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
4032677dec6eSriastradh WREG32(mmRLC_PG_DELAY, data);
4033677dec6eSriastradh
4034677dec6eSriastradh WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
4035677dec6eSriastradh WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
4036677dec6eSriastradh
4037677dec6eSriastradh }
4038677dec6eSriastradh
cz_enable_sck_slow_down_on_power_up(struct amdgpu_device * adev,bool enable)4039677dec6eSriastradh static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
4040677dec6eSriastradh bool enable)
4041677dec6eSriastradh {
4042677dec6eSriastradh WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
4043677dec6eSriastradh }
4044677dec6eSriastradh
cz_enable_sck_slow_down_on_power_down(struct amdgpu_device * adev,bool enable)4045677dec6eSriastradh static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
4046677dec6eSriastradh bool enable)
4047677dec6eSriastradh {
4048677dec6eSriastradh WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
4049677dec6eSriastradh }
4050677dec6eSriastradh
cz_enable_cp_power_gating(struct amdgpu_device * adev,bool enable)4051677dec6eSriastradh static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
4052677dec6eSriastradh {
4053677dec6eSriastradh WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
4054677dec6eSriastradh }
4055677dec6eSriastradh
gfx_v8_0_init_pg(struct amdgpu_device * adev)4056677dec6eSriastradh static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
4057677dec6eSriastradh {
4058677dec6eSriastradh if ((adev->asic_type == CHIP_CARRIZO) ||
4059677dec6eSriastradh (adev->asic_type == CHIP_STONEY)) {
4060677dec6eSriastradh gfx_v8_0_init_csb(adev);
4061677dec6eSriastradh gfx_v8_0_init_save_restore_list(adev);
4062677dec6eSriastradh gfx_v8_0_enable_save_restore_machine(adev);
4063677dec6eSriastradh WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4064677dec6eSriastradh gfx_v8_0_init_power_gating(adev);
4065677dec6eSriastradh WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4066677dec6eSriastradh } else if ((adev->asic_type == CHIP_POLARIS11) ||
4067677dec6eSriastradh (adev->asic_type == CHIP_POLARIS12) ||
4068677dec6eSriastradh (adev->asic_type == CHIP_VEGAM)) {
4069677dec6eSriastradh gfx_v8_0_init_csb(adev);
4070677dec6eSriastradh gfx_v8_0_init_save_restore_list(adev);
4071677dec6eSriastradh gfx_v8_0_enable_save_restore_machine(adev);
4072677dec6eSriastradh gfx_v8_0_init_power_gating(adev);
4073677dec6eSriastradh }
4074677dec6eSriastradh
4075677dec6eSriastradh }
4076677dec6eSriastradh
gfx_v8_0_rlc_stop(struct amdgpu_device * adev)4077677dec6eSriastradh static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
4078677dec6eSriastradh {
4079677dec6eSriastradh WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
4080a30d5d3aSriastradh
4081a30d5d3aSriastradh gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4082a30d5d3aSriastradh gfx_v8_0_wait_for_rlc_serdes(adev);
4083a30d5d3aSriastradh }
4084a30d5d3aSriastradh
gfx_v8_0_rlc_reset(struct amdgpu_device * adev)4085a30d5d3aSriastradh static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
4086a30d5d3aSriastradh {
4087677dec6eSriastradh WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4088a30d5d3aSriastradh udelay(50);
4089677dec6eSriastradh
4090677dec6eSriastradh WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4091a30d5d3aSriastradh udelay(50);
4092a30d5d3aSriastradh }
4093a30d5d3aSriastradh
gfx_v8_0_rlc_start(struct amdgpu_device * adev)4094a30d5d3aSriastradh static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
4095a30d5d3aSriastradh {
4096677dec6eSriastradh WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
4097a30d5d3aSriastradh
4098a30d5d3aSriastradh /* carrizo do enable cp interrupt after cp inited */
4099a30d5d3aSriastradh if (!(adev->flags & AMD_IS_APU))
4100a30d5d3aSriastradh gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4101a30d5d3aSriastradh
4102a30d5d3aSriastradh udelay(50);
4103a30d5d3aSriastradh }
4104a30d5d3aSriastradh
gfx_v8_0_rlc_resume(struct amdgpu_device * adev)4105677dec6eSriastradh static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
4106a30d5d3aSriastradh {
4107677dec6eSriastradh if (amdgpu_sriov_vf(adev)) {
4108677dec6eSriastradh gfx_v8_0_init_csb(adev);
4109a30d5d3aSriastradh return 0;
4110a30d5d3aSriastradh }
4111a30d5d3aSriastradh
4112677dec6eSriastradh adev->gfx.rlc.funcs->stop(adev);
4113677dec6eSriastradh adev->gfx.rlc.funcs->reset(adev);
4114677dec6eSriastradh gfx_v8_0_init_pg(adev);
4115677dec6eSriastradh adev->gfx.rlc.funcs->start(adev);
4116a30d5d3aSriastradh
4117a30d5d3aSriastradh return 0;
4118a30d5d3aSriastradh }
4119a30d5d3aSriastradh
gfx_v8_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)4120a30d5d3aSriastradh static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
4121a30d5d3aSriastradh {
4122a30d5d3aSriastradh int i;
4123a30d5d3aSriastradh u32 tmp = RREG32(mmCP_ME_CNTL);
4124a30d5d3aSriastradh
4125a30d5d3aSriastradh if (enable) {
4126a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4127a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4128a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4129a30d5d3aSriastradh } else {
4130a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4131a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4132a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
4133a30d5d3aSriastradh for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4134677dec6eSriastradh adev->gfx.gfx_ring[i].sched.ready = false;
4135a30d5d3aSriastradh }
4136a30d5d3aSriastradh WREG32(mmCP_ME_CNTL, tmp);
4137a30d5d3aSriastradh udelay(50);
4138a30d5d3aSriastradh }
4139a30d5d3aSriastradh
gfx_v8_0_get_csb_size(struct amdgpu_device * adev)4140a30d5d3aSriastradh static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
4141a30d5d3aSriastradh {
4142a30d5d3aSriastradh u32 count = 0;
4143a30d5d3aSriastradh const struct cs_section_def *sect = NULL;
4144a30d5d3aSriastradh const struct cs_extent_def *ext = NULL;
4145a30d5d3aSriastradh
4146a30d5d3aSriastradh /* begin clear state */
4147a30d5d3aSriastradh count += 2;
4148a30d5d3aSriastradh /* context control state */
4149a30d5d3aSriastradh count += 3;
4150a30d5d3aSriastradh
4151a30d5d3aSriastradh for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4152a30d5d3aSriastradh for (ext = sect->section; ext->extent != NULL; ++ext) {
4153a30d5d3aSriastradh if (sect->id == SECT_CONTEXT)
4154a30d5d3aSriastradh count += 2 + ext->reg_count;
4155a30d5d3aSriastradh else
4156a30d5d3aSriastradh return 0;
4157a30d5d3aSriastradh }
4158a30d5d3aSriastradh }
4159a30d5d3aSriastradh /* pa_sc_raster_config/pa_sc_raster_config1 */
4160a30d5d3aSriastradh count += 4;
4161a30d5d3aSriastradh /* end clear state */
4162a30d5d3aSriastradh count += 2;
4163a30d5d3aSriastradh /* clear state */
4164a30d5d3aSriastradh count += 2;
4165a30d5d3aSriastradh
4166a30d5d3aSriastradh return count;
4167a30d5d3aSriastradh }
4168a30d5d3aSriastradh
gfx_v8_0_cp_gfx_start(struct amdgpu_device * adev)4169a30d5d3aSriastradh static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
4170a30d5d3aSriastradh {
4171a30d5d3aSriastradh struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
4172a30d5d3aSriastradh const struct cs_section_def *sect = NULL;
4173a30d5d3aSriastradh const struct cs_extent_def *ext = NULL;
4174a30d5d3aSriastradh int r, i;
4175a30d5d3aSriastradh
4176a30d5d3aSriastradh /* init the CP */
4177a30d5d3aSriastradh WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
4178a30d5d3aSriastradh WREG32(mmCP_ENDIAN_SWAP, 0);
4179a30d5d3aSriastradh WREG32(mmCP_DEVICE_ID, 1);
4180a30d5d3aSriastradh
4181a30d5d3aSriastradh gfx_v8_0_cp_gfx_enable(adev, true);
4182a30d5d3aSriastradh
4183677dec6eSriastradh r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
4184a30d5d3aSriastradh if (r) {
4185a30d5d3aSriastradh DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
4186a30d5d3aSriastradh return r;
4187a30d5d3aSriastradh }
4188a30d5d3aSriastradh
4189a30d5d3aSriastradh /* clear state buffer */
4190a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4191a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4192a30d5d3aSriastradh
4193a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4194a30d5d3aSriastradh amdgpu_ring_write(ring, 0x80000000);
4195a30d5d3aSriastradh amdgpu_ring_write(ring, 0x80000000);
4196a30d5d3aSriastradh
4197a30d5d3aSriastradh for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4198a30d5d3aSriastradh for (ext = sect->section; ext->extent != NULL; ++ext) {
4199a30d5d3aSriastradh if (sect->id == SECT_CONTEXT) {
4200a30d5d3aSriastradh amdgpu_ring_write(ring,
4201a30d5d3aSriastradh PACKET3(PACKET3_SET_CONTEXT_REG,
4202a30d5d3aSriastradh ext->reg_count));
4203a30d5d3aSriastradh amdgpu_ring_write(ring,
4204a30d5d3aSriastradh ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4205a30d5d3aSriastradh for (i = 0; i < ext->reg_count; i++)
4206a30d5d3aSriastradh amdgpu_ring_write(ring, ext->extent[i]);
4207a30d5d3aSriastradh }
4208a30d5d3aSriastradh }
4209a30d5d3aSriastradh }
4210a30d5d3aSriastradh
4211a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4212a30d5d3aSriastradh amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4213677dec6eSriastradh amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
4214677dec6eSriastradh amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
4215a30d5d3aSriastradh
4216a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4217a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4218a30d5d3aSriastradh
4219a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4220a30d5d3aSriastradh amdgpu_ring_write(ring, 0);
4221a30d5d3aSriastradh
4222a30d5d3aSriastradh /* init the CE partitions */
4223a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4224a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4225a30d5d3aSriastradh amdgpu_ring_write(ring, 0x8000);
4226a30d5d3aSriastradh amdgpu_ring_write(ring, 0x8000);
4227a30d5d3aSriastradh
4228677dec6eSriastradh amdgpu_ring_commit(ring);
4229a30d5d3aSriastradh
4230a30d5d3aSriastradh return 0;
4231a30d5d3aSriastradh }
gfx_v8_0_set_cpg_door_bell(struct amdgpu_device * adev,struct amdgpu_ring * ring)4232677dec6eSriastradh static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring)
4233677dec6eSriastradh {
4234677dec6eSriastradh u32 tmp;
4235677dec6eSriastradh /* no gfx doorbells on iceland */
4236677dec6eSriastradh if (adev->asic_type == CHIP_TOPAZ)
4237677dec6eSriastradh return;
4238677dec6eSriastradh
4239677dec6eSriastradh tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4240677dec6eSriastradh
4241677dec6eSriastradh if (ring->use_doorbell) {
4242677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4243677dec6eSriastradh DOORBELL_OFFSET, ring->doorbell_index);
4244677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4245677dec6eSriastradh DOORBELL_HIT, 0);
4246677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4247677dec6eSriastradh DOORBELL_EN, 1);
4248677dec6eSriastradh } else {
4249677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
4250677dec6eSriastradh }
4251677dec6eSriastradh
4252677dec6eSriastradh WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4253677dec6eSriastradh
4254677dec6eSriastradh if (adev->flags & AMD_IS_APU)
4255677dec6eSriastradh return;
4256677dec6eSriastradh
4257677dec6eSriastradh tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4258677dec6eSriastradh DOORBELL_RANGE_LOWER,
4259677dec6eSriastradh adev->doorbell_index.gfx_ring0);
4260677dec6eSriastradh WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4261677dec6eSriastradh
4262677dec6eSriastradh WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4263677dec6eSriastradh CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4264677dec6eSriastradh }
4265a30d5d3aSriastradh
gfx_v8_0_cp_gfx_resume(struct amdgpu_device * adev)4266a30d5d3aSriastradh static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4267a30d5d3aSriastradh {
4268a30d5d3aSriastradh struct amdgpu_ring *ring;
4269a30d5d3aSriastradh u32 tmp;
4270a30d5d3aSriastradh u32 rb_bufsz;
4271677dec6eSriastradh u64 rb_addr, rptr_addr, wptr_gpu_addr;
4272a30d5d3aSriastradh
4273a30d5d3aSriastradh /* Set the write pointer delay */
4274a30d5d3aSriastradh WREG32(mmCP_RB_WPTR_DELAY, 0);
4275a30d5d3aSriastradh
4276a30d5d3aSriastradh /* set the RB to use vmid 0 */
4277a30d5d3aSriastradh WREG32(mmCP_RB_VMID, 0);
4278a30d5d3aSriastradh
4279a30d5d3aSriastradh /* Set ring buffer size */
4280a30d5d3aSriastradh ring = &adev->gfx.gfx_ring[0];
4281a30d5d3aSriastradh rb_bufsz = order_base_2(ring->ring_size / 8);
4282a30d5d3aSriastradh tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4283a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4284a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4285a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4286a30d5d3aSriastradh #ifdef __BIG_ENDIAN
4287a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4288a30d5d3aSriastradh #endif
4289a30d5d3aSriastradh WREG32(mmCP_RB0_CNTL, tmp);
4290a30d5d3aSriastradh
4291a30d5d3aSriastradh /* Initialize the ring buffer's read and write pointers */
4292a30d5d3aSriastradh WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4293a30d5d3aSriastradh ring->wptr = 0;
4294677dec6eSriastradh WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4295a30d5d3aSriastradh
4296a30d5d3aSriastradh /* set the wb address wether it's enabled or not */
4297a30d5d3aSriastradh rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4298a30d5d3aSriastradh WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4299a30d5d3aSriastradh WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4300a30d5d3aSriastradh
4301677dec6eSriastradh wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4302677dec6eSriastradh WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
4303677dec6eSriastradh WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
4304a30d5d3aSriastradh mdelay(1);
4305a30d5d3aSriastradh WREG32(mmCP_RB0_CNTL, tmp);
4306a30d5d3aSriastradh
4307a30d5d3aSriastradh rb_addr = ring->gpu_addr >> 8;
4308a30d5d3aSriastradh WREG32(mmCP_RB0_BASE, rb_addr);
4309a30d5d3aSriastradh WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4310a30d5d3aSriastradh
4311677dec6eSriastradh gfx_v8_0_set_cpg_door_bell(adev, ring);
4312a30d5d3aSriastradh /* start the ring */
4313677dec6eSriastradh amdgpu_ring_clear_ring(ring);
4314a30d5d3aSriastradh gfx_v8_0_cp_gfx_start(adev);
4315677dec6eSriastradh ring->sched.ready = true;
4316a30d5d3aSriastradh
4317a30d5d3aSriastradh return 0;
4318a30d5d3aSriastradh }
4319a30d5d3aSriastradh
gfx_v8_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)4320a30d5d3aSriastradh static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4321a30d5d3aSriastradh {
4322a30d5d3aSriastradh int i;
4323a30d5d3aSriastradh
4324a30d5d3aSriastradh if (enable) {
4325a30d5d3aSriastradh WREG32(mmCP_MEC_CNTL, 0);
4326a30d5d3aSriastradh } else {
4327a30d5d3aSriastradh WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4328a30d5d3aSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++)
4329677dec6eSriastradh adev->gfx.compute_ring[i].sched.ready = false;
4330677dec6eSriastradh adev->gfx.kiq.ring.sched.ready = false;
4331a30d5d3aSriastradh }
4332a30d5d3aSriastradh udelay(50);
4333a30d5d3aSriastradh }
4334a30d5d3aSriastradh
4335677dec6eSriastradh /* KIQ functions */
gfx_v8_0_kiq_setting(struct amdgpu_ring * ring)4336677dec6eSriastradh static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
4337a30d5d3aSriastradh {
4338677dec6eSriastradh uint32_t tmp;
4339677dec6eSriastradh struct amdgpu_device *adev = ring->adev;
4340677dec6eSriastradh
4341677dec6eSriastradh /* tell RLC which is KIQ queue */
4342677dec6eSriastradh tmp = RREG32(mmRLC_CP_SCHEDULERS);
4343677dec6eSriastradh tmp &= 0xffffff00;
4344677dec6eSriastradh tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
4345677dec6eSriastradh WREG32(mmRLC_CP_SCHEDULERS, tmp);
4346677dec6eSriastradh tmp |= 0x80;
4347677dec6eSriastradh WREG32(mmRLC_CP_SCHEDULERS, tmp);
4348677dec6eSriastradh }
4349677dec6eSriastradh
gfx_v8_0_kiq_kcq_enable(struct amdgpu_device * adev)4350677dec6eSriastradh static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
4351677dec6eSriastradh {
4352677dec6eSriastradh struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4353677dec6eSriastradh uint64_t queue_mask = 0;
4354677dec6eSriastradh int r, i;
4355677dec6eSriastradh
4356677dec6eSriastradh for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
4357677dec6eSriastradh if (!test_bit(i, adev->gfx.mec.queue_bitmap))
4358677dec6eSriastradh continue;
4359677dec6eSriastradh
4360677dec6eSriastradh /* This situation may be hit in the future if a new HW
4361677dec6eSriastradh * generation exposes more than 64 queues. If so, the
4362677dec6eSriastradh * definition of queue_mask needs updating */
4363677dec6eSriastradh if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
4364677dec6eSriastradh DRM_ERROR("Invalid KCQ enabled: %d\n", i);
4365677dec6eSriastradh break;
4366677dec6eSriastradh }
4367677dec6eSriastradh
4368677dec6eSriastradh queue_mask |= (1ull << i);
4369677dec6eSriastradh }
4370677dec6eSriastradh
4371677dec6eSriastradh r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
4372677dec6eSriastradh if (r) {
4373677dec6eSriastradh DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4374677dec6eSriastradh return r;
4375677dec6eSriastradh }
4376677dec6eSriastradh /* set resources */
4377677dec6eSriastradh amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
4378677dec6eSriastradh amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
4379677dec6eSriastradh amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
4380677dec6eSriastradh amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
4381677dec6eSriastradh amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
4382677dec6eSriastradh amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
4383677dec6eSriastradh amdgpu_ring_write(kiq_ring, 0); /* oac mask */
4384677dec6eSriastradh amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
4385677dec6eSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4386677dec6eSriastradh struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4387677dec6eSriastradh uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
4388677dec6eSriastradh uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4389677dec6eSriastradh
4390677dec6eSriastradh /* map queues */
4391677dec6eSriastradh amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
4392677dec6eSriastradh /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
4393677dec6eSriastradh amdgpu_ring_write(kiq_ring,
4394677dec6eSriastradh PACKET3_MAP_QUEUES_NUM_QUEUES(1));
4395677dec6eSriastradh amdgpu_ring_write(kiq_ring,
4396677dec6eSriastradh PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) |
4397677dec6eSriastradh PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
4398677dec6eSriastradh PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
4399677dec6eSriastradh PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */
4400677dec6eSriastradh amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
4401677dec6eSriastradh amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
4402677dec6eSriastradh amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
4403677dec6eSriastradh amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
4404677dec6eSriastradh }
4405677dec6eSriastradh
4406677dec6eSriastradh amdgpu_ring_commit(kiq_ring);
4407a30d5d3aSriastradh
4408a30d5d3aSriastradh return 0;
4409a30d5d3aSriastradh }
4410a30d5d3aSriastradh
gfx_v8_0_deactivate_hqd(struct amdgpu_device * adev,u32 req)4411677dec6eSriastradh static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
4412a30d5d3aSriastradh {
4413677dec6eSriastradh int i, r = 0;
4414a30d5d3aSriastradh
4415677dec6eSriastradh if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
4416677dec6eSriastradh WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);
4417677dec6eSriastradh for (i = 0; i < adev->usec_timeout; i++) {
4418677dec6eSriastradh if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
4419677dec6eSriastradh break;
4420677dec6eSriastradh udelay(1);
4421677dec6eSriastradh }
4422677dec6eSriastradh if (i == adev->usec_timeout)
4423677dec6eSriastradh r = -ETIMEDOUT;
4424677dec6eSriastradh }
4425677dec6eSriastradh WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
4426677dec6eSriastradh WREG32(mmCP_HQD_PQ_RPTR, 0);
4427677dec6eSriastradh WREG32(mmCP_HQD_PQ_WPTR, 0);
4428a30d5d3aSriastradh
4429677dec6eSriastradh return r;
4430a30d5d3aSriastradh }
4431a30d5d3aSriastradh
gfx_v8_0_mqd_init(struct amdgpu_ring * ring)4432677dec6eSriastradh static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
4433a30d5d3aSriastradh {
4434677dec6eSriastradh struct amdgpu_device *adev = ring->adev;
4435677dec6eSriastradh struct vi_mqd *mqd = ring->mqd_ptr;
4436677dec6eSriastradh uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
4437677dec6eSriastradh uint32_t tmp;
4438a30d5d3aSriastradh
4439a30d5d3aSriastradh mqd->header = 0xC0310800;
4440a30d5d3aSriastradh mqd->compute_pipelinestat_enable = 0x00000001;
4441a30d5d3aSriastradh mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4442a30d5d3aSriastradh mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4443a30d5d3aSriastradh mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4444a30d5d3aSriastradh mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4445a30d5d3aSriastradh mqd->compute_misc_reserved = 0x00000003;
4446677dec6eSriastradh mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
4447677dec6eSriastradh + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4448677dec6eSriastradh mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
4449677dec6eSriastradh + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4450677dec6eSriastradh eop_base_addr = ring->eop_gpu_addr >> 8;
4451677dec6eSriastradh mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
4452677dec6eSriastradh mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
4453a30d5d3aSriastradh
4454677dec6eSriastradh /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4455677dec6eSriastradh tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4456677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4457677dec6eSriastradh (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1));
4458a30d5d3aSriastradh
4459677dec6eSriastradh mqd->cp_hqd_eop_control = tmp;
4460a30d5d3aSriastradh
4461a30d5d3aSriastradh /* enable doorbell? */
4462677dec6eSriastradh tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
4463677dec6eSriastradh CP_HQD_PQ_DOORBELL_CONTROL,
4464677dec6eSriastradh DOORBELL_EN,
4465677dec6eSriastradh ring->use_doorbell ? 1 : 0);
4466677dec6eSriastradh
4467a30d5d3aSriastradh mqd->cp_hqd_pq_doorbell_control = tmp;
4468a30d5d3aSriastradh
4469a30d5d3aSriastradh /* set the pointer to the MQD */
4470677dec6eSriastradh mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
4471677dec6eSriastradh mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
4472a30d5d3aSriastradh
4473a30d5d3aSriastradh /* set MQD vmid to 0 */
4474a30d5d3aSriastradh tmp = RREG32(mmCP_MQD_CONTROL);
4475a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4476a30d5d3aSriastradh mqd->cp_mqd_control = tmp;
4477a30d5d3aSriastradh
4478a30d5d3aSriastradh /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4479a30d5d3aSriastradh hqd_gpu_addr = ring->gpu_addr >> 8;
4480a30d5d3aSriastradh mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4481a30d5d3aSriastradh mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4482a30d5d3aSriastradh
4483a30d5d3aSriastradh /* set up the HQD, this is similar to CP_RB0_CNTL */
4484a30d5d3aSriastradh tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4485a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4486a30d5d3aSriastradh (order_base_2(ring->ring_size / 4) - 1));
4487a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4488a30d5d3aSriastradh ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4489a30d5d3aSriastradh #ifdef __BIG_ENDIAN
4490a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4491a30d5d3aSriastradh #endif
4492a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4493a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4494a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4495a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4496a30d5d3aSriastradh mqd->cp_hqd_pq_control = tmp;
4497a30d5d3aSriastradh
4498677dec6eSriastradh /* set the wb address whether it's enabled or not */
4499a30d5d3aSriastradh wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4500a30d5d3aSriastradh mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4501a30d5d3aSriastradh mqd->cp_hqd_pq_rptr_report_addr_hi =
4502a30d5d3aSriastradh upper_32_bits(wb_gpu_addr) & 0xffff;
4503a30d5d3aSriastradh
4504a30d5d3aSriastradh /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4505a30d5d3aSriastradh wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4506677dec6eSriastradh mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4507a30d5d3aSriastradh mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4508a30d5d3aSriastradh
4509677dec6eSriastradh tmp = 0;
4510a30d5d3aSriastradh /* enable the doorbell if requested */
4511677dec6eSriastradh if (ring->use_doorbell) {
4512a30d5d3aSriastradh tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4513a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4514a30d5d3aSriastradh DOORBELL_OFFSET, ring->doorbell_index);
4515a30d5d3aSriastradh
4516677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4517677dec6eSriastradh DOORBELL_EN, 1);
4518677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4519677dec6eSriastradh DOORBELL_SOURCE, 0);
4520677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4521677dec6eSriastradh DOORBELL_HIT, 0);
4522a30d5d3aSriastradh }
4523677dec6eSriastradh
4524677dec6eSriastradh mqd->cp_hqd_pq_doorbell_control = tmp;
4525a30d5d3aSriastradh
4526a30d5d3aSriastradh /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4527a30d5d3aSriastradh ring->wptr = 0;
4528a30d5d3aSriastradh mqd->cp_hqd_pq_wptr = ring->wptr;
4529a30d5d3aSriastradh mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4530a30d5d3aSriastradh
4531a30d5d3aSriastradh /* set the vmid for the queue */
4532a30d5d3aSriastradh mqd->cp_hqd_vmid = 0;
4533a30d5d3aSriastradh
4534a30d5d3aSriastradh tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4535a30d5d3aSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4536a30d5d3aSriastradh mqd->cp_hqd_persistent_state = tmp;
4537a30d5d3aSriastradh
4538677dec6eSriastradh /* set MTYPE */
4539677dec6eSriastradh tmp = RREG32(mmCP_HQD_IB_CONTROL);
4540677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
4541677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
4542677dec6eSriastradh mqd->cp_hqd_ib_control = tmp;
4543a30d5d3aSriastradh
4544677dec6eSriastradh tmp = RREG32(mmCP_HQD_IQ_TIMER);
4545677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
4546677dec6eSriastradh mqd->cp_hqd_iq_timer = tmp;
4547677dec6eSriastradh
4548677dec6eSriastradh tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
4549677dec6eSriastradh tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
4550677dec6eSriastradh mqd->cp_hqd_ctx_save_control = tmp;
4551677dec6eSriastradh
4552677dec6eSriastradh /* defaults */
4553677dec6eSriastradh mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
4554677dec6eSriastradh mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
4555677dec6eSriastradh mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
4556677dec6eSriastradh mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
4557677dec6eSriastradh mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
4558677dec6eSriastradh mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
4559677dec6eSriastradh mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
4560677dec6eSriastradh mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
4561677dec6eSriastradh mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
4562677dec6eSriastradh mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
4563677dec6eSriastradh mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
4564677dec6eSriastradh mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
4565677dec6eSriastradh mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
4566677dec6eSriastradh mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
4567677dec6eSriastradh mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
4568677dec6eSriastradh
4569677dec6eSriastradh /* map_queues packet doesn't need activate the queue,
4570677dec6eSriastradh * so only kiq need set this field.
4571677dec6eSriastradh */
4572677dec6eSriastradh if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
4573677dec6eSriastradh mqd->cp_hqd_active = 1;
4574677dec6eSriastradh
4575677dec6eSriastradh return 0;
4576677dec6eSriastradh }
4577677dec6eSriastradh
gfx_v8_0_mqd_commit(struct amdgpu_device * adev,struct vi_mqd * mqd)4578677dec6eSriastradh int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
4579677dec6eSriastradh struct vi_mqd *mqd)
4580677dec6eSriastradh {
4581677dec6eSriastradh uint32_t mqd_reg;
4582677dec6eSriastradh uint32_t *mqd_data;
4583677dec6eSriastradh
4584677dec6eSriastradh /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */
4585677dec6eSriastradh mqd_data = &mqd->cp_mqd_base_addr_lo;
4586677dec6eSriastradh
4587677dec6eSriastradh /* disable wptr polling */
4588677dec6eSriastradh WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
4589677dec6eSriastradh
4590677dec6eSriastradh /* program all HQD registers */
4591677dec6eSriastradh for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
4592677dec6eSriastradh WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4593677dec6eSriastradh
4594677dec6eSriastradh /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
4595677dec6eSriastradh * This is safe since EOP RPTR==WPTR for any inactive HQD
4596677dec6eSriastradh * on ASICs that do not support context-save.
4597677dec6eSriastradh * EOP writes/reads can start anywhere in the ring.
4598677dec6eSriastradh */
4599677dec6eSriastradh if (adev->asic_type != CHIP_TONGA) {
4600677dec6eSriastradh WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
4601677dec6eSriastradh WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
4602677dec6eSriastradh WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
4603677dec6eSriastradh }
4604677dec6eSriastradh
4605677dec6eSriastradh for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++)
4606677dec6eSriastradh WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4607677dec6eSriastradh
4608677dec6eSriastradh /* activate the HQD */
4609677dec6eSriastradh for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
4610677dec6eSriastradh WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4611677dec6eSriastradh
4612677dec6eSriastradh return 0;
4613677dec6eSriastradh }
4614677dec6eSriastradh
gfx_v8_0_kiq_init_queue(struct amdgpu_ring * ring)4615677dec6eSriastradh static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
4616677dec6eSriastradh {
4617677dec6eSriastradh struct amdgpu_device *adev = ring->adev;
4618677dec6eSriastradh struct vi_mqd *mqd = ring->mqd_ptr;
4619677dec6eSriastradh int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
4620677dec6eSriastradh
4621677dec6eSriastradh gfx_v8_0_kiq_setting(ring);
4622677dec6eSriastradh
4623677dec6eSriastradh if (adev->in_gpu_reset) { /* for GPU_RESET case */
4624677dec6eSriastradh /* reset MQD to a clean status */
4625677dec6eSriastradh if (adev->gfx.mec.mqd_backup[mqd_idx])
4626677dec6eSriastradh memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4627677dec6eSriastradh
4628677dec6eSriastradh /* reset ring buffer */
4629677dec6eSriastradh ring->wptr = 0;
4630677dec6eSriastradh amdgpu_ring_clear_ring(ring);
4631677dec6eSriastradh mutex_lock(&adev->srbm_mutex);
4632677dec6eSriastradh vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4633677dec6eSriastradh gfx_v8_0_mqd_commit(adev, mqd);
4634677dec6eSriastradh vi_srbm_select(adev, 0, 0, 0, 0);
4635677dec6eSriastradh mutex_unlock(&adev->srbm_mutex);
4636677dec6eSriastradh } else {
4637677dec6eSriastradh memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4638677dec6eSriastradh ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4639677dec6eSriastradh ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4640677dec6eSriastradh mutex_lock(&adev->srbm_mutex);
4641677dec6eSriastradh vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4642677dec6eSriastradh gfx_v8_0_mqd_init(ring);
4643677dec6eSriastradh gfx_v8_0_mqd_commit(adev, mqd);
4644a30d5d3aSriastradh vi_srbm_select(adev, 0, 0, 0, 0);
4645a30d5d3aSriastradh mutex_unlock(&adev->srbm_mutex);
4646a30d5d3aSriastradh
4647677dec6eSriastradh if (adev->gfx.mec.mqd_backup[mqd_idx])
4648677dec6eSriastradh memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4649677dec6eSriastradh }
4650677dec6eSriastradh
4651677dec6eSriastradh return 0;
4652677dec6eSriastradh }
4653677dec6eSriastradh
gfx_v8_0_kcq_init_queue(struct amdgpu_ring * ring)4654677dec6eSriastradh static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
4655677dec6eSriastradh {
4656677dec6eSriastradh struct amdgpu_device *adev = ring->adev;
4657677dec6eSriastradh struct vi_mqd *mqd = ring->mqd_ptr;
4658677dec6eSriastradh int mqd_idx = ring - &adev->gfx.compute_ring[0];
4659677dec6eSriastradh
4660677dec6eSriastradh if (!adev->in_gpu_reset && !adev->in_suspend) {
4661677dec6eSriastradh memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4662677dec6eSriastradh ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4663677dec6eSriastradh ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4664677dec6eSriastradh mutex_lock(&adev->srbm_mutex);
4665677dec6eSriastradh vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4666677dec6eSriastradh gfx_v8_0_mqd_init(ring);
4667677dec6eSriastradh vi_srbm_select(adev, 0, 0, 0, 0);
4668677dec6eSriastradh mutex_unlock(&adev->srbm_mutex);
4669677dec6eSriastradh
4670677dec6eSriastradh if (adev->gfx.mec.mqd_backup[mqd_idx])
4671677dec6eSriastradh memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4672677dec6eSriastradh } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
4673677dec6eSriastradh /* reset MQD to a clean status */
4674677dec6eSriastradh if (adev->gfx.mec.mqd_backup[mqd_idx])
4675677dec6eSriastradh memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4676677dec6eSriastradh /* reset ring buffer */
4677677dec6eSriastradh ring->wptr = 0;
4678677dec6eSriastradh amdgpu_ring_clear_ring(ring);
4679677dec6eSriastradh } else {
4680677dec6eSriastradh amdgpu_ring_clear_ring(ring);
4681677dec6eSriastradh }
4682677dec6eSriastradh return 0;
4683677dec6eSriastradh }
4684677dec6eSriastradh
gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device * adev)4685677dec6eSriastradh static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
4686677dec6eSriastradh {
4687677dec6eSriastradh if (adev->asic_type > CHIP_TONGA) {
4688677dec6eSriastradh WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);
4689677dec6eSriastradh WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);
4690677dec6eSriastradh }
4691677dec6eSriastradh /* enable doorbells */
4692677dec6eSriastradh WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4693677dec6eSriastradh }
4694677dec6eSriastradh
gfx_v8_0_kiq_resume(struct amdgpu_device * adev)4695677dec6eSriastradh static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
4696677dec6eSriastradh {
4697677dec6eSriastradh struct amdgpu_ring *ring;
4698677dec6eSriastradh int r;
4699677dec6eSriastradh
4700677dec6eSriastradh ring = &adev->gfx.kiq.ring;
4701677dec6eSriastradh
4702677dec6eSriastradh r = amdgpu_bo_reserve(ring->mqd_obj, false);
4703677dec6eSriastradh if (unlikely(r != 0))
4704677dec6eSriastradh return r;
4705677dec6eSriastradh
4706677dec6eSriastradh r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4707677dec6eSriastradh if (unlikely(r != 0))
4708677dec6eSriastradh return r;
4709677dec6eSriastradh
4710677dec6eSriastradh gfx_v8_0_kiq_init_queue(ring);
4711a30d5d3aSriastradh amdgpu_bo_kunmap(ring->mqd_obj);
4712677dec6eSriastradh ring->mqd_ptr = NULL;
4713a30d5d3aSriastradh amdgpu_bo_unreserve(ring->mqd_obj);
4714677dec6eSriastradh ring->sched.ready = true;
4715677dec6eSriastradh return 0;
4716a30d5d3aSriastradh }
4717a30d5d3aSriastradh
gfx_v8_0_kcq_resume(struct amdgpu_device * adev)4718677dec6eSriastradh static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
4719677dec6eSriastradh {
4720677dec6eSriastradh struct amdgpu_ring *ring = NULL;
4721677dec6eSriastradh int r = 0, i;
4722677dec6eSriastradh
4723677dec6eSriastradh gfx_v8_0_cp_compute_enable(adev, true);
4724677dec6eSriastradh
4725677dec6eSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4726677dec6eSriastradh ring = &adev->gfx.compute_ring[i];
4727677dec6eSriastradh
4728677dec6eSriastradh r = amdgpu_bo_reserve(ring->mqd_obj, false);
4729677dec6eSriastradh if (unlikely(r != 0))
4730677dec6eSriastradh goto done;
4731677dec6eSriastradh r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4732677dec6eSriastradh if (!r) {
4733677dec6eSriastradh r = gfx_v8_0_kcq_init_queue(ring);
4734677dec6eSriastradh amdgpu_bo_kunmap(ring->mqd_obj);
4735677dec6eSriastradh ring->mqd_ptr = NULL;
4736677dec6eSriastradh }
4737677dec6eSriastradh amdgpu_bo_unreserve(ring->mqd_obj);
4738677dec6eSriastradh if (r)
4739677dec6eSriastradh goto done;
4740a30d5d3aSriastradh }
4741a30d5d3aSriastradh
4742677dec6eSriastradh gfx_v8_0_set_mec_doorbell_range(adev);
4743677dec6eSriastradh
4744677dec6eSriastradh r = gfx_v8_0_kiq_kcq_enable(adev);
4745677dec6eSriastradh if (r)
4746677dec6eSriastradh goto done;
4747677dec6eSriastradh
4748677dec6eSriastradh done:
4749677dec6eSriastradh return r;
4750677dec6eSriastradh }
4751677dec6eSriastradh
gfx_v8_0_cp_test_all_rings(struct amdgpu_device * adev)4752677dec6eSriastradh static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)
4753677dec6eSriastradh {
4754677dec6eSriastradh int r, i;
4755677dec6eSriastradh struct amdgpu_ring *ring;
4756677dec6eSriastradh
4757677dec6eSriastradh /* collect all the ring_tests here, gfx, kiq, compute */
4758677dec6eSriastradh ring = &adev->gfx.gfx_ring[0];
4759677dec6eSriastradh r = amdgpu_ring_test_helper(ring);
4760677dec6eSriastradh if (r)
4761677dec6eSriastradh return r;
4762677dec6eSriastradh
4763677dec6eSriastradh ring = &adev->gfx.kiq.ring;
4764677dec6eSriastradh r = amdgpu_ring_test_helper(ring);
4765a30d5d3aSriastradh if (r)
4766a30d5d3aSriastradh return r;
4767a30d5d3aSriastradh
4768a30d5d3aSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4769677dec6eSriastradh ring = &adev->gfx.compute_ring[i];
4770677dec6eSriastradh amdgpu_ring_test_helper(ring);
4771a30d5d3aSriastradh }
4772a30d5d3aSriastradh
4773a30d5d3aSriastradh return 0;
4774a30d5d3aSriastradh }
4775a30d5d3aSriastradh
gfx_v8_0_cp_resume(struct amdgpu_device * adev)4776a30d5d3aSriastradh static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4777a30d5d3aSriastradh {
4778a30d5d3aSriastradh int r;
4779a30d5d3aSriastradh
4780a30d5d3aSriastradh if (!(adev->flags & AMD_IS_APU))
4781a30d5d3aSriastradh gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4782a30d5d3aSriastradh
4783677dec6eSriastradh r = gfx_v8_0_kiq_resume(adev);
4784a30d5d3aSriastradh if (r)
4785a30d5d3aSriastradh return r;
4786a30d5d3aSriastradh
4787a30d5d3aSriastradh r = gfx_v8_0_cp_gfx_resume(adev);
4788a30d5d3aSriastradh if (r)
4789a30d5d3aSriastradh return r;
4790a30d5d3aSriastradh
4791677dec6eSriastradh r = gfx_v8_0_kcq_resume(adev);
4792677dec6eSriastradh if (r)
4793677dec6eSriastradh return r;
4794677dec6eSriastradh
4795677dec6eSriastradh r = gfx_v8_0_cp_test_all_rings(adev);
4796a30d5d3aSriastradh if (r)
4797a30d5d3aSriastradh return r;
4798a30d5d3aSriastradh
4799a30d5d3aSriastradh gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4800a30d5d3aSriastradh
4801a30d5d3aSriastradh return 0;
4802a30d5d3aSriastradh }
4803a30d5d3aSriastradh
gfx_v8_0_cp_enable(struct amdgpu_device * adev,bool enable)4804a30d5d3aSriastradh static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4805a30d5d3aSriastradh {
4806a30d5d3aSriastradh gfx_v8_0_cp_gfx_enable(adev, enable);
4807a30d5d3aSriastradh gfx_v8_0_cp_compute_enable(adev, enable);
4808a30d5d3aSriastradh }
4809a30d5d3aSriastradh
gfx_v8_0_hw_init(void * handle)4810a30d5d3aSriastradh static int gfx_v8_0_hw_init(void *handle)
4811a30d5d3aSriastradh {
4812a30d5d3aSriastradh int r;
4813a30d5d3aSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4814a30d5d3aSriastradh
4815a30d5d3aSriastradh gfx_v8_0_init_golden_registers(adev);
4816677dec6eSriastradh gfx_v8_0_constants_init(adev);
4817a30d5d3aSriastradh
4818677dec6eSriastradh r = adev->gfx.rlc.funcs->resume(adev);
4819a30d5d3aSriastradh if (r)
4820a30d5d3aSriastradh return r;
4821a30d5d3aSriastradh
4822a30d5d3aSriastradh r = gfx_v8_0_cp_resume(adev);
4823677dec6eSriastradh
4824677dec6eSriastradh return r;
4825677dec6eSriastradh }
4826677dec6eSriastradh
gfx_v8_0_kcq_disable(struct amdgpu_device * adev)4827677dec6eSriastradh static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)
4828677dec6eSriastradh {
4829677dec6eSriastradh int r, i;
4830677dec6eSriastradh struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4831677dec6eSriastradh
4832677dec6eSriastradh r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
4833a30d5d3aSriastradh if (r)
4834677dec6eSriastradh DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4835677dec6eSriastradh
4836677dec6eSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4837677dec6eSriastradh struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4838677dec6eSriastradh
4839677dec6eSriastradh amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
4840677dec6eSriastradh amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
4841677dec6eSriastradh PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
4842677dec6eSriastradh PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
4843677dec6eSriastradh PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
4844677dec6eSriastradh PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
4845677dec6eSriastradh amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
4846677dec6eSriastradh amdgpu_ring_write(kiq_ring, 0);
4847677dec6eSriastradh amdgpu_ring_write(kiq_ring, 0);
4848677dec6eSriastradh amdgpu_ring_write(kiq_ring, 0);
4849677dec6eSriastradh }
4850677dec6eSriastradh r = amdgpu_ring_test_helper(kiq_ring);
4851677dec6eSriastradh if (r)
4852677dec6eSriastradh DRM_ERROR("KCQ disable failed\n");
4853a30d5d3aSriastradh
4854a30d5d3aSriastradh return r;
4855a30d5d3aSriastradh }
4856a30d5d3aSriastradh
gfx_v8_0_is_idle(void * handle)4857a30d5d3aSriastradh static bool gfx_v8_0_is_idle(void *handle)
4858a30d5d3aSriastradh {
4859a30d5d3aSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4860a30d5d3aSriastradh
4861677dec6eSriastradh if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
4862677dec6eSriastradh || RREG32(mmGRBM_STATUS2) != 0x8)
4863a30d5d3aSriastradh return false;
4864a30d5d3aSriastradh else
4865a30d5d3aSriastradh return true;
4866a30d5d3aSriastradh }
4867a30d5d3aSriastradh
gfx_v8_0_rlc_is_idle(void * handle)4868677dec6eSriastradh static bool gfx_v8_0_rlc_is_idle(void *handle)
4869a30d5d3aSriastradh {
4870677dec6eSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4871677dec6eSriastradh
4872677dec6eSriastradh if (RREG32(mmGRBM_STATUS2) != 0x8)
4873677dec6eSriastradh return false;
4874677dec6eSriastradh else
4875677dec6eSriastradh return true;
4876677dec6eSriastradh }
4877677dec6eSriastradh
gfx_v8_0_wait_for_rlc_idle(void * handle)4878677dec6eSriastradh static int gfx_v8_0_wait_for_rlc_idle(void *handle)
4879677dec6eSriastradh {
4880677dec6eSriastradh unsigned int i;
4881a30d5d3aSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4882a30d5d3aSriastradh
4883a30d5d3aSriastradh for (i = 0; i < adev->usec_timeout; i++) {
4884677dec6eSriastradh if (gfx_v8_0_rlc_is_idle(handle))
4885a30d5d3aSriastradh return 0;
4886677dec6eSriastradh
4887a30d5d3aSriastradh udelay(1);
4888a30d5d3aSriastradh }
4889a30d5d3aSriastradh return -ETIMEDOUT;
4890a30d5d3aSriastradh }
4891a30d5d3aSriastradh
gfx_v8_0_wait_for_idle(void * handle)4892677dec6eSriastradh static int gfx_v8_0_wait_for_idle(void *handle)
4893a30d5d3aSriastradh {
4894677dec6eSriastradh unsigned int i;
4895a30d5d3aSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4896a30d5d3aSriastradh
4897677dec6eSriastradh for (i = 0; i < adev->usec_timeout; i++) {
4898677dec6eSriastradh if (gfx_v8_0_is_idle(handle))
4899677dec6eSriastradh return 0;
4900a30d5d3aSriastradh
4901677dec6eSriastradh udelay(1);
4902a30d5d3aSriastradh }
4903677dec6eSriastradh return -ETIMEDOUT;
4904a30d5d3aSriastradh }
4905a30d5d3aSriastradh
gfx_v8_0_hw_fini(void * handle)4906677dec6eSriastradh static int gfx_v8_0_hw_fini(void *handle)
4907a30d5d3aSriastradh {
4908677dec6eSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4909677dec6eSriastradh
4910677dec6eSriastradh amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4911677dec6eSriastradh amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4912677dec6eSriastradh
4913677dec6eSriastradh amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
4914677dec6eSriastradh
4915677dec6eSriastradh amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0);
4916677dec6eSriastradh
4917677dec6eSriastradh /* disable KCQ to avoid CPC touch memory not valid anymore */
4918677dec6eSriastradh gfx_v8_0_kcq_disable(adev);
4919677dec6eSriastradh
4920677dec6eSriastradh if (amdgpu_sriov_vf(adev)) {
4921677dec6eSriastradh pr_debug("For SRIOV client, shouldn't do anything.\n");
4922677dec6eSriastradh return 0;
4923677dec6eSriastradh }
4924677dec6eSriastradh amdgpu_gfx_rlc_enter_safe_mode(adev);
4925677dec6eSriastradh if (!gfx_v8_0_wait_for_idle(adev))
4926677dec6eSriastradh gfx_v8_0_cp_enable(adev, false);
4927677dec6eSriastradh else
4928677dec6eSriastradh pr_err("cp is busy, skip halt cp\n");
4929677dec6eSriastradh if (!gfx_v8_0_wait_for_rlc_idle(adev))
4930677dec6eSriastradh adev->gfx.rlc.funcs->stop(adev);
4931677dec6eSriastradh else
4932677dec6eSriastradh pr_err("rlc is busy, skip halt rlc\n");
4933677dec6eSriastradh amdgpu_gfx_rlc_exit_safe_mode(adev);
4934677dec6eSriastradh
4935677dec6eSriastradh return 0;
4936677dec6eSriastradh }
4937677dec6eSriastradh
gfx_v8_0_suspend(void * handle)4938677dec6eSriastradh static int gfx_v8_0_suspend(void *handle)
4939677dec6eSriastradh {
4940677dec6eSriastradh return gfx_v8_0_hw_fini(handle);
4941677dec6eSriastradh }
4942677dec6eSriastradh
gfx_v8_0_resume(void * handle)4943677dec6eSriastradh static int gfx_v8_0_resume(void *handle)
4944677dec6eSriastradh {
4945677dec6eSriastradh return gfx_v8_0_hw_init(handle);
4946677dec6eSriastradh }
4947677dec6eSriastradh
gfx_v8_0_check_soft_reset(void * handle)4948677dec6eSriastradh static bool gfx_v8_0_check_soft_reset(void *handle)
4949677dec6eSriastradh {
4950677dec6eSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4951a30d5d3aSriastradh u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4952a30d5d3aSriastradh u32 tmp;
4953a30d5d3aSriastradh
4954a30d5d3aSriastradh /* GRBM_STATUS */
4955a30d5d3aSriastradh tmp = RREG32(mmGRBM_STATUS);
4956a30d5d3aSriastradh if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4957a30d5d3aSriastradh GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4958a30d5d3aSriastradh GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4959a30d5d3aSriastradh GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4960a30d5d3aSriastradh GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4961677dec6eSriastradh GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK |
4962677dec6eSriastradh GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4963a30d5d3aSriastradh grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4964a30d5d3aSriastradh GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4965a30d5d3aSriastradh grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4966a30d5d3aSriastradh GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4967a30d5d3aSriastradh srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4968a30d5d3aSriastradh SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4969a30d5d3aSriastradh }
4970a30d5d3aSriastradh
4971a30d5d3aSriastradh /* GRBM_STATUS2 */
4972a30d5d3aSriastradh tmp = RREG32(mmGRBM_STATUS2);
4973a30d5d3aSriastradh if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4974a30d5d3aSriastradh grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4975a30d5d3aSriastradh GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4976a30d5d3aSriastradh
4977677dec6eSriastradh if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
4978677dec6eSriastradh REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
4979677dec6eSriastradh REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
4980677dec6eSriastradh grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4981677dec6eSriastradh SOFT_RESET_CPF, 1);
4982677dec6eSriastradh grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4983677dec6eSriastradh SOFT_RESET_CPC, 1);
4984677dec6eSriastradh grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4985677dec6eSriastradh SOFT_RESET_CPG, 1);
4986677dec6eSriastradh srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
4987677dec6eSriastradh SOFT_RESET_GRBM, 1);
4988677dec6eSriastradh }
4989677dec6eSriastradh
4990a30d5d3aSriastradh /* SRBM_STATUS */
4991a30d5d3aSriastradh tmp = RREG32(mmSRBM_STATUS);
4992a30d5d3aSriastradh if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4993a30d5d3aSriastradh srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4994a30d5d3aSriastradh SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4995677dec6eSriastradh if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
4996677dec6eSriastradh srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4997677dec6eSriastradh SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
4998a30d5d3aSriastradh
4999a30d5d3aSriastradh if (grbm_soft_reset || srbm_soft_reset) {
5000677dec6eSriastradh adev->gfx.grbm_soft_reset = grbm_soft_reset;
5001677dec6eSriastradh adev->gfx.srbm_soft_reset = srbm_soft_reset;
5002677dec6eSriastradh return true;
5003677dec6eSriastradh } else {
5004677dec6eSriastradh adev->gfx.grbm_soft_reset = 0;
5005677dec6eSriastradh adev->gfx.srbm_soft_reset = 0;
5006677dec6eSriastradh return false;
5007677dec6eSriastradh }
5008677dec6eSriastradh }
5009a30d5d3aSriastradh
gfx_v8_0_pre_soft_reset(void * handle)5010677dec6eSriastradh static int gfx_v8_0_pre_soft_reset(void *handle)
5011677dec6eSriastradh {
5012677dec6eSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5013677dec6eSriastradh u32 grbm_soft_reset = 0;
5014677dec6eSriastradh
5015677dec6eSriastradh if ((!adev->gfx.grbm_soft_reset) &&
5016677dec6eSriastradh (!adev->gfx.srbm_soft_reset))
5017677dec6eSriastradh return 0;
5018677dec6eSriastradh
5019677dec6eSriastradh grbm_soft_reset = adev->gfx.grbm_soft_reset;
5020677dec6eSriastradh
5021677dec6eSriastradh /* stop the rlc */
5022677dec6eSriastradh adev->gfx.rlc.funcs->stop(adev);
5023677dec6eSriastradh
5024677dec6eSriastradh if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5025677dec6eSriastradh REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5026a30d5d3aSriastradh /* Disable GFX parsing/prefetching */
5027a30d5d3aSriastradh gfx_v8_0_cp_gfx_enable(adev, false);
5028a30d5d3aSriastradh
5029677dec6eSriastradh if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5030677dec6eSriastradh REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5031677dec6eSriastradh REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5032677dec6eSriastradh REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5033677dec6eSriastradh int i;
5034677dec6eSriastradh
5035677dec6eSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5036677dec6eSriastradh struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5037677dec6eSriastradh
5038677dec6eSriastradh mutex_lock(&adev->srbm_mutex);
5039677dec6eSriastradh vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5040677dec6eSriastradh gfx_v8_0_deactivate_hqd(adev, 2);
5041677dec6eSriastradh vi_srbm_select(adev, 0, 0, 0, 0);
5042677dec6eSriastradh mutex_unlock(&adev->srbm_mutex);
5043677dec6eSriastradh }
5044a30d5d3aSriastradh /* Disable MEC parsing/prefetching */
5045677dec6eSriastradh gfx_v8_0_cp_compute_enable(adev, false);
5046677dec6eSriastradh }
5047677dec6eSriastradh
5048677dec6eSriastradh return 0;
5049677dec6eSriastradh }
5050677dec6eSriastradh
gfx_v8_0_soft_reset(void * handle)5051677dec6eSriastradh static int gfx_v8_0_soft_reset(void *handle)
5052677dec6eSriastradh {
5053677dec6eSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5054677dec6eSriastradh u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5055677dec6eSriastradh u32 tmp;
5056677dec6eSriastradh
5057677dec6eSriastradh if ((!adev->gfx.grbm_soft_reset) &&
5058677dec6eSriastradh (!adev->gfx.srbm_soft_reset))
5059677dec6eSriastradh return 0;
5060677dec6eSriastradh
5061677dec6eSriastradh grbm_soft_reset = adev->gfx.grbm_soft_reset;
5062677dec6eSriastradh srbm_soft_reset = adev->gfx.srbm_soft_reset;
5063677dec6eSriastradh
5064677dec6eSriastradh if (grbm_soft_reset || srbm_soft_reset) {
5065677dec6eSriastradh tmp = RREG32(mmGMCON_DEBUG);
5066677dec6eSriastradh tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
5067677dec6eSriastradh tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
5068677dec6eSriastradh WREG32(mmGMCON_DEBUG, tmp);
5069677dec6eSriastradh udelay(50);
5070677dec6eSriastradh }
5071a30d5d3aSriastradh
5072a30d5d3aSriastradh if (grbm_soft_reset) {
5073a30d5d3aSriastradh tmp = RREG32(mmGRBM_SOFT_RESET);
5074a30d5d3aSriastradh tmp |= grbm_soft_reset;
5075a30d5d3aSriastradh dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5076a30d5d3aSriastradh WREG32(mmGRBM_SOFT_RESET, tmp);
5077a30d5d3aSriastradh tmp = RREG32(mmGRBM_SOFT_RESET);
5078a30d5d3aSriastradh
5079a30d5d3aSriastradh udelay(50);
5080a30d5d3aSriastradh
5081a30d5d3aSriastradh tmp &= ~grbm_soft_reset;
5082a30d5d3aSriastradh WREG32(mmGRBM_SOFT_RESET, tmp);
5083a30d5d3aSriastradh tmp = RREG32(mmGRBM_SOFT_RESET);
5084a30d5d3aSriastradh }
5085a30d5d3aSriastradh
5086a30d5d3aSriastradh if (srbm_soft_reset) {
5087a30d5d3aSriastradh tmp = RREG32(mmSRBM_SOFT_RESET);
5088a30d5d3aSriastradh tmp |= srbm_soft_reset;
5089a30d5d3aSriastradh dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5090a30d5d3aSriastradh WREG32(mmSRBM_SOFT_RESET, tmp);
5091a30d5d3aSriastradh tmp = RREG32(mmSRBM_SOFT_RESET);
5092a30d5d3aSriastradh
5093a30d5d3aSriastradh udelay(50);
5094a30d5d3aSriastradh
5095a30d5d3aSriastradh tmp &= ~srbm_soft_reset;
5096a30d5d3aSriastradh WREG32(mmSRBM_SOFT_RESET, tmp);
5097a30d5d3aSriastradh tmp = RREG32(mmSRBM_SOFT_RESET);
5098a30d5d3aSriastradh }
5099677dec6eSriastradh
5100677dec6eSriastradh if (grbm_soft_reset || srbm_soft_reset) {
5101677dec6eSriastradh tmp = RREG32(mmGMCON_DEBUG);
5102677dec6eSriastradh tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
5103677dec6eSriastradh tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
5104677dec6eSriastradh WREG32(mmGMCON_DEBUG, tmp);
5105677dec6eSriastradh }
5106677dec6eSriastradh
5107a30d5d3aSriastradh /* Wait a little for things to settle down */
5108a30d5d3aSriastradh udelay(50);
5109677dec6eSriastradh
5110677dec6eSriastradh return 0;
5111a30d5d3aSriastradh }
5112677dec6eSriastradh
gfx_v8_0_post_soft_reset(void * handle)5113677dec6eSriastradh static int gfx_v8_0_post_soft_reset(void *handle)
5114677dec6eSriastradh {
5115677dec6eSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5116677dec6eSriastradh u32 grbm_soft_reset = 0;
5117677dec6eSriastradh
5118677dec6eSriastradh if ((!adev->gfx.grbm_soft_reset) &&
5119677dec6eSriastradh (!adev->gfx.srbm_soft_reset))
5120677dec6eSriastradh return 0;
5121677dec6eSriastradh
5122677dec6eSriastradh grbm_soft_reset = adev->gfx.grbm_soft_reset;
5123677dec6eSriastradh
5124677dec6eSriastradh if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5125677dec6eSriastradh REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5126677dec6eSriastradh REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5127677dec6eSriastradh REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5128677dec6eSriastradh int i;
5129677dec6eSriastradh
5130677dec6eSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5131677dec6eSriastradh struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5132677dec6eSriastradh
5133677dec6eSriastradh mutex_lock(&adev->srbm_mutex);
5134677dec6eSriastradh vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5135677dec6eSriastradh gfx_v8_0_deactivate_hqd(adev, 2);
5136677dec6eSriastradh vi_srbm_select(adev, 0, 0, 0, 0);
5137677dec6eSriastradh mutex_unlock(&adev->srbm_mutex);
5138677dec6eSriastradh }
5139677dec6eSriastradh gfx_v8_0_kiq_resume(adev);
5140677dec6eSriastradh gfx_v8_0_kcq_resume(adev);
5141677dec6eSriastradh }
5142677dec6eSriastradh
5143677dec6eSriastradh if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5144677dec6eSriastradh REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5145677dec6eSriastradh gfx_v8_0_cp_gfx_resume(adev);
5146677dec6eSriastradh
5147677dec6eSriastradh gfx_v8_0_cp_test_all_rings(adev);
5148677dec6eSriastradh
5149677dec6eSriastradh adev->gfx.rlc.funcs->start(adev);
5150677dec6eSriastradh
5151a30d5d3aSriastradh return 0;
5152a30d5d3aSriastradh }
5153a30d5d3aSriastradh
5154a30d5d3aSriastradh /**
5155a30d5d3aSriastradh * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5156a30d5d3aSriastradh *
5157a30d5d3aSriastradh * @adev: amdgpu_device pointer
5158a30d5d3aSriastradh *
5159a30d5d3aSriastradh * Fetches a GPU clock counter snapshot.
5160a30d5d3aSriastradh * Returns the 64 bit clock counter snapshot.
5161a30d5d3aSriastradh */
gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device * adev)5162677dec6eSriastradh static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
5163a30d5d3aSriastradh {
5164a30d5d3aSriastradh uint64_t clock;
5165a30d5d3aSriastradh
5166a30d5d3aSriastradh mutex_lock(&adev->gfx.gpu_clock_mutex);
5167a30d5d3aSriastradh WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5168a30d5d3aSriastradh clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5169a30d5d3aSriastradh ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5170a30d5d3aSriastradh mutex_unlock(&adev->gfx.gpu_clock_mutex);
5171a30d5d3aSriastradh return clock;
5172a30d5d3aSriastradh }
5173a30d5d3aSriastradh
gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)5174a30d5d3aSriastradh static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5175a30d5d3aSriastradh uint32_t vmid,
5176a30d5d3aSriastradh uint32_t gds_base, uint32_t gds_size,
5177a30d5d3aSriastradh uint32_t gws_base, uint32_t gws_size,
5178a30d5d3aSriastradh uint32_t oa_base, uint32_t oa_size)
5179a30d5d3aSriastradh {
5180a30d5d3aSriastradh /* GDS Base */
5181a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5182a30d5d3aSriastradh amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5183a30d5d3aSriastradh WRITE_DATA_DST_SEL(0)));
5184a30d5d3aSriastradh amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5185a30d5d3aSriastradh amdgpu_ring_write(ring, 0);
5186a30d5d3aSriastradh amdgpu_ring_write(ring, gds_base);
5187a30d5d3aSriastradh
5188a30d5d3aSriastradh /* GDS Size */
5189a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5190a30d5d3aSriastradh amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5191a30d5d3aSriastradh WRITE_DATA_DST_SEL(0)));
5192a30d5d3aSriastradh amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5193a30d5d3aSriastradh amdgpu_ring_write(ring, 0);
5194a30d5d3aSriastradh amdgpu_ring_write(ring, gds_size);
5195a30d5d3aSriastradh
5196a30d5d3aSriastradh /* GWS */
5197a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5198a30d5d3aSriastradh amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5199a30d5d3aSriastradh WRITE_DATA_DST_SEL(0)));
5200a30d5d3aSriastradh amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5201a30d5d3aSriastradh amdgpu_ring_write(ring, 0);
5202a30d5d3aSriastradh amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5203a30d5d3aSriastradh
5204a30d5d3aSriastradh /* OA */
5205a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5206a30d5d3aSriastradh amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5207a30d5d3aSriastradh WRITE_DATA_DST_SEL(0)));
5208a30d5d3aSriastradh amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5209a30d5d3aSriastradh amdgpu_ring_write(ring, 0);
5210a30d5d3aSriastradh amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5211a30d5d3aSriastradh }
5212a30d5d3aSriastradh
wave_read_ind(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t address)5213677dec6eSriastradh static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5214677dec6eSriastradh {
5215677dec6eSriastradh WREG32(mmSQ_IND_INDEX,
5216677dec6eSriastradh (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5217677dec6eSriastradh (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5218677dec6eSriastradh (address << SQ_IND_INDEX__INDEX__SHIFT) |
5219677dec6eSriastradh (SQ_IND_INDEX__FORCE_READ_MASK));
5220677dec6eSriastradh return RREG32(mmSQ_IND_DATA);
5221677dec6eSriastradh }
5222677dec6eSriastradh
wave_read_regs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)5223677dec6eSriastradh static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
5224677dec6eSriastradh uint32_t wave, uint32_t thread,
5225677dec6eSriastradh uint32_t regno, uint32_t num, uint32_t *out)
5226677dec6eSriastradh {
5227677dec6eSriastradh WREG32(mmSQ_IND_INDEX,
5228677dec6eSriastradh (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5229677dec6eSriastradh (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5230677dec6eSriastradh (regno << SQ_IND_INDEX__INDEX__SHIFT) |
5231677dec6eSriastradh (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
5232677dec6eSriastradh (SQ_IND_INDEX__FORCE_READ_MASK) |
5233677dec6eSriastradh (SQ_IND_INDEX__AUTO_INCR_MASK));
5234677dec6eSriastradh while (num--)
5235677dec6eSriastradh *(out++) = RREG32(mmSQ_IND_DATA);
5236677dec6eSriastradh }
5237677dec6eSriastradh
gfx_v8_0_read_wave_data(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)5238677dec6eSriastradh static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5239677dec6eSriastradh {
5240677dec6eSriastradh /* type 0 wave data */
5241677dec6eSriastradh dst[(*no_fields)++] = 0;
5242677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
5243677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
5244677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
5245677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
5246677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
5247677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
5248677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
5249677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
5250677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
5251677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
5252677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
5253677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
5254677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
5255677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
5256677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
5257677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
5258677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
5259677dec6eSriastradh dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
5260677dec6eSriastradh }
5261677dec6eSriastradh
gfx_v8_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)5262677dec6eSriastradh static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
5263677dec6eSriastradh uint32_t wave, uint32_t start,
5264677dec6eSriastradh uint32_t size, uint32_t *dst)
5265677dec6eSriastradh {
5266677dec6eSriastradh wave_read_regs(
5267677dec6eSriastradh adev, simd, wave, 0,
5268677dec6eSriastradh start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
5269677dec6eSriastradh }
5270677dec6eSriastradh
5271677dec6eSriastradh
5272677dec6eSriastradh static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5273677dec6eSriastradh .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
5274677dec6eSriastradh .select_se_sh = &gfx_v8_0_select_se_sh,
5275677dec6eSriastradh .read_wave_data = &gfx_v8_0_read_wave_data,
5276677dec6eSriastradh .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5277677dec6eSriastradh .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
5278677dec6eSriastradh };
5279677dec6eSriastradh
gfx_v8_0_early_init(void * handle)5280a30d5d3aSriastradh static int gfx_v8_0_early_init(void *handle)
5281a30d5d3aSriastradh {
5282a30d5d3aSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5283a30d5d3aSriastradh
5284a30d5d3aSriastradh adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5285677dec6eSriastradh adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
5286677dec6eSriastradh adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
5287a30d5d3aSriastradh gfx_v8_0_set_ring_funcs(adev);
5288a30d5d3aSriastradh gfx_v8_0_set_irq_funcs(adev);
5289a30d5d3aSriastradh gfx_v8_0_set_gds_init(adev);
5290677dec6eSriastradh gfx_v8_0_set_rlc_funcs(adev);
5291a30d5d3aSriastradh
5292a30d5d3aSriastradh return 0;
5293a30d5d3aSriastradh }
5294a30d5d3aSriastradh
gfx_v8_0_late_init(void * handle)5295677dec6eSriastradh static int gfx_v8_0_late_init(void *handle)
5296677dec6eSriastradh {
5297677dec6eSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5298677dec6eSriastradh int r;
5299677dec6eSriastradh
5300677dec6eSriastradh r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5301677dec6eSriastradh if (r)
5302677dec6eSriastradh return r;
5303677dec6eSriastradh
5304677dec6eSriastradh r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5305677dec6eSriastradh if (r)
5306677dec6eSriastradh return r;
5307677dec6eSriastradh
5308677dec6eSriastradh /* requires IBs so do in late init after IB pool is initialized */
5309677dec6eSriastradh r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5310677dec6eSriastradh if (r)
5311677dec6eSriastradh return r;
5312677dec6eSriastradh
5313677dec6eSriastradh r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
5314677dec6eSriastradh if (r) {
5315677dec6eSriastradh DRM_ERROR("amdgpu_irq_get() failed to get IRQ for EDC, r: %d.\n", r);
5316677dec6eSriastradh return r;
5317677dec6eSriastradh }
5318677dec6eSriastradh
5319677dec6eSriastradh r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0);
5320677dec6eSriastradh if (r) {
5321677dec6eSriastradh DRM_ERROR(
5322677dec6eSriastradh "amdgpu_irq_get() failed to get IRQ for SQ, r: %d.\n",
5323677dec6eSriastradh r);
5324677dec6eSriastradh return r;
5325677dec6eSriastradh }
5326677dec6eSriastradh
5327677dec6eSriastradh return 0;
5328677dec6eSriastradh }
5329677dec6eSriastradh
gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device * adev,bool enable)5330677dec6eSriastradh static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5331677dec6eSriastradh bool enable)
5332677dec6eSriastradh {
5333677dec6eSriastradh if (((adev->asic_type == CHIP_POLARIS11) ||
5334677dec6eSriastradh (adev->asic_type == CHIP_POLARIS12) ||
5335677dec6eSriastradh (adev->asic_type == CHIP_VEGAM)) &&
5336677dec6eSriastradh adev->powerplay.pp_funcs->set_powergating_by_smu)
5337677dec6eSriastradh /* Send msg to SMU via Powerplay */
5338677dec6eSriastradh amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
5339677dec6eSriastradh
5340677dec6eSriastradh WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5341677dec6eSriastradh }
5342677dec6eSriastradh
gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device * adev,bool enable)5343677dec6eSriastradh static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5344677dec6eSriastradh bool enable)
5345677dec6eSriastradh {
5346677dec6eSriastradh WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
5347677dec6eSriastradh }
5348677dec6eSriastradh
polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device * adev,bool enable)5349677dec6eSriastradh static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
5350677dec6eSriastradh bool enable)
5351677dec6eSriastradh {
5352677dec6eSriastradh WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
5353677dec6eSriastradh }
5354677dec6eSriastradh
cz_enable_gfx_cg_power_gating(struct amdgpu_device * adev,bool enable)5355677dec6eSriastradh static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
5356677dec6eSriastradh bool enable)
5357677dec6eSriastradh {
5358677dec6eSriastradh WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
5359677dec6eSriastradh }
5360677dec6eSriastradh
cz_enable_gfx_pipeline_power_gating(struct amdgpu_device * adev,bool enable)5361677dec6eSriastradh static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
5362677dec6eSriastradh bool enable)
5363677dec6eSriastradh {
5364677dec6eSriastradh WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
5365677dec6eSriastradh
5366677dec6eSriastradh /* Read any GFX register to wake up GFX. */
5367677dec6eSriastradh if (!enable)
5368677dec6eSriastradh RREG32(mmDB_RENDER_CONTROL);
5369677dec6eSriastradh }
5370677dec6eSriastradh
cz_update_gfx_cg_power_gating(struct amdgpu_device * adev,bool enable)5371677dec6eSriastradh static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
5372677dec6eSriastradh bool enable)
5373677dec6eSriastradh {
5374677dec6eSriastradh if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
5375677dec6eSriastradh cz_enable_gfx_cg_power_gating(adev, true);
5376677dec6eSriastradh if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
5377677dec6eSriastradh cz_enable_gfx_pipeline_power_gating(adev, true);
5378677dec6eSriastradh } else {
5379677dec6eSriastradh cz_enable_gfx_cg_power_gating(adev, false);
5380677dec6eSriastradh cz_enable_gfx_pipeline_power_gating(adev, false);
5381677dec6eSriastradh }
5382677dec6eSriastradh }
5383677dec6eSriastradh
gfx_v8_0_set_powergating_state(void * handle,enum amd_powergating_state state)5384a30d5d3aSriastradh static int gfx_v8_0_set_powergating_state(void *handle,
5385a30d5d3aSriastradh enum amd_powergating_state state)
5386a30d5d3aSriastradh {
5387677dec6eSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5388677dec6eSriastradh bool enable = (state == AMD_PG_STATE_GATE);
5389677dec6eSriastradh
5390677dec6eSriastradh if (amdgpu_sriov_vf(adev))
5391677dec6eSriastradh return 0;
5392677dec6eSriastradh
5393677dec6eSriastradh if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5394677dec6eSriastradh AMD_PG_SUPPORT_RLC_SMU_HS |
5395677dec6eSriastradh AMD_PG_SUPPORT_CP |
5396677dec6eSriastradh AMD_PG_SUPPORT_GFX_DMG))
5397677dec6eSriastradh amdgpu_gfx_rlc_enter_safe_mode(adev);
5398677dec6eSriastradh switch (adev->asic_type) {
5399677dec6eSriastradh case CHIP_CARRIZO:
5400677dec6eSriastradh case CHIP_STONEY:
5401677dec6eSriastradh
5402677dec6eSriastradh if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
5403677dec6eSriastradh cz_enable_sck_slow_down_on_power_up(adev, true);
5404677dec6eSriastradh cz_enable_sck_slow_down_on_power_down(adev, true);
5405677dec6eSriastradh } else {
5406677dec6eSriastradh cz_enable_sck_slow_down_on_power_up(adev, false);
5407677dec6eSriastradh cz_enable_sck_slow_down_on_power_down(adev, false);
5408677dec6eSriastradh }
5409677dec6eSriastradh if (adev->pg_flags & AMD_PG_SUPPORT_CP)
5410677dec6eSriastradh cz_enable_cp_power_gating(adev, true);
5411677dec6eSriastradh else
5412677dec6eSriastradh cz_enable_cp_power_gating(adev, false);
5413677dec6eSriastradh
5414677dec6eSriastradh cz_update_gfx_cg_power_gating(adev, enable);
5415677dec6eSriastradh
5416677dec6eSriastradh if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5417677dec6eSriastradh gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5418677dec6eSriastradh else
5419677dec6eSriastradh gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5420677dec6eSriastradh
5421677dec6eSriastradh if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5422677dec6eSriastradh gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5423677dec6eSriastradh else
5424677dec6eSriastradh gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5425677dec6eSriastradh break;
5426677dec6eSriastradh case CHIP_POLARIS11:
5427677dec6eSriastradh case CHIP_POLARIS12:
5428677dec6eSriastradh case CHIP_VEGAM:
5429677dec6eSriastradh if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5430677dec6eSriastradh gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5431677dec6eSriastradh else
5432677dec6eSriastradh gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5433677dec6eSriastradh
5434677dec6eSriastradh if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5435677dec6eSriastradh gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5436677dec6eSriastradh else
5437677dec6eSriastradh gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5438677dec6eSriastradh
5439677dec6eSriastradh if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
5440677dec6eSriastradh polaris11_enable_gfx_quick_mg_power_gating(adev, true);
5441677dec6eSriastradh else
5442677dec6eSriastradh polaris11_enable_gfx_quick_mg_power_gating(adev, false);
5443677dec6eSriastradh break;
5444677dec6eSriastradh default:
5445677dec6eSriastradh break;
5446677dec6eSriastradh }
5447677dec6eSriastradh if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5448677dec6eSriastradh AMD_PG_SUPPORT_RLC_SMU_HS |
5449677dec6eSriastradh AMD_PG_SUPPORT_CP |
5450677dec6eSriastradh AMD_PG_SUPPORT_GFX_DMG))
5451677dec6eSriastradh amdgpu_gfx_rlc_exit_safe_mode(adev);
5452677dec6eSriastradh return 0;
5453677dec6eSriastradh }
5454677dec6eSriastradh
gfx_v8_0_get_clockgating_state(void * handle,u32 * flags)5455677dec6eSriastradh static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags)
5456677dec6eSriastradh {
5457677dec6eSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5458677dec6eSriastradh int data;
5459677dec6eSriastradh
5460677dec6eSriastradh if (amdgpu_sriov_vf(adev))
5461677dec6eSriastradh *flags = 0;
5462677dec6eSriastradh
5463677dec6eSriastradh /* AMD_CG_SUPPORT_GFX_MGCG */
5464677dec6eSriastradh data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5465677dec6eSriastradh if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK))
5466677dec6eSriastradh *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5467677dec6eSriastradh
5468677dec6eSriastradh /* AMD_CG_SUPPORT_GFX_CGLG */
5469677dec6eSriastradh data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5470677dec6eSriastradh if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5471677dec6eSriastradh *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5472677dec6eSriastradh
5473677dec6eSriastradh /* AMD_CG_SUPPORT_GFX_CGLS */
5474677dec6eSriastradh if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5475677dec6eSriastradh *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5476677dec6eSriastradh
5477677dec6eSriastradh /* AMD_CG_SUPPORT_GFX_CGTS */
5478677dec6eSriastradh data = RREG32(mmCGTS_SM_CTRL_REG);
5479677dec6eSriastradh if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK))
5480677dec6eSriastradh *flags |= AMD_CG_SUPPORT_GFX_CGTS;
5481677dec6eSriastradh
5482677dec6eSriastradh /* AMD_CG_SUPPORT_GFX_CGTS_LS */
5483677dec6eSriastradh if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK))
5484677dec6eSriastradh *flags |= AMD_CG_SUPPORT_GFX_CGTS_LS;
5485677dec6eSriastradh
5486677dec6eSriastradh /* AMD_CG_SUPPORT_GFX_RLC_LS */
5487677dec6eSriastradh data = RREG32(mmRLC_MEM_SLP_CNTL);
5488677dec6eSriastradh if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
5489677dec6eSriastradh *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
5490677dec6eSriastradh
5491677dec6eSriastradh /* AMD_CG_SUPPORT_GFX_CP_LS */
5492677dec6eSriastradh data = RREG32(mmCP_MEM_SLP_CNTL);
5493677dec6eSriastradh if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
5494677dec6eSriastradh *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
5495677dec6eSriastradh }
5496677dec6eSriastradh
gfx_v8_0_send_serdes_cmd(struct amdgpu_device * adev,uint32_t reg_addr,uint32_t cmd)5497677dec6eSriastradh static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
5498677dec6eSriastradh uint32_t reg_addr, uint32_t cmd)
5499677dec6eSriastradh {
5500677dec6eSriastradh uint32_t data;
5501677dec6eSriastradh
5502677dec6eSriastradh gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5503677dec6eSriastradh
5504677dec6eSriastradh WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5505677dec6eSriastradh WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5506677dec6eSriastradh
5507677dec6eSriastradh data = RREG32(mmRLC_SERDES_WR_CTRL);
5508677dec6eSriastradh if (adev->asic_type == CHIP_STONEY)
5509677dec6eSriastradh data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5510677dec6eSriastradh RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5511677dec6eSriastradh RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5512677dec6eSriastradh RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5513677dec6eSriastradh RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5514677dec6eSriastradh RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5515677dec6eSriastradh RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5516677dec6eSriastradh RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5517677dec6eSriastradh RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5518677dec6eSriastradh else
5519677dec6eSriastradh data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5520677dec6eSriastradh RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5521677dec6eSriastradh RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5522677dec6eSriastradh RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5523677dec6eSriastradh RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5524677dec6eSriastradh RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5525677dec6eSriastradh RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5526677dec6eSriastradh RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5527677dec6eSriastradh RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5528677dec6eSriastradh RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5529677dec6eSriastradh RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5530677dec6eSriastradh data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
5531677dec6eSriastradh (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5532677dec6eSriastradh (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5533677dec6eSriastradh (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
5534677dec6eSriastradh
5535677dec6eSriastradh WREG32(mmRLC_SERDES_WR_CTRL, data);
5536677dec6eSriastradh }
5537677dec6eSriastradh
5538677dec6eSriastradh #define MSG_ENTER_RLC_SAFE_MODE 1
5539677dec6eSriastradh #define MSG_EXIT_RLC_SAFE_MODE 0
5540677dec6eSriastradh #define RLC_GPR_REG2__REQ_MASK 0x00000001
5541677dec6eSriastradh #define RLC_GPR_REG2__REQ__SHIFT 0
5542677dec6eSriastradh #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5543677dec6eSriastradh #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5544677dec6eSriastradh
gfx_v8_0_is_rlc_enabled(struct amdgpu_device * adev)5545677dec6eSriastradh static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev)
5546677dec6eSriastradh {
5547677dec6eSriastradh uint32_t rlc_setting;
5548677dec6eSriastradh
5549677dec6eSriastradh rlc_setting = RREG32(mmRLC_CNTL);
5550677dec6eSriastradh if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
5551677dec6eSriastradh return false;
5552677dec6eSriastradh
5553677dec6eSriastradh return true;
5554677dec6eSriastradh }
5555677dec6eSriastradh
gfx_v8_0_set_safe_mode(struct amdgpu_device * adev)5556677dec6eSriastradh static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev)
5557677dec6eSriastradh {
5558677dec6eSriastradh uint32_t data;
5559677dec6eSriastradh unsigned i;
5560677dec6eSriastradh data = RREG32(mmRLC_CNTL);
5561677dec6eSriastradh data |= RLC_SAFE_MODE__CMD_MASK;
5562677dec6eSriastradh data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5563677dec6eSriastradh data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5564677dec6eSriastradh WREG32(mmRLC_SAFE_MODE, data);
5565677dec6eSriastradh
5566677dec6eSriastradh /* wait for RLC_SAFE_MODE */
5567677dec6eSriastradh for (i = 0; i < adev->usec_timeout; i++) {
5568677dec6eSriastradh if ((RREG32(mmRLC_GPM_STAT) &
5569677dec6eSriastradh (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5570677dec6eSriastradh RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5571677dec6eSriastradh (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5572677dec6eSriastradh RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5573677dec6eSriastradh break;
5574677dec6eSriastradh udelay(1);
5575677dec6eSriastradh }
5576677dec6eSriastradh for (i = 0; i < adev->usec_timeout; i++) {
5577677dec6eSriastradh if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5578677dec6eSriastradh break;
5579677dec6eSriastradh udelay(1);
5580677dec6eSriastradh }
5581677dec6eSriastradh }
5582677dec6eSriastradh
gfx_v8_0_unset_safe_mode(struct amdgpu_device * adev)5583677dec6eSriastradh static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev)
5584677dec6eSriastradh {
5585677dec6eSriastradh uint32_t data;
5586677dec6eSriastradh unsigned i;
5587677dec6eSriastradh
5588677dec6eSriastradh data = RREG32(mmRLC_CNTL);
5589677dec6eSriastradh data |= RLC_SAFE_MODE__CMD_MASK;
5590677dec6eSriastradh data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5591677dec6eSriastradh WREG32(mmRLC_SAFE_MODE, data);
5592677dec6eSriastradh
5593677dec6eSriastradh for (i = 0; i < adev->usec_timeout; i++) {
5594677dec6eSriastradh if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5595677dec6eSriastradh break;
5596677dec6eSriastradh udelay(1);
5597677dec6eSriastradh }
5598677dec6eSriastradh }
5599677dec6eSriastradh
5600677dec6eSriastradh static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5601677dec6eSriastradh .is_rlc_enabled = gfx_v8_0_is_rlc_enabled,
5602677dec6eSriastradh .set_safe_mode = gfx_v8_0_set_safe_mode,
5603677dec6eSriastradh .unset_safe_mode = gfx_v8_0_unset_safe_mode,
5604677dec6eSriastradh .init = gfx_v8_0_rlc_init,
5605677dec6eSriastradh .get_csb_size = gfx_v8_0_get_csb_size,
5606677dec6eSriastradh .get_csb_buffer = gfx_v8_0_get_csb_buffer,
5607677dec6eSriastradh .get_cp_table_num = gfx_v8_0_cp_jump_table_num,
5608677dec6eSriastradh .resume = gfx_v8_0_rlc_resume,
5609677dec6eSriastradh .stop = gfx_v8_0_rlc_stop,
5610677dec6eSriastradh .reset = gfx_v8_0_rlc_reset,
5611677dec6eSriastradh .start = gfx_v8_0_rlc_start
5612677dec6eSriastradh };
5613677dec6eSriastradh
gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)5614677dec6eSriastradh static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5615677dec6eSriastradh bool enable)
5616677dec6eSriastradh {
5617677dec6eSriastradh uint32_t temp, data;
5618677dec6eSriastradh
5619677dec6eSriastradh amdgpu_gfx_rlc_enter_safe_mode(adev);
5620677dec6eSriastradh
5621677dec6eSriastradh /* It is disabled by HW by default */
5622677dec6eSriastradh if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5623677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5624677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS)
5625677dec6eSriastradh /* 1 - RLC memory Light sleep */
5626677dec6eSriastradh WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);
5627677dec6eSriastradh
5628677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS)
5629677dec6eSriastradh WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);
5630677dec6eSriastradh }
5631677dec6eSriastradh
5632677dec6eSriastradh /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5633677dec6eSriastradh temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5634677dec6eSriastradh if (adev->flags & AMD_IS_APU)
5635677dec6eSriastradh data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5636677dec6eSriastradh RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5637677dec6eSriastradh RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5638677dec6eSriastradh else
5639677dec6eSriastradh data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5640677dec6eSriastradh RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5641677dec6eSriastradh RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5642677dec6eSriastradh RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5643677dec6eSriastradh
5644677dec6eSriastradh if (temp != data)
5645677dec6eSriastradh WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5646677dec6eSriastradh
5647677dec6eSriastradh /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5648677dec6eSriastradh gfx_v8_0_wait_for_rlc_serdes(adev);
5649677dec6eSriastradh
5650677dec6eSriastradh /* 5 - clear mgcg override */
5651677dec6eSriastradh gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5652677dec6eSriastradh
5653677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5654677dec6eSriastradh /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5655677dec6eSriastradh temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5656677dec6eSriastradh data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5657677dec6eSriastradh data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5658677dec6eSriastradh data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5659677dec6eSriastradh data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5660677dec6eSriastradh if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5661677dec6eSriastradh (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5662677dec6eSriastradh data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5663677dec6eSriastradh data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5664677dec6eSriastradh data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5665677dec6eSriastradh if (temp != data)
5666677dec6eSriastradh WREG32(mmCGTS_SM_CTRL_REG, data);
5667677dec6eSriastradh }
5668677dec6eSriastradh udelay(50);
5669677dec6eSriastradh
5670677dec6eSriastradh /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5671677dec6eSriastradh gfx_v8_0_wait_for_rlc_serdes(adev);
5672677dec6eSriastradh } else {
5673677dec6eSriastradh /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5674677dec6eSriastradh temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5675677dec6eSriastradh data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5676677dec6eSriastradh RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5677677dec6eSriastradh RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5678677dec6eSriastradh RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5679677dec6eSriastradh if (temp != data)
5680677dec6eSriastradh WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5681677dec6eSriastradh
5682677dec6eSriastradh /* 2 - disable MGLS in RLC */
5683677dec6eSriastradh data = RREG32(mmRLC_MEM_SLP_CNTL);
5684677dec6eSriastradh if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5685677dec6eSriastradh data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5686677dec6eSriastradh WREG32(mmRLC_MEM_SLP_CNTL, data);
5687677dec6eSriastradh }
5688677dec6eSriastradh
5689677dec6eSriastradh /* 3 - disable MGLS in CP */
5690677dec6eSriastradh data = RREG32(mmCP_MEM_SLP_CNTL);
5691677dec6eSriastradh if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5692677dec6eSriastradh data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5693677dec6eSriastradh WREG32(mmCP_MEM_SLP_CNTL, data);
5694677dec6eSriastradh }
5695677dec6eSriastradh
5696677dec6eSriastradh /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5697677dec6eSriastradh temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5698677dec6eSriastradh data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5699677dec6eSriastradh CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5700677dec6eSriastradh if (temp != data)
5701677dec6eSriastradh WREG32(mmCGTS_SM_CTRL_REG, data);
5702677dec6eSriastradh
5703677dec6eSriastradh /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5704677dec6eSriastradh gfx_v8_0_wait_for_rlc_serdes(adev);
5705677dec6eSriastradh
5706677dec6eSriastradh /* 6 - set mgcg override */
5707677dec6eSriastradh gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5708677dec6eSriastradh
5709677dec6eSriastradh udelay(50);
5710677dec6eSriastradh
5711677dec6eSriastradh /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5712677dec6eSriastradh gfx_v8_0_wait_for_rlc_serdes(adev);
5713677dec6eSriastradh }
5714677dec6eSriastradh
5715677dec6eSriastradh amdgpu_gfx_rlc_exit_safe_mode(adev);
5716677dec6eSriastradh }
5717677dec6eSriastradh
gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)5718677dec6eSriastradh static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5719677dec6eSriastradh bool enable)
5720677dec6eSriastradh {
5721677dec6eSriastradh uint32_t temp, temp1, data, data1;
5722677dec6eSriastradh
5723677dec6eSriastradh temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5724677dec6eSriastradh
5725677dec6eSriastradh amdgpu_gfx_rlc_enter_safe_mode(adev);
5726677dec6eSriastradh
5727677dec6eSriastradh if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5728677dec6eSriastradh temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5729677dec6eSriastradh data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5730677dec6eSriastradh if (temp1 != data1)
5731677dec6eSriastradh WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5732677dec6eSriastradh
5733677dec6eSriastradh /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5734677dec6eSriastradh gfx_v8_0_wait_for_rlc_serdes(adev);
5735677dec6eSriastradh
5736677dec6eSriastradh /* 2 - clear cgcg override */
5737677dec6eSriastradh gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5738677dec6eSriastradh
5739677dec6eSriastradh /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5740677dec6eSriastradh gfx_v8_0_wait_for_rlc_serdes(adev);
5741677dec6eSriastradh
5742677dec6eSriastradh /* 3 - write cmd to set CGLS */
5743677dec6eSriastradh gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
5744677dec6eSriastradh
5745677dec6eSriastradh /* 4 - enable cgcg */
5746677dec6eSriastradh data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5747677dec6eSriastradh
5748677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5749677dec6eSriastradh /* enable cgls*/
5750677dec6eSriastradh data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5751677dec6eSriastradh
5752677dec6eSriastradh temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5753677dec6eSriastradh data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
5754677dec6eSriastradh
5755677dec6eSriastradh if (temp1 != data1)
5756677dec6eSriastradh WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5757677dec6eSriastradh } else {
5758677dec6eSriastradh data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5759677dec6eSriastradh }
5760677dec6eSriastradh
5761677dec6eSriastradh if (temp != data)
5762677dec6eSriastradh WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5763677dec6eSriastradh
5764677dec6eSriastradh /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
5765677dec6eSriastradh * Cmp_busy/GFX_Idle interrupts
5766677dec6eSriastradh */
5767677dec6eSriastradh gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5768677dec6eSriastradh } else {
5769677dec6eSriastradh /* disable cntx_empty_int_enable & GFX Idle interrupt */
5770677dec6eSriastradh gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5771677dec6eSriastradh
5772677dec6eSriastradh /* TEST CGCG */
5773677dec6eSriastradh temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5774677dec6eSriastradh data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5775677dec6eSriastradh RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5776677dec6eSriastradh if (temp1 != data1)
5777677dec6eSriastradh WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5778677dec6eSriastradh
5779677dec6eSriastradh /* read gfx register to wake up cgcg */
5780677dec6eSriastradh RREG32(mmCB_CGTT_SCLK_CTRL);
5781677dec6eSriastradh RREG32(mmCB_CGTT_SCLK_CTRL);
5782677dec6eSriastradh RREG32(mmCB_CGTT_SCLK_CTRL);
5783677dec6eSriastradh RREG32(mmCB_CGTT_SCLK_CTRL);
5784677dec6eSriastradh
5785677dec6eSriastradh /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5786677dec6eSriastradh gfx_v8_0_wait_for_rlc_serdes(adev);
5787677dec6eSriastradh
5788677dec6eSriastradh /* write cmd to Set CGCG Overrride */
5789677dec6eSriastradh gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5790677dec6eSriastradh
5791677dec6eSriastradh /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5792677dec6eSriastradh gfx_v8_0_wait_for_rlc_serdes(adev);
5793677dec6eSriastradh
5794677dec6eSriastradh /* write cmd to Clear CGLS */
5795677dec6eSriastradh gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
5796677dec6eSriastradh
5797677dec6eSriastradh /* disable cgcg, cgls should be disabled too. */
5798677dec6eSriastradh data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
5799677dec6eSriastradh RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
5800677dec6eSriastradh if (temp != data)
5801677dec6eSriastradh WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5802677dec6eSriastradh /* enable interrupts again for PG */
5803677dec6eSriastradh gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5804677dec6eSriastradh }
5805677dec6eSriastradh
5806677dec6eSriastradh gfx_v8_0_wait_for_rlc_serdes(adev);
5807677dec6eSriastradh
5808677dec6eSriastradh amdgpu_gfx_rlc_exit_safe_mode(adev);
5809677dec6eSriastradh }
gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)5810677dec6eSriastradh static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5811677dec6eSriastradh bool enable)
5812677dec6eSriastradh {
5813677dec6eSriastradh if (enable) {
5814677dec6eSriastradh /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5815677dec6eSriastradh * === MGCG + MGLS + TS(CG/LS) ===
5816677dec6eSriastradh */
5817677dec6eSriastradh gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5818677dec6eSriastradh gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5819677dec6eSriastradh } else {
5820677dec6eSriastradh /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5821677dec6eSriastradh * === CGCG + CGLS ===
5822677dec6eSriastradh */
5823677dec6eSriastradh gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5824677dec6eSriastradh gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5825677dec6eSriastradh }
5826677dec6eSriastradh return 0;
5827677dec6eSriastradh }
5828677dec6eSriastradh
gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device * adev,enum amd_clockgating_state state)5829677dec6eSriastradh static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5830677dec6eSriastradh enum amd_clockgating_state state)
5831677dec6eSriastradh {
5832677dec6eSriastradh uint32_t msg_id, pp_state = 0;
5833677dec6eSriastradh uint32_t pp_support_state = 0;
5834677dec6eSriastradh
5835677dec6eSriastradh if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5836677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5837677dec6eSriastradh pp_support_state = PP_STATE_SUPPORT_LS;
5838677dec6eSriastradh pp_state = PP_STATE_LS;
5839677dec6eSriastradh }
5840677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5841677dec6eSriastradh pp_support_state |= PP_STATE_SUPPORT_CG;
5842677dec6eSriastradh pp_state |= PP_STATE_CG;
5843677dec6eSriastradh }
5844677dec6eSriastradh if (state == AMD_CG_STATE_UNGATE)
5845677dec6eSriastradh pp_state = 0;
5846677dec6eSriastradh
5847677dec6eSriastradh msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5848677dec6eSriastradh PP_BLOCK_GFX_CG,
5849677dec6eSriastradh pp_support_state,
5850677dec6eSriastradh pp_state);
5851677dec6eSriastradh if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5852677dec6eSriastradh amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5853677dec6eSriastradh }
5854677dec6eSriastradh
5855677dec6eSriastradh if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5856677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5857677dec6eSriastradh pp_support_state = PP_STATE_SUPPORT_LS;
5858677dec6eSriastradh pp_state = PP_STATE_LS;
5859677dec6eSriastradh }
5860677dec6eSriastradh
5861677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5862677dec6eSriastradh pp_support_state |= PP_STATE_SUPPORT_CG;
5863677dec6eSriastradh pp_state |= PP_STATE_CG;
5864677dec6eSriastradh }
5865677dec6eSriastradh
5866677dec6eSriastradh if (state == AMD_CG_STATE_UNGATE)
5867677dec6eSriastradh pp_state = 0;
5868677dec6eSriastradh
5869677dec6eSriastradh msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5870677dec6eSriastradh PP_BLOCK_GFX_MG,
5871677dec6eSriastradh pp_support_state,
5872677dec6eSriastradh pp_state);
5873677dec6eSriastradh if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5874677dec6eSriastradh amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5875677dec6eSriastradh }
5876677dec6eSriastradh
5877677dec6eSriastradh return 0;
5878677dec6eSriastradh }
5879677dec6eSriastradh
gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device * adev,enum amd_clockgating_state state)5880677dec6eSriastradh static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
5881677dec6eSriastradh enum amd_clockgating_state state)
5882677dec6eSriastradh {
5883677dec6eSriastradh
5884677dec6eSriastradh uint32_t msg_id, pp_state = 0;
5885677dec6eSriastradh uint32_t pp_support_state = 0;
5886677dec6eSriastradh
5887677dec6eSriastradh if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5888677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5889677dec6eSriastradh pp_support_state = PP_STATE_SUPPORT_LS;
5890677dec6eSriastradh pp_state = PP_STATE_LS;
5891677dec6eSriastradh }
5892677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5893677dec6eSriastradh pp_support_state |= PP_STATE_SUPPORT_CG;
5894677dec6eSriastradh pp_state |= PP_STATE_CG;
5895677dec6eSriastradh }
5896677dec6eSriastradh if (state == AMD_CG_STATE_UNGATE)
5897677dec6eSriastradh pp_state = 0;
5898677dec6eSriastradh
5899677dec6eSriastradh msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5900677dec6eSriastradh PP_BLOCK_GFX_CG,
5901677dec6eSriastradh pp_support_state,
5902677dec6eSriastradh pp_state);
5903677dec6eSriastradh if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5904677dec6eSriastradh amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5905677dec6eSriastradh }
5906677dec6eSriastradh
5907677dec6eSriastradh if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
5908677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
5909677dec6eSriastradh pp_support_state = PP_STATE_SUPPORT_LS;
5910677dec6eSriastradh pp_state = PP_STATE_LS;
5911677dec6eSriastradh }
5912677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
5913677dec6eSriastradh pp_support_state |= PP_STATE_SUPPORT_CG;
5914677dec6eSriastradh pp_state |= PP_STATE_CG;
5915677dec6eSriastradh }
5916677dec6eSriastradh if (state == AMD_CG_STATE_UNGATE)
5917677dec6eSriastradh pp_state = 0;
5918677dec6eSriastradh
5919677dec6eSriastradh msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5920677dec6eSriastradh PP_BLOCK_GFX_3D,
5921677dec6eSriastradh pp_support_state,
5922677dec6eSriastradh pp_state);
5923677dec6eSriastradh if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5924677dec6eSriastradh amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5925677dec6eSriastradh }
5926677dec6eSriastradh
5927677dec6eSriastradh if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5928677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5929677dec6eSriastradh pp_support_state = PP_STATE_SUPPORT_LS;
5930677dec6eSriastradh pp_state = PP_STATE_LS;
5931677dec6eSriastradh }
5932677dec6eSriastradh
5933677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5934677dec6eSriastradh pp_support_state |= PP_STATE_SUPPORT_CG;
5935677dec6eSriastradh pp_state |= PP_STATE_CG;
5936677dec6eSriastradh }
5937677dec6eSriastradh
5938677dec6eSriastradh if (state == AMD_CG_STATE_UNGATE)
5939677dec6eSriastradh pp_state = 0;
5940677dec6eSriastradh
5941677dec6eSriastradh msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5942677dec6eSriastradh PP_BLOCK_GFX_MG,
5943677dec6eSriastradh pp_support_state,
5944677dec6eSriastradh pp_state);
5945677dec6eSriastradh if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5946677dec6eSriastradh amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5947677dec6eSriastradh }
5948677dec6eSriastradh
5949677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5950677dec6eSriastradh pp_support_state = PP_STATE_SUPPORT_LS;
5951677dec6eSriastradh
5952677dec6eSriastradh if (state == AMD_CG_STATE_UNGATE)
5953677dec6eSriastradh pp_state = 0;
5954677dec6eSriastradh else
5955677dec6eSriastradh pp_state = PP_STATE_LS;
5956677dec6eSriastradh
5957677dec6eSriastradh msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5958677dec6eSriastradh PP_BLOCK_GFX_RLC,
5959677dec6eSriastradh pp_support_state,
5960677dec6eSriastradh pp_state);
5961677dec6eSriastradh if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5962677dec6eSriastradh amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5963677dec6eSriastradh }
5964677dec6eSriastradh
5965677dec6eSriastradh if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5966677dec6eSriastradh pp_support_state = PP_STATE_SUPPORT_LS;
5967677dec6eSriastradh
5968677dec6eSriastradh if (state == AMD_CG_STATE_UNGATE)
5969677dec6eSriastradh pp_state = 0;
5970677dec6eSriastradh else
5971677dec6eSriastradh pp_state = PP_STATE_LS;
5972677dec6eSriastradh msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5973677dec6eSriastradh PP_BLOCK_GFX_CP,
5974677dec6eSriastradh pp_support_state,
5975677dec6eSriastradh pp_state);
5976677dec6eSriastradh if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5977677dec6eSriastradh amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5978677dec6eSriastradh }
5979677dec6eSriastradh
5980a30d5d3aSriastradh return 0;
5981a30d5d3aSriastradh }
5982a30d5d3aSriastradh
gfx_v8_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)5983a30d5d3aSriastradh static int gfx_v8_0_set_clockgating_state(void *handle,
5984a30d5d3aSriastradh enum amd_clockgating_state state)
5985a30d5d3aSriastradh {
5986677dec6eSriastradh struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5987677dec6eSriastradh
5988677dec6eSriastradh if (amdgpu_sriov_vf(adev))
5989677dec6eSriastradh return 0;
5990677dec6eSriastradh
5991677dec6eSriastradh switch (adev->asic_type) {
5992677dec6eSriastradh case CHIP_FIJI:
5993677dec6eSriastradh case CHIP_CARRIZO:
5994677dec6eSriastradh case CHIP_STONEY:
5995677dec6eSriastradh gfx_v8_0_update_gfx_clock_gating(adev,
5996677dec6eSriastradh state == AMD_CG_STATE_GATE);
5997677dec6eSriastradh break;
5998677dec6eSriastradh case CHIP_TONGA:
5999677dec6eSriastradh gfx_v8_0_tonga_update_gfx_clock_gating(adev, state);
6000677dec6eSriastradh break;
6001677dec6eSriastradh case CHIP_POLARIS10:
6002677dec6eSriastradh case CHIP_POLARIS11:
6003677dec6eSriastradh case CHIP_POLARIS12:
6004677dec6eSriastradh case CHIP_VEGAM:
6005677dec6eSriastradh gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
6006677dec6eSriastradh break;
6007677dec6eSriastradh default:
6008677dec6eSriastradh break;
6009677dec6eSriastradh }
6010a30d5d3aSriastradh return 0;
6011a30d5d3aSriastradh }
6012a30d5d3aSriastradh
gfx_v8_0_ring_get_rptr(struct amdgpu_ring * ring)6013677dec6eSriastradh static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
6014a30d5d3aSriastradh {
6015677dec6eSriastradh return ring->adev->wb.wb[ring->rptr_offs];
6016a30d5d3aSriastradh }
6017a30d5d3aSriastradh
gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)6018677dec6eSriastradh static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
6019a30d5d3aSriastradh {
6020a30d5d3aSriastradh struct amdgpu_device *adev = ring->adev;
6021a30d5d3aSriastradh
6022a30d5d3aSriastradh if (ring->use_doorbell)
6023a30d5d3aSriastradh /* XXX check if swapping is necessary on BE */
6024677dec6eSriastradh return ring->adev->wb.wb[ring->wptr_offs];
6025a30d5d3aSriastradh else
6026677dec6eSriastradh return RREG32(mmCP_RB0_WPTR);
6027a30d5d3aSriastradh }
6028a30d5d3aSriastradh
gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)6029a30d5d3aSriastradh static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
6030a30d5d3aSriastradh {
6031a30d5d3aSriastradh struct amdgpu_device *adev = ring->adev;
6032a30d5d3aSriastradh
6033a30d5d3aSriastradh if (ring->use_doorbell) {
6034a30d5d3aSriastradh /* XXX check if swapping is necessary on BE */
6035677dec6eSriastradh adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6036677dec6eSriastradh WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6037a30d5d3aSriastradh } else {
6038677dec6eSriastradh WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6039a30d5d3aSriastradh (void)RREG32(mmCP_RB0_WPTR);
6040a30d5d3aSriastradh }
6041a30d5d3aSriastradh }
6042a30d5d3aSriastradh
gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)6043a30d5d3aSriastradh static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
6044a30d5d3aSriastradh {
6045a30d5d3aSriastradh u32 ref_and_mask, reg_mem_engine;
6046a30d5d3aSriastradh
6047677dec6eSriastradh if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) ||
6048677dec6eSriastradh (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) {
6049a30d5d3aSriastradh switch (ring->me) {
6050a30d5d3aSriastradh case 1:
6051a30d5d3aSriastradh ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
6052a30d5d3aSriastradh break;
6053a30d5d3aSriastradh case 2:
6054a30d5d3aSriastradh ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
6055a30d5d3aSriastradh break;
6056a30d5d3aSriastradh default:
6057a30d5d3aSriastradh return;
6058a30d5d3aSriastradh }
6059a30d5d3aSriastradh reg_mem_engine = 0;
6060a30d5d3aSriastradh } else {
6061a30d5d3aSriastradh ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
6062a30d5d3aSriastradh reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
6063a30d5d3aSriastradh }
6064a30d5d3aSriastradh
6065a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6066a30d5d3aSriastradh amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
6067a30d5d3aSriastradh WAIT_REG_MEM_FUNCTION(3) | /* == */
6068a30d5d3aSriastradh reg_mem_engine));
6069a30d5d3aSriastradh amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
6070a30d5d3aSriastradh amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
6071a30d5d3aSriastradh amdgpu_ring_write(ring, ref_and_mask);
6072a30d5d3aSriastradh amdgpu_ring_write(ring, ref_and_mask);
6073a30d5d3aSriastradh amdgpu_ring_write(ring, 0x20); /* poll interval */
6074a30d5d3aSriastradh }
6075a30d5d3aSriastradh
gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring * ring)6076677dec6eSriastradh static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
6077a30d5d3aSriastradh {
6078677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6079677dec6eSriastradh amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
6080677dec6eSriastradh EVENT_INDEX(4));
6081a30d5d3aSriastradh
6082677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6083677dec6eSriastradh amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
6084677dec6eSriastradh EVENT_INDEX(0));
6085a30d5d3aSriastradh }
6086a30d5d3aSriastradh
gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)6087677dec6eSriastradh static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6088677dec6eSriastradh struct amdgpu_job *job,
6089677dec6eSriastradh struct amdgpu_ib *ib,
6090677dec6eSriastradh uint32_t flags)
6091677dec6eSriastradh {
6092677dec6eSriastradh unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6093677dec6eSriastradh u32 header, control = 0;
6094677dec6eSriastradh
6095a30d5d3aSriastradh if (ib->flags & AMDGPU_IB_FLAG_CE)
6096a30d5d3aSriastradh header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
6097a30d5d3aSriastradh else
6098a30d5d3aSriastradh header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
6099a30d5d3aSriastradh
6100677dec6eSriastradh control |= ib->length_dw | (vmid << 24);
6101677dec6eSriastradh
6102677dec6eSriastradh if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
6103677dec6eSriastradh control |= INDIRECT_BUFFER_PRE_ENB(1);
6104677dec6eSriastradh
6105677dec6eSriastradh if (!(ib->flags & AMDGPU_IB_FLAG_CE))
6106677dec6eSriastradh gfx_v8_0_ring_emit_de_meta(ring);
6107677dec6eSriastradh }
6108a30d5d3aSriastradh
6109a30d5d3aSriastradh amdgpu_ring_write(ring, header);
6110a30d5d3aSriastradh amdgpu_ring_write(ring,
6111a30d5d3aSriastradh #ifdef __BIG_ENDIAN
6112a30d5d3aSriastradh (2 << 0) |
6113a30d5d3aSriastradh #endif
6114a30d5d3aSriastradh (ib->gpu_addr & 0xFFFFFFFC));
6115a30d5d3aSriastradh amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6116a30d5d3aSriastradh amdgpu_ring_write(ring, control);
6117a30d5d3aSriastradh }
6118a30d5d3aSriastradh
gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)6119a30d5d3aSriastradh static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
6120677dec6eSriastradh struct amdgpu_job *job,
6121677dec6eSriastradh struct amdgpu_ib *ib,
6122677dec6eSriastradh uint32_t flags)
6123a30d5d3aSriastradh {
6124677dec6eSriastradh unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6125677dec6eSriastradh u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
6126a30d5d3aSriastradh
6127677dec6eSriastradh /* Currently, there is a high possibility to get wave ID mismatch
6128677dec6eSriastradh * between ME and GDS, leading to a hw deadlock, because ME generates
6129677dec6eSriastradh * different wave IDs than the GDS expects. This situation happens
6130677dec6eSriastradh * randomly when at least 5 compute pipes use GDS ordered append.
6131677dec6eSriastradh * The wave IDs generated by ME are also wrong after suspend/resume.
6132677dec6eSriastradh * Those are probably bugs somewhere else in the kernel driver.
6133677dec6eSriastradh *
6134677dec6eSriastradh * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
6135677dec6eSriastradh * GDS to 0 for this ring (me/pipe).
6136677dec6eSriastradh */
6137677dec6eSriastradh if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
6138677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
6139677dec6eSriastradh amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
6140677dec6eSriastradh amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
6141677dec6eSriastradh }
6142a30d5d3aSriastradh
6143677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
6144a30d5d3aSriastradh amdgpu_ring_write(ring,
6145a30d5d3aSriastradh #ifdef __BIG_ENDIAN
6146a30d5d3aSriastradh (2 << 0) |
6147a30d5d3aSriastradh #endif
6148a30d5d3aSriastradh (ib->gpu_addr & 0xFFFFFFFC));
6149a30d5d3aSriastradh amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6150a30d5d3aSriastradh amdgpu_ring_write(ring, control);
6151a30d5d3aSriastradh }
6152a30d5d3aSriastradh
gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)6153a30d5d3aSriastradh static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
6154a30d5d3aSriastradh u64 seq, unsigned flags)
6155a30d5d3aSriastradh {
6156a30d5d3aSriastradh bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6157a30d5d3aSriastradh bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6158a30d5d3aSriastradh
6159677dec6eSriastradh /* Workaround for cache flush problems. First send a dummy EOP
6160677dec6eSriastradh * event down the pipe with seq one below.
6161677dec6eSriastradh */
6162a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6163a30d5d3aSriastradh amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6164a30d5d3aSriastradh EOP_TC_ACTION_EN |
6165677dec6eSriastradh EOP_TC_WB_ACTION_EN |
6166677dec6eSriastradh EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6167677dec6eSriastradh EVENT_INDEX(5)));
6168677dec6eSriastradh amdgpu_ring_write(ring, addr & 0xfffffffc);
6169677dec6eSriastradh amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6170677dec6eSriastradh DATA_SEL(1) | INT_SEL(0));
6171677dec6eSriastradh amdgpu_ring_write(ring, lower_32_bits(seq - 1));
6172677dec6eSriastradh amdgpu_ring_write(ring, upper_32_bits(seq - 1));
6173677dec6eSriastradh
6174677dec6eSriastradh /* Then send the real EOP event down the pipe:
6175677dec6eSriastradh * EVENT_WRITE_EOP - flush caches, send int */
6176677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6177677dec6eSriastradh amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6178677dec6eSriastradh EOP_TC_ACTION_EN |
6179677dec6eSriastradh EOP_TC_WB_ACTION_EN |
6180a30d5d3aSriastradh EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6181a30d5d3aSriastradh EVENT_INDEX(5)));
6182a30d5d3aSriastradh amdgpu_ring_write(ring, addr & 0xfffffffc);
6183a30d5d3aSriastradh amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6184a30d5d3aSriastradh DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6185a30d5d3aSriastradh amdgpu_ring_write(ring, lower_32_bits(seq));
6186a30d5d3aSriastradh amdgpu_ring_write(ring, upper_32_bits(seq));
6187a30d5d3aSriastradh
6188a30d5d3aSriastradh }
6189a30d5d3aSriastradh
gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)6190677dec6eSriastradh static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
6191a30d5d3aSriastradh {
6192677dec6eSriastradh int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6193677dec6eSriastradh uint32_t seq = ring->fence_drv.sync_seq;
6194a30d5d3aSriastradh uint64_t addr = ring->fence_drv.gpu_addr;
6195a30d5d3aSriastradh
6196a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6197a30d5d3aSriastradh amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
6198a30d5d3aSriastradh WAIT_REG_MEM_FUNCTION(3) | /* equal */
6199a30d5d3aSriastradh WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
6200a30d5d3aSriastradh amdgpu_ring_write(ring, addr & 0xfffffffc);
6201a30d5d3aSriastradh amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
6202a30d5d3aSriastradh amdgpu_ring_write(ring, seq);
6203a30d5d3aSriastradh amdgpu_ring_write(ring, 0xffffffff);
6204a30d5d3aSriastradh amdgpu_ring_write(ring, 4); /* poll interval */
6205a30d5d3aSriastradh }
6206a30d5d3aSriastradh
gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)6207677dec6eSriastradh static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6208677dec6eSriastradh unsigned vmid, uint64_t pd_addr)
6209677dec6eSriastradh {
6210677dec6eSriastradh int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6211a30d5d3aSriastradh
6212677dec6eSriastradh amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
6213a30d5d3aSriastradh
6214a30d5d3aSriastradh /* wait for the invalidate to complete */
6215a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6216a30d5d3aSriastradh amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6217a30d5d3aSriastradh WAIT_REG_MEM_FUNCTION(0) | /* always */
6218a30d5d3aSriastradh WAIT_REG_MEM_ENGINE(0))); /* me */
6219a30d5d3aSriastradh amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6220a30d5d3aSriastradh amdgpu_ring_write(ring, 0);
6221a30d5d3aSriastradh amdgpu_ring_write(ring, 0); /* ref */
6222a30d5d3aSriastradh amdgpu_ring_write(ring, 0); /* mask */
6223a30d5d3aSriastradh amdgpu_ring_write(ring, 0x20); /* poll interval */
6224a30d5d3aSriastradh
6225a30d5d3aSriastradh /* compute doesn't have PFP */
6226a30d5d3aSriastradh if (usepfp) {
6227a30d5d3aSriastradh /* sync PFP to ME, otherwise we might get invalid PFP reads */
6228a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6229a30d5d3aSriastradh amdgpu_ring_write(ring, 0x0);
6230a30d5d3aSriastradh }
6231a30d5d3aSriastradh }
6232a30d5d3aSriastradh
gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring * ring)6233677dec6eSriastradh static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6234a30d5d3aSriastradh {
6235a30d5d3aSriastradh return ring->adev->wb.wb[ring->wptr_offs];
6236a30d5d3aSriastradh }
6237a30d5d3aSriastradh
gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring * ring)6238a30d5d3aSriastradh static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6239a30d5d3aSriastradh {
6240a30d5d3aSriastradh struct amdgpu_device *adev = ring->adev;
6241a30d5d3aSriastradh
6242a30d5d3aSriastradh /* XXX check if swapping is necessary on BE */
6243677dec6eSriastradh adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6244677dec6eSriastradh WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6245677dec6eSriastradh }
6246677dec6eSriastradh
gfx_v8_0_ring_set_pipe_percent(struct amdgpu_ring * ring,bool acquire)6247677dec6eSriastradh static void gfx_v8_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
6248677dec6eSriastradh bool acquire)
6249677dec6eSriastradh {
6250677dec6eSriastradh struct amdgpu_device *adev = ring->adev;
6251677dec6eSriastradh int pipe_num, tmp, reg;
6252677dec6eSriastradh int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
6253677dec6eSriastradh
6254677dec6eSriastradh pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
6255677dec6eSriastradh
6256677dec6eSriastradh /* first me only has 2 entries, GFX and HP3D */
6257677dec6eSriastradh if (ring->me > 0)
6258677dec6eSriastradh pipe_num -= 2;
6259677dec6eSriastradh
6260677dec6eSriastradh reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num;
6261677dec6eSriastradh tmp = RREG32(reg);
6262677dec6eSriastradh tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
6263677dec6eSriastradh WREG32(reg, tmp);
6264677dec6eSriastradh }
6265677dec6eSriastradh
gfx_v8_0_pipe_reserve_resources(struct amdgpu_device * adev,struct amdgpu_ring * ring,bool acquire)6266677dec6eSriastradh static void gfx_v8_0_pipe_reserve_resources(struct amdgpu_device *adev,
6267677dec6eSriastradh struct amdgpu_ring *ring,
6268677dec6eSriastradh bool acquire)
6269677dec6eSriastradh {
6270677dec6eSriastradh int i, pipe;
6271677dec6eSriastradh bool reserve;
6272677dec6eSriastradh struct amdgpu_ring *iring;
6273677dec6eSriastradh
6274677dec6eSriastradh mutex_lock(&adev->gfx.pipe_reserve_mutex);
6275677dec6eSriastradh pipe = amdgpu_gfx_mec_queue_to_bit(adev, ring->me, ring->pipe, 0);
6276677dec6eSriastradh if (acquire)
6277677dec6eSriastradh set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6278677dec6eSriastradh else
6279677dec6eSriastradh clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6280677dec6eSriastradh
6281677dec6eSriastradh if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
6282677dec6eSriastradh /* Clear all reservations - everyone reacquires all resources */
6283677dec6eSriastradh for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
6284677dec6eSriastradh gfx_v8_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
6285677dec6eSriastradh true);
6286677dec6eSriastradh
6287677dec6eSriastradh for (i = 0; i < adev->gfx.num_compute_rings; ++i)
6288677dec6eSriastradh gfx_v8_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
6289677dec6eSriastradh true);
6290677dec6eSriastradh } else {
6291677dec6eSriastradh /* Lower all pipes without a current reservation */
6292677dec6eSriastradh for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
6293677dec6eSriastradh iring = &adev->gfx.gfx_ring[i];
6294677dec6eSriastradh pipe = amdgpu_gfx_mec_queue_to_bit(adev,
6295677dec6eSriastradh iring->me,
6296677dec6eSriastradh iring->pipe,
6297677dec6eSriastradh 0);
6298677dec6eSriastradh reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6299677dec6eSriastradh gfx_v8_0_ring_set_pipe_percent(iring, reserve);
6300677dec6eSriastradh }
6301677dec6eSriastradh
6302677dec6eSriastradh for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
6303677dec6eSriastradh iring = &adev->gfx.compute_ring[i];
6304677dec6eSriastradh pipe = amdgpu_gfx_mec_queue_to_bit(adev,
6305677dec6eSriastradh iring->me,
6306677dec6eSriastradh iring->pipe,
6307677dec6eSriastradh 0);
6308677dec6eSriastradh reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6309677dec6eSriastradh gfx_v8_0_ring_set_pipe_percent(iring, reserve);
6310677dec6eSriastradh }
6311677dec6eSriastradh }
6312677dec6eSriastradh
6313677dec6eSriastradh mutex_unlock(&adev->gfx.pipe_reserve_mutex);
6314677dec6eSriastradh }
6315677dec6eSriastradh
gfx_v8_0_hqd_set_priority(struct amdgpu_device * adev,struct amdgpu_ring * ring,bool acquire)6316677dec6eSriastradh static void gfx_v8_0_hqd_set_priority(struct amdgpu_device *adev,
6317677dec6eSriastradh struct amdgpu_ring *ring,
6318677dec6eSriastradh bool acquire)
6319677dec6eSriastradh {
6320677dec6eSriastradh uint32_t pipe_priority = acquire ? 0x2 : 0x0;
6321677dec6eSriastradh uint32_t queue_priority = acquire ? 0xf : 0x0;
6322677dec6eSriastradh
6323677dec6eSriastradh mutex_lock(&adev->srbm_mutex);
6324677dec6eSriastradh vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6325677dec6eSriastradh
6326677dec6eSriastradh WREG32(mmCP_HQD_PIPE_PRIORITY, pipe_priority);
6327677dec6eSriastradh WREG32(mmCP_HQD_QUEUE_PRIORITY, queue_priority);
6328677dec6eSriastradh
6329677dec6eSriastradh vi_srbm_select(adev, 0, 0, 0, 0);
6330677dec6eSriastradh mutex_unlock(&adev->srbm_mutex);
6331677dec6eSriastradh }
gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring * ring,enum drm_sched_priority priority)6332677dec6eSriastradh static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring,
6333677dec6eSriastradh enum drm_sched_priority priority)
6334677dec6eSriastradh {
6335677dec6eSriastradh struct amdgpu_device *adev = ring->adev;
6336677dec6eSriastradh bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
6337677dec6eSriastradh
6338677dec6eSriastradh if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
6339677dec6eSriastradh return;
6340677dec6eSriastradh
6341677dec6eSriastradh gfx_v8_0_hqd_set_priority(adev, ring, acquire);
6342677dec6eSriastradh gfx_v8_0_pipe_reserve_resources(adev, ring, acquire);
6343a30d5d3aSriastradh }
6344a30d5d3aSriastradh
gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)6345a30d5d3aSriastradh static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6346a30d5d3aSriastradh u64 addr, u64 seq,
6347a30d5d3aSriastradh unsigned flags)
6348a30d5d3aSriastradh {
6349a30d5d3aSriastradh bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6350a30d5d3aSriastradh bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6351a30d5d3aSriastradh
6352a30d5d3aSriastradh /* RELEASE_MEM - flush caches, send int */
6353a30d5d3aSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6354a30d5d3aSriastradh amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6355a30d5d3aSriastradh EOP_TC_ACTION_EN |
6356a30d5d3aSriastradh EOP_TC_WB_ACTION_EN |
6357a30d5d3aSriastradh EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6358a30d5d3aSriastradh EVENT_INDEX(5)));
6359a30d5d3aSriastradh amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6360a30d5d3aSriastradh amdgpu_ring_write(ring, addr & 0xfffffffc);
6361a30d5d3aSriastradh amdgpu_ring_write(ring, upper_32_bits(addr));
6362a30d5d3aSriastradh amdgpu_ring_write(ring, lower_32_bits(seq));
6363a30d5d3aSriastradh amdgpu_ring_write(ring, upper_32_bits(seq));
6364a30d5d3aSriastradh }
6365a30d5d3aSriastradh
gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)6366677dec6eSriastradh static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
6367677dec6eSriastradh u64 seq, unsigned int flags)
6368677dec6eSriastradh {
6369677dec6eSriastradh /* we only allocate 32bit for each seq wb address */
6370677dec6eSriastradh BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
6371677dec6eSriastradh
6372677dec6eSriastradh /* write fence seq to the "addr" */
6373677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6374677dec6eSriastradh amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6375677dec6eSriastradh WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
6376677dec6eSriastradh amdgpu_ring_write(ring, lower_32_bits(addr));
6377677dec6eSriastradh amdgpu_ring_write(ring, upper_32_bits(addr));
6378677dec6eSriastradh amdgpu_ring_write(ring, lower_32_bits(seq));
6379677dec6eSriastradh
6380677dec6eSriastradh if (flags & AMDGPU_FENCE_FLAG_INT) {
6381677dec6eSriastradh /* set register to trigger INT */
6382677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6383677dec6eSriastradh amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6384677dec6eSriastradh WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
6385677dec6eSriastradh amdgpu_ring_write(ring, mmCPC_INT_STATUS);
6386677dec6eSriastradh amdgpu_ring_write(ring, 0);
6387677dec6eSriastradh amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
6388677dec6eSriastradh }
6389677dec6eSriastradh }
6390677dec6eSriastradh
gfx_v8_ring_emit_sb(struct amdgpu_ring * ring)6391677dec6eSriastradh static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
6392677dec6eSriastradh {
6393677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6394677dec6eSriastradh amdgpu_ring_write(ring, 0);
6395677dec6eSriastradh }
6396677dec6eSriastradh
gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)6397677dec6eSriastradh static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6398677dec6eSriastradh {
6399677dec6eSriastradh uint32_t dw2 = 0;
6400677dec6eSriastradh
6401677dec6eSriastradh if (amdgpu_sriov_vf(ring->adev))
6402677dec6eSriastradh gfx_v8_0_ring_emit_ce_meta(ring);
6403677dec6eSriastradh
6404677dec6eSriastradh dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6405677dec6eSriastradh if (flags & AMDGPU_HAVE_CTX_SWITCH) {
6406677dec6eSriastradh gfx_v8_0_ring_emit_vgt_flush(ring);
6407677dec6eSriastradh /* set load_global_config & load_global_uconfig */
6408677dec6eSriastradh dw2 |= 0x8001;
6409677dec6eSriastradh /* set load_cs_sh_regs */
6410677dec6eSriastradh dw2 |= 0x01000000;
6411677dec6eSriastradh /* set load_per_context_state & load_gfx_sh_regs for GFX */
6412677dec6eSriastradh dw2 |= 0x10002;
6413677dec6eSriastradh
6414677dec6eSriastradh /* set load_ce_ram if preamble presented */
6415677dec6eSriastradh if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
6416677dec6eSriastradh dw2 |= 0x10000000;
6417677dec6eSriastradh } else {
6418677dec6eSriastradh /* still load_ce_ram if this is the first time preamble presented
6419677dec6eSriastradh * although there is no context switch happens.
6420677dec6eSriastradh */
6421677dec6eSriastradh if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
6422677dec6eSriastradh dw2 |= 0x10000000;
6423677dec6eSriastradh }
6424677dec6eSriastradh
6425677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6426677dec6eSriastradh amdgpu_ring_write(ring, dw2);
6427677dec6eSriastradh amdgpu_ring_write(ring, 0);
6428677dec6eSriastradh }
6429677dec6eSriastradh
gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring)6430677dec6eSriastradh static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
6431677dec6eSriastradh {
6432677dec6eSriastradh unsigned ret;
6433677dec6eSriastradh
6434677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
6435677dec6eSriastradh amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
6436677dec6eSriastradh amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
6437677dec6eSriastradh amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
6438677dec6eSriastradh ret = ring->wptr & ring->buf_mask;
6439677dec6eSriastradh amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
6440677dec6eSriastradh return ret;
6441677dec6eSriastradh }
6442677dec6eSriastradh
gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)6443677dec6eSriastradh static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
6444677dec6eSriastradh {
6445677dec6eSriastradh unsigned cur;
6446677dec6eSriastradh
6447677dec6eSriastradh BUG_ON(offset > ring->buf_mask);
6448677dec6eSriastradh BUG_ON(ring->ring[offset] != 0x55aa55aa);
6449677dec6eSriastradh
6450677dec6eSriastradh cur = (ring->wptr & ring->buf_mask) - 1;
6451677dec6eSriastradh if (likely(cur > offset))
6452677dec6eSriastradh ring->ring[offset] = cur - offset;
6453677dec6eSriastradh else
6454677dec6eSriastradh ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
6455677dec6eSriastradh }
6456677dec6eSriastradh
gfx_v8_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg)6457677dec6eSriastradh static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
6458677dec6eSriastradh {
6459677dec6eSriastradh struct amdgpu_device *adev = ring->adev;
6460677dec6eSriastradh struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6461677dec6eSriastradh
6462677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
6463677dec6eSriastradh amdgpu_ring_write(ring, 0 | /* src: register*/
6464677dec6eSriastradh (5 << 8) | /* dst: memory */
6465677dec6eSriastradh (1 << 20)); /* write confirm */
6466677dec6eSriastradh amdgpu_ring_write(ring, reg);
6467677dec6eSriastradh amdgpu_ring_write(ring, 0);
6468677dec6eSriastradh amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
6469677dec6eSriastradh kiq->reg_val_offs * 4));
6470677dec6eSriastradh amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
6471677dec6eSriastradh kiq->reg_val_offs * 4));
6472677dec6eSriastradh }
6473677dec6eSriastradh
gfx_v8_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)6474677dec6eSriastradh static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
6475677dec6eSriastradh uint32_t val)
6476677dec6eSriastradh {
6477677dec6eSriastradh uint32_t cmd;
6478677dec6eSriastradh
6479677dec6eSriastradh switch (ring->funcs->type) {
6480677dec6eSriastradh case AMDGPU_RING_TYPE_GFX:
6481677dec6eSriastradh cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
6482677dec6eSriastradh break;
6483677dec6eSriastradh case AMDGPU_RING_TYPE_KIQ:
6484677dec6eSriastradh cmd = 1 << 16; /* no inc addr */
6485677dec6eSriastradh break;
6486677dec6eSriastradh default:
6487677dec6eSriastradh cmd = WR_CONFIRM;
6488677dec6eSriastradh break;
6489677dec6eSriastradh }
6490677dec6eSriastradh
6491677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6492677dec6eSriastradh amdgpu_ring_write(ring, cmd);
6493677dec6eSriastradh amdgpu_ring_write(ring, reg);
6494677dec6eSriastradh amdgpu_ring_write(ring, 0);
6495677dec6eSriastradh amdgpu_ring_write(ring, val);
6496677dec6eSriastradh }
6497677dec6eSriastradh
gfx_v8_0_ring_soft_recovery(struct amdgpu_ring * ring,unsigned vmid)6498677dec6eSriastradh static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
6499677dec6eSriastradh {
6500677dec6eSriastradh struct amdgpu_device *adev = ring->adev;
6501677dec6eSriastradh uint32_t value = 0;
6502677dec6eSriastradh
6503677dec6eSriastradh value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
6504677dec6eSriastradh value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
6505677dec6eSriastradh value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
6506677dec6eSriastradh value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
6507677dec6eSriastradh WREG32(mmSQ_CMD, value);
6508677dec6eSriastradh }
6509677dec6eSriastradh
gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,enum amdgpu_interrupt_state state)6510a30d5d3aSriastradh static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6511a30d5d3aSriastradh enum amdgpu_interrupt_state state)
6512a30d5d3aSriastradh {
6513677dec6eSriastradh WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
6514677dec6eSriastradh state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6515a30d5d3aSriastradh }
6516a30d5d3aSriastradh
gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)6517a30d5d3aSriastradh static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6518a30d5d3aSriastradh int me, int pipe,
6519a30d5d3aSriastradh enum amdgpu_interrupt_state state)
6520a30d5d3aSriastradh {
6521a30d5d3aSriastradh u32 mec_int_cntl, mec_int_cntl_reg;
6522a30d5d3aSriastradh
6523a30d5d3aSriastradh /*
6524677dec6eSriastradh * amdgpu controls only the first MEC. That's why this function only
6525677dec6eSriastradh * handles the setting of interrupts for this specific MEC. All other
6526a30d5d3aSriastradh * pipes' interrupts are set by amdkfd.
6527a30d5d3aSriastradh */
6528a30d5d3aSriastradh
6529a30d5d3aSriastradh if (me == 1) {
6530a30d5d3aSriastradh switch (pipe) {
6531a30d5d3aSriastradh case 0:
6532a30d5d3aSriastradh mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6533a30d5d3aSriastradh break;
6534677dec6eSriastradh case 1:
6535677dec6eSriastradh mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
6536677dec6eSriastradh break;
6537677dec6eSriastradh case 2:
6538677dec6eSriastradh mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
6539677dec6eSriastradh break;
6540677dec6eSriastradh case 3:
6541677dec6eSriastradh mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
6542677dec6eSriastradh break;
6543a30d5d3aSriastradh default:
6544a30d5d3aSriastradh DRM_DEBUG("invalid pipe %d\n", pipe);
6545a30d5d3aSriastradh return;
6546a30d5d3aSriastradh }
6547a30d5d3aSriastradh } else {
6548a30d5d3aSriastradh DRM_DEBUG("invalid me %d\n", me);
6549a30d5d3aSriastradh return;
6550a30d5d3aSriastradh }
6551a30d5d3aSriastradh
6552a30d5d3aSriastradh switch (state) {
6553a30d5d3aSriastradh case AMDGPU_IRQ_STATE_DISABLE:
6554a30d5d3aSriastradh mec_int_cntl = RREG32(mec_int_cntl_reg);
6555677dec6eSriastradh mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6556a30d5d3aSriastradh WREG32(mec_int_cntl_reg, mec_int_cntl);
6557a30d5d3aSriastradh break;
6558a30d5d3aSriastradh case AMDGPU_IRQ_STATE_ENABLE:
6559a30d5d3aSriastradh mec_int_cntl = RREG32(mec_int_cntl_reg);
6560677dec6eSriastradh mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6561a30d5d3aSriastradh WREG32(mec_int_cntl_reg, mec_int_cntl);
6562a30d5d3aSriastradh break;
6563a30d5d3aSriastradh default:
6564a30d5d3aSriastradh break;
6565a30d5d3aSriastradh }
6566a30d5d3aSriastradh }
6567a30d5d3aSriastradh
gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)6568a30d5d3aSriastradh static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6569a30d5d3aSriastradh struct amdgpu_irq_src *source,
6570a30d5d3aSriastradh unsigned type,
6571a30d5d3aSriastradh enum amdgpu_interrupt_state state)
6572a30d5d3aSriastradh {
6573677dec6eSriastradh WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
6574677dec6eSriastradh state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6575a30d5d3aSriastradh
6576a30d5d3aSriastradh return 0;
6577a30d5d3aSriastradh }
6578a30d5d3aSriastradh
gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)6579a30d5d3aSriastradh static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6580a30d5d3aSriastradh struct amdgpu_irq_src *source,
6581a30d5d3aSriastradh unsigned type,
6582a30d5d3aSriastradh enum amdgpu_interrupt_state state)
6583a30d5d3aSriastradh {
6584677dec6eSriastradh WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
6585677dec6eSriastradh state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6586a30d5d3aSriastradh
6587a30d5d3aSriastradh return 0;
6588a30d5d3aSriastradh }
6589a30d5d3aSriastradh
gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)6590a30d5d3aSriastradh static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6591a30d5d3aSriastradh struct amdgpu_irq_src *src,
6592a30d5d3aSriastradh unsigned type,
6593a30d5d3aSriastradh enum amdgpu_interrupt_state state)
6594a30d5d3aSriastradh {
6595a30d5d3aSriastradh switch (type) {
6596677dec6eSriastradh case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
6597a30d5d3aSriastradh gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6598a30d5d3aSriastradh break;
6599a30d5d3aSriastradh case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6600a30d5d3aSriastradh gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6601a30d5d3aSriastradh break;
6602a30d5d3aSriastradh case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6603a30d5d3aSriastradh gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6604a30d5d3aSriastradh break;
6605a30d5d3aSriastradh case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6606a30d5d3aSriastradh gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6607a30d5d3aSriastradh break;
6608a30d5d3aSriastradh case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6609a30d5d3aSriastradh gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6610a30d5d3aSriastradh break;
6611a30d5d3aSriastradh case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6612a30d5d3aSriastradh gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6613a30d5d3aSriastradh break;
6614a30d5d3aSriastradh case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6615a30d5d3aSriastradh gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6616a30d5d3aSriastradh break;
6617a30d5d3aSriastradh case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6618a30d5d3aSriastradh gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6619a30d5d3aSriastradh break;
6620a30d5d3aSriastradh case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6621a30d5d3aSriastradh gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6622a30d5d3aSriastradh break;
6623a30d5d3aSriastradh default:
6624a30d5d3aSriastradh break;
6625a30d5d3aSriastradh }
6626a30d5d3aSriastradh return 0;
6627a30d5d3aSriastradh }
6628a30d5d3aSriastradh
gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)6629677dec6eSriastradh static int gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device *adev,
6630677dec6eSriastradh struct amdgpu_irq_src *source,
6631677dec6eSriastradh unsigned int type,
6632677dec6eSriastradh enum amdgpu_interrupt_state state)
6633677dec6eSriastradh {
6634677dec6eSriastradh int enable_flag;
6635677dec6eSriastradh
6636677dec6eSriastradh switch (state) {
6637677dec6eSriastradh case AMDGPU_IRQ_STATE_DISABLE:
6638677dec6eSriastradh enable_flag = 0;
6639677dec6eSriastradh break;
6640677dec6eSriastradh
6641677dec6eSriastradh case AMDGPU_IRQ_STATE_ENABLE:
6642677dec6eSriastradh enable_flag = 1;
6643677dec6eSriastradh break;
6644677dec6eSriastradh
6645677dec6eSriastradh default:
6646677dec6eSriastradh return -EINVAL;
6647677dec6eSriastradh }
6648677dec6eSriastradh
6649677dec6eSriastradh WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6650677dec6eSriastradh WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6651677dec6eSriastradh WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6652677dec6eSriastradh WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6653677dec6eSriastradh WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6654677dec6eSriastradh WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6655677dec6eSriastradh enable_flag);
6656677dec6eSriastradh WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6657677dec6eSriastradh enable_flag);
6658677dec6eSriastradh WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6659677dec6eSriastradh enable_flag);
6660677dec6eSriastradh WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6661677dec6eSriastradh enable_flag);
6662677dec6eSriastradh WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6663677dec6eSriastradh enable_flag);
6664677dec6eSriastradh WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6665677dec6eSriastradh enable_flag);
6666677dec6eSriastradh WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6667677dec6eSriastradh enable_flag);
6668677dec6eSriastradh WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6669677dec6eSriastradh enable_flag);
6670677dec6eSriastradh
6671677dec6eSriastradh return 0;
6672677dec6eSriastradh }
6673677dec6eSriastradh
gfx_v8_0_set_sq_int_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)6674677dec6eSriastradh static int gfx_v8_0_set_sq_int_state(struct amdgpu_device *adev,
6675677dec6eSriastradh struct amdgpu_irq_src *source,
6676677dec6eSriastradh unsigned int type,
6677677dec6eSriastradh enum amdgpu_interrupt_state state)
6678677dec6eSriastradh {
6679677dec6eSriastradh int enable_flag;
6680677dec6eSriastradh
6681677dec6eSriastradh switch (state) {
6682677dec6eSriastradh case AMDGPU_IRQ_STATE_DISABLE:
6683677dec6eSriastradh enable_flag = 1;
6684677dec6eSriastradh break;
6685677dec6eSriastradh
6686677dec6eSriastradh case AMDGPU_IRQ_STATE_ENABLE:
6687677dec6eSriastradh enable_flag = 0;
6688677dec6eSriastradh break;
6689677dec6eSriastradh
6690677dec6eSriastradh default:
6691677dec6eSriastradh return -EINVAL;
6692677dec6eSriastradh }
6693677dec6eSriastradh
6694677dec6eSriastradh WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL,
6695677dec6eSriastradh enable_flag);
6696677dec6eSriastradh
6697677dec6eSriastradh return 0;
6698677dec6eSriastradh }
6699677dec6eSriastradh
gfx_v8_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6700a30d5d3aSriastradh static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6701a30d5d3aSriastradh struct amdgpu_irq_src *source,
6702a30d5d3aSriastradh struct amdgpu_iv_entry *entry)
6703a30d5d3aSriastradh {
6704a30d5d3aSriastradh int i;
6705a30d5d3aSriastradh u8 me_id, pipe_id, queue_id;
6706a30d5d3aSriastradh struct amdgpu_ring *ring;
6707a30d5d3aSriastradh
6708a30d5d3aSriastradh DRM_DEBUG("IH: CP EOP\n");
6709a30d5d3aSriastradh me_id = (entry->ring_id & 0x0c) >> 2;
6710a30d5d3aSriastradh pipe_id = (entry->ring_id & 0x03) >> 0;
6711a30d5d3aSriastradh queue_id = (entry->ring_id & 0x70) >> 4;
6712a30d5d3aSriastradh
6713a30d5d3aSriastradh switch (me_id) {
6714a30d5d3aSriastradh case 0:
6715a30d5d3aSriastradh amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6716a30d5d3aSriastradh break;
6717a30d5d3aSriastradh case 1:
6718a30d5d3aSriastradh case 2:
6719a30d5d3aSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6720a30d5d3aSriastradh ring = &adev->gfx.compute_ring[i];
6721a30d5d3aSriastradh /* Per-queue interrupt is supported for MEC starting from VI.
6722a30d5d3aSriastradh * The interrupt can only be enabled/disabled per pipe instead of per queue.
6723a30d5d3aSriastradh */
6724a30d5d3aSriastradh if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6725a30d5d3aSriastradh amdgpu_fence_process(ring);
6726a30d5d3aSriastradh }
6727a30d5d3aSriastradh break;
6728a30d5d3aSriastradh }
6729a30d5d3aSriastradh return 0;
6730a30d5d3aSriastradh }
6731a30d5d3aSriastradh
gfx_v8_0_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)6732677dec6eSriastradh static void gfx_v8_0_fault(struct amdgpu_device *adev,
6733677dec6eSriastradh struct amdgpu_iv_entry *entry)
6734677dec6eSriastradh {
6735677dec6eSriastradh u8 me_id, pipe_id, queue_id;
6736677dec6eSriastradh struct amdgpu_ring *ring;
6737677dec6eSriastradh int i;
6738677dec6eSriastradh
6739677dec6eSriastradh me_id = (entry->ring_id & 0x0c) >> 2;
6740677dec6eSriastradh pipe_id = (entry->ring_id & 0x03) >> 0;
6741677dec6eSriastradh queue_id = (entry->ring_id & 0x70) >> 4;
6742677dec6eSriastradh
6743677dec6eSriastradh switch (me_id) {
6744677dec6eSriastradh case 0:
6745677dec6eSriastradh drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
6746677dec6eSriastradh break;
6747677dec6eSriastradh case 1:
6748677dec6eSriastradh case 2:
6749677dec6eSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6750677dec6eSriastradh ring = &adev->gfx.compute_ring[i];
6751677dec6eSriastradh if (ring->me == me_id && ring->pipe == pipe_id &&
6752677dec6eSriastradh ring->queue == queue_id)
6753677dec6eSriastradh drm_sched_fault(&ring->sched);
6754677dec6eSriastradh }
6755677dec6eSriastradh break;
6756677dec6eSriastradh }
6757677dec6eSriastradh }
6758677dec6eSriastradh
gfx_v8_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6759a30d5d3aSriastradh static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6760a30d5d3aSriastradh struct amdgpu_irq_src *source,
6761a30d5d3aSriastradh struct amdgpu_iv_entry *entry)
6762a30d5d3aSriastradh {
6763a30d5d3aSriastradh DRM_ERROR("Illegal register access in command stream\n");
6764677dec6eSriastradh gfx_v8_0_fault(adev, entry);
6765a30d5d3aSriastradh return 0;
6766a30d5d3aSriastradh }
6767a30d5d3aSriastradh
gfx_v8_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6768a30d5d3aSriastradh static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6769a30d5d3aSriastradh struct amdgpu_irq_src *source,
6770a30d5d3aSriastradh struct amdgpu_iv_entry *entry)
6771a30d5d3aSriastradh {
6772a30d5d3aSriastradh DRM_ERROR("Illegal instruction in command stream\n");
6773677dec6eSriastradh gfx_v8_0_fault(adev, entry);
6774a30d5d3aSriastradh return 0;
6775a30d5d3aSriastradh }
6776a30d5d3aSriastradh
gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6777677dec6eSriastradh static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev,
6778677dec6eSriastradh struct amdgpu_irq_src *source,
6779677dec6eSriastradh struct amdgpu_iv_entry *entry)
6780677dec6eSriastradh {
6781677dec6eSriastradh DRM_ERROR("CP EDC/ECC error detected.");
6782677dec6eSriastradh return 0;
6783677dec6eSriastradh }
6784677dec6eSriastradh
gfx_v8_0_parse_sq_irq(struct amdgpu_device * adev,unsigned ih_data)6785677dec6eSriastradh static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data)
6786677dec6eSriastradh {
6787677dec6eSriastradh u32 enc, se_id, sh_id, cu_id;
6788677dec6eSriastradh char type[20];
6789677dec6eSriastradh int sq_edc_source = -1;
6790677dec6eSriastradh
6791677dec6eSriastradh enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
6792677dec6eSriastradh se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
6793677dec6eSriastradh
6794677dec6eSriastradh switch (enc) {
6795677dec6eSriastradh case 0:
6796677dec6eSriastradh DRM_INFO("SQ general purpose intr detected:"
6797677dec6eSriastradh "se_id %d, immed_overflow %d, host_reg_overflow %d,"
6798677dec6eSriastradh "host_cmd_overflow %d, cmd_timestamp %d,"
6799677dec6eSriastradh "reg_timestamp %d, thread_trace_buff_full %d,"
6800677dec6eSriastradh "wlt %d, thread_trace %d.\n",
6801677dec6eSriastradh se_id,
6802677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
6803677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
6804677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
6805677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
6806677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
6807677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
6808677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT),
6809677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
6810677dec6eSriastradh );
6811677dec6eSriastradh break;
6812677dec6eSriastradh case 1:
6813677dec6eSriastradh case 2:
6814677dec6eSriastradh
6815677dec6eSriastradh cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);
6816677dec6eSriastradh sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID);
6817677dec6eSriastradh
6818677dec6eSriastradh /*
6819677dec6eSriastradh * This function can be called either directly from ISR
6820677dec6eSriastradh * or from BH in which case we can access SQ_EDC_INFO
6821677dec6eSriastradh * instance
6822677dec6eSriastradh */
6823677dec6eSriastradh if (in_task()) {
6824677dec6eSriastradh mutex_lock(&adev->grbm_idx_mutex);
6825677dec6eSriastradh gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id);
6826677dec6eSriastradh
6827677dec6eSriastradh sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
6828677dec6eSriastradh
6829677dec6eSriastradh gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6830677dec6eSriastradh mutex_unlock(&adev->grbm_idx_mutex);
6831677dec6eSriastradh }
6832677dec6eSriastradh
6833677dec6eSriastradh if (enc == 1)
6834677dec6eSriastradh snprintf(type, sizeof type, "instruction intr");
6835677dec6eSriastradh else
6836677dec6eSriastradh snprintf(type, sizeof type, "EDC/ECC error");
6837677dec6eSriastradh
6838677dec6eSriastradh DRM_INFO(
6839677dec6eSriastradh "SQ %s detected: "
6840677dec6eSriastradh "se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d "
6841677dec6eSriastradh "trap %s, sq_ed_info.source %s.\n",
6842677dec6eSriastradh type, se_id, sh_id, cu_id,
6843677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
6844677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
6845677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID),
6846677dec6eSriastradh REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
6847677dec6eSriastradh (sq_edc_source != -1) ? sq_edc_source_names[sq_edc_source] : "unavailable"
6848677dec6eSriastradh );
6849677dec6eSriastradh break;
6850677dec6eSriastradh default:
6851677dec6eSriastradh DRM_ERROR("SQ invalid encoding type\n.");
6852677dec6eSriastradh }
6853677dec6eSriastradh }
6854677dec6eSriastradh
gfx_v8_0_sq_irq_work_func(struct work_struct * work)6855677dec6eSriastradh static void gfx_v8_0_sq_irq_work_func(struct work_struct *work)
6856677dec6eSriastradh {
6857677dec6eSriastradh
6858677dec6eSriastradh struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work);
6859677dec6eSriastradh struct sq_work *sq_work = container_of(work, struct sq_work, work);
6860677dec6eSriastradh
6861677dec6eSriastradh gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data);
6862677dec6eSriastradh }
6863677dec6eSriastradh
gfx_v8_0_sq_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6864677dec6eSriastradh static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
6865677dec6eSriastradh struct amdgpu_irq_src *source,
6866677dec6eSriastradh struct amdgpu_iv_entry *entry)
6867677dec6eSriastradh {
6868677dec6eSriastradh unsigned ih_data = entry->src_data[0];
6869677dec6eSriastradh
6870677dec6eSriastradh /*
6871677dec6eSriastradh * Try to submit work so SQ_EDC_INFO can be accessed from
6872677dec6eSriastradh * BH. If previous work submission hasn't finished yet
6873677dec6eSriastradh * just print whatever info is possible directly from the ISR.
6874677dec6eSriastradh */
6875677dec6eSriastradh if (work_pending(&adev->gfx.sq_work.work)) {
6876677dec6eSriastradh gfx_v8_0_parse_sq_irq(adev, ih_data);
6877677dec6eSriastradh } else {
6878677dec6eSriastradh adev->gfx.sq_work.ih_data = ih_data;
6879677dec6eSriastradh schedule_work(&adev->gfx.sq_work.work);
6880677dec6eSriastradh }
6881677dec6eSriastradh
6882677dec6eSriastradh return 0;
6883677dec6eSriastradh }
6884677dec6eSriastradh
6885677dec6eSriastradh static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
6886677dec6eSriastradh .name = "gfx_v8_0",
6887a30d5d3aSriastradh .early_init = gfx_v8_0_early_init,
6888677dec6eSriastradh .late_init = gfx_v8_0_late_init,
6889a30d5d3aSriastradh .sw_init = gfx_v8_0_sw_init,
6890a30d5d3aSriastradh .sw_fini = gfx_v8_0_sw_fini,
6891a30d5d3aSriastradh .hw_init = gfx_v8_0_hw_init,
6892a30d5d3aSriastradh .hw_fini = gfx_v8_0_hw_fini,
6893a30d5d3aSriastradh .suspend = gfx_v8_0_suspend,
6894a30d5d3aSriastradh .resume = gfx_v8_0_resume,
6895a30d5d3aSriastradh .is_idle = gfx_v8_0_is_idle,
6896a30d5d3aSriastradh .wait_for_idle = gfx_v8_0_wait_for_idle,
6897677dec6eSriastradh .check_soft_reset = gfx_v8_0_check_soft_reset,
6898677dec6eSriastradh .pre_soft_reset = gfx_v8_0_pre_soft_reset,
6899a30d5d3aSriastradh .soft_reset = gfx_v8_0_soft_reset,
6900677dec6eSriastradh .post_soft_reset = gfx_v8_0_post_soft_reset,
6901a30d5d3aSriastradh .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6902a30d5d3aSriastradh .set_powergating_state = gfx_v8_0_set_powergating_state,
6903677dec6eSriastradh .get_clockgating_state = gfx_v8_0_get_clockgating_state,
6904a30d5d3aSriastradh };
6905a30d5d3aSriastradh
6906a30d5d3aSriastradh static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6907677dec6eSriastradh .type = AMDGPU_RING_TYPE_GFX,
6908677dec6eSriastradh .align_mask = 0xff,
6909677dec6eSriastradh .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6910677dec6eSriastradh .support_64bit_ptrs = false,
6911677dec6eSriastradh .get_rptr = gfx_v8_0_ring_get_rptr,
6912a30d5d3aSriastradh .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6913a30d5d3aSriastradh .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6914677dec6eSriastradh .emit_frame_size = /* maximum 215dw if count 16 IBs in */
6915677dec6eSriastradh 5 + /* COND_EXEC */
6916677dec6eSriastradh 7 + /* PIPELINE_SYNC */
6917677dec6eSriastradh VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
6918677dec6eSriastradh 12 + /* FENCE for VM_FLUSH */
6919677dec6eSriastradh 20 + /* GDS switch */
6920677dec6eSriastradh 4 + /* double SWITCH_BUFFER,
6921677dec6eSriastradh the first COND_EXEC jump to the place just
6922677dec6eSriastradh prior to this double SWITCH_BUFFER */
6923677dec6eSriastradh 5 + /* COND_EXEC */
6924677dec6eSriastradh 7 + /* HDP_flush */
6925677dec6eSriastradh 4 + /* VGT_flush */
6926677dec6eSriastradh 14 + /* CE_META */
6927677dec6eSriastradh 31 + /* DE_META */
6928677dec6eSriastradh 3 + /* CNTX_CTRL */
6929677dec6eSriastradh 5 + /* HDP_INVL */
6930677dec6eSriastradh 12 + 12 + /* FENCE x2 */
6931677dec6eSriastradh 2, /* SWITCH_BUFFER */
6932677dec6eSriastradh .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
6933a30d5d3aSriastradh .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
6934a30d5d3aSriastradh .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
6935677dec6eSriastradh .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6936a30d5d3aSriastradh .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6937a30d5d3aSriastradh .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6938a30d5d3aSriastradh .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6939a30d5d3aSriastradh .test_ring = gfx_v8_0_ring_test_ring,
6940a30d5d3aSriastradh .test_ib = gfx_v8_0_ring_test_ib,
6941a30d5d3aSriastradh .insert_nop = amdgpu_ring_insert_nop,
6942677dec6eSriastradh .pad_ib = amdgpu_ring_generic_pad_ib,
6943677dec6eSriastradh .emit_switch_buffer = gfx_v8_ring_emit_sb,
6944677dec6eSriastradh .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
6945677dec6eSriastradh .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
6946677dec6eSriastradh .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
6947677dec6eSriastradh .emit_wreg = gfx_v8_0_ring_emit_wreg,
6948677dec6eSriastradh .soft_recovery = gfx_v8_0_ring_soft_recovery,
6949a30d5d3aSriastradh };
6950a30d5d3aSriastradh
6951a30d5d3aSriastradh static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6952677dec6eSriastradh .type = AMDGPU_RING_TYPE_COMPUTE,
6953677dec6eSriastradh .align_mask = 0xff,
6954677dec6eSriastradh .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6955677dec6eSriastradh .support_64bit_ptrs = false,
6956677dec6eSriastradh .get_rptr = gfx_v8_0_ring_get_rptr,
6957a30d5d3aSriastradh .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6958a30d5d3aSriastradh .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6959677dec6eSriastradh .emit_frame_size =
6960677dec6eSriastradh 20 + /* gfx_v8_0_ring_emit_gds_switch */
6961677dec6eSriastradh 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6962677dec6eSriastradh 5 + /* hdp_invalidate */
6963677dec6eSriastradh 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6964677dec6eSriastradh VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
6965677dec6eSriastradh 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6966677dec6eSriastradh .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6967a30d5d3aSriastradh .emit_ib = gfx_v8_0_ring_emit_ib_compute,
6968a30d5d3aSriastradh .emit_fence = gfx_v8_0_ring_emit_fence_compute,
6969677dec6eSriastradh .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6970a30d5d3aSriastradh .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6971a30d5d3aSriastradh .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6972a30d5d3aSriastradh .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6973a30d5d3aSriastradh .test_ring = gfx_v8_0_ring_test_ring,
6974a30d5d3aSriastradh .test_ib = gfx_v8_0_ring_test_ib,
6975a30d5d3aSriastradh .insert_nop = amdgpu_ring_insert_nop,
6976677dec6eSriastradh .pad_ib = amdgpu_ring_generic_pad_ib,
6977677dec6eSriastradh .set_priority = gfx_v8_0_ring_set_priority_compute,
6978677dec6eSriastradh .emit_wreg = gfx_v8_0_ring_emit_wreg,
6979677dec6eSriastradh };
6980677dec6eSriastradh
6981677dec6eSriastradh static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
6982677dec6eSriastradh .type = AMDGPU_RING_TYPE_KIQ,
6983677dec6eSriastradh .align_mask = 0xff,
6984677dec6eSriastradh .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6985677dec6eSriastradh .support_64bit_ptrs = false,
6986677dec6eSriastradh .get_rptr = gfx_v8_0_ring_get_rptr,
6987677dec6eSriastradh .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6988677dec6eSriastradh .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6989677dec6eSriastradh .emit_frame_size =
6990677dec6eSriastradh 20 + /* gfx_v8_0_ring_emit_gds_switch */
6991677dec6eSriastradh 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6992677dec6eSriastradh 5 + /* hdp_invalidate */
6993677dec6eSriastradh 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6994677dec6eSriastradh 17 + /* gfx_v8_0_ring_emit_vm_flush */
6995677dec6eSriastradh 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6996677dec6eSriastradh .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6997677dec6eSriastradh .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
6998677dec6eSriastradh .test_ring = gfx_v8_0_ring_test_ring,
6999677dec6eSriastradh .insert_nop = amdgpu_ring_insert_nop,
7000677dec6eSriastradh .pad_ib = amdgpu_ring_generic_pad_ib,
7001677dec6eSriastradh .emit_rreg = gfx_v8_0_ring_emit_rreg,
7002677dec6eSriastradh .emit_wreg = gfx_v8_0_ring_emit_wreg,
7003a30d5d3aSriastradh };
7004a30d5d3aSriastradh
gfx_v8_0_set_ring_funcs(struct amdgpu_device * adev)7005a30d5d3aSriastradh static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
7006a30d5d3aSriastradh {
7007a30d5d3aSriastradh int i;
7008a30d5d3aSriastradh
7009677dec6eSriastradh adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq;
7010677dec6eSriastradh
7011a30d5d3aSriastradh for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7012a30d5d3aSriastradh adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
7013a30d5d3aSriastradh
7014a30d5d3aSriastradh for (i = 0; i < adev->gfx.num_compute_rings; i++)
7015a30d5d3aSriastradh adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
7016a30d5d3aSriastradh }
7017a30d5d3aSriastradh
7018a30d5d3aSriastradh static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
7019a30d5d3aSriastradh .set = gfx_v8_0_set_eop_interrupt_state,
7020a30d5d3aSriastradh .process = gfx_v8_0_eop_irq,
7021a30d5d3aSriastradh };
7022a30d5d3aSriastradh
7023a30d5d3aSriastradh static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
7024a30d5d3aSriastradh .set = gfx_v8_0_set_priv_reg_fault_state,
7025a30d5d3aSriastradh .process = gfx_v8_0_priv_reg_irq,
7026a30d5d3aSriastradh };
7027a30d5d3aSriastradh
7028a30d5d3aSriastradh static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
7029a30d5d3aSriastradh .set = gfx_v8_0_set_priv_inst_fault_state,
7030a30d5d3aSriastradh .process = gfx_v8_0_priv_inst_irq,
7031a30d5d3aSriastradh };
7032a30d5d3aSriastradh
7033677dec6eSriastradh static const struct amdgpu_irq_src_funcs gfx_v8_0_cp_ecc_error_irq_funcs = {
7034677dec6eSriastradh .set = gfx_v8_0_set_cp_ecc_int_state,
7035677dec6eSriastradh .process = gfx_v8_0_cp_ecc_error_irq,
7036677dec6eSriastradh };
7037677dec6eSriastradh
7038677dec6eSriastradh static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = {
7039677dec6eSriastradh .set = gfx_v8_0_set_sq_int_state,
7040677dec6eSriastradh .process = gfx_v8_0_sq_irq,
7041677dec6eSriastradh };
7042677dec6eSriastradh
gfx_v8_0_set_irq_funcs(struct amdgpu_device * adev)7043a30d5d3aSriastradh static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
7044a30d5d3aSriastradh {
7045a30d5d3aSriastradh adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
7046a30d5d3aSriastradh adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
7047a30d5d3aSriastradh
7048a30d5d3aSriastradh adev->gfx.priv_reg_irq.num_types = 1;
7049a30d5d3aSriastradh adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
7050a30d5d3aSriastradh
7051a30d5d3aSriastradh adev->gfx.priv_inst_irq.num_types = 1;
7052a30d5d3aSriastradh adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
7053677dec6eSriastradh
7054677dec6eSriastradh adev->gfx.cp_ecc_error_irq.num_types = 1;
7055677dec6eSriastradh adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs;
7056677dec6eSriastradh
7057677dec6eSriastradh adev->gfx.sq_irq.num_types = 1;
7058677dec6eSriastradh adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs;
7059677dec6eSriastradh }
7060677dec6eSriastradh
gfx_v8_0_set_rlc_funcs(struct amdgpu_device * adev)7061677dec6eSriastradh static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
7062677dec6eSriastradh {
7063677dec6eSriastradh adev->gfx.rlc.funcs = &iceland_rlc_funcs;
7064a30d5d3aSriastradh }
7065a30d5d3aSriastradh
gfx_v8_0_set_gds_init(struct amdgpu_device * adev)7066a30d5d3aSriastradh static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
7067a30d5d3aSriastradh {
7068a30d5d3aSriastradh /* init asci gds info */
7069677dec6eSriastradh adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
7070677dec6eSriastradh adev->gds.gws_size = 64;
7071677dec6eSriastradh adev->gds.oa_size = 16;
7072677dec6eSriastradh adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
7073a30d5d3aSriastradh }
7074a30d5d3aSriastradh
gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device * adev,u32 bitmap)7075677dec6eSriastradh static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
7076677dec6eSriastradh u32 bitmap)
7077a30d5d3aSriastradh {
7078677dec6eSriastradh u32 data;
7079a30d5d3aSriastradh
7080677dec6eSriastradh if (!bitmap)
7081677dec6eSriastradh return;
7082a30d5d3aSriastradh
7083677dec6eSriastradh data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
7084677dec6eSriastradh data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
7085a30d5d3aSriastradh
7086677dec6eSriastradh WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
7087a30d5d3aSriastradh }
7088a30d5d3aSriastradh
gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device * adev)7089677dec6eSriastradh static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
7090677dec6eSriastradh {
7091677dec6eSriastradh u32 data, mask;
7092677dec6eSriastradh
7093677dec6eSriastradh data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
7094677dec6eSriastradh RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
7095677dec6eSriastradh
7096677dec6eSriastradh mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
7097677dec6eSriastradh
7098677dec6eSriastradh return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
7099a30d5d3aSriastradh }
7100a30d5d3aSriastradh
gfx_v8_0_get_cu_info(struct amdgpu_device * adev)7101677dec6eSriastradh static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
7102a30d5d3aSriastradh {
7103a30d5d3aSriastradh int i, j, k, counter, active_cu_number = 0;
7104a30d5d3aSriastradh u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7105677dec6eSriastradh struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
7106677dec6eSriastradh unsigned disable_masks[4 * 2];
7107677dec6eSriastradh u32 ao_cu_num;
7108a30d5d3aSriastradh
7109677dec6eSriastradh memset(cu_info, 0, sizeof(*cu_info));
7110677dec6eSriastradh
7111677dec6eSriastradh if (adev->flags & AMD_IS_APU)
7112677dec6eSriastradh ao_cu_num = 2;
7113677dec6eSriastradh else
7114677dec6eSriastradh ao_cu_num = adev->gfx.config.max_cu_per_sh;
7115677dec6eSriastradh
7116677dec6eSriastradh amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
7117a30d5d3aSriastradh
7118a30d5d3aSriastradh mutex_lock(&adev->grbm_idx_mutex);
7119a30d5d3aSriastradh for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7120a30d5d3aSriastradh for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7121a30d5d3aSriastradh mask = 1;
7122a30d5d3aSriastradh ao_bitmap = 0;
7123a30d5d3aSriastradh counter = 0;
7124677dec6eSriastradh gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
7125677dec6eSriastradh if (i < 4 && j < 2)
7126677dec6eSriastradh gfx_v8_0_set_user_cu_inactive_bitmap(
7127677dec6eSriastradh adev, disable_masks[i * 2 + j]);
7128677dec6eSriastradh bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
7129a30d5d3aSriastradh cu_info->bitmap[i][j] = bitmap;
7130a30d5d3aSriastradh
7131a30d5d3aSriastradh for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7132a30d5d3aSriastradh if (bitmap & mask) {
7133677dec6eSriastradh if (counter < ao_cu_num)
7134a30d5d3aSriastradh ao_bitmap |= mask;
7135a30d5d3aSriastradh counter ++;
7136a30d5d3aSriastradh }
7137a30d5d3aSriastradh mask <<= 1;
7138a30d5d3aSriastradh }
7139a30d5d3aSriastradh active_cu_number += counter;
7140677dec6eSriastradh if (i < 2 && j < 2)
7141a30d5d3aSriastradh ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7142677dec6eSriastradh cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
7143a30d5d3aSriastradh }
7144a30d5d3aSriastradh }
7145677dec6eSriastradh gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
7146677dec6eSriastradh mutex_unlock(&adev->grbm_idx_mutex);
7147a30d5d3aSriastradh
7148a30d5d3aSriastradh cu_info->number = active_cu_number;
7149a30d5d3aSriastradh cu_info->ao_cu_mask = ao_cu_mask;
7150677dec6eSriastradh cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7151677dec6eSriastradh cu_info->max_waves_per_simd = 10;
7152677dec6eSriastradh cu_info->max_scratch_slots_per_cu = 32;
7153677dec6eSriastradh cu_info->wave_front_size = 64;
7154677dec6eSriastradh cu_info->lds_size = 64;
7155677dec6eSriastradh }
7156677dec6eSriastradh
7157677dec6eSriastradh const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
7158677dec6eSriastradh {
7159677dec6eSriastradh .type = AMD_IP_BLOCK_TYPE_GFX,
7160677dec6eSriastradh .major = 8,
7161677dec6eSriastradh .minor = 0,
7162677dec6eSriastradh .rev = 0,
7163677dec6eSriastradh .funcs = &gfx_v8_0_ip_funcs,
7164677dec6eSriastradh };
7165677dec6eSriastradh
7166677dec6eSriastradh const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
7167677dec6eSriastradh {
7168677dec6eSriastradh .type = AMD_IP_BLOCK_TYPE_GFX,
7169677dec6eSriastradh .major = 8,
7170677dec6eSriastradh .minor = 1,
7171677dec6eSriastradh .rev = 0,
7172677dec6eSriastradh .funcs = &gfx_v8_0_ip_funcs,
7173677dec6eSriastradh };
7174677dec6eSriastradh
gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring * ring)7175677dec6eSriastradh static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
7176677dec6eSriastradh {
7177677dec6eSriastradh uint64_t ce_payload_addr;
7178677dec6eSriastradh int cnt_ce;
7179677dec6eSriastradh union {
7180677dec6eSriastradh struct vi_ce_ib_state regular;
7181677dec6eSriastradh struct vi_ce_ib_state_chained_ib chained;
7182677dec6eSriastradh } ce_payload = {};
7183677dec6eSriastradh
7184677dec6eSriastradh if (ring->adev->virt.chained_ib_support) {
7185677dec6eSriastradh ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7186677dec6eSriastradh offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
7187677dec6eSriastradh cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
7188677dec6eSriastradh } else {
7189677dec6eSriastradh ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7190677dec6eSriastradh offsetof(struct vi_gfx_meta_data, ce_payload);
7191677dec6eSriastradh cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
7192677dec6eSriastradh }
7193677dec6eSriastradh
7194677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));
7195677dec6eSriastradh amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7196677dec6eSriastradh WRITE_DATA_DST_SEL(8) |
7197677dec6eSriastradh WR_CONFIRM) |
7198677dec6eSriastradh WRITE_DATA_CACHE_POLICY(0));
7199677dec6eSriastradh amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr));
7200677dec6eSriastradh amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr));
7201677dec6eSriastradh amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
7202677dec6eSriastradh }
7203677dec6eSriastradh
gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring * ring)7204677dec6eSriastradh static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
7205677dec6eSriastradh {
7206677dec6eSriastradh uint64_t de_payload_addr, gds_addr, csa_addr;
7207677dec6eSriastradh int cnt_de;
7208677dec6eSriastradh union {
7209677dec6eSriastradh struct vi_de_ib_state regular;
7210677dec6eSriastradh struct vi_de_ib_state_chained_ib chained;
7211677dec6eSriastradh } de_payload = {};
7212677dec6eSriastradh
7213677dec6eSriastradh csa_addr = amdgpu_csa_vaddr(ring->adev);
7214677dec6eSriastradh gds_addr = csa_addr + 4096;
7215677dec6eSriastradh if (ring->adev->virt.chained_ib_support) {
7216677dec6eSriastradh de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
7217677dec6eSriastradh de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);
7218677dec6eSriastradh de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload);
7219677dec6eSriastradh cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2;
7220677dec6eSriastradh } else {
7221677dec6eSriastradh de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr);
7222677dec6eSriastradh de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr);
7223677dec6eSriastradh de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload);
7224677dec6eSriastradh cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2;
7225677dec6eSriastradh }
7226677dec6eSriastradh
7227677dec6eSriastradh amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));
7228677dec6eSriastradh amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7229677dec6eSriastradh WRITE_DATA_DST_SEL(8) |
7230677dec6eSriastradh WR_CONFIRM) |
7231677dec6eSriastradh WRITE_DATA_CACHE_POLICY(0));
7232677dec6eSriastradh amdgpu_ring_write(ring, lower_32_bits(de_payload_addr));
7233677dec6eSriastradh amdgpu_ring_write(ring, upper_32_bits(de_payload_addr));
7234677dec6eSriastradh amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2);
7235a30d5d3aSriastradh }
7236