1*677dec6eSriastradh /* $NetBSD: amdgpu_umc.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */ 21571a7a1Sriastradh 31571a7a1Sriastradh /* 41571a7a1Sriastradh * Copyright (C) 2019 Advanced Micro Devices, Inc. 51571a7a1Sriastradh * 61571a7a1Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 71571a7a1Sriastradh * copy of this software and associated documentation files (the "Software"), 81571a7a1Sriastradh * to deal in the Software without restriction, including without limitation 91571a7a1Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 101571a7a1Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 111571a7a1Sriastradh * Software is furnished to do so, subject to the following conditions: 121571a7a1Sriastradh * 131571a7a1Sriastradh * The above copyright notice and this permission notice shall be included 141571a7a1Sriastradh * in all copies or substantial portions of the Software. 151571a7a1Sriastradh * 161571a7a1Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 171571a7a1Sriastradh * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 181571a7a1Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 191571a7a1Sriastradh * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 201571a7a1Sriastradh * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 211571a7a1Sriastradh * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 221571a7a1Sriastradh */ 231571a7a1Sriastradh #ifndef __AMDGPU_UMC_H__ 241571a7a1Sriastradh #define __AMDGPU_UMC_H__ 251571a7a1Sriastradh 261571a7a1Sriastradh struct amdgpu_umc_funcs { 271571a7a1Sriastradh void (*err_cnt_init)(struct amdgpu_device *adev); 281571a7a1Sriastradh int (*ras_late_init)(struct amdgpu_device *adev); 291571a7a1Sriastradh void (*query_ras_error_count)(struct amdgpu_device *adev, 301571a7a1Sriastradh void *ras_error_status); 311571a7a1Sriastradh void (*query_ras_error_address)(struct amdgpu_device *adev, 321571a7a1Sriastradh void *ras_error_status); 331571a7a1Sriastradh void (*init_registers)(struct amdgpu_device *adev); 341571a7a1Sriastradh }; 351571a7a1Sriastradh 361571a7a1Sriastradh struct amdgpu_umc { 371571a7a1Sriastradh /* max error count in one ras query call */ 381571a7a1Sriastradh uint32_t max_ras_err_cnt_per_query; 391571a7a1Sriastradh /* number of umc channel instance with memory map register access */ 401571a7a1Sriastradh uint32_t channel_inst_num; 411571a7a1Sriastradh /* number of umc instance with memory map register access */ 421571a7a1Sriastradh uint32_t umc_inst_num; 431571a7a1Sriastradh /* UMC regiser per channel offset */ 441571a7a1Sriastradh uint32_t channel_offs; 451571a7a1Sriastradh /* channel index table of interleaved memory */ 461571a7a1Sriastradh const uint32_t *channel_idx_tbl; 471571a7a1Sriastradh struct ras_common_if *ras_if; 481571a7a1Sriastradh 491571a7a1Sriastradh const struct amdgpu_umc_funcs *funcs; 501571a7a1Sriastradh }; 511571a7a1Sriastradh 521571a7a1Sriastradh int amdgpu_umc_ras_late_init(struct amdgpu_device *adev); 531571a7a1Sriastradh void amdgpu_umc_ras_fini(struct amdgpu_device *adev); 541571a7a1Sriastradh int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 551571a7a1Sriastradh void *ras_error_status, 561571a7a1Sriastradh struct amdgpu_iv_entry *entry); 571571a7a1Sriastradh int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 581571a7a1Sriastradh struct amdgpu_irq_src *source, 591571a7a1Sriastradh struct amdgpu_iv_entry *entry); 601571a7a1Sriastradh #endif 61