1*677dec6eSriastradh /* $NetBSD: si_enums.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 21571a7a1Sriastradh 31571a7a1Sriastradh /* 41571a7a1Sriastradh * Copyright 2016 Advanced Micro Devices, Inc. 51571a7a1Sriastradh * 61571a7a1Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 71571a7a1Sriastradh * copy of this software and associated documentation files (the "Software"), 81571a7a1Sriastradh * to deal in the Software without restriction, including without limitation 91571a7a1Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 101571a7a1Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 111571a7a1Sriastradh * Software is furnished to do so, subject to the following conditions: 121571a7a1Sriastradh * 131571a7a1Sriastradh * The above copyright notice and this permission notice shall be included in 141571a7a1Sriastradh * all copies or substantial portions of the Software. 151571a7a1Sriastradh * 161571a7a1Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 171571a7a1Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 181571a7a1Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 191571a7a1Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 201571a7a1Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 211571a7a1Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 221571a7a1Sriastradh * OTHER DEALINGS IN THE SOFTWARE. 231571a7a1Sriastradh * 241571a7a1Sriastradh */ 251571a7a1Sriastradh #ifndef SI_ENUMS_H 261571a7a1Sriastradh #define SI_ENUMS_H 271571a7a1Sriastradh 281571a7a1Sriastradh #define VBLANK_INT_MASK (1 << 0) 291571a7a1Sriastradh #define DC_HPDx_INT_EN (1 << 16) 301571a7a1Sriastradh #define VBLANK_ACK (1 << 4) 311571a7a1Sriastradh #define VLINE_ACK (1 << 4) 321571a7a1Sriastradh 331571a7a1Sriastradh #define CURSOR_WIDTH 64 341571a7a1Sriastradh #define CURSOR_HEIGHT 64 351571a7a1Sriastradh 361571a7a1Sriastradh #define VGA_VSTATUS_CNTL 0xFFFCFFFF 371571a7a1Sriastradh #define PRIORITY_MARK_MASK 0x7fff 381571a7a1Sriastradh #define PRIORITY_OFF (1 << 16) 391571a7a1Sriastradh #define PRIORITY_ALWAYS_ON (1 << 20) 401571a7a1Sriastradh #define INTERLEAVE_EN (1 << 0) 411571a7a1Sriastradh 421571a7a1Sriastradh #define LATENCY_WATERMARK_MASK(x) ((x) << 16) 431571a7a1Sriastradh #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 441571a7a1Sriastradh #define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) 451571a7a1Sriastradh 461571a7a1Sriastradh #define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 471571a7a1Sriastradh #define GRPH_ENDIAN_NONE 0 481571a7a1Sriastradh #define GRPH_ENDIAN_8IN16 1 491571a7a1Sriastradh #define GRPH_ENDIAN_8IN32 2 501571a7a1Sriastradh #define GRPH_ENDIAN_8IN64 3 511571a7a1Sriastradh #define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) 521571a7a1Sriastradh #define GRPH_RED_SEL_R 0 531571a7a1Sriastradh #define GRPH_RED_SEL_G 1 541571a7a1Sriastradh #define GRPH_RED_SEL_B 2 551571a7a1Sriastradh #define GRPH_RED_SEL_A 3 561571a7a1Sriastradh #define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) 571571a7a1Sriastradh #define GRPH_GREEN_SEL_G 0 581571a7a1Sriastradh #define GRPH_GREEN_SEL_B 1 591571a7a1Sriastradh #define GRPH_GREEN_SEL_A 2 601571a7a1Sriastradh #define GRPH_GREEN_SEL_R 3 611571a7a1Sriastradh #define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) 621571a7a1Sriastradh #define GRPH_BLUE_SEL_B 0 631571a7a1Sriastradh #define GRPH_BLUE_SEL_A 1 641571a7a1Sriastradh #define GRPH_BLUE_SEL_R 2 651571a7a1Sriastradh #define GRPH_BLUE_SEL_G 3 661571a7a1Sriastradh #define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) 671571a7a1Sriastradh #define GRPH_ALPHA_SEL_A 0 681571a7a1Sriastradh #define GRPH_ALPHA_SEL_R 1 691571a7a1Sriastradh #define GRPH_ALPHA_SEL_G 2 701571a7a1Sriastradh #define GRPH_ALPHA_SEL_B 3 711571a7a1Sriastradh 721571a7a1Sriastradh #define GRPH_DEPTH(x) (((x) & 0x3) << 0) 731571a7a1Sriastradh #define GRPH_DEPTH_8BPP 0 741571a7a1Sriastradh #define GRPH_DEPTH_16BPP 1 751571a7a1Sriastradh #define GRPH_DEPTH_32BPP 2 761571a7a1Sriastradh 771571a7a1Sriastradh #define GRPH_FORMAT(x) (((x) & 0x7) << 8) 781571a7a1Sriastradh #define GRPH_FORMAT_INDEXED 0 791571a7a1Sriastradh #define GRPH_FORMAT_ARGB1555 0 801571a7a1Sriastradh #define GRPH_FORMAT_ARGB565 1 811571a7a1Sriastradh #define GRPH_FORMAT_ARGB4444 2 821571a7a1Sriastradh #define GRPH_FORMAT_AI88 3 831571a7a1Sriastradh #define GRPH_FORMAT_MONO16 4 841571a7a1Sriastradh #define GRPH_FORMAT_BGRA5551 5 851571a7a1Sriastradh #define GRPH_FORMAT_ARGB8888 0 861571a7a1Sriastradh #define GRPH_FORMAT_ARGB2101010 1 871571a7a1Sriastradh #define GRPH_FORMAT_32BPP_DIG 2 881571a7a1Sriastradh #define GRPH_FORMAT_8B_ARGB2101010 3 891571a7a1Sriastradh #define GRPH_FORMAT_BGRA1010102 4 901571a7a1Sriastradh #define GRPH_FORMAT_8B_BGRA1010102 5 911571a7a1Sriastradh #define GRPH_FORMAT_RGB111110 6 921571a7a1Sriastradh #define GRPH_FORMAT_BGR101111 7 931571a7a1Sriastradh 941571a7a1Sriastradh #define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) 951571a7a1Sriastradh #define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 961571a7a1Sriastradh #define GRPH_ARRAY_LINEAR_GENERAL 0 971571a7a1Sriastradh #define GRPH_ARRAY_LINEAR_ALIGNED 1 981571a7a1Sriastradh #define GRPH_ARRAY_1D_TILED_THIN1 2 991571a7a1Sriastradh #define GRPH_ARRAY_2D_TILED_THIN1 4 1001571a7a1Sriastradh #define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) 1011571a7a1Sriastradh #define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) 1021571a7a1Sriastradh #define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) 1031571a7a1Sriastradh #define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) 1041571a7a1Sriastradh #define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 1051571a7a1Sriastradh #define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24) 1061571a7a1Sriastradh 1071571a7a1Sriastradh #define CURSOR_EN (1 << 0) 1081571a7a1Sriastradh #define CURSOR_MODE(x) (((x) & 0x3) << 8) 1091571a7a1Sriastradh #define CURSOR_MONO 0 1101571a7a1Sriastradh #define CURSOR_24_1 1 1111571a7a1Sriastradh #define CURSOR_24_8_PRE_MULT 2 1121571a7a1Sriastradh #define CURSOR_24_8_UNPRE_MULT 3 1131571a7a1Sriastradh #define CURSOR_2X_MAGNIFY (1 << 16) 1141571a7a1Sriastradh #define CURSOR_FORCE_MC_ON (1 << 20) 1151571a7a1Sriastradh #define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) 1161571a7a1Sriastradh #define CURSOR_URGENT_ALWAYS 0 1171571a7a1Sriastradh #define CURSOR_URGENT_1_8 1 1181571a7a1Sriastradh #define CURSOR_URGENT_1_4 2 1191571a7a1Sriastradh #define CURSOR_URGENT_3_8 3 1201571a7a1Sriastradh #define CURSOR_URGENT_1_2 4 1211571a7a1Sriastradh #define CURSOR_UPDATE_PENDING (1 << 0) 1221571a7a1Sriastradh #define CURSOR_UPDATE_TAKEN (1 << 1) 1231571a7a1Sriastradh #define CURSOR_UPDATE_LOCK (1 << 16) 1241571a7a1Sriastradh #define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 1251571a7a1Sriastradh 1261571a7a1Sriastradh #define AMDGPU_NUM_OF_VMIDS 8 1271571a7a1Sriastradh #define SI_CRTC0_REGISTER_OFFSET 0 1281571a7a1Sriastradh #define SI_CRTC1_REGISTER_OFFSET 0x300 1291571a7a1Sriastradh #define SI_CRTC2_REGISTER_OFFSET 0x2600 1301571a7a1Sriastradh #define SI_CRTC3_REGISTER_OFFSET 0x2900 1311571a7a1Sriastradh #define SI_CRTC4_REGISTER_OFFSET 0x2c00 1321571a7a1Sriastradh #define SI_CRTC5_REGISTER_OFFSET 0x2f00 1331571a7a1Sriastradh 1341571a7a1Sriastradh #define DMA0_REGISTER_OFFSET 0x000 1351571a7a1Sriastradh #define DMA1_REGISTER_OFFSET 0x200 1361571a7a1Sriastradh #define ES_AND_GS_AUTO 3 1371571a7a1Sriastradh #define RADEON_PACKET_TYPE3 3 1381571a7a1Sriastradh #define CE_PARTITION_BASE 3 1391571a7a1Sriastradh #define BUF_SWAP_32BIT (2 << 16) 1401571a7a1Sriastradh 1411571a7a1Sriastradh #define GFX_POWER_STATUS (1 << 1) 1421571a7a1Sriastradh #define GFX_CLOCK_STATUS (1 << 2) 1431571a7a1Sriastradh #define GFX_LS_STATUS (1 << 3) 1441571a7a1Sriastradh #define RLC_BUSY_STATUS (1 << 0) 1451571a7a1Sriastradh 1461571a7a1Sriastradh #define RLC_PUD(x) ((x) << 0) 1471571a7a1Sriastradh #define RLC_PUD_MASK (0xff << 0) 1481571a7a1Sriastradh #define RLC_PDD(x) ((x) << 8) 1491571a7a1Sriastradh #define RLC_PDD_MASK (0xff << 8) 1501571a7a1Sriastradh #define RLC_TTPD(x) ((x) << 16) 1511571a7a1Sriastradh #define RLC_TTPD_MASK (0xff << 16) 1521571a7a1Sriastradh #define RLC_MSD(x) ((x) << 24) 1531571a7a1Sriastradh #define RLC_MSD_MASK (0xff << 24) 1541571a7a1Sriastradh #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1551571a7a1Sriastradh #define WRITE_DATA_DST_SEL(x) ((x) << 8) 1561571a7a1Sriastradh #define EVENT_TYPE(x) ((x) << 0) 1571571a7a1Sriastradh #define EVENT_INDEX(x) ((x) << 8) 1581571a7a1Sriastradh #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1591571a7a1Sriastradh #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1601571a7a1Sriastradh #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1611571a7a1Sriastradh 1621571a7a1Sriastradh #define GFX6_NUM_GFX_RINGS 1 1631571a7a1Sriastradh #define GFX6_NUM_COMPUTE_RINGS 2 1641571a7a1Sriastradh #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 1651571a7a1Sriastradh #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 1661571a7a1Sriastradh 1671571a7a1Sriastradh #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 1681571a7a1Sriastradh #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x02010002 1691571a7a1Sriastradh #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 1701571a7a1Sriastradh 1711571a7a1Sriastradh #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1721571a7a1Sriastradh (((op) & 0xFF) << 8) | \ 1731571a7a1Sriastradh ((n) & 0x3FFF) << 16) 1741571a7a1Sriastradh #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1751571a7a1Sriastradh #define PACKET3_NOP 0x10 1761571a7a1Sriastradh #define PACKET3_SET_BASE 0x11 1771571a7a1Sriastradh #define PACKET3_BASE_INDEX(x) ((x) << 0) 1781571a7a1Sriastradh #define PACKET3_CLEAR_STATE 0x12 1791571a7a1Sriastradh #define PACKET3_INDEX_BUFFER_SIZE 0x13 1801571a7a1Sriastradh #define PACKET3_DISPATCH_DIRECT 0x15 1811571a7a1Sriastradh #define PACKET3_DISPATCH_INDIRECT 0x16 1821571a7a1Sriastradh #define PACKET3_ALLOC_GDS 0x1B 1831571a7a1Sriastradh #define PACKET3_WRITE_GDS_RAM 0x1C 1841571a7a1Sriastradh #define PACKET3_ATOMIC_GDS 0x1D 1851571a7a1Sriastradh #define PACKET3_ATOMIC 0x1E 1861571a7a1Sriastradh #define PACKET3_OCCLUSION_QUERY 0x1F 1871571a7a1Sriastradh #define PACKET3_SET_PREDICATION 0x20 1881571a7a1Sriastradh #define PACKET3_REG_RMW 0x21 1891571a7a1Sriastradh #define PACKET3_COND_EXEC 0x22 1901571a7a1Sriastradh #define PACKET3_PRED_EXEC 0x23 1911571a7a1Sriastradh #define PACKET3_DRAW_INDIRECT 0x24 1921571a7a1Sriastradh #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1931571a7a1Sriastradh #define PACKET3_INDEX_BASE 0x26 1941571a7a1Sriastradh #define PACKET3_DRAW_INDEX_2 0x27 1951571a7a1Sriastradh #define PACKET3_CONTEXT_CONTROL 0x28 1961571a7a1Sriastradh #define PACKET3_INDEX_TYPE 0x2A 1971571a7a1Sriastradh #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1981571a7a1Sriastradh #define PACKET3_DRAW_INDEX_AUTO 0x2D 1991571a7a1Sriastradh #define PACKET3_DRAW_INDEX_IMMD 0x2E 2001571a7a1Sriastradh #define PACKET3_NUM_INSTANCES 0x2F 2011571a7a1Sriastradh #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 2021571a7a1Sriastradh #define PACKET3_INDIRECT_BUFFER_CONST 0x31 2031571a7a1Sriastradh #define PACKET3_INDIRECT_BUFFER 0x3F 2041571a7a1Sriastradh #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 2051571a7a1Sriastradh #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 2061571a7a1Sriastradh #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 2071571a7a1Sriastradh #define PACKET3_WRITE_DATA 0x37 2081571a7a1Sriastradh #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 2091571a7a1Sriastradh #define PACKET3_MEM_SEMAPHORE 0x39 2101571a7a1Sriastradh #define PACKET3_MPEG_INDEX 0x3A 2111571a7a1Sriastradh #define PACKET3_COPY_DW 0x3B 2121571a7a1Sriastradh #define PACKET3_WAIT_REG_MEM 0x3C 2131571a7a1Sriastradh #define PACKET3_MEM_WRITE 0x3D 2141571a7a1Sriastradh #define PACKET3_COPY_DATA 0x40 2151571a7a1Sriastradh #define PACKET3_CP_DMA 0x41 2161571a7a1Sriastradh # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 2171571a7a1Sriastradh # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 2181571a7a1Sriastradh # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 2191571a7a1Sriastradh # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 2201571a7a1Sriastradh # define PACKET3_CP_DMA_DIS_WC (1 << 21) 2211571a7a1Sriastradh # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 2221571a7a1Sriastradh # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 2231571a7a1Sriastradh # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 2241571a7a1Sriastradh # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 2251571a7a1Sriastradh # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 2261571a7a1Sriastradh # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 2271571a7a1Sriastradh # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 2281571a7a1Sriastradh #define PACKET3_PFP_SYNC_ME 0x42 2291571a7a1Sriastradh #define PACKET3_SURFACE_SYNC 0x43 2301571a7a1Sriastradh # define PACKET3_DEST_BASE_0_ENA (1 << 0) 2311571a7a1Sriastradh # define PACKET3_DEST_BASE_1_ENA (1 << 1) 2321571a7a1Sriastradh # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 2331571a7a1Sriastradh # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 2341571a7a1Sriastradh # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 2351571a7a1Sriastradh # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 2361571a7a1Sriastradh # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 2371571a7a1Sriastradh # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 2381571a7a1Sriastradh # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 2391571a7a1Sriastradh # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 2401571a7a1Sriastradh # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 2411571a7a1Sriastradh # define PACKET3_DEST_BASE_2_ENA (1 << 19) 2421571a7a1Sriastradh # define PACKET3_DEST_BASE_3_ENA (1 << 21) 2431571a7a1Sriastradh # define PACKET3_TCL1_ACTION_ENA (1 << 22) 2441571a7a1Sriastradh # define PACKET3_TC_ACTION_ENA (1 << 23) 2451571a7a1Sriastradh # define PACKET3_CB_ACTION_ENA (1 << 25) 2461571a7a1Sriastradh # define PACKET3_DB_ACTION_ENA (1 << 26) 2471571a7a1Sriastradh # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 2481571a7a1Sriastradh # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 2491571a7a1Sriastradh #define PACKET3_ME_INITIALIZE 0x44 2501571a7a1Sriastradh #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 2511571a7a1Sriastradh #define PACKET3_COND_WRITE 0x45 2521571a7a1Sriastradh #define PACKET3_EVENT_WRITE 0x46 2531571a7a1Sriastradh #define PACKET3_EVENT_WRITE_EOP 0x47 2541571a7a1Sriastradh #define PACKET3_EVENT_WRITE_EOS 0x48 2551571a7a1Sriastradh #define PACKET3_PREAMBLE_CNTL 0x4A 2561571a7a1Sriastradh # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 2571571a7a1Sriastradh # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 2581571a7a1Sriastradh #define PACKET3_ONE_REG_WRITE 0x57 2591571a7a1Sriastradh #define PACKET3_LOAD_CONFIG_REG 0x5F 2601571a7a1Sriastradh #define PACKET3_LOAD_CONTEXT_REG 0x60 2611571a7a1Sriastradh #define PACKET3_LOAD_SH_REG 0x61 2621571a7a1Sriastradh #define PACKET3_SET_CONFIG_REG 0x68 2631571a7a1Sriastradh #define PACKET3_SET_CONFIG_REG_START 0x00002000 2641571a7a1Sriastradh #define PACKET3_SET_CONFIG_REG_END 0x00002c00 2651571a7a1Sriastradh #define PACKET3_SET_CONTEXT_REG 0x69 2661571a7a1Sriastradh #define PACKET3_SET_CONTEXT_REG_START 0x000a000 2671571a7a1Sriastradh #define PACKET3_SET_CONTEXT_REG_END 0x000a400 2681571a7a1Sriastradh #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 2691571a7a1Sriastradh #define PACKET3_SET_RESOURCE_INDIRECT 0x74 2701571a7a1Sriastradh #define PACKET3_SET_SH_REG 0x76 2711571a7a1Sriastradh #define PACKET3_SET_SH_REG_START 0x00002c00 2721571a7a1Sriastradh #define PACKET3_SET_SH_REG_END 0x00003000 2731571a7a1Sriastradh #define PACKET3_SET_SH_REG_OFFSET 0x77 2741571a7a1Sriastradh #define PACKET3_ME_WRITE 0x7A 2751571a7a1Sriastradh #define PACKET3_SCRATCH_RAM_WRITE 0x7D 2761571a7a1Sriastradh #define PACKET3_SCRATCH_RAM_READ 0x7E 2771571a7a1Sriastradh #define PACKET3_CE_WRITE 0x7F 2781571a7a1Sriastradh #define PACKET3_LOAD_CONST_RAM 0x80 2791571a7a1Sriastradh #define PACKET3_WRITE_CONST_RAM 0x81 2801571a7a1Sriastradh #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 2811571a7a1Sriastradh #define PACKET3_DUMP_CONST_RAM 0x83 2821571a7a1Sriastradh #define PACKET3_INCREMENT_CE_COUNTER 0x84 2831571a7a1Sriastradh #define PACKET3_INCREMENT_DE_COUNTER 0x85 2841571a7a1Sriastradh #define PACKET3_WAIT_ON_CE_COUNTER 0x86 2851571a7a1Sriastradh #define PACKET3_WAIT_ON_DE_COUNTER 0x87 2861571a7a1Sriastradh #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 2871571a7a1Sriastradh #define PACKET3_SET_CE_DE_COUNTERS 0x89 2881571a7a1Sriastradh #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 2891571a7a1Sriastradh #define PACKET3_SWITCH_BUFFER 0x8B 2901571a7a1Sriastradh #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 2911571a7a1Sriastradh #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 2921571a7a1Sriastradh #define PACKET3_SEM_SEL_WAIT (0x7 << 29) 2931571a7a1Sriastradh 2941571a7a1Sriastradh #endif 295