1*677dec6eSriastradh /* $NetBSD: dc.h,v 1.2 2021/12/18 23:45:00 riastradh Exp $ */ 21571a7a1Sriastradh 31571a7a1Sriastradh /* 41571a7a1Sriastradh * Copyright 2012-14 Advanced Micro Devices, Inc. 51571a7a1Sriastradh * 61571a7a1Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 71571a7a1Sriastradh * copy of this software and associated documentation files (the "Software"), 81571a7a1Sriastradh * to deal in the Software without restriction, including without limitation 91571a7a1Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 101571a7a1Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 111571a7a1Sriastradh * Software is furnished to do so, subject to the following conditions: 121571a7a1Sriastradh * 131571a7a1Sriastradh * The above copyright notice and this permission notice shall be included in 141571a7a1Sriastradh * all copies or substantial portions of the Software. 151571a7a1Sriastradh * 161571a7a1Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 171571a7a1Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 181571a7a1Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 191571a7a1Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 201571a7a1Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 211571a7a1Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 221571a7a1Sriastradh * OTHER DEALINGS IN THE SOFTWARE. 231571a7a1Sriastradh * 241571a7a1Sriastradh * Authors: AMD 251571a7a1Sriastradh * 261571a7a1Sriastradh */ 271571a7a1Sriastradh 281571a7a1Sriastradh #ifndef DC_INTERFACE_H_ 291571a7a1Sriastradh #define DC_INTERFACE_H_ 301571a7a1Sriastradh 311571a7a1Sriastradh #include "dc_types.h" 321571a7a1Sriastradh #include "grph_object_defs.h" 331571a7a1Sriastradh #include "logger_types.h" 341571a7a1Sriastradh #include "gpio_types.h" 351571a7a1Sriastradh #include "link_service_types.h" 361571a7a1Sriastradh #include "grph_object_ctrl_defs.h" 371571a7a1Sriastradh #include <inc/hw/opp.h> 381571a7a1Sriastradh 391571a7a1Sriastradh #include "inc/hw_sequencer.h" 401571a7a1Sriastradh #include "inc/compressor.h" 411571a7a1Sriastradh #include "inc/hw/dmcu.h" 421571a7a1Sriastradh #include "dml/display_mode_lib.h" 431571a7a1Sriastradh 441571a7a1Sriastradh #define DC_VER "3.2.69" 451571a7a1Sriastradh 461571a7a1Sriastradh #define MAX_SURFACES 3 471571a7a1Sriastradh #define MAX_PLANES 6 481571a7a1Sriastradh #define MAX_STREAMS 6 491571a7a1Sriastradh #define MAX_SINKS_PER_LINK 4 501571a7a1Sriastradh 511571a7a1Sriastradh /******************************************************************************* 521571a7a1Sriastradh * Display Core Interfaces 531571a7a1Sriastradh ******************************************************************************/ 541571a7a1Sriastradh struct dc_versions { 551571a7a1Sriastradh const char *dc_ver; 561571a7a1Sriastradh struct dmcu_version dmcu_version; 571571a7a1Sriastradh }; 581571a7a1Sriastradh 591571a7a1Sriastradh enum dp_protocol_version { 601571a7a1Sriastradh DP_VERSION_1_4, 611571a7a1Sriastradh }; 621571a7a1Sriastradh 631571a7a1Sriastradh enum dc_plane_type { 641571a7a1Sriastradh DC_PLANE_TYPE_INVALID, 651571a7a1Sriastradh DC_PLANE_TYPE_DCE_RGB, 661571a7a1Sriastradh DC_PLANE_TYPE_DCE_UNDERLAY, 671571a7a1Sriastradh DC_PLANE_TYPE_DCN_UNIVERSAL, 681571a7a1Sriastradh }; 691571a7a1Sriastradh 701571a7a1Sriastradh struct dc_plane_cap { 711571a7a1Sriastradh enum dc_plane_type type; 721571a7a1Sriastradh uint32_t blends_with_above : 1; 731571a7a1Sriastradh uint32_t blends_with_below : 1; 741571a7a1Sriastradh uint32_t per_pixel_alpha : 1; 751571a7a1Sriastradh struct { 761571a7a1Sriastradh uint32_t argb8888 : 1; 771571a7a1Sriastradh uint32_t nv12 : 1; 781571a7a1Sriastradh uint32_t fp16 : 1; 791571a7a1Sriastradh uint32_t p010 : 1; 801571a7a1Sriastradh uint32_t ayuv : 1; 811571a7a1Sriastradh } pixel_format_support; 821571a7a1Sriastradh // max upscaling factor x1000 831571a7a1Sriastradh // upscaling factors are always >= 1 841571a7a1Sriastradh // for example, 1080p -> 8K is 4.0, or 4000 raw value 851571a7a1Sriastradh struct { 861571a7a1Sriastradh uint32_t argb8888; 871571a7a1Sriastradh uint32_t nv12; 881571a7a1Sriastradh uint32_t fp16; 891571a7a1Sriastradh } max_upscale_factor; 901571a7a1Sriastradh // max downscale factor x1000 911571a7a1Sriastradh // downscale factors are always <= 1 921571a7a1Sriastradh // for example, 8K -> 1080p is 0.25, or 250 raw value 931571a7a1Sriastradh struct { 941571a7a1Sriastradh uint32_t argb8888; 951571a7a1Sriastradh uint32_t nv12; 961571a7a1Sriastradh uint32_t fp16; 971571a7a1Sriastradh } max_downscale_factor; 981571a7a1Sriastradh }; 991571a7a1Sriastradh 1001571a7a1Sriastradh struct dc_caps { 1011571a7a1Sriastradh uint32_t max_streams; 1021571a7a1Sriastradh uint32_t max_links; 1031571a7a1Sriastradh uint32_t max_audios; 1041571a7a1Sriastradh uint32_t max_slave_planes; 1051571a7a1Sriastradh uint32_t max_planes; 1061571a7a1Sriastradh uint32_t max_downscale_ratio; 1071571a7a1Sriastradh uint32_t i2c_speed_in_khz; 1081571a7a1Sriastradh uint32_t dmdata_alloc_size; 1091571a7a1Sriastradh unsigned int max_cursor_size; 1101571a7a1Sriastradh unsigned int max_video_width; 1111571a7a1Sriastradh int linear_pitch_alignment; 1121571a7a1Sriastradh bool dcc_const_color; 1131571a7a1Sriastradh bool dynamic_audio; 1141571a7a1Sriastradh bool is_apu; 1151571a7a1Sriastradh bool dual_link_dvi; 1161571a7a1Sriastradh bool post_blend_color_processing; 1171571a7a1Sriastradh bool force_dp_tps4_for_cp2520; 1181571a7a1Sriastradh bool disable_dp_clk_share; 1191571a7a1Sriastradh bool psp_setup_panel_mode; 1201571a7a1Sriastradh bool extended_aux_timeout_support; 1211571a7a1Sriastradh bool dmcub_support; 1221571a7a1Sriastradh bool hw_3d_lut; 1231571a7a1Sriastradh enum dp_protocol_version max_dp_protocol_version; 1241571a7a1Sriastradh struct dc_plane_cap planes[MAX_PLANES]; 1251571a7a1Sriastradh }; 1261571a7a1Sriastradh 1271571a7a1Sriastradh struct dc_bug_wa { 1281571a7a1Sriastradh bool no_connect_phy_config; 1291571a7a1Sriastradh bool dedcn20_305_wa; 1301571a7a1Sriastradh bool skip_clock_update; 1311571a7a1Sriastradh }; 1321571a7a1Sriastradh 1331571a7a1Sriastradh struct dc_dcc_surface_param { 1341571a7a1Sriastradh struct dc_size surface_size; 1351571a7a1Sriastradh enum surface_pixel_format format; 1361571a7a1Sriastradh enum swizzle_mode_values swizzle_mode; 1371571a7a1Sriastradh enum dc_scan_direction scan; 1381571a7a1Sriastradh }; 1391571a7a1Sriastradh 1401571a7a1Sriastradh struct dc_dcc_setting { 1411571a7a1Sriastradh unsigned int max_compressed_blk_size; 1421571a7a1Sriastradh unsigned int max_uncompressed_blk_size; 1431571a7a1Sriastradh bool independent_64b_blks; 1441571a7a1Sriastradh }; 1451571a7a1Sriastradh 1461571a7a1Sriastradh struct dc_surface_dcc_cap { 1471571a7a1Sriastradh union { 1481571a7a1Sriastradh struct { 1491571a7a1Sriastradh struct dc_dcc_setting rgb; 1501571a7a1Sriastradh } grph; 1511571a7a1Sriastradh 1521571a7a1Sriastradh struct { 1531571a7a1Sriastradh struct dc_dcc_setting luma; 1541571a7a1Sriastradh struct dc_dcc_setting chroma; 1551571a7a1Sriastradh } video; 1561571a7a1Sriastradh }; 1571571a7a1Sriastradh 1581571a7a1Sriastradh bool capable; 1591571a7a1Sriastradh bool const_color_support; 1601571a7a1Sriastradh }; 1611571a7a1Sriastradh 1621571a7a1Sriastradh struct dc_static_screen_params { 1631571a7a1Sriastradh struct { 1641571a7a1Sriastradh bool force_trigger; 1651571a7a1Sriastradh bool cursor_update; 1661571a7a1Sriastradh bool surface_update; 1671571a7a1Sriastradh bool overlay_update; 1681571a7a1Sriastradh } triggers; 1691571a7a1Sriastradh unsigned int num_frames; 1701571a7a1Sriastradh }; 1711571a7a1Sriastradh 1721571a7a1Sriastradh 1731571a7a1Sriastradh /* Surface update type is used by dc_update_surfaces_and_stream 1741571a7a1Sriastradh * The update type is determined at the very beginning of the function based 1751571a7a1Sriastradh * on parameters passed in and decides how much programming (or updating) is 1761571a7a1Sriastradh * going to be done during the call. 1771571a7a1Sriastradh * 1781571a7a1Sriastradh * UPDATE_TYPE_FAST is used for really fast updates that do not require much 1791571a7a1Sriastradh * logical calculations or hardware register programming. This update MUST be 1801571a7a1Sriastradh * ISR safe on windows. Currently fast update will only be used to flip surface 1811571a7a1Sriastradh * address. 1821571a7a1Sriastradh * 1831571a7a1Sriastradh * UPDATE_TYPE_MED is used for slower updates which require significant hw 1841571a7a1Sriastradh * re-programming however do not affect bandwidth consumption or clock 1851571a7a1Sriastradh * requirements. At present, this is the level at which front end updates 1861571a7a1Sriastradh * that do not require us to run bw_calcs happen. These are in/out transfer func 1871571a7a1Sriastradh * updates, viewport offset changes, recout size changes and pixel depth changes. 1881571a7a1Sriastradh * This update can be done at ISR, but we want to minimize how often this happens. 1891571a7a1Sriastradh * 1901571a7a1Sriastradh * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 1911571a7a1Sriastradh * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 1921571a7a1Sriastradh * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 1931571a7a1Sriastradh * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 1941571a7a1Sriastradh * a full update. This cannot be done at ISR level and should be a rare event. 1951571a7a1Sriastradh * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 1961571a7a1Sriastradh * underscan we don't expect to see this call at all. 1971571a7a1Sriastradh */ 1981571a7a1Sriastradh 1991571a7a1Sriastradh enum surface_update_type { 2001571a7a1Sriastradh UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 2011571a7a1Sriastradh UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 2021571a7a1Sriastradh UPDATE_TYPE_FULL, /* may need to shuffle resources */ 2031571a7a1Sriastradh }; 2041571a7a1Sriastradh 2051571a7a1Sriastradh /* Forward declaration*/ 2061571a7a1Sriastradh struct dc; 2071571a7a1Sriastradh struct dc_plane_state; 2081571a7a1Sriastradh struct dc_state; 2091571a7a1Sriastradh 2101571a7a1Sriastradh 2111571a7a1Sriastradh struct dc_cap_funcs { 2121571a7a1Sriastradh bool (*get_dcc_compression_cap)(const struct dc *dc, 2131571a7a1Sriastradh const struct dc_dcc_surface_param *input, 2141571a7a1Sriastradh struct dc_surface_dcc_cap *output); 2151571a7a1Sriastradh }; 2161571a7a1Sriastradh 2171571a7a1Sriastradh struct link_training_settings; 2181571a7a1Sriastradh 2191571a7a1Sriastradh 2201571a7a1Sriastradh /* Structure to hold configuration flags set by dm at dc creation. */ 2211571a7a1Sriastradh struct dc_config { 2221571a7a1Sriastradh bool gpu_vm_support; 2231571a7a1Sriastradh bool disable_disp_pll_sharing; 2241571a7a1Sriastradh bool fbc_support; 2251571a7a1Sriastradh bool optimize_edp_link_rate; 2261571a7a1Sriastradh bool disable_fractional_pwm; 2271571a7a1Sriastradh bool allow_seamless_boot_optimization; 2281571a7a1Sriastradh bool power_down_display_on_boot; 2291571a7a1Sriastradh bool edp_not_connected; 2301571a7a1Sriastradh bool force_enum_edp; 2311571a7a1Sriastradh bool forced_clocks; 2321571a7a1Sriastradh bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well 2331571a7a1Sriastradh bool multi_mon_pp_mclk_switch; 2341571a7a1Sriastradh }; 2351571a7a1Sriastradh 2361571a7a1Sriastradh enum visual_confirm { 2371571a7a1Sriastradh VISUAL_CONFIRM_DISABLE = 0, 2381571a7a1Sriastradh VISUAL_CONFIRM_SURFACE = 1, 2391571a7a1Sriastradh VISUAL_CONFIRM_HDR = 2, 2401571a7a1Sriastradh VISUAL_CONFIRM_MPCTREE = 4, 2411571a7a1Sriastradh }; 2421571a7a1Sriastradh 2431571a7a1Sriastradh enum dcc_option { 2441571a7a1Sriastradh DCC_ENABLE = 0, 2451571a7a1Sriastradh DCC_DISABLE = 1, 2461571a7a1Sriastradh DCC_HALF_REQ_DISALBE = 2, 2471571a7a1Sriastradh }; 2481571a7a1Sriastradh 2491571a7a1Sriastradh enum pipe_split_policy { 2501571a7a1Sriastradh MPC_SPLIT_DYNAMIC = 0, 2511571a7a1Sriastradh MPC_SPLIT_AVOID = 1, 2521571a7a1Sriastradh MPC_SPLIT_AVOID_MULT_DISP = 2, 2531571a7a1Sriastradh }; 2541571a7a1Sriastradh 2551571a7a1Sriastradh enum wm_report_mode { 2561571a7a1Sriastradh WM_REPORT_DEFAULT = 0, 2571571a7a1Sriastradh WM_REPORT_OVERRIDE = 1, 2581571a7a1Sriastradh }; 2591571a7a1Sriastradh enum dtm_pstate{ 2601571a7a1Sriastradh dtm_level_p0 = 0,/*highest voltage*/ 2611571a7a1Sriastradh dtm_level_p1, 2621571a7a1Sriastradh dtm_level_p2, 2631571a7a1Sriastradh dtm_level_p3, 2641571a7a1Sriastradh dtm_level_p4,/*when active_display_count = 0*/ 2651571a7a1Sriastradh }; 2661571a7a1Sriastradh 2671571a7a1Sriastradh enum dcn_pwr_state { 2681571a7a1Sriastradh DCN_PWR_STATE_UNKNOWN = -1, 2691571a7a1Sriastradh DCN_PWR_STATE_MISSION_MODE = 0, 2701571a7a1Sriastradh DCN_PWR_STATE_LOW_POWER = 3, 2711571a7a1Sriastradh }; 2721571a7a1Sriastradh 2731571a7a1Sriastradh /* 2741571a7a1Sriastradh * For any clocks that may differ per pipe 2751571a7a1Sriastradh * only the max is stored in this structure 2761571a7a1Sriastradh */ 2771571a7a1Sriastradh struct dc_clocks { 2781571a7a1Sriastradh int dispclk_khz; 2791571a7a1Sriastradh int dppclk_khz; 2801571a7a1Sriastradh int dcfclk_khz; 2811571a7a1Sriastradh int socclk_khz; 2821571a7a1Sriastradh int dcfclk_deep_sleep_khz; 2831571a7a1Sriastradh int fclk_khz; 2841571a7a1Sriastradh int phyclk_khz; 2851571a7a1Sriastradh int dramclk_khz; 2861571a7a1Sriastradh bool p_state_change_support; 2871571a7a1Sriastradh enum dcn_pwr_state pwr_state; 2881571a7a1Sriastradh /* 2891571a7a1Sriastradh * Elements below are not compared for the purposes of 2901571a7a1Sriastradh * optimization required 2911571a7a1Sriastradh */ 2921571a7a1Sriastradh bool prev_p_state_change_support; 2931571a7a1Sriastradh enum dtm_pstate dtm_level; 2941571a7a1Sriastradh int max_supported_dppclk_khz; 2951571a7a1Sriastradh int max_supported_dispclk_khz; 2961571a7a1Sriastradh int bw_dppclk_khz; /*a copy of dppclk_khz*/ 2971571a7a1Sriastradh int bw_dispclk_khz; 2981571a7a1Sriastradh }; 2991571a7a1Sriastradh 3001571a7a1Sriastradh struct dc_bw_validation_profile { 3011571a7a1Sriastradh bool enable; 3021571a7a1Sriastradh 3031571a7a1Sriastradh unsigned long long total_ticks; 3041571a7a1Sriastradh unsigned long long voltage_level_ticks; 3051571a7a1Sriastradh unsigned long long watermark_ticks; 3061571a7a1Sriastradh unsigned long long rq_dlg_ticks; 3071571a7a1Sriastradh 3081571a7a1Sriastradh unsigned long long total_count; 3091571a7a1Sriastradh unsigned long long skip_fast_count; 3101571a7a1Sriastradh unsigned long long skip_pass_count; 3111571a7a1Sriastradh unsigned long long skip_fail_count; 3121571a7a1Sriastradh }; 3131571a7a1Sriastradh 3141571a7a1Sriastradh #define BW_VAL_TRACE_SETUP() \ 3151571a7a1Sriastradh unsigned long long end_tick = 0; \ 3161571a7a1Sriastradh unsigned long long voltage_level_tick = 0; \ 3171571a7a1Sriastradh unsigned long long watermark_tick = 0; \ 3181571a7a1Sriastradh unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 3191571a7a1Sriastradh dm_get_timestamp(dc->ctx) : 0 3201571a7a1Sriastradh 3211571a7a1Sriastradh #define BW_VAL_TRACE_COUNT() \ 3221571a7a1Sriastradh if (dc->debug.bw_val_profile.enable) \ 3231571a7a1Sriastradh dc->debug.bw_val_profile.total_count++ 3241571a7a1Sriastradh 3251571a7a1Sriastradh #define BW_VAL_TRACE_SKIP(status) \ 3261571a7a1Sriastradh if (dc->debug.bw_val_profile.enable) { \ 3271571a7a1Sriastradh if (!voltage_level_tick) \ 3281571a7a1Sriastradh voltage_level_tick = dm_get_timestamp(dc->ctx); \ 3291571a7a1Sriastradh dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 3301571a7a1Sriastradh } 3311571a7a1Sriastradh 3321571a7a1Sriastradh #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 3331571a7a1Sriastradh if (dc->debug.bw_val_profile.enable) \ 3341571a7a1Sriastradh voltage_level_tick = dm_get_timestamp(dc->ctx) 3351571a7a1Sriastradh 3361571a7a1Sriastradh #define BW_VAL_TRACE_END_WATERMARKS() \ 3371571a7a1Sriastradh if (dc->debug.bw_val_profile.enable) \ 3381571a7a1Sriastradh watermark_tick = dm_get_timestamp(dc->ctx) 3391571a7a1Sriastradh 3401571a7a1Sriastradh #define BW_VAL_TRACE_FINISH() \ 3411571a7a1Sriastradh if (dc->debug.bw_val_profile.enable) { \ 3421571a7a1Sriastradh end_tick = dm_get_timestamp(dc->ctx); \ 3431571a7a1Sriastradh dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 3441571a7a1Sriastradh dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 3451571a7a1Sriastradh if (watermark_tick) { \ 3461571a7a1Sriastradh dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 3471571a7a1Sriastradh dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 3481571a7a1Sriastradh } \ 3491571a7a1Sriastradh } 3501571a7a1Sriastradh 3511571a7a1Sriastradh struct dc_debug_options { 3521571a7a1Sriastradh enum visual_confirm visual_confirm; 3531571a7a1Sriastradh bool sanity_checks; 3541571a7a1Sriastradh bool max_disp_clk; 3551571a7a1Sriastradh bool surface_trace; 3561571a7a1Sriastradh bool timing_trace; 3571571a7a1Sriastradh bool clock_trace; 3581571a7a1Sriastradh bool validation_trace; 3591571a7a1Sriastradh bool bandwidth_calcs_trace; 3601571a7a1Sriastradh int max_downscale_src_width; 3611571a7a1Sriastradh 3621571a7a1Sriastradh /* stutter efficiency related */ 3631571a7a1Sriastradh bool disable_stutter; 3641571a7a1Sriastradh bool use_max_lb; 3651571a7a1Sriastradh enum dcc_option disable_dcc; 3661571a7a1Sriastradh enum pipe_split_policy pipe_split_policy; 3671571a7a1Sriastradh bool force_single_disp_pipe_split; 3681571a7a1Sriastradh bool voltage_align_fclk; 3691571a7a1Sriastradh 3701571a7a1Sriastradh bool disable_dfs_bypass; 3711571a7a1Sriastradh bool disable_dpp_power_gate; 3721571a7a1Sriastradh bool disable_hubp_power_gate; 3731571a7a1Sriastradh bool disable_dsc_power_gate; 3741571a7a1Sriastradh int dsc_min_slice_height_override; 3751571a7a1Sriastradh int dsc_bpp_increment_div; 3761571a7a1Sriastradh bool native422_support; 3771571a7a1Sriastradh bool disable_pplib_wm_range; 3781571a7a1Sriastradh enum wm_report_mode pplib_wm_report_mode; 3791571a7a1Sriastradh unsigned int min_disp_clk_khz; 3801571a7a1Sriastradh unsigned int min_dpp_clk_khz; 3811571a7a1Sriastradh int sr_exit_time_dpm0_ns; 3821571a7a1Sriastradh int sr_enter_plus_exit_time_dpm0_ns; 3831571a7a1Sriastradh int sr_exit_time_ns; 3841571a7a1Sriastradh int sr_enter_plus_exit_time_ns; 3851571a7a1Sriastradh int urgent_latency_ns; 3861571a7a1Sriastradh uint32_t underflow_assert_delay_us; 3871571a7a1Sriastradh int percent_of_ideal_drambw; 3881571a7a1Sriastradh int dram_clock_change_latency_ns; 3891571a7a1Sriastradh bool optimized_watermark; 3901571a7a1Sriastradh int always_scale; 3911571a7a1Sriastradh bool disable_pplib_clock_request; 3921571a7a1Sriastradh bool disable_clock_gate; 3931571a7a1Sriastradh bool disable_dmcu; 3941571a7a1Sriastradh bool disable_psr; 3951571a7a1Sriastradh bool force_abm_enable; 3961571a7a1Sriastradh bool disable_stereo_support; 3971571a7a1Sriastradh bool vsr_support; 3981571a7a1Sriastradh bool performance_trace; 3991571a7a1Sriastradh bool az_endpoint_mute_only; 4001571a7a1Sriastradh bool always_use_regamma; 4011571a7a1Sriastradh bool p010_mpo_support; 4021571a7a1Sriastradh bool recovery_enabled; 4031571a7a1Sriastradh bool avoid_vbios_exec_table; 4041571a7a1Sriastradh bool scl_reset_length10; 4051571a7a1Sriastradh bool hdmi20_disable; 4061571a7a1Sriastradh bool skip_detection_link_training; 4071571a7a1Sriastradh bool remove_disconnect_edp; 4081571a7a1Sriastradh unsigned int force_odm_combine; //bit vector based on otg inst 4091571a7a1Sriastradh unsigned int force_fclk_khz; 4101571a7a1Sriastradh bool disable_tri_buf; 4111571a7a1Sriastradh bool dmub_offload_enabled; 4121571a7a1Sriastradh bool dmcub_emulation; 4131571a7a1Sriastradh bool dmub_command_table; /* for testing only */ 4141571a7a1Sriastradh struct dc_bw_validation_profile bw_val_profile; 4151571a7a1Sriastradh bool disable_fec; 4161571a7a1Sriastradh bool disable_48mhz_pwrdwn; 4171571a7a1Sriastradh /* This forces a hard min on the DCFCLK requested to SMU/PP 4181571a7a1Sriastradh * watermarks are not affected. 4191571a7a1Sriastradh */ 4201571a7a1Sriastradh unsigned int force_min_dcfclk_mhz; 4211571a7a1Sriastradh bool disable_timing_sync; 4221571a7a1Sriastradh bool cm_in_bypass; 4231571a7a1Sriastradh int force_clock_mode;/*every mode change.*/ 4241571a7a1Sriastradh 4251571a7a1Sriastradh bool nv12_iflip_vm_wa; 4261571a7a1Sriastradh bool disable_dram_clock_change_vactive_support; 4271571a7a1Sriastradh bool validate_dml_output; 4281571a7a1Sriastradh bool enable_dmcub_surface_flip; 4291571a7a1Sriastradh bool usbc_combo_phy_reset_wa; 4301571a7a1Sriastradh bool disable_dsc; 4311571a7a1Sriastradh }; 4321571a7a1Sriastradh 4331571a7a1Sriastradh struct dc_debug_data { 4341571a7a1Sriastradh uint32_t ltFailCount; 4351571a7a1Sriastradh uint32_t i2cErrorCount; 4361571a7a1Sriastradh uint32_t auxErrorCount; 4371571a7a1Sriastradh }; 4381571a7a1Sriastradh 4391571a7a1Sriastradh struct dc_phy_addr_space_config { 4401571a7a1Sriastradh struct { 4411571a7a1Sriastradh uint64_t start_addr; 4421571a7a1Sriastradh uint64_t end_addr; 4431571a7a1Sriastradh uint64_t fb_top; 4441571a7a1Sriastradh uint64_t fb_offset; 4451571a7a1Sriastradh uint64_t fb_base; 4461571a7a1Sriastradh uint64_t agp_top; 4471571a7a1Sriastradh uint64_t agp_bot; 4481571a7a1Sriastradh uint64_t agp_base; 4491571a7a1Sriastradh } system_aperture; 4501571a7a1Sriastradh 4511571a7a1Sriastradh struct { 4521571a7a1Sriastradh uint64_t page_table_start_addr; 4531571a7a1Sriastradh uint64_t page_table_end_addr; 4541571a7a1Sriastradh uint64_t page_table_base_addr; 4551571a7a1Sriastradh } gart_config; 4561571a7a1Sriastradh 4571571a7a1Sriastradh bool valid; 4581571a7a1Sriastradh uint64_t page_table_default_page_addr; 4591571a7a1Sriastradh }; 4601571a7a1Sriastradh 4611571a7a1Sriastradh struct dc_virtual_addr_space_config { 4621571a7a1Sriastradh uint64_t page_table_base_addr; 4631571a7a1Sriastradh uint64_t page_table_start_addr; 4641571a7a1Sriastradh uint64_t page_table_end_addr; 4651571a7a1Sriastradh uint32_t page_table_block_size_in_bytes; 4661571a7a1Sriastradh uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 4671571a7a1Sriastradh }; 4681571a7a1Sriastradh 4691571a7a1Sriastradh struct dc_bounding_box_overrides { 4701571a7a1Sriastradh int sr_exit_time_ns; 4711571a7a1Sriastradh int sr_enter_plus_exit_time_ns; 4721571a7a1Sriastradh int urgent_latency_ns; 4731571a7a1Sriastradh int percent_of_ideal_drambw; 4741571a7a1Sriastradh int dram_clock_change_latency_ns; 4751571a7a1Sriastradh /* This forces a hard min on the DCFCLK we use 4761571a7a1Sriastradh * for DML. Unlike the debug option for forcing 4771571a7a1Sriastradh * DCFCLK, this override affects watermark calculations 4781571a7a1Sriastradh */ 4791571a7a1Sriastradh int min_dcfclk_mhz; 4801571a7a1Sriastradh }; 4811571a7a1Sriastradh 4821571a7a1Sriastradh struct dc_state; 4831571a7a1Sriastradh struct resource_pool; 4841571a7a1Sriastradh struct dce_hwseq; 4851571a7a1Sriastradh struct gpu_info_soc_bounding_box_v1_0; 4861571a7a1Sriastradh struct dc { 4871571a7a1Sriastradh struct dc_versions versions; 4881571a7a1Sriastradh struct dc_caps caps; 4891571a7a1Sriastradh struct dc_cap_funcs cap_funcs; 4901571a7a1Sriastradh struct dc_config config; 4911571a7a1Sriastradh struct dc_debug_options debug; 4921571a7a1Sriastradh struct dc_bounding_box_overrides bb_overrides; 4931571a7a1Sriastradh struct dc_bug_wa work_arounds; 4941571a7a1Sriastradh struct dc_context *ctx; 4951571a7a1Sriastradh struct dc_phy_addr_space_config vm_pa_config; 4961571a7a1Sriastradh 4971571a7a1Sriastradh uint8_t link_count; 4981571a7a1Sriastradh struct dc_link *links[MAX_PIPES * 2]; 4991571a7a1Sriastradh 5001571a7a1Sriastradh struct dc_state *current_state; 5011571a7a1Sriastradh struct resource_pool *res_pool; 5021571a7a1Sriastradh 5031571a7a1Sriastradh struct clk_mgr *clk_mgr; 5041571a7a1Sriastradh 5051571a7a1Sriastradh /* Display Engine Clock levels */ 5061571a7a1Sriastradh struct dm_pp_clock_levels sclk_lvls; 5071571a7a1Sriastradh 5081571a7a1Sriastradh /* Inputs into BW and WM calculations. */ 5091571a7a1Sriastradh struct bw_calcs_dceip *bw_dceip; 5101571a7a1Sriastradh struct bw_calcs_vbios *bw_vbios; 5111571a7a1Sriastradh #ifdef CONFIG_DRM_AMD_DC_DCN 5121571a7a1Sriastradh struct dcn_soc_bounding_box *dcn_soc; 5131571a7a1Sriastradh struct dcn_ip_params *dcn_ip; 5141571a7a1Sriastradh struct display_mode_lib dml; 5151571a7a1Sriastradh #endif 5161571a7a1Sriastradh 5171571a7a1Sriastradh /* HW functions */ 5181571a7a1Sriastradh struct hw_sequencer_funcs hwss; 5191571a7a1Sriastradh struct dce_hwseq *hwseq; 5201571a7a1Sriastradh 5211571a7a1Sriastradh /* Require to optimize clocks and bandwidth for added/removed planes */ 5221571a7a1Sriastradh bool optimized_required; 5231571a7a1Sriastradh 5241571a7a1Sriastradh /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 5251571a7a1Sriastradh int optimize_seamless_boot_streams; 5261571a7a1Sriastradh 5271571a7a1Sriastradh /* FBC compressor */ 5281571a7a1Sriastradh struct compressor *fbc_compressor; 5291571a7a1Sriastradh 5301571a7a1Sriastradh struct dc_debug_data debug_data; 5311571a7a1Sriastradh 5321571a7a1Sriastradh const char *build_id; 5331571a7a1Sriastradh struct vm_helper *vm_helper; 5341571a7a1Sriastradh const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 5351571a7a1Sriastradh }; 5361571a7a1Sriastradh 5371571a7a1Sriastradh enum frame_buffer_mode { 5381571a7a1Sriastradh FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 5391571a7a1Sriastradh FRAME_BUFFER_MODE_ZFB_ONLY, 5401571a7a1Sriastradh FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 5411571a7a1Sriastradh } ; 5421571a7a1Sriastradh 5431571a7a1Sriastradh struct dchub_init_data { 5441571a7a1Sriastradh int64_t zfb_phys_addr_base; 5451571a7a1Sriastradh int64_t zfb_mc_base_addr; 5461571a7a1Sriastradh uint64_t zfb_size_in_byte; 5471571a7a1Sriastradh enum frame_buffer_mode fb_mode; 5481571a7a1Sriastradh bool dchub_initialzied; 5491571a7a1Sriastradh bool dchub_info_valid; 5501571a7a1Sriastradh }; 5511571a7a1Sriastradh 5521571a7a1Sriastradh struct dc_init_data { 5531571a7a1Sriastradh struct hw_asic_id asic_id; 5541571a7a1Sriastradh void *driver; /* ctx */ 5551571a7a1Sriastradh struct cgs_device *cgs_device; 5561571a7a1Sriastradh struct dc_bounding_box_overrides bb_overrides; 5571571a7a1Sriastradh 5581571a7a1Sriastradh int num_virtual_links; 5591571a7a1Sriastradh /* 5601571a7a1Sriastradh * If 'vbios_override' not NULL, it will be called instead 5611571a7a1Sriastradh * of the real VBIOS. Intended use is Diagnostics on FPGA. 5621571a7a1Sriastradh */ 5631571a7a1Sriastradh struct dc_bios *vbios_override; 5641571a7a1Sriastradh enum dce_environment dce_environment; 5651571a7a1Sriastradh 5661571a7a1Sriastradh struct dmub_offload_funcs *dmub_if; 5671571a7a1Sriastradh struct dc_reg_helper_state *dmub_offload; 5681571a7a1Sriastradh 5691571a7a1Sriastradh struct dc_config flags; 5701571a7a1Sriastradh uint32_t log_mask; 5711571a7a1Sriastradh /** 5721571a7a1Sriastradh * gpu_info FW provided soc bounding box struct or 0 if not 5731571a7a1Sriastradh * available in FW 5741571a7a1Sriastradh */ 5751571a7a1Sriastradh const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 5761571a7a1Sriastradh }; 5771571a7a1Sriastradh 5781571a7a1Sriastradh struct dc_callback_init { 5791571a7a1Sriastradh #ifdef CONFIG_DRM_AMD_DC_HDCP 5801571a7a1Sriastradh struct cp_psp cp_psp; 5811571a7a1Sriastradh #else 5821571a7a1Sriastradh uint8_t reserved; 5831571a7a1Sriastradh #endif 5841571a7a1Sriastradh }; 5851571a7a1Sriastradh 5861571a7a1Sriastradh struct dc *dc_create(const struct dc_init_data *init_params); 5871571a7a1Sriastradh void dc_hardware_init(struct dc *dc); 5881571a7a1Sriastradh 5891571a7a1Sriastradh int dc_get_vmid_use_vector(struct dc *dc); 5901571a7a1Sriastradh void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 5911571a7a1Sriastradh /* Returns the number of vmids supported */ 5921571a7a1Sriastradh int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 5931571a7a1Sriastradh void dc_init_callbacks(struct dc *dc, 5941571a7a1Sriastradh const struct dc_callback_init *init_params); 5951571a7a1Sriastradh void dc_deinit_callbacks(struct dc *dc); 5961571a7a1Sriastradh void dc_destroy(struct dc **dc); 5971571a7a1Sriastradh 5981571a7a1Sriastradh /******************************************************************************* 5991571a7a1Sriastradh * Surface Interfaces 6001571a7a1Sriastradh ******************************************************************************/ 6011571a7a1Sriastradh 6021571a7a1Sriastradh enum { 6031571a7a1Sriastradh TRANSFER_FUNC_POINTS = 1025 6041571a7a1Sriastradh }; 6051571a7a1Sriastradh 6061571a7a1Sriastradh struct dc_hdr_static_metadata { 6071571a7a1Sriastradh /* display chromaticities and white point in units of 0.00001 */ 6081571a7a1Sriastradh unsigned int chromaticity_green_x; 6091571a7a1Sriastradh unsigned int chromaticity_green_y; 6101571a7a1Sriastradh unsigned int chromaticity_blue_x; 6111571a7a1Sriastradh unsigned int chromaticity_blue_y; 6121571a7a1Sriastradh unsigned int chromaticity_red_x; 6131571a7a1Sriastradh unsigned int chromaticity_red_y; 6141571a7a1Sriastradh unsigned int chromaticity_white_point_x; 6151571a7a1Sriastradh unsigned int chromaticity_white_point_y; 6161571a7a1Sriastradh 6171571a7a1Sriastradh uint32_t min_luminance; 6181571a7a1Sriastradh uint32_t max_luminance; 6191571a7a1Sriastradh uint32_t maximum_content_light_level; 6201571a7a1Sriastradh uint32_t maximum_frame_average_light_level; 6211571a7a1Sriastradh }; 6221571a7a1Sriastradh 6231571a7a1Sriastradh enum dc_transfer_func_type { 6241571a7a1Sriastradh TF_TYPE_PREDEFINED, 6251571a7a1Sriastradh TF_TYPE_DISTRIBUTED_POINTS, 6261571a7a1Sriastradh TF_TYPE_BYPASS, 6271571a7a1Sriastradh TF_TYPE_HWPWL 6281571a7a1Sriastradh }; 6291571a7a1Sriastradh 6301571a7a1Sriastradh struct dc_transfer_func_distributed_points { 6311571a7a1Sriastradh struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 6321571a7a1Sriastradh struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 6331571a7a1Sriastradh struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 6341571a7a1Sriastradh 6351571a7a1Sriastradh uint16_t end_exponent; 6361571a7a1Sriastradh uint16_t x_point_at_y1_red; 6371571a7a1Sriastradh uint16_t x_point_at_y1_green; 6381571a7a1Sriastradh uint16_t x_point_at_y1_blue; 6391571a7a1Sriastradh }; 6401571a7a1Sriastradh 6411571a7a1Sriastradh enum dc_transfer_func_predefined { 6421571a7a1Sriastradh TRANSFER_FUNCTION_SRGB, 6431571a7a1Sriastradh TRANSFER_FUNCTION_BT709, 6441571a7a1Sriastradh TRANSFER_FUNCTION_PQ, 6451571a7a1Sriastradh TRANSFER_FUNCTION_LINEAR, 6461571a7a1Sriastradh TRANSFER_FUNCTION_UNITY, 6471571a7a1Sriastradh TRANSFER_FUNCTION_HLG, 6481571a7a1Sriastradh TRANSFER_FUNCTION_HLG12, 6491571a7a1Sriastradh TRANSFER_FUNCTION_GAMMA22, 6501571a7a1Sriastradh TRANSFER_FUNCTION_GAMMA24, 6511571a7a1Sriastradh TRANSFER_FUNCTION_GAMMA26 6521571a7a1Sriastradh }; 6531571a7a1Sriastradh 6541571a7a1Sriastradh 6551571a7a1Sriastradh struct dc_transfer_func { 6561571a7a1Sriastradh struct kref refcount; 6571571a7a1Sriastradh enum dc_transfer_func_type type; 6581571a7a1Sriastradh enum dc_transfer_func_predefined tf; 6591571a7a1Sriastradh /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 6601571a7a1Sriastradh uint32_t sdr_ref_white_level; 6611571a7a1Sriastradh struct dc_context *ctx; 6621571a7a1Sriastradh union { 6631571a7a1Sriastradh struct pwl_params pwl; 6641571a7a1Sriastradh struct dc_transfer_func_distributed_points tf_pts; 6651571a7a1Sriastradh }; 6661571a7a1Sriastradh }; 6671571a7a1Sriastradh 6681571a7a1Sriastradh 6691571a7a1Sriastradh union dc_3dlut_state { 6701571a7a1Sriastradh struct { 6711571a7a1Sriastradh uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 6721571a7a1Sriastradh uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 6731571a7a1Sriastradh uint32_t rmu_mux_num:3; /*index of mux to use*/ 6741571a7a1Sriastradh uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 6751571a7a1Sriastradh uint32_t mpc_rmu1_mux:4; 6761571a7a1Sriastradh uint32_t mpc_rmu2_mux:4; 6771571a7a1Sriastradh uint32_t reserved:15; 6781571a7a1Sriastradh } bits; 6791571a7a1Sriastradh uint32_t raw; 6801571a7a1Sriastradh }; 6811571a7a1Sriastradh 6821571a7a1Sriastradh 6831571a7a1Sriastradh struct dc_3dlut { 6841571a7a1Sriastradh struct kref refcount; 6851571a7a1Sriastradh struct tetrahedral_params lut_3d; 6861571a7a1Sriastradh struct fixed31_32 hdr_multiplier; 6871571a7a1Sriastradh bool initialized; /*remove after diag fix*/ 6881571a7a1Sriastradh union dc_3dlut_state state; 6891571a7a1Sriastradh struct dc_context *ctx; 6901571a7a1Sriastradh }; 6911571a7a1Sriastradh /* 6921571a7a1Sriastradh * This structure is filled in by dc_surface_get_status and contains 6931571a7a1Sriastradh * the last requested address and the currently active address so the called 6941571a7a1Sriastradh * can determine if there are any outstanding flips 6951571a7a1Sriastradh */ 6961571a7a1Sriastradh struct dc_plane_status { 6971571a7a1Sriastradh struct dc_plane_address requested_address; 6981571a7a1Sriastradh struct dc_plane_address current_address; 6991571a7a1Sriastradh bool is_flip_pending; 7001571a7a1Sriastradh bool is_right_eye; 7011571a7a1Sriastradh }; 7021571a7a1Sriastradh 7031571a7a1Sriastradh union surface_update_flags { 7041571a7a1Sriastradh 7051571a7a1Sriastradh struct { 7061571a7a1Sriastradh uint32_t addr_update:1; 7071571a7a1Sriastradh /* Medium updates */ 7081571a7a1Sriastradh uint32_t dcc_change:1; 7091571a7a1Sriastradh uint32_t color_space_change:1; 7101571a7a1Sriastradh uint32_t horizontal_mirror_change:1; 7111571a7a1Sriastradh uint32_t per_pixel_alpha_change:1; 7121571a7a1Sriastradh uint32_t global_alpha_change:1; 7131571a7a1Sriastradh uint32_t hdr_mult:1; 7141571a7a1Sriastradh uint32_t rotation_change:1; 7151571a7a1Sriastradh uint32_t swizzle_change:1; 7161571a7a1Sriastradh uint32_t scaling_change:1; 7171571a7a1Sriastradh uint32_t position_change:1; 7181571a7a1Sriastradh uint32_t in_transfer_func_change:1; 7191571a7a1Sriastradh uint32_t input_csc_change:1; 7201571a7a1Sriastradh uint32_t coeff_reduction_change:1; 7211571a7a1Sriastradh uint32_t output_tf_change:1; 7221571a7a1Sriastradh uint32_t pixel_format_change:1; 7231571a7a1Sriastradh uint32_t plane_size_change:1; 7241571a7a1Sriastradh 7251571a7a1Sriastradh /* Full updates */ 7261571a7a1Sriastradh uint32_t new_plane:1; 7271571a7a1Sriastradh uint32_t bpp_change:1; 7281571a7a1Sriastradh uint32_t gamma_change:1; 7291571a7a1Sriastradh uint32_t bandwidth_change:1; 7301571a7a1Sriastradh uint32_t clock_change:1; 7311571a7a1Sriastradh uint32_t stereo_format_change:1; 7321571a7a1Sriastradh uint32_t full_update:1; 7331571a7a1Sriastradh } bits; 7341571a7a1Sriastradh 7351571a7a1Sriastradh uint32_t raw; 7361571a7a1Sriastradh }; 7371571a7a1Sriastradh 7381571a7a1Sriastradh struct dc_plane_state { 7391571a7a1Sriastradh struct dc_plane_address address; 7401571a7a1Sriastradh struct dc_plane_flip_time time; 7411571a7a1Sriastradh bool triplebuffer_flips; 7421571a7a1Sriastradh struct scaling_taps scaling_quality; 7431571a7a1Sriastradh struct rect src_rect; 7441571a7a1Sriastradh struct rect dst_rect; 7451571a7a1Sriastradh struct rect clip_rect; 7461571a7a1Sriastradh 7471571a7a1Sriastradh struct plane_size plane_size; 7481571a7a1Sriastradh union dc_tiling_info tiling_info; 7491571a7a1Sriastradh 7501571a7a1Sriastradh struct dc_plane_dcc_param dcc; 7511571a7a1Sriastradh 7521571a7a1Sriastradh struct dc_gamma *gamma_correction; 7531571a7a1Sriastradh struct dc_transfer_func *in_transfer_func; 7541571a7a1Sriastradh struct dc_bias_and_scale *bias_and_scale; 7551571a7a1Sriastradh struct dc_csc_transform input_csc_color_matrix; 7561571a7a1Sriastradh struct fixed31_32 coeff_reduction_factor; 7571571a7a1Sriastradh struct fixed31_32 hdr_mult; 7581571a7a1Sriastradh 7591571a7a1Sriastradh // TODO: No longer used, remove 7601571a7a1Sriastradh struct dc_hdr_static_metadata hdr_static_ctx; 7611571a7a1Sriastradh 7621571a7a1Sriastradh enum dc_color_space color_space; 7631571a7a1Sriastradh 7641571a7a1Sriastradh struct dc_3dlut *lut3d_func; 7651571a7a1Sriastradh struct dc_transfer_func *in_shaper_func; 7661571a7a1Sriastradh struct dc_transfer_func *blend_tf; 7671571a7a1Sriastradh 7681571a7a1Sriastradh enum surface_pixel_format format; 7691571a7a1Sriastradh enum dc_rotation_angle rotation; 7701571a7a1Sriastradh enum plane_stereo_format stereo_format; 7711571a7a1Sriastradh 7721571a7a1Sriastradh bool is_tiling_rotated; 7731571a7a1Sriastradh bool per_pixel_alpha; 7741571a7a1Sriastradh bool global_alpha; 7751571a7a1Sriastradh int global_alpha_value; 7761571a7a1Sriastradh bool visible; 7771571a7a1Sriastradh bool flip_immediate; 7781571a7a1Sriastradh bool horizontal_mirror; 7791571a7a1Sriastradh int layer_index; 7801571a7a1Sriastradh 7811571a7a1Sriastradh union surface_update_flags update_flags; 7821571a7a1Sriastradh /* private to DC core */ 7831571a7a1Sriastradh struct dc_plane_status status; 7841571a7a1Sriastradh struct dc_context *ctx; 7851571a7a1Sriastradh 7861571a7a1Sriastradh /* HACK: Workaround for forcing full reprogramming under some conditions */ 7871571a7a1Sriastradh bool force_full_update; 7881571a7a1Sriastradh 7891571a7a1Sriastradh /* private to dc_surface.c */ 7901571a7a1Sriastradh enum dc_irq_source irq_source; 7911571a7a1Sriastradh struct kref refcount; 7921571a7a1Sriastradh }; 7931571a7a1Sriastradh 7941571a7a1Sriastradh struct dc_plane_info { 7951571a7a1Sriastradh struct plane_size plane_size; 7961571a7a1Sriastradh union dc_tiling_info tiling_info; 7971571a7a1Sriastradh struct dc_plane_dcc_param dcc; 7981571a7a1Sriastradh enum surface_pixel_format format; 7991571a7a1Sriastradh enum dc_rotation_angle rotation; 8001571a7a1Sriastradh enum plane_stereo_format stereo_format; 8011571a7a1Sriastradh enum dc_color_space color_space; 8021571a7a1Sriastradh bool horizontal_mirror; 8031571a7a1Sriastradh bool visible; 8041571a7a1Sriastradh bool per_pixel_alpha; 8051571a7a1Sriastradh bool global_alpha; 8061571a7a1Sriastradh int global_alpha_value; 8071571a7a1Sriastradh bool input_csc_enabled; 8081571a7a1Sriastradh int layer_index; 8091571a7a1Sriastradh }; 8101571a7a1Sriastradh 8111571a7a1Sriastradh struct dc_scaling_info { 8121571a7a1Sriastradh struct rect src_rect; 8131571a7a1Sriastradh struct rect dst_rect; 8141571a7a1Sriastradh struct rect clip_rect; 8151571a7a1Sriastradh struct scaling_taps scaling_quality; 8161571a7a1Sriastradh }; 8171571a7a1Sriastradh 8181571a7a1Sriastradh struct dc_surface_update { 8191571a7a1Sriastradh struct dc_plane_state *surface; 8201571a7a1Sriastradh 8211571a7a1Sriastradh /* isr safe update parameters. null means no updates */ 8221571a7a1Sriastradh const struct dc_flip_addrs *flip_addr; 8231571a7a1Sriastradh const struct dc_plane_info *plane_info; 8241571a7a1Sriastradh const struct dc_scaling_info *scaling_info; 8251571a7a1Sriastradh struct fixed31_32 hdr_mult; 8261571a7a1Sriastradh /* following updates require alloc/sleep/spin that is not isr safe, 8271571a7a1Sriastradh * null means no updates 8281571a7a1Sriastradh */ 8291571a7a1Sriastradh const struct dc_gamma *gamma; 8301571a7a1Sriastradh const struct dc_transfer_func *in_transfer_func; 8311571a7a1Sriastradh 8321571a7a1Sriastradh const struct dc_csc_transform *input_csc_color_matrix; 8331571a7a1Sriastradh const struct fixed31_32 *coeff_reduction_factor; 8341571a7a1Sriastradh const struct dc_transfer_func *func_shaper; 8351571a7a1Sriastradh const struct dc_3dlut *lut3d_func; 8361571a7a1Sriastradh const struct dc_transfer_func *blend_tf; 8371571a7a1Sriastradh }; 8381571a7a1Sriastradh 8391571a7a1Sriastradh /* 8401571a7a1Sriastradh * Create a new surface with default parameters; 8411571a7a1Sriastradh */ 8421571a7a1Sriastradh struct dc_plane_state *dc_create_plane_state(struct dc *dc); 8431571a7a1Sriastradh const struct dc_plane_status *dc_plane_get_status( 8441571a7a1Sriastradh const struct dc_plane_state *plane_state); 8451571a7a1Sriastradh 8461571a7a1Sriastradh void dc_plane_state_retain(struct dc_plane_state *plane_state); 8471571a7a1Sriastradh void dc_plane_state_release(struct dc_plane_state *plane_state); 8481571a7a1Sriastradh 8491571a7a1Sriastradh void dc_gamma_retain(struct dc_gamma *dc_gamma); 8501571a7a1Sriastradh void dc_gamma_release(struct dc_gamma **dc_gamma); 8511571a7a1Sriastradh struct dc_gamma *dc_create_gamma(void); 8521571a7a1Sriastradh 8531571a7a1Sriastradh void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 8541571a7a1Sriastradh void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 8551571a7a1Sriastradh struct dc_transfer_func *dc_create_transfer_func(void); 8561571a7a1Sriastradh 8571571a7a1Sriastradh struct dc_3dlut *dc_create_3dlut_func(void); 8581571a7a1Sriastradh void dc_3dlut_func_release(struct dc_3dlut *lut); 8591571a7a1Sriastradh void dc_3dlut_func_retain(struct dc_3dlut *lut); 8601571a7a1Sriastradh /* 8611571a7a1Sriastradh * This structure holds a surface address. There could be multiple addresses 8621571a7a1Sriastradh * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 8631571a7a1Sriastradh * as frame durations and DCC format can also be set. 8641571a7a1Sriastradh */ 8651571a7a1Sriastradh struct dc_flip_addrs { 8661571a7a1Sriastradh struct dc_plane_address address; 8671571a7a1Sriastradh unsigned int flip_timestamp_in_us; 8681571a7a1Sriastradh bool flip_immediate; 8691571a7a1Sriastradh /* TODO: add flip duration for FreeSync */ 8701571a7a1Sriastradh }; 8711571a7a1Sriastradh 8721571a7a1Sriastradh bool dc_post_update_surfaces_to_stream( 8731571a7a1Sriastradh struct dc *dc); 8741571a7a1Sriastradh 8751571a7a1Sriastradh #include "dc_stream.h" 8761571a7a1Sriastradh 8771571a7a1Sriastradh /* 8781571a7a1Sriastradh * Structure to store surface/stream associations for validation 8791571a7a1Sriastradh */ 8801571a7a1Sriastradh struct dc_validation_set { 8811571a7a1Sriastradh struct dc_stream_state *stream; 8821571a7a1Sriastradh struct dc_plane_state *plane_states[MAX_SURFACES]; 8831571a7a1Sriastradh uint8_t plane_count; 8841571a7a1Sriastradh }; 8851571a7a1Sriastradh 8861571a7a1Sriastradh bool dc_validate_seamless_boot_timing(const struct dc *dc, 8871571a7a1Sriastradh const struct dc_sink *sink, 8881571a7a1Sriastradh struct dc_crtc_timing *crtc_timing); 8891571a7a1Sriastradh 8901571a7a1Sriastradh enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 8911571a7a1Sriastradh 8921571a7a1Sriastradh void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 8931571a7a1Sriastradh 8941571a7a1Sriastradh bool dc_set_generic_gpio_for_stereo(bool enable, 8951571a7a1Sriastradh struct gpio_service *gpio_service); 8961571a7a1Sriastradh 8971571a7a1Sriastradh /* 8981571a7a1Sriastradh * fast_validate: we return after determining if we can support the new state, 8991571a7a1Sriastradh * but before we populate the programming info 9001571a7a1Sriastradh */ 9011571a7a1Sriastradh enum dc_status dc_validate_global_state( 9021571a7a1Sriastradh struct dc *dc, 9031571a7a1Sriastradh struct dc_state *new_ctx, 9041571a7a1Sriastradh bool fast_validate); 9051571a7a1Sriastradh 9061571a7a1Sriastradh 9071571a7a1Sriastradh void dc_resource_state_construct( 9081571a7a1Sriastradh const struct dc *dc, 9091571a7a1Sriastradh struct dc_state *dst_ctx); 9101571a7a1Sriastradh 9111571a7a1Sriastradh void dc_resource_state_copy_construct( 9121571a7a1Sriastradh const struct dc_state *src_ctx, 9131571a7a1Sriastradh struct dc_state *dst_ctx); 9141571a7a1Sriastradh 9151571a7a1Sriastradh void dc_resource_state_copy_construct_current( 9161571a7a1Sriastradh const struct dc *dc, 9171571a7a1Sriastradh struct dc_state *dst_ctx); 9181571a7a1Sriastradh 9191571a7a1Sriastradh void dc_resource_state_destruct(struct dc_state *context); 9201571a7a1Sriastradh 9211571a7a1Sriastradh bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 9221571a7a1Sriastradh 9231571a7a1Sriastradh /* 9241571a7a1Sriastradh * TODO update to make it about validation sets 9251571a7a1Sriastradh * Set up streams and links associated to drive sinks 9261571a7a1Sriastradh * The streams parameter is an absolute set of all active streams. 9271571a7a1Sriastradh * 9281571a7a1Sriastradh * After this call: 9291571a7a1Sriastradh * Phy, Encoder, Timing Generator are programmed and enabled. 9301571a7a1Sriastradh * New streams are enabled with blank stream; no memory read. 9311571a7a1Sriastradh */ 9321571a7a1Sriastradh bool dc_commit_state(struct dc *dc, struct dc_state *context); 9331571a7a1Sriastradh 9341571a7a1Sriastradh 9351571a7a1Sriastradh struct dc_state *dc_create_state(struct dc *dc); 9361571a7a1Sriastradh struct dc_state *dc_copy_state(struct dc_state *src_ctx); 9371571a7a1Sriastradh void dc_retain_state(struct dc_state *context); 9381571a7a1Sriastradh void dc_release_state(struct dc_state *context); 9391571a7a1Sriastradh 9401571a7a1Sriastradh /******************************************************************************* 9411571a7a1Sriastradh * Link Interfaces 9421571a7a1Sriastradh ******************************************************************************/ 9431571a7a1Sriastradh 9441571a7a1Sriastradh struct dpcd_caps { 9451571a7a1Sriastradh union dpcd_rev dpcd_rev; 9461571a7a1Sriastradh union max_lane_count max_ln_count; 9471571a7a1Sriastradh union max_down_spread max_down_spread; 9481571a7a1Sriastradh union dprx_feature dprx_feature; 9491571a7a1Sriastradh 9501571a7a1Sriastradh /* valid only for eDP v1.4 or higher*/ 9511571a7a1Sriastradh uint8_t edp_supported_link_rates_count; 9521571a7a1Sriastradh enum dc_link_rate edp_supported_link_rates[8]; 9531571a7a1Sriastradh 9541571a7a1Sriastradh /* dongle type (DP converter, CV smart dongle) */ 9551571a7a1Sriastradh enum display_dongle_type dongle_type; 9561571a7a1Sriastradh /* branch device or sink device */ 9571571a7a1Sriastradh bool is_branch_dev; 9581571a7a1Sriastradh /* Dongle's downstream count. */ 9591571a7a1Sriastradh union sink_count sink_count; 9601571a7a1Sriastradh /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 9611571a7a1Sriastradh indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 9621571a7a1Sriastradh struct dc_dongle_caps dongle_caps; 9631571a7a1Sriastradh 9641571a7a1Sriastradh uint32_t sink_dev_id; 9651571a7a1Sriastradh int8_t sink_dev_id_str[6]; 9661571a7a1Sriastradh int8_t sink_hw_revision; 9671571a7a1Sriastradh int8_t sink_fw_revision[2]; 9681571a7a1Sriastradh 9691571a7a1Sriastradh uint32_t branch_dev_id; 9701571a7a1Sriastradh int8_t branch_dev_name[6]; 9711571a7a1Sriastradh int8_t branch_hw_revision; 9721571a7a1Sriastradh int8_t branch_fw_revision[2]; 9731571a7a1Sriastradh 9741571a7a1Sriastradh bool allow_invalid_MSA_timing_param; 9751571a7a1Sriastradh bool panel_mode_edp; 9761571a7a1Sriastradh bool dpcd_display_control_capable; 9771571a7a1Sriastradh bool ext_receiver_cap_field_present; 9781571a7a1Sriastradh union dpcd_fec_capability fec_cap; 9791571a7a1Sriastradh struct dpcd_dsc_capabilities dsc_caps; 9801571a7a1Sriastradh struct dc_lttpr_caps lttpr_caps; 9811571a7a1Sriastradh 9821571a7a1Sriastradh }; 9831571a7a1Sriastradh 9841571a7a1Sriastradh #include "dc_link.h" 9851571a7a1Sriastradh 9861571a7a1Sriastradh /******************************************************************************* 9871571a7a1Sriastradh * Sink Interfaces - A sink corresponds to a display output device 9881571a7a1Sriastradh ******************************************************************************/ 9891571a7a1Sriastradh 9901571a7a1Sriastradh struct dc_container_id { 9911571a7a1Sriastradh // 128bit GUID in binary form 9921571a7a1Sriastradh unsigned char guid[16]; 9931571a7a1Sriastradh // 8 byte port ID -> ELD.PortID 9941571a7a1Sriastradh unsigned int portId[2]; 9951571a7a1Sriastradh // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 9961571a7a1Sriastradh unsigned short manufacturerName; 9971571a7a1Sriastradh // 2 byte product code -> ELD.ProductCode 9981571a7a1Sriastradh unsigned short productCode; 9991571a7a1Sriastradh }; 10001571a7a1Sriastradh 10011571a7a1Sriastradh 10021571a7a1Sriastradh struct dc_sink_dsc_caps { 10031571a7a1Sriastradh // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 10041571a7a1Sriastradh // 'false' if they are sink's DSC caps 10051571a7a1Sriastradh bool is_virtual_dpcd_dsc; 10061571a7a1Sriastradh struct dsc_dec_dpcd_caps dsc_dec_caps; 10071571a7a1Sriastradh }; 10081571a7a1Sriastradh 10091571a7a1Sriastradh /* 10101571a7a1Sriastradh * The sink structure contains EDID and other display device properties 10111571a7a1Sriastradh */ 10121571a7a1Sriastradh struct dc_sink { 10131571a7a1Sriastradh enum signal_type sink_signal; 10141571a7a1Sriastradh struct dc_edid dc_edid; /* raw edid */ 10151571a7a1Sriastradh struct dc_edid_caps edid_caps; /* parse display caps */ 10161571a7a1Sriastradh struct dc_container_id *dc_container_id; 10171571a7a1Sriastradh uint32_t dongle_max_pix_clk; 10181571a7a1Sriastradh void *priv; 10191571a7a1Sriastradh struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 10201571a7a1Sriastradh bool converter_disable_audio; 10211571a7a1Sriastradh 10221571a7a1Sriastradh struct dc_sink_dsc_caps sink_dsc_caps; 10231571a7a1Sriastradh 10241571a7a1Sriastradh /* private to DC core */ 10251571a7a1Sriastradh struct dc_link *link; 10261571a7a1Sriastradh struct dc_context *ctx; 10271571a7a1Sriastradh 10281571a7a1Sriastradh uint32_t sink_id; 10291571a7a1Sriastradh 10301571a7a1Sriastradh /* private to dc_sink.c */ 10311571a7a1Sriastradh // refcount must be the last member in dc_sink, since we want the 10321571a7a1Sriastradh // sink structure to be logically cloneable up to (but not including) 10331571a7a1Sriastradh // refcount 10341571a7a1Sriastradh struct kref refcount; 10351571a7a1Sriastradh }; 10361571a7a1Sriastradh 10371571a7a1Sriastradh void dc_sink_retain(struct dc_sink *sink); 10381571a7a1Sriastradh void dc_sink_release(struct dc_sink *sink); 10391571a7a1Sriastradh 10401571a7a1Sriastradh struct dc_sink_init_data { 10411571a7a1Sriastradh enum signal_type sink_signal; 10421571a7a1Sriastradh struct dc_link *link; 10431571a7a1Sriastradh uint32_t dongle_max_pix_clk; 10441571a7a1Sriastradh bool converter_disable_audio; 10451571a7a1Sriastradh }; 10461571a7a1Sriastradh 10471571a7a1Sriastradh struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 10481571a7a1Sriastradh 10491571a7a1Sriastradh /* Newer interfaces */ 10501571a7a1Sriastradh struct dc_cursor { 10511571a7a1Sriastradh struct dc_plane_address address; 10521571a7a1Sriastradh struct dc_cursor_attributes attributes; 10531571a7a1Sriastradh }; 10541571a7a1Sriastradh 10551571a7a1Sriastradh 10561571a7a1Sriastradh /******************************************************************************* 10571571a7a1Sriastradh * Interrupt interfaces 10581571a7a1Sriastradh ******************************************************************************/ 10591571a7a1Sriastradh enum dc_irq_source dc_interrupt_to_irq_source( 10601571a7a1Sriastradh struct dc *dc, 10611571a7a1Sriastradh uint32_t src_id, 10621571a7a1Sriastradh uint32_t ext_id); 10631571a7a1Sriastradh bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 10641571a7a1Sriastradh void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 10651571a7a1Sriastradh enum dc_irq_source dc_get_hpd_irq_source_at_index( 10661571a7a1Sriastradh struct dc *dc, uint32_t link_index); 10671571a7a1Sriastradh 10681571a7a1Sriastradh /******************************************************************************* 10691571a7a1Sriastradh * Power Interfaces 10701571a7a1Sriastradh ******************************************************************************/ 10711571a7a1Sriastradh 10721571a7a1Sriastradh void dc_set_power_state( 10731571a7a1Sriastradh struct dc *dc, 10741571a7a1Sriastradh enum dc_acpi_cm_power_state power_state); 10751571a7a1Sriastradh void dc_resume(struct dc *dc); 10761571a7a1Sriastradh unsigned int dc_get_current_backlight_pwm(struct dc *dc); 10771571a7a1Sriastradh unsigned int dc_get_target_backlight_pwm(struct dc *dc); 10781571a7a1Sriastradh 10791571a7a1Sriastradh bool dc_is_dmcu_initialized(struct dc *dc); 10801571a7a1Sriastradh bool dc_is_hw_initialized(struct dc *dc); 10811571a7a1Sriastradh 10821571a7a1Sriastradh enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 10831571a7a1Sriastradh void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 10841571a7a1Sriastradh /******************************************************************************* 10851571a7a1Sriastradh * DSC Interfaces 10861571a7a1Sriastradh ******************************************************************************/ 10871571a7a1Sriastradh #include "dc_dsc.h" 10881571a7a1Sriastradh #endif /* DC_INTERFACE_H_ */ 1089