1*677dec6eSriastradh /* $NetBSD: uvd_4_0_d.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 21571a7a1Sriastradh 31571a7a1Sriastradh /* 41571a7a1Sriastradh * 51571a7a1Sriastradh * Copyright (C) 2016 Advanced Micro Devices, Inc. 61571a7a1Sriastradh * 71571a7a1Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 81571a7a1Sriastradh * copy of this software and associated documentation files (the "Software"), 91571a7a1Sriastradh * to deal in the Software without restriction, including without limitation 101571a7a1Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 111571a7a1Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 121571a7a1Sriastradh * Software is furnished to do so, subject to the following conditions: 131571a7a1Sriastradh * 141571a7a1Sriastradh * The above copyright notice and this permission notice shall be included 151571a7a1Sriastradh * in all copies or substantial portions of the Software. 161571a7a1Sriastradh * 171571a7a1Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 181571a7a1Sriastradh * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 191571a7a1Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 201571a7a1Sriastradh * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 211571a7a1Sriastradh * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 221571a7a1Sriastradh * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 231571a7a1Sriastradh */ 241571a7a1Sriastradh 251571a7a1Sriastradh #ifndef UVD_4_0_D_H 261571a7a1Sriastradh #define UVD_4_0_D_H 271571a7a1Sriastradh 281571a7a1Sriastradh #define ixUVD_CGC_CTRL2 0x00C1 291571a7a1Sriastradh #define ixUVD_CGC_MEM_CTRL 0x00C0 301571a7a1Sriastradh #define ixUVD_LMI_ADDR_EXT2 0x00AB 311571a7a1Sriastradh #define ixUVD_LMI_CACHE_CTRL 0x009B 321571a7a1Sriastradh #define ixUVD_LMI_SWAP_CNTL2 0x00AA 331571a7a1Sriastradh #define ixUVD_MIF_CURR_ADDR_CONFIG 0x0048 341571a7a1Sriastradh #define ixUVD_MIF_RECON1_ADDR_CONFIG 0x0114 351571a7a1Sriastradh #define ixUVD_MIF_REF_ADDR_CONFIG 0x004C 361571a7a1Sriastradh #define mmUVD_CGC_CTRL 0x3D2C 371571a7a1Sriastradh #define mmUVD_CGC_GATE 0x3D2A 381571a7a1Sriastradh #define mmUVD_CGC_STATUS 0x3D2B 391571a7a1Sriastradh #define mmUVD_CGC_UDEC_STATUS 0x3D2D 401571a7a1Sriastradh #define mmUVD_CONTEXT_ID 0x3DBD 411571a7a1Sriastradh #define mmUVD_CTX_DATA 0x3D29 421571a7a1Sriastradh #define mmUVD_CTX_INDEX 0x3D28 431571a7a1Sriastradh #define mmUVD_ENGINE_CNTL 0x3BC6 441571a7a1Sriastradh #define mmUVD_GPCOM_VCPU_CMD 0x3BC3 451571a7a1Sriastradh #define mmUVD_GPCOM_VCPU_DATA0 0x3BC4 461571a7a1Sriastradh #define mmUVD_GPCOM_VCPU_DATA1 0x3BC5 471571a7a1Sriastradh #define mmUVD_GP_SCRATCH4 0x3D38 481571a7a1Sriastradh #define mmUVD_LMI_ADDR_EXT 0x3D65 491571a7a1Sriastradh #define mmUVD_LMI_CTRL 0x3D66 501571a7a1Sriastradh #define mmUVD_LMI_CTRL2 0x3D3D 511571a7a1Sriastradh #define mmUVD_LMI_EXT40_ADDR 0x3D26 521571a7a1Sriastradh #define mmUVD_LMI_STATUS 0x3D67 531571a7a1Sriastradh #define mmUVD_LMI_SWAP_CNTL 0x3D6D 541571a7a1Sriastradh #define mmUVD_MASTINT_EN 0x3D40 551571a7a1Sriastradh #define mmUVD_MPC_CNTL 0x3D77 561571a7a1Sriastradh #define mmUVD_MPC_SET_ALU 0x3D7E 571571a7a1Sriastradh #define mmUVD_MPC_SET_MUX 0x3D7D 581571a7a1Sriastradh #define mmUVD_MPC_SET_MUXA0 0x3D79 591571a7a1Sriastradh #define mmUVD_MPC_SET_MUXA1 0x3D7A 601571a7a1Sriastradh #define mmUVD_MPC_SET_MUXB0 0x3D7B 611571a7a1Sriastradh #define mmUVD_MPC_SET_MUXB1 0x3D7C 621571a7a1Sriastradh #define mmUVD_MP_SWAP_CNTL 0x3D6F 631571a7a1Sriastradh #define mmUVD_NO_OP 0x3BFF 641571a7a1Sriastradh #define mmUVD_PGFSM_CONFIG 0x38F8 651571a7a1Sriastradh #define mmUVD_PGFSM_READ_TILE1 0x38FA 661571a7a1Sriastradh #define mmUVD_PGFSM_READ_TILE2 0x38FB 671571a7a1Sriastradh #define mmUVD_POWER_STATUS 0x38FC 681571a7a1Sriastradh #define mmUVD_RBC_IB_BASE 0x3DA1 691571a7a1Sriastradh #define mmUVD_RBC_IB_SIZE 0x3DA2 701571a7a1Sriastradh #define mmUVD_RBC_IB_SIZE_UPDATE 0x3DF1 711571a7a1Sriastradh #define mmUVD_RBC_RB_BASE 0x3DA3 721571a7a1Sriastradh #define mmUVD_RBC_RB_CNTL 0x3DA9 731571a7a1Sriastradh #define mmUVD_RBC_RB_RPTR 0x3DA4 741571a7a1Sriastradh #define mmUVD_RBC_RB_RPTR_ADDR 0x3DAA 751571a7a1Sriastradh #define mmUVD_RBC_RB_WPTR 0x3DA5 761571a7a1Sriastradh #define mmUVD_RBC_RB_WPTR_CNTL 0x3DA6 771571a7a1Sriastradh #define mmUVD_SEMA_ADDR_HIGH 0x3BC1 781571a7a1Sriastradh #define mmUVD_SEMA_ADDR_LOW 0x3BC0 791571a7a1Sriastradh #define mmUVD_SEMA_CMD 0x3BC2 801571a7a1Sriastradh #define mmUVD_SEMA_CNTL 0x3D00 811571a7a1Sriastradh #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3DB3 821571a7a1Sriastradh #define mmUVD_SEMA_TIMEOUT_STATUS 0x3DB0 831571a7a1Sriastradh #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3DB2 841571a7a1Sriastradh #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3DB1 851571a7a1Sriastradh #define mmUVD_SOFT_RESET 0x3DA0 861571a7a1Sriastradh #define mmUVD_STATUS 0x3DAF 871571a7a1Sriastradh #define mmUVD_UDEC_ADDR_CONFIG 0x3BD3 881571a7a1Sriastradh #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3BD4 891571a7a1Sriastradh #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3BD5 901571a7a1Sriastradh #define mmUVD_VCPU_CACHE_OFFSET0 0x3D36 911571a7a1Sriastradh #define mmUVD_VCPU_CACHE_OFFSET1 0x3D38 921571a7a1Sriastradh #define mmUVD_VCPU_CACHE_OFFSET2 0x3D3A 931571a7a1Sriastradh #define mmUVD_VCPU_CACHE_SIZE0 0x3D37 941571a7a1Sriastradh #define mmUVD_VCPU_CACHE_SIZE1 0x3D39 951571a7a1Sriastradh #define mmUVD_VCPU_CACHE_SIZE2 0x3D3B 961571a7a1Sriastradh #define mmUVD_VCPU_CNTL 0x3D98 971571a7a1Sriastradh 981571a7a1Sriastradh #endif 99