1*677dec6eSriastradh /* $NetBSD: uvd_5_0_d.h,v 1.3 2021/12/18 23:45:24 riastradh Exp $ */ 2d350ecf5Sriastradh 3d350ecf5Sriastradh /* 4d350ecf5Sriastradh * UVD_5_0 Register documentation 5d350ecf5Sriastradh * 6d350ecf5Sriastradh * Copyright (C) 2014 Advanced Micro Devices, Inc. 7d350ecf5Sriastradh * 8d350ecf5Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 9d350ecf5Sriastradh * copy of this software and associated documentation files (the "Software"), 10d350ecf5Sriastradh * to deal in the Software without restriction, including without limitation 11d350ecf5Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12d350ecf5Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 13d350ecf5Sriastradh * Software is furnished to do so, subject to the following conditions: 14d350ecf5Sriastradh * 15d350ecf5Sriastradh * The above copyright notice and this permission notice shall be included 16d350ecf5Sriastradh * in all copies or substantial portions of the Software. 17d350ecf5Sriastradh * 18d350ecf5Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19d350ecf5Sriastradh * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20d350ecf5Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21d350ecf5Sriastradh * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22d350ecf5Sriastradh * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23d350ecf5Sriastradh * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24d350ecf5Sriastradh */ 25d350ecf5Sriastradh 26d350ecf5Sriastradh #ifndef UVD_5_0_D_H 27d350ecf5Sriastradh #define UVD_5_0_D_H 28d350ecf5Sriastradh 29d350ecf5Sriastradh #define mmUVD_SEMA_ADDR_LOW 0x3bc0 30d350ecf5Sriastradh #define mmUVD_SEMA_ADDR_HIGH 0x3bc1 31d350ecf5Sriastradh #define mmUVD_SEMA_CMD 0x3bc2 32d350ecf5Sriastradh #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 33d350ecf5Sriastradh #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 34d350ecf5Sriastradh #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 35d350ecf5Sriastradh #define mmUVD_ENGINE_CNTL 0x3bc6 36d350ecf5Sriastradh #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 37d350ecf5Sriastradh #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 38d350ecf5Sriastradh #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 39*677dec6eSriastradh #define mmUVD_NO_OP 0x3bff 40d350ecf5Sriastradh #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 41d350ecf5Sriastradh #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 42d350ecf5Sriastradh #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 43d350ecf5Sriastradh #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66 44d350ecf5Sriastradh #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f 45d350ecf5Sriastradh #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e 46d350ecf5Sriastradh #define mmUVD_SEMA_CNTL 0x3d00 47d350ecf5Sriastradh #define mmUVD_LMI_EXT40_ADDR 0x3d26 48d350ecf5Sriastradh #define mmUVD_CTX_INDEX 0x3d28 49d350ecf5Sriastradh #define mmUVD_CTX_DATA 0x3d29 50d350ecf5Sriastradh #define mmUVD_CGC_GATE 0x3d2a 51d350ecf5Sriastradh #define mmUVD_CGC_STATUS 0x3d2b 52d350ecf5Sriastradh #define mmUVD_CGC_CTRL 0x3d2c 53d350ecf5Sriastradh #define mmUVD_CGC_UDEC_STATUS 0x3d2d 54d350ecf5Sriastradh #define mmUVD_LMI_CTRL2 0x3d3d 55d350ecf5Sriastradh #define mmUVD_MASTINT_EN 0x3d40 56d350ecf5Sriastradh #define mmUVD_LMI_ADDR_EXT 0x3d65 57d350ecf5Sriastradh #define mmUVD_LMI_CTRL 0x3d66 58d350ecf5Sriastradh #define mmUVD_LMI_STATUS 0x3d67 59d350ecf5Sriastradh #define mmUVD_LMI_SWAP_CNTL 0x3d6d 60d350ecf5Sriastradh #define mmUVD_MP_SWAP_CNTL 0x3d6f 61d350ecf5Sriastradh #define mmUVD_MPC_CNTL 0x3d77 62d350ecf5Sriastradh #define mmUVD_MPC_SET_MUXA0 0x3d79 63d350ecf5Sriastradh #define mmUVD_MPC_SET_MUXA1 0x3d7a 64d350ecf5Sriastradh #define mmUVD_MPC_SET_MUXB0 0x3d7b 65d350ecf5Sriastradh #define mmUVD_MPC_SET_MUXB1 0x3d7c 66d350ecf5Sriastradh #define mmUVD_MPC_SET_MUX 0x3d7d 67d350ecf5Sriastradh #define mmUVD_MPC_SET_ALU 0x3d7e 68d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 69d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 70d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 71d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 72d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 73d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_SIZE2 0x3d87 74d350ecf5Sriastradh #define mmUVD_VCPU_CNTL 0x3d98 75d350ecf5Sriastradh #define mmUVD_SOFT_RESET 0x3da0 76d350ecf5Sriastradh #define mmUVD_LMI_RBC_IB_VMID 0x3da1 77d350ecf5Sriastradh #define mmUVD_RBC_IB_SIZE 0x3da2 78d350ecf5Sriastradh #define mmUVD_LMI_RBC_RB_VMID 0x3da3 79d350ecf5Sriastradh #define mmUVD_RBC_RB_RPTR 0x3da4 80d350ecf5Sriastradh #define mmUVD_RBC_RB_WPTR 0x3da5 81d350ecf5Sriastradh #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 82d350ecf5Sriastradh #define mmUVD_RBC_RB_CNTL 0x3da9 83d350ecf5Sriastradh #define mmUVD_RBC_RB_RPTR_ADDR 0x3daa 84d350ecf5Sriastradh #define mmUVD_STATUS 0x3daf 85d350ecf5Sriastradh #define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 86d350ecf5Sriastradh #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1 87d350ecf5Sriastradh #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2 88d350ecf5Sriastradh #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 89d350ecf5Sriastradh #define mmUVD_CONTEXT_ID 0x3dbd 90d350ecf5Sriastradh #define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1 91d350ecf5Sriastradh #define mmUVD_SUVD_CGC_GATE 0x3be4 92d350ecf5Sriastradh #define mmUVD_SUVD_CGC_STATUS 0x3be5 93d350ecf5Sriastradh #define mmUVD_SUVD_CGC_CTRL 0x3be6 94d350ecf5Sriastradh #define ixUVD_LMI_VMID_INTERNAL 0x99 95d350ecf5Sriastradh #define ixUVD_LMI_VMID_INTERNAL2 0x9a 96d350ecf5Sriastradh #define ixUVD_LMI_CACHE_CTRL 0x9b 97d350ecf5Sriastradh #define ixUVD_LMI_SWAP_CNTL2 0xaa 98d350ecf5Sriastradh #define ixUVD_LMI_ADDR_EXT2 0xab 99d350ecf5Sriastradh #define ixUVD_CGC_MEM_CTRL 0xc0 100d350ecf5Sriastradh #define ixUVD_CGC_CTRL2 0xc1 101d350ecf5Sriastradh #define ixUVD_LMI_VMID_INTERNAL3 0x162 102d350ecf5Sriastradh #define mmUVD_PGFSM_CONFIG 0x38c0 103d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE1 0x38c2 104d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE2 0x38c3 105d350ecf5Sriastradh #define mmUVD_POWER_STATUS 0x38c4 106d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE3 0x38c5 107d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE4 0x38c6 108d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE5 0x38c8 109d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE6 0x38ee 110d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE7 0x38ef 111d350ecf5Sriastradh #define mmUVD_MIF_CURR_ADDR_CONFIG 0x3992 112d350ecf5Sriastradh #define mmUVD_MIF_REF_ADDR_CONFIG 0x3993 113d350ecf5Sriastradh #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5 114d350ecf5Sriastradh #define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4 115d350ecf5Sriastradh #define mmUVD_JPEG_ADDR_CONFIG 0x3a1f 116d350ecf5Sriastradh 117d350ecf5Sriastradh #endif /* UVD_5_0_D_H */ 118