1*d350ecf5Sriastradh /* $NetBSD: uvd_6_0_d.h,v 1.1.1.1 2018/08/27 01:34:53 riastradh Exp $ */ 2*d350ecf5Sriastradh 3*d350ecf5Sriastradh /* 4*d350ecf5Sriastradh * UVD_6_0 Register documentation 5*d350ecf5Sriastradh * 6*d350ecf5Sriastradh * Copyright (C) 2014 Advanced Micro Devices, Inc. 7*d350ecf5Sriastradh * 8*d350ecf5Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 9*d350ecf5Sriastradh * copy of this software and associated documentation files (the "Software"), 10*d350ecf5Sriastradh * to deal in the Software without restriction, including without limitation 11*d350ecf5Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12*d350ecf5Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 13*d350ecf5Sriastradh * Software is furnished to do so, subject to the following conditions: 14*d350ecf5Sriastradh * 15*d350ecf5Sriastradh * The above copyright notice and this permission notice shall be included 16*d350ecf5Sriastradh * in all copies or substantial portions of the Software. 17*d350ecf5Sriastradh * 18*d350ecf5Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19*d350ecf5Sriastradh * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20*d350ecf5Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21*d350ecf5Sriastradh * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22*d350ecf5Sriastradh * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23*d350ecf5Sriastradh * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24*d350ecf5Sriastradh */ 25*d350ecf5Sriastradh 26*d350ecf5Sriastradh #ifndef UVD_6_0_D_H 27*d350ecf5Sriastradh #define UVD_6_0_D_H 28*d350ecf5Sriastradh 29*d350ecf5Sriastradh #define mmUVD_SEMA_ADDR_LOW 0x3bc0 30*d350ecf5Sriastradh #define mmUVD_SEMA_ADDR_HIGH 0x3bc1 31*d350ecf5Sriastradh #define mmUVD_SEMA_CMD 0x3bc2 32*d350ecf5Sriastradh #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 33*d350ecf5Sriastradh #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 34*d350ecf5Sriastradh #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 35*d350ecf5Sriastradh #define mmUVD_ENGINE_CNTL 0x3bc6 36*d350ecf5Sriastradh #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 37*d350ecf5Sriastradh #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 38*d350ecf5Sriastradh #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 39*d350ecf5Sriastradh #define mmUVD_POWER_STATUS_U 0x3bfd 40*d350ecf5Sriastradh #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 41*d350ecf5Sriastradh #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 42*d350ecf5Sriastradh #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 43*d350ecf5Sriastradh #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66 44*d350ecf5Sriastradh #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f 45*d350ecf5Sriastradh #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e 46*d350ecf5Sriastradh #define mmUVD_SEMA_CNTL 0x3d00 47*d350ecf5Sriastradh #define mmUVD_LMI_EXT40_ADDR 0x3d26 48*d350ecf5Sriastradh #define mmUVD_CTX_INDEX 0x3d28 49*d350ecf5Sriastradh #define mmUVD_CTX_DATA 0x3d29 50*d350ecf5Sriastradh #define mmUVD_CGC_GATE 0x3d2a 51*d350ecf5Sriastradh #define mmUVD_CGC_STATUS 0x3d2b 52*d350ecf5Sriastradh #define mmUVD_CGC_CTRL 0x3d2c 53*d350ecf5Sriastradh #define mmUVD_CGC_UDEC_STATUS 0x3d2d 54*d350ecf5Sriastradh #define mmUVD_LMI_CTRL2 0x3d3d 55*d350ecf5Sriastradh #define mmUVD_MASTINT_EN 0x3d40 56*d350ecf5Sriastradh #define mmUVD_LMI_ADDR_EXT 0x3d65 57*d350ecf5Sriastradh #define mmUVD_LMI_CTRL 0x3d66 58*d350ecf5Sriastradh #define mmUVD_LMI_STATUS 0x3d67 59*d350ecf5Sriastradh #define mmUVD_LMI_SWAP_CNTL 0x3d6d 60*d350ecf5Sriastradh #define mmUVD_MP_SWAP_CNTL 0x3d6f 61*d350ecf5Sriastradh #define mmUVD_MPC_CNTL 0x3d77 62*d350ecf5Sriastradh #define mmUVD_MPC_SET_MUXA0 0x3d79 63*d350ecf5Sriastradh #define mmUVD_MPC_SET_MUXA1 0x3d7a 64*d350ecf5Sriastradh #define mmUVD_MPC_SET_MUXB0 0x3d7b 65*d350ecf5Sriastradh #define mmUVD_MPC_SET_MUXB1 0x3d7c 66*d350ecf5Sriastradh #define mmUVD_MPC_SET_MUX 0x3d7d 67*d350ecf5Sriastradh #define mmUVD_MPC_SET_ALU 0x3d7e 68*d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 69*d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 70*d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 71*d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 72*d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 73*d350ecf5Sriastradh #define mmUVD_VCPU_CACHE_SIZE2 0x3d87 74*d350ecf5Sriastradh #define mmUVD_VCPU_CNTL 0x3d98 75*d350ecf5Sriastradh #define mmUVD_SOFT_RESET 0x3da0 76*d350ecf5Sriastradh #define mmUVD_LMI_RBC_IB_VMID 0x3da1 77*d350ecf5Sriastradh #define mmUVD_RBC_IB_SIZE 0x3da2 78*d350ecf5Sriastradh #define mmUVD_LMI_RBC_RB_VMID 0x3da3 79*d350ecf5Sriastradh #define mmUVD_RBC_RB_RPTR 0x3da4 80*d350ecf5Sriastradh #define mmUVD_RBC_RB_WPTR 0x3da5 81*d350ecf5Sriastradh #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 82*d350ecf5Sriastradh #define mmUVD_RBC_RB_CNTL 0x3da9 83*d350ecf5Sriastradh #define mmUVD_RBC_RB_RPTR_ADDR 0x3daa 84*d350ecf5Sriastradh #define mmUVD_STATUS 0x3daf 85*d350ecf5Sriastradh #define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 86*d350ecf5Sriastradh #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1 87*d350ecf5Sriastradh #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2 88*d350ecf5Sriastradh #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 89*d350ecf5Sriastradh #define mmUVD_CONTEXT_ID 0x3dbd 90*d350ecf5Sriastradh #define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1 91*d350ecf5Sriastradh #define mmUVD_SUVD_CGC_GATE 0x3be4 92*d350ecf5Sriastradh #define mmUVD_SUVD_CGC_STATUS 0x3be5 93*d350ecf5Sriastradh #define mmUVD_SUVD_CGC_CTRL 0x3be6 94*d350ecf5Sriastradh #define ixUVD_LMI_VMID_INTERNAL 0x99 95*d350ecf5Sriastradh #define ixUVD_LMI_VMID_INTERNAL2 0x9a 96*d350ecf5Sriastradh #define ixUVD_LMI_CACHE_CTRL 0x9b 97*d350ecf5Sriastradh #define ixUVD_LMI_SWAP_CNTL2 0xaa 98*d350ecf5Sriastradh #define ixUVD_LMI_ADDR_EXT2 0xab 99*d350ecf5Sriastradh #define ixUVD_CGC_MEM_CTRL 0xc0 100*d350ecf5Sriastradh #define ixUVD_CGC_CTRL2 0xc1 101*d350ecf5Sriastradh #define ixUVD_LMI_VMID_INTERNAL3 0x162 102*d350ecf5Sriastradh #define mmUVD_PGFSM_CONFIG 0x38c0 103*d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE1 0x38c2 104*d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE2 0x38c3 105*d350ecf5Sriastradh #define mmUVD_POWER_STATUS 0x38c4 106*d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE3 0x38c5 107*d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE4 0x38c6 108*d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE5 0x38c8 109*d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE6 0x38ee 110*d350ecf5Sriastradh #define mmUVD_PGFSM_READ_TILE7 0x38ef 111*d350ecf5Sriastradh #define mmUVD_MIF_CURR_ADDR_CONFIG 0x3992 112*d350ecf5Sriastradh #define mmUVD_MIF_REF_ADDR_CONFIG 0x3993 113*d350ecf5Sriastradh #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5 114*d350ecf5Sriastradh #define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4 115*d350ecf5Sriastradh #define mmUVD_JPEG_ADDR_CONFIG 0x3a1f 116*d350ecf5Sriastradh 117*d350ecf5Sriastradh #endif /* UVD_6_0_D_H */ 118