1*677dec6eSriastradh /* $NetBSD: vce_4_0_offset.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 21571a7a1Sriastradh 31571a7a1Sriastradh /* 41571a7a1Sriastradh * Copyright (C) 2017 Advanced Micro Devices, Inc. 51571a7a1Sriastradh * 61571a7a1Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 71571a7a1Sriastradh * copy of this software and associated documentation files (the "Software"), 81571a7a1Sriastradh * to deal in the Software without restriction, including without limitation 91571a7a1Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 101571a7a1Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 111571a7a1Sriastradh * Software is furnished to do so, subject to the following conditions: 121571a7a1Sriastradh * 131571a7a1Sriastradh * The above copyright notice and this permission notice shall be included 141571a7a1Sriastradh * in all copies or substantial portions of the Software. 151571a7a1Sriastradh * 161571a7a1Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 171571a7a1Sriastradh * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 181571a7a1Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 191571a7a1Sriastradh * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 201571a7a1Sriastradh * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 211571a7a1Sriastradh * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 221571a7a1Sriastradh */ 231571a7a1Sriastradh #ifndef _vce_4_0_OFFSET_HEADER 241571a7a1Sriastradh #define _vce_4_0_OFFSET_HEADER 251571a7a1Sriastradh 261571a7a1Sriastradh 271571a7a1Sriastradh 281571a7a1Sriastradh // addressBlock: vce0_vce_dec 291571a7a1Sriastradh // base address: 0x22000 301571a7a1Sriastradh #define mmVCE_STATUS 0x0a01 311571a7a1Sriastradh #define mmVCE_STATUS_BASE_IDX 0 321571a7a1Sriastradh #define mmVCE_VCPU_CNTL 0x0a05 331571a7a1Sriastradh #define mmVCE_VCPU_CNTL_BASE_IDX 0 341571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET0 0x0a09 351571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0 361571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE0 0x0a0a 371571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0 381571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET1 0x0a0b 391571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET1_BASE_IDX 0 401571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE1 0x0a0c 411571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE1_BASE_IDX 0 421571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET2 0x0a0d 431571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET2_BASE_IDX 0 441571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE2 0x0a0e 451571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE2_BASE_IDX 0 461571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET3 0x0a0f 471571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET3_BASE_IDX 0 481571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE3 0x0a10 491571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE3_BASE_IDX 0 501571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET4 0x0a11 511571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET4_BASE_IDX 0 521571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE4 0x0a12 531571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE4_BASE_IDX 0 541571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET5 0x0a13 551571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET5_BASE_IDX 0 561571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE5 0x0a14 571571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE5_BASE_IDX 0 581571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET6 0x0a15 591571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET6_BASE_IDX 0 601571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE6 0x0a16 611571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE6_BASE_IDX 0 621571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET7 0x0a17 631571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET7_BASE_IDX 0 641571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE7 0x0a18 651571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE7_BASE_IDX 0 661571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET8 0x0a19 671571a7a1Sriastradh #define mmVCE_VCPU_CACHE_OFFSET8_BASE_IDX 0 681571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE8 0x0a1a 691571a7a1Sriastradh #define mmVCE_VCPU_CACHE_SIZE8_BASE_IDX 0 701571a7a1Sriastradh #define mmVCE_SOFT_RESET 0x0a48 711571a7a1Sriastradh #define mmVCE_SOFT_RESET_BASE_IDX 0 721571a7a1Sriastradh #define mmVCE_RB_BASE_LO2 0x0a5b 731571a7a1Sriastradh #define mmVCE_RB_BASE_LO2_BASE_IDX 0 741571a7a1Sriastradh #define mmVCE_RB_BASE_HI2 0x0a5c 751571a7a1Sriastradh #define mmVCE_RB_BASE_HI2_BASE_IDX 0 761571a7a1Sriastradh #define mmVCE_RB_SIZE2 0x0a5d 771571a7a1Sriastradh #define mmVCE_RB_SIZE2_BASE_IDX 0 781571a7a1Sriastradh #define mmVCE_RB_RPTR2 0x0a5e 791571a7a1Sriastradh #define mmVCE_RB_RPTR2_BASE_IDX 0 801571a7a1Sriastradh #define mmVCE_RB_WPTR2 0x0a5f 811571a7a1Sriastradh #define mmVCE_RB_WPTR2_BASE_IDX 0 821571a7a1Sriastradh #define mmVCE_RB_BASE_LO 0x0a60 831571a7a1Sriastradh #define mmVCE_RB_BASE_LO_BASE_IDX 0 841571a7a1Sriastradh #define mmVCE_RB_BASE_HI 0x0a61 851571a7a1Sriastradh #define mmVCE_RB_BASE_HI_BASE_IDX 0 861571a7a1Sriastradh #define mmVCE_RB_SIZE 0x0a62 871571a7a1Sriastradh #define mmVCE_RB_SIZE_BASE_IDX 0 881571a7a1Sriastradh #define mmVCE_RB_RPTR 0x0a63 891571a7a1Sriastradh #define mmVCE_RB_RPTR_BASE_IDX 0 901571a7a1Sriastradh #define mmVCE_RB_WPTR 0x0a64 911571a7a1Sriastradh #define mmVCE_RB_WPTR_BASE_IDX 0 921571a7a1Sriastradh #define mmVCE_RB_ARB_CTRL 0x0a9f 931571a7a1Sriastradh #define mmVCE_RB_ARB_CTRL_BASE_IDX 0 941571a7a1Sriastradh #define mmVCE_CLOCK_GATING_A 0x0abe 951571a7a1Sriastradh #define mmVCE_CLOCK_GATING_A_BASE_IDX 0 961571a7a1Sriastradh #define mmVCE_CLOCK_GATING_B 0x0abf 971571a7a1Sriastradh #define mmVCE_CLOCK_GATING_B_BASE_IDX 0 981571a7a1Sriastradh #define mmVCE_RB_BASE_LO3 0x0ad4 991571a7a1Sriastradh #define mmVCE_RB_BASE_LO3_BASE_IDX 0 1001571a7a1Sriastradh #define mmVCE_RB_BASE_HI3 0x0ad5 1011571a7a1Sriastradh #define mmVCE_RB_BASE_HI3_BASE_IDX 0 1021571a7a1Sriastradh #define mmVCE_RB_SIZE3 0x0ad6 1031571a7a1Sriastradh #define mmVCE_RB_SIZE3_BASE_IDX 0 1041571a7a1Sriastradh #define mmVCE_RB_RPTR3 0x0ad7 1051571a7a1Sriastradh #define mmVCE_RB_RPTR3_BASE_IDX 0 1061571a7a1Sriastradh #define mmVCE_RB_WPTR3 0x0ad8 1071571a7a1Sriastradh #define mmVCE_RB_WPTR3_BASE_IDX 0 1081571a7a1Sriastradh #define mmVCE_SYS_INT_EN 0x0b00 1091571a7a1Sriastradh #define mmVCE_SYS_INT_EN_BASE_IDX 0 1101571a7a1Sriastradh #define mmVCE_SYS_INT_ACK 0x0b01 1111571a7a1Sriastradh #define mmVCE_SYS_INT_ACK_BASE_IDX 0 1121571a7a1Sriastradh #define mmVCE_SYS_INT_STATUS 0x0b01 1131571a7a1Sriastradh #define mmVCE_SYS_INT_STATUS_BASE_IDX 0 1141571a7a1Sriastradh 1151571a7a1Sriastradh 1161571a7a1Sriastradh // addressBlock: vce0_ctl_dec 1171571a7a1Sriastradh // base address: 0x22780 1181571a7a1Sriastradh #define mmVCE_UENC_CLOCK_GATING 0x0bef 1191571a7a1Sriastradh #define mmVCE_UENC_CLOCK_GATING_BASE_IDX 0 1201571a7a1Sriastradh #define mmVCE_UENC_REG_CLOCK_GATING 0x0bf0 1211571a7a1Sriastradh #define mmVCE_UENC_REG_CLOCK_GATING_BASE_IDX 0 1221571a7a1Sriastradh #define mmVCE_UENC_CLOCK_GATING_2 0x0c10 1231571a7a1Sriastradh #define mmVCE_UENC_CLOCK_GATING_2_BASE_IDX 0 1241571a7a1Sriastradh 1251571a7a1Sriastradh 1261571a7a1Sriastradh // addressBlock: vce0_vce_sclk_dec 1271571a7a1Sriastradh // base address: 0x23700 1281571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x0fcc 1291571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_BASE_IDX 0 1301571a7a1Sriastradh #define mmVCE_LMI_CTRL2 0x0fcf 1311571a7a1Sriastradh #define mmVCE_LMI_CTRL2_BASE_IDX 0 1321571a7a1Sriastradh #define mmVCE_LMI_SWAP_CNTL3 0x0fd0 1331571a7a1Sriastradh #define mmVCE_LMI_SWAP_CNTL3_BASE_IDX 0 1341571a7a1Sriastradh #define mmVCE_LMI_CTRL 0x0fd6 1351571a7a1Sriastradh #define mmVCE_LMI_CTRL_BASE_IDX 0 1361571a7a1Sriastradh #define mmVCE_LMI_STATUS 0x0fd7 1371571a7a1Sriastradh #define mmVCE_LMI_STATUS_BASE_IDX 0 1381571a7a1Sriastradh #define mmVCE_LMI_VM_CTRL 0x0fd8 1391571a7a1Sriastradh #define mmVCE_LMI_VM_CTRL_BASE_IDX 0 1401571a7a1Sriastradh #define mmVCE_LMI_SWAP_CNTL 0x0fdd 1411571a7a1Sriastradh #define mmVCE_LMI_SWAP_CNTL_BASE_IDX 0 1421571a7a1Sriastradh #define mmVCE_LMI_SWAP_CNTL1 0x0fde 1431571a7a1Sriastradh #define mmVCE_LMI_SWAP_CNTL1_BASE_IDX 0 1441571a7a1Sriastradh #define mmVCE_LMI_SWAP_CNTL2 0x0fe2 1451571a7a1Sriastradh #define mmVCE_LMI_SWAP_CNTL2_BASE_IDX 0 1461571a7a1Sriastradh #define mmVCE_LMI_CACHE_CTRL 0x0fec 1471571a7a1Sriastradh #define mmVCE_LMI_CACHE_CTRL_BASE_IDX 0 1481571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0 0x1086 1491571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_BASE_IDX 0 1501571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1 0x1087 1511571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_BASE_IDX 0 1521571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2 0x1088 1531571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_BASE_IDX 0 1541571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3 0x1089 1551571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_BASE_IDX 0 1561571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4 0x108a 1571571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_BASE_IDX 0 1581571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5 0x108b 1591571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_BASE_IDX 0 1601571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6 0x108c 1611571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_BASE_IDX 0 1621571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7 0x108d 1631571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_BASE_IDX 0 1641571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x1096 1651571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_BASE_IDX 0 1661571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x1097 1671571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_BASE_IDX 0 1681571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x1098 1691571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_BASE_IDX 0 1701571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3 0x1099 1711571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_BASE_IDX 0 1721571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4 0x109a 1731571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_BASE_IDX 0 1741571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5 0x109b 1751571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_BASE_IDX 0 1761571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6 0x109c 1771571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_BASE_IDX 0 1781571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7 0x109d 1791571a7a1Sriastradh #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_BASE_IDX 0 1801571a7a1Sriastradh 1811571a7a1Sriastradh 1821571a7a1Sriastradh // addressBlock: vce0_mmsch_dec 1831571a7a1Sriastradh // base address: 0x23b00 1841571a7a1Sriastradh #define mmVCE_MMSCH_VF_VMID 0x10cb 1851571a7a1Sriastradh #define mmVCE_MMSCH_VF_VMID_BASE_IDX 0 1861571a7a1Sriastradh #define mmVCE_MMSCH_VF_CTX_ADDR_LO 0x10cc 1871571a7a1Sriastradh #define mmVCE_MMSCH_VF_CTX_ADDR_LO_BASE_IDX 0 1881571a7a1Sriastradh #define mmVCE_MMSCH_VF_CTX_ADDR_HI 0x10cd 1891571a7a1Sriastradh #define mmVCE_MMSCH_VF_CTX_ADDR_HI_BASE_IDX 0 1901571a7a1Sriastradh #define mmVCE_MMSCH_VF_CTX_SIZE 0x10ce 1911571a7a1Sriastradh #define mmVCE_MMSCH_VF_CTX_SIZE_BASE_IDX 0 1921571a7a1Sriastradh #define mmVCE_MMSCH_VF_GPCOM_ADDR_LO 0x10cf 1931571a7a1Sriastradh #define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0 1941571a7a1Sriastradh #define mmVCE_MMSCH_VF_GPCOM_ADDR_HI 0x10d0 1951571a7a1Sriastradh #define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0 1961571a7a1Sriastradh #define mmVCE_MMSCH_VF_GPCOM_SIZE 0x10d1 1971571a7a1Sriastradh #define mmVCE_MMSCH_VF_GPCOM_SIZE_BASE_IDX 0 1981571a7a1Sriastradh #define mmVCE_MMSCH_VF_MAILBOX_HOST 0x10d2 1991571a7a1Sriastradh #define mmVCE_MMSCH_VF_MAILBOX_HOST_BASE_IDX 0 2001571a7a1Sriastradh #define mmVCE_MMSCH_VF_MAILBOX_RESP 0x10d3 2011571a7a1Sriastradh #define mmVCE_MMSCH_VF_MAILBOX_RESP_BASE_IDX 0 2021571a7a1Sriastradh 2031571a7a1Sriastradh 2041571a7a1Sriastradh // addressBlock: vce0_vce_rb_pg_dec 2051571a7a1Sriastradh // base address: 0x23fa0 2061571a7a1Sriastradh #define mmVCE_HW_VERSION 0x11e8 2071571a7a1Sriastradh #define mmVCE_HW_VERSION_BASE_IDX 0 2081571a7a1Sriastradh 2091571a7a1Sriastradh 2101571a7a1Sriastradh #endif 211