1*677dec6eSriastradh /*	$NetBSD: hwmgr_ppt.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $	*/
21571a7a1Sriastradh 
31571a7a1Sriastradh /*
41571a7a1Sriastradh  * Copyright 2015 Advanced Micro Devices, Inc.
51571a7a1Sriastradh  *
61571a7a1Sriastradh  * Permission is hereby granted, free of charge, to any person obtaining a
71571a7a1Sriastradh  * copy of this software and associated documentation files (the "Software"),
81571a7a1Sriastradh  * to deal in the Software without restriction, including without limitation
91571a7a1Sriastradh  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
101571a7a1Sriastradh  * and/or sell copies of the Software, and to permit persons to whom the
111571a7a1Sriastradh  * Software is furnished to do so, subject to the following conditions:
121571a7a1Sriastradh  *
131571a7a1Sriastradh  * The above copyright notice and this permission notice shall be included in
141571a7a1Sriastradh  * all copies or substantial portions of the Software.
151571a7a1Sriastradh  *
161571a7a1Sriastradh  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
171571a7a1Sriastradh  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
181571a7a1Sriastradh  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
191571a7a1Sriastradh  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
201571a7a1Sriastradh  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
211571a7a1Sriastradh  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
221571a7a1Sriastradh  * OTHER DEALINGS IN THE SOFTWARE.
231571a7a1Sriastradh  *
241571a7a1Sriastradh  */
251571a7a1Sriastradh 
261571a7a1Sriastradh #ifndef PP_HWMGR_PPT_H
271571a7a1Sriastradh #define PP_HWMGR_PPT_H
281571a7a1Sriastradh 
291571a7a1Sriastradh #include "hardwaremanager.h"
301571a7a1Sriastradh #include "smumgr.h"
311571a7a1Sriastradh #include "atom-types.h"
321571a7a1Sriastradh 
331571a7a1Sriastradh struct phm_ppt_v1_clock_voltage_dependency_record {
341571a7a1Sriastradh 	uint32_t clk;
351571a7a1Sriastradh 	uint8_t  vddInd;
361571a7a1Sriastradh 	uint8_t  vddciInd;
371571a7a1Sriastradh 	uint8_t  mvddInd;
381571a7a1Sriastradh 	uint16_t vdd_offset;
391571a7a1Sriastradh 	uint16_t vddc;
401571a7a1Sriastradh 	uint16_t vddgfx;
411571a7a1Sriastradh 	uint16_t vddci;
421571a7a1Sriastradh 	uint16_t mvdd;
431571a7a1Sriastradh 	uint8_t  phases;
441571a7a1Sriastradh 	uint8_t  cks_enable;
451571a7a1Sriastradh 	uint8_t  cks_voffset;
461571a7a1Sriastradh 	uint32_t sclk_offset;
471571a7a1Sriastradh };
481571a7a1Sriastradh 
491571a7a1Sriastradh typedef struct phm_ppt_v1_clock_voltage_dependency_record phm_ppt_v1_clock_voltage_dependency_record;
501571a7a1Sriastradh 
511571a7a1Sriastradh struct phm_ppt_v1_clock_voltage_dependency_table {
521571a7a1Sriastradh 	uint32_t count;                                            /* Number of entries. */
531571a7a1Sriastradh 	phm_ppt_v1_clock_voltage_dependency_record entries[1];     /* Dynamically allocate count entries. */
541571a7a1Sriastradh };
551571a7a1Sriastradh 
561571a7a1Sriastradh typedef struct phm_ppt_v1_clock_voltage_dependency_table phm_ppt_v1_clock_voltage_dependency_table;
571571a7a1Sriastradh 
581571a7a1Sriastradh 
591571a7a1Sriastradh /* Multimedia Clock Voltage Dependency records and table */
601571a7a1Sriastradh struct phm_ppt_v1_mm_clock_voltage_dependency_record {
611571a7a1Sriastradh 	uint32_t  dclk;                                              /* UVD D-clock */
621571a7a1Sriastradh 	uint32_t  vclk;                                              /* UVD V-clock */
631571a7a1Sriastradh 	uint32_t  eclk;                                              /* VCE clock */
641571a7a1Sriastradh 	uint32_t  aclk;                                              /* ACP clock */
651571a7a1Sriastradh 	uint32_t  samclock;                                          /* SAMU clock */
661571a7a1Sriastradh 	uint8_t	vddcInd;
671571a7a1Sriastradh 	uint16_t vddgfx_offset;
681571a7a1Sriastradh 	uint16_t vddc;
691571a7a1Sriastradh 	uint16_t vddgfx;
701571a7a1Sriastradh 	uint8_t phases;
711571a7a1Sriastradh };
721571a7a1Sriastradh typedef struct phm_ppt_v1_mm_clock_voltage_dependency_record phm_ppt_v1_mm_clock_voltage_dependency_record;
731571a7a1Sriastradh 
741571a7a1Sriastradh struct phm_ppt_v1_mm_clock_voltage_dependency_table {
751571a7a1Sriastradh 	uint32_t count;													/* Number of entries. */
761571a7a1Sriastradh 	phm_ppt_v1_mm_clock_voltage_dependency_record entries[1];		/* Dynamically allocate count entries. */
771571a7a1Sriastradh };
781571a7a1Sriastradh typedef struct phm_ppt_v1_mm_clock_voltage_dependency_table phm_ppt_v1_mm_clock_voltage_dependency_table;
791571a7a1Sriastradh 
801571a7a1Sriastradh struct phm_ppt_v1_voltage_lookup_record {
811571a7a1Sriastradh 	uint16_t us_calculated;
821571a7a1Sriastradh 	uint16_t us_vdd;												/* Base voltage */
831571a7a1Sriastradh 	uint16_t us_cac_low;
841571a7a1Sriastradh 	uint16_t us_cac_mid;
851571a7a1Sriastradh 	uint16_t us_cac_high;
861571a7a1Sriastradh };
871571a7a1Sriastradh typedef struct phm_ppt_v1_voltage_lookup_record phm_ppt_v1_voltage_lookup_record;
881571a7a1Sriastradh 
891571a7a1Sriastradh struct phm_ppt_v1_voltage_lookup_table {
901571a7a1Sriastradh 	uint32_t count;
911571a7a1Sriastradh 	phm_ppt_v1_voltage_lookup_record entries[1];    /* Dynamically allocate count entries. */
921571a7a1Sriastradh };
931571a7a1Sriastradh typedef struct phm_ppt_v1_voltage_lookup_table phm_ppt_v1_voltage_lookup_table;
941571a7a1Sriastradh 
951571a7a1Sriastradh /* PCIE records and Table */
961571a7a1Sriastradh 
971571a7a1Sriastradh struct phm_ppt_v1_pcie_record {
981571a7a1Sriastradh 	uint8_t gen_speed;
991571a7a1Sriastradh 	uint8_t lane_width;
1001571a7a1Sriastradh 	uint16_t usreserved;
1011571a7a1Sriastradh 	uint16_t reserved;
1021571a7a1Sriastradh 	uint32_t pcie_sclk;
1031571a7a1Sriastradh };
1041571a7a1Sriastradh typedef struct phm_ppt_v1_pcie_record phm_ppt_v1_pcie_record;
1051571a7a1Sriastradh 
1061571a7a1Sriastradh struct phm_ppt_v1_pcie_table {
1071571a7a1Sriastradh 	uint32_t count;                                            /* Number of entries. */
1081571a7a1Sriastradh 	phm_ppt_v1_pcie_record entries[1];                         /* Dynamically allocate count entries. */
1091571a7a1Sriastradh };
1101571a7a1Sriastradh typedef struct phm_ppt_v1_pcie_table phm_ppt_v1_pcie_table;
1111571a7a1Sriastradh 
1121571a7a1Sriastradh struct phm_ppt_v1_gpio_table {
1131571a7a1Sriastradh 	uint8_t vrhot_triggered_sclk_dpm_index;           /* SCLK DPM level index to switch to when VRHot is triggered */
1141571a7a1Sriastradh };
1151571a7a1Sriastradh typedef struct phm_ppt_v1_gpio_table phm_ppt_v1_gpio_table;
1161571a7a1Sriastradh 
1171571a7a1Sriastradh #endif
1181571a7a1Sriastradh 
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