1*677dec6eSriastradh /* $NetBSD: smu74_discrete.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 21571a7a1Sriastradh 31571a7a1Sriastradh /* 41571a7a1Sriastradh * Copyright 2014 Advanced Micro Devices, Inc. 51571a7a1Sriastradh * 61571a7a1Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 71571a7a1Sriastradh * copy of this software and associated documentation files (the "Software"), 81571a7a1Sriastradh * to deal in the Software without restriction, including without limitation 91571a7a1Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 101571a7a1Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 111571a7a1Sriastradh * Software is furnished to do so, subject to the following conditions: 121571a7a1Sriastradh * 131571a7a1Sriastradh * The above copyright notice and this permission notice shall be included in 141571a7a1Sriastradh * all copies or substantial portions of the Software. 151571a7a1Sriastradh * 161571a7a1Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 171571a7a1Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 181571a7a1Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 191571a7a1Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 201571a7a1Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 211571a7a1Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 221571a7a1Sriastradh * OTHER DEALINGS IN THE SOFTWARE. 231571a7a1Sriastradh * 241571a7a1Sriastradh */ 251571a7a1Sriastradh 261571a7a1Sriastradh #ifndef SMU74_DISCRETE_H 271571a7a1Sriastradh #define SMU74_DISCRETE_H 281571a7a1Sriastradh 291571a7a1Sriastradh #include "smu74.h" 301571a7a1Sriastradh 311571a7a1Sriastradh #pragma pack(push, 1) 321571a7a1Sriastradh 331571a7a1Sriastradh 341571a7a1Sriastradh #define NUM_SCLK_RANGE 8 351571a7a1Sriastradh 361571a7a1Sriastradh #define VCO_3_6 1 371571a7a1Sriastradh #define VCO_2_4 3 381571a7a1Sriastradh 391571a7a1Sriastradh #define POSTDIV_DIV_BY_1 0 401571a7a1Sriastradh #define POSTDIV_DIV_BY_2 1 411571a7a1Sriastradh #define POSTDIV_DIV_BY_4 2 421571a7a1Sriastradh #define POSTDIV_DIV_BY_8 3 431571a7a1Sriastradh #define POSTDIV_DIV_BY_16 4 441571a7a1Sriastradh 451571a7a1Sriastradh struct sclkFcwRange_t { 461571a7a1Sriastradh uint8_t vco_setting; 471571a7a1Sriastradh uint8_t postdiv; 481571a7a1Sriastradh uint16_t fcw_pcc; 491571a7a1Sriastradh 501571a7a1Sriastradh uint16_t fcw_trans_upper; 511571a7a1Sriastradh uint16_t fcw_trans_lower; 521571a7a1Sriastradh }; 531571a7a1Sriastradh typedef struct sclkFcwRange_t sclkFcwRange_t; 541571a7a1Sriastradh 551571a7a1Sriastradh struct SMIO_Pattern { 561571a7a1Sriastradh uint16_t Voltage; 571571a7a1Sriastradh uint8_t Smio; 581571a7a1Sriastradh uint8_t padding; 591571a7a1Sriastradh }; 601571a7a1Sriastradh 611571a7a1Sriastradh typedef struct SMIO_Pattern SMIO_Pattern; 621571a7a1Sriastradh 631571a7a1Sriastradh struct SMIO_Table { 641571a7a1Sriastradh SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; 651571a7a1Sriastradh }; 661571a7a1Sriastradh 671571a7a1Sriastradh typedef struct SMIO_Table SMIO_Table; 681571a7a1Sriastradh 691571a7a1Sriastradh struct SMU_SclkSetting { 701571a7a1Sriastradh uint32_t SclkFrequency; 711571a7a1Sriastradh uint16_t Fcw_int; 721571a7a1Sriastradh uint16_t Fcw_frac; 731571a7a1Sriastradh uint16_t Pcc_fcw_int; 741571a7a1Sriastradh uint8_t PllRange; 751571a7a1Sriastradh uint8_t SSc_En; 761571a7a1Sriastradh uint16_t Sclk_slew_rate; 771571a7a1Sriastradh uint16_t Pcc_up_slew_rate; 781571a7a1Sriastradh uint16_t Pcc_down_slew_rate; 791571a7a1Sriastradh uint16_t Fcw1_int; 801571a7a1Sriastradh uint16_t Fcw1_frac; 811571a7a1Sriastradh uint16_t Sclk_ss_slew_rate; 821571a7a1Sriastradh }; 831571a7a1Sriastradh typedef struct SMU_SclkSetting SMU_SclkSetting; 841571a7a1Sriastradh 851571a7a1Sriastradh struct SMU74_Discrete_GraphicsLevel { 861571a7a1Sriastradh SMU_VoltageLevel MinVoltage; 871571a7a1Sriastradh uint8_t pcieDpmLevel; 881571a7a1Sriastradh uint8_t DeepSleepDivId; 891571a7a1Sriastradh uint16_t ActivityLevel; 901571a7a1Sriastradh uint32_t CgSpllFuncCntl3; 911571a7a1Sriastradh uint32_t CgSpllFuncCntl4; 921571a7a1Sriastradh uint32_t CcPwrDynRm; 931571a7a1Sriastradh uint32_t CcPwrDynRm1; 941571a7a1Sriastradh uint8_t SclkDid; 951571a7a1Sriastradh uint8_t padding; 961571a7a1Sriastradh uint8_t EnabledForActivity; 971571a7a1Sriastradh uint8_t EnabledForThrottle; 981571a7a1Sriastradh uint8_t UpHyst; 991571a7a1Sriastradh uint8_t DownHyst; 1001571a7a1Sriastradh uint8_t VoltageDownHyst; 1011571a7a1Sriastradh uint8_t PowerThrottle; 1021571a7a1Sriastradh SMU_SclkSetting SclkSetting; 1031571a7a1Sriastradh }; 1041571a7a1Sriastradh 1051571a7a1Sriastradh typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel; 1061571a7a1Sriastradh 1071571a7a1Sriastradh struct SMU74_Discrete_ACPILevel { 1081571a7a1Sriastradh uint32_t Flags; 1091571a7a1Sriastradh SMU_VoltageLevel MinVoltage; 1101571a7a1Sriastradh uint32_t SclkFrequency; 1111571a7a1Sriastradh uint8_t SclkDid; 1121571a7a1Sriastradh uint8_t DisplayWatermark; 1131571a7a1Sriastradh uint8_t DeepSleepDivId; 1141571a7a1Sriastradh uint8_t padding; 1151571a7a1Sriastradh uint32_t CcPwrDynRm; 1161571a7a1Sriastradh uint32_t CcPwrDynRm1; 1171571a7a1Sriastradh 1181571a7a1Sriastradh SMU_SclkSetting SclkSetting; 1191571a7a1Sriastradh }; 1201571a7a1Sriastradh 1211571a7a1Sriastradh typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel; 1221571a7a1Sriastradh 1231571a7a1Sriastradh struct SMU74_Discrete_Ulv { 1241571a7a1Sriastradh uint32_t CcPwrDynRm; 1251571a7a1Sriastradh uint32_t CcPwrDynRm1; 1261571a7a1Sriastradh uint16_t VddcOffset; 1271571a7a1Sriastradh uint8_t VddcOffsetVid; 1281571a7a1Sriastradh uint8_t VddcPhase; 1291571a7a1Sriastradh uint16_t BifSclkDfs; 1301571a7a1Sriastradh uint16_t Reserved; 1311571a7a1Sriastradh }; 1321571a7a1Sriastradh 1331571a7a1Sriastradh typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv; 1341571a7a1Sriastradh 1351571a7a1Sriastradh struct SMU74_Discrete_MemoryLevel { 1361571a7a1Sriastradh SMU_VoltageLevel MinVoltage; 1371571a7a1Sriastradh uint32_t MinMvdd; 1381571a7a1Sriastradh 1391571a7a1Sriastradh uint32_t MclkFrequency; 1401571a7a1Sriastradh 1411571a7a1Sriastradh uint8_t StutterEnable; 1421571a7a1Sriastradh uint8_t EnabledForThrottle; 1431571a7a1Sriastradh uint8_t EnabledForActivity; 1441571a7a1Sriastradh uint8_t padding_0; 1451571a7a1Sriastradh 1461571a7a1Sriastradh uint8_t UpHyst; 1471571a7a1Sriastradh uint8_t DownHyst; 1481571a7a1Sriastradh uint8_t VoltageDownHyst; 1491571a7a1Sriastradh uint8_t padding_1; 1501571a7a1Sriastradh 1511571a7a1Sriastradh uint16_t ActivityLevel; 1521571a7a1Sriastradh uint8_t DisplayWatermark; 1531571a7a1Sriastradh uint8_t Reserved; 1541571a7a1Sriastradh }; 1551571a7a1Sriastradh 1561571a7a1Sriastradh typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel; 1571571a7a1Sriastradh 1581571a7a1Sriastradh struct SMU74_Discrete_LinkLevel { 1591571a7a1Sriastradh uint8_t PcieGenSpeed; 1601571a7a1Sriastradh uint8_t PcieLaneCount; 1611571a7a1Sriastradh uint8_t EnabledForActivity; 1621571a7a1Sriastradh uint8_t SPC; 1631571a7a1Sriastradh uint32_t DownThreshold; 1641571a7a1Sriastradh uint32_t UpThreshold; 1651571a7a1Sriastradh uint16_t BifSclkDfs; 1661571a7a1Sriastradh uint16_t Reserved; 1671571a7a1Sriastradh }; 1681571a7a1Sriastradh 1691571a7a1Sriastradh typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel; 1701571a7a1Sriastradh 1711571a7a1Sriastradh struct SMU74_Discrete_MCArbDramTimingTableEntry { 1721571a7a1Sriastradh uint32_t McArbDramTiming; 1731571a7a1Sriastradh uint32_t McArbDramTiming2; 1741571a7a1Sriastradh uint8_t McArbBurstTime; 1751571a7a1Sriastradh uint8_t padding[3]; 1761571a7a1Sriastradh }; 1771571a7a1Sriastradh 1781571a7a1Sriastradh typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry; 1791571a7a1Sriastradh 1801571a7a1Sriastradh struct SMU74_Discrete_MCArbDramTimingTable { 1811571a7a1Sriastradh SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 1821571a7a1Sriastradh }; 1831571a7a1Sriastradh 1841571a7a1Sriastradh typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable; 1851571a7a1Sriastradh 1861571a7a1Sriastradh struct SMU74_Discrete_UvdLevel { 1871571a7a1Sriastradh uint32_t VclkFrequency; 1881571a7a1Sriastradh uint32_t DclkFrequency; 1891571a7a1Sriastradh SMU_VoltageLevel MinVoltage; 1901571a7a1Sriastradh uint8_t VclkDivider; 1911571a7a1Sriastradh uint8_t DclkDivider; 1921571a7a1Sriastradh uint8_t padding[2]; 1931571a7a1Sriastradh }; 1941571a7a1Sriastradh 1951571a7a1Sriastradh typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel; 1961571a7a1Sriastradh 1971571a7a1Sriastradh struct SMU74_Discrete_ExtClkLevel { 1981571a7a1Sriastradh uint32_t Frequency; 1991571a7a1Sriastradh SMU_VoltageLevel MinVoltage; 2001571a7a1Sriastradh uint8_t Divider; 2011571a7a1Sriastradh uint8_t padding[3]; 2021571a7a1Sriastradh }; 2031571a7a1Sriastradh 2041571a7a1Sriastradh typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel; 2051571a7a1Sriastradh 2061571a7a1Sriastradh struct SMU74_Discrete_StateInfo { 2071571a7a1Sriastradh uint32_t SclkFrequency; 2081571a7a1Sriastradh uint32_t MclkFrequency; 2091571a7a1Sriastradh uint32_t VclkFrequency; 2101571a7a1Sriastradh uint32_t DclkFrequency; 2111571a7a1Sriastradh uint32_t SamclkFrequency; 2121571a7a1Sriastradh uint32_t AclkFrequency; 2131571a7a1Sriastradh uint32_t EclkFrequency; 2141571a7a1Sriastradh uint16_t MvddVoltage; 2151571a7a1Sriastradh uint16_t padding16; 2161571a7a1Sriastradh uint8_t DisplayWatermark; 2171571a7a1Sriastradh uint8_t McArbIndex; 2181571a7a1Sriastradh uint8_t McRegIndex; 2191571a7a1Sriastradh uint8_t SeqIndex; 2201571a7a1Sriastradh uint8_t SclkDid; 2211571a7a1Sriastradh int8_t SclkIndex; 2221571a7a1Sriastradh int8_t MclkIndex; 2231571a7a1Sriastradh uint8_t PCIeGen; 2241571a7a1Sriastradh }; 2251571a7a1Sriastradh 2261571a7a1Sriastradh typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo; 2271571a7a1Sriastradh 2281571a7a1Sriastradh struct SMU_QuadraticCoeffs { 2291571a7a1Sriastradh int32_t m1; 2301571a7a1Sriastradh uint32_t b; 2311571a7a1Sriastradh 2321571a7a1Sriastradh int16_t m2; 2331571a7a1Sriastradh uint8_t m1_shift; 2341571a7a1Sriastradh uint8_t m2_shift; 2351571a7a1Sriastradh }; 2361571a7a1Sriastradh typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs; 2371571a7a1Sriastradh 2381571a7a1Sriastradh struct SMU74_Discrete_DpmTable { 2391571a7a1Sriastradh 2401571a7a1Sriastradh SMU74_PIDController GraphicsPIDController; 2411571a7a1Sriastradh SMU74_PIDController MemoryPIDController; 2421571a7a1Sriastradh SMU74_PIDController LinkPIDController; 2431571a7a1Sriastradh 2441571a7a1Sriastradh uint32_t SystemFlags; 2451571a7a1Sriastradh 2461571a7a1Sriastradh uint32_t VRConfig; 2471571a7a1Sriastradh uint32_t SmioMask1; 2481571a7a1Sriastradh uint32_t SmioMask2; 2491571a7a1Sriastradh SMIO_Table SmioTable1; 2501571a7a1Sriastradh SMIO_Table SmioTable2; 2511571a7a1Sriastradh 2521571a7a1Sriastradh uint32_t MvddLevelCount; 2531571a7a1Sriastradh 2541571a7a1Sriastradh 2551571a7a1Sriastradh uint8_t BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC]; 2561571a7a1Sriastradh uint8_t BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC]; 2571571a7a1Sriastradh uint8_t BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC]; 2581571a7a1Sriastradh 2591571a7a1Sriastradh uint8_t GraphicsDpmLevelCount; 2601571a7a1Sriastradh uint8_t MemoryDpmLevelCount; 2611571a7a1Sriastradh uint8_t LinkLevelCount; 2621571a7a1Sriastradh uint8_t MasterDeepSleepControl; 2631571a7a1Sriastradh 2641571a7a1Sriastradh uint8_t UvdLevelCount; 2651571a7a1Sriastradh uint8_t VceLevelCount; 2661571a7a1Sriastradh uint8_t AcpLevelCount; 2671571a7a1Sriastradh uint8_t SamuLevelCount; 2681571a7a1Sriastradh 2691571a7a1Sriastradh uint8_t ThermOutGpio; 2701571a7a1Sriastradh uint8_t ThermOutPolarity; 2711571a7a1Sriastradh uint8_t ThermOutMode; 2721571a7a1Sriastradh uint8_t BootPhases; 2731571a7a1Sriastradh 2741571a7a1Sriastradh uint8_t VRHotLevel; 2751571a7a1Sriastradh uint8_t LdoRefSel; 2761571a7a1Sriastradh uint8_t Reserved1[2]; 2771571a7a1Sriastradh uint16_t FanStartTemperature; 2781571a7a1Sriastradh uint16_t FanStopTemperature; 2791571a7a1Sriastradh uint16_t MaxVoltage; 2801571a7a1Sriastradh uint16_t Reserved2; 2811571a7a1Sriastradh uint32_t Reserved[1]; 2821571a7a1Sriastradh 2831571a7a1Sriastradh SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS]; 2841571a7a1Sriastradh SMU74_Discrete_MemoryLevel MemoryACPILevel; 2851571a7a1Sriastradh SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY]; 2861571a7a1Sriastradh SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK]; 2871571a7a1Sriastradh SMU74_Discrete_ACPILevel ACPILevel; 2881571a7a1Sriastradh SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD]; 2891571a7a1Sriastradh SMU74_Discrete_ExtClkLevel VceLevel[SMU74_MAX_LEVELS_VCE]; 2901571a7a1Sriastradh SMU74_Discrete_ExtClkLevel AcpLevel[SMU74_MAX_LEVELS_ACP]; 2911571a7a1Sriastradh SMU74_Discrete_ExtClkLevel SamuLevel[SMU74_MAX_LEVELS_SAMU]; 2921571a7a1Sriastradh SMU74_Discrete_Ulv Ulv; 2931571a7a1Sriastradh 2941571a7a1Sriastradh uint8_t DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS]; 2951571a7a1Sriastradh 2961571a7a1Sriastradh uint32_t SclkStepSize; 2971571a7a1Sriastradh uint32_t Smio[SMU74_MAX_ENTRIES_SMIO]; 2981571a7a1Sriastradh 2991571a7a1Sriastradh uint8_t UvdBootLevel; 3001571a7a1Sriastradh uint8_t VceBootLevel; 3011571a7a1Sriastradh uint8_t AcpBootLevel; 3021571a7a1Sriastradh uint8_t SamuBootLevel; 3031571a7a1Sriastradh 3041571a7a1Sriastradh uint8_t GraphicsBootLevel; 3051571a7a1Sriastradh uint8_t GraphicsVoltageChangeEnable; 3061571a7a1Sriastradh uint8_t GraphicsThermThrottleEnable; 3071571a7a1Sriastradh uint8_t GraphicsInterval; 3081571a7a1Sriastradh 3091571a7a1Sriastradh uint8_t VoltageInterval; 3101571a7a1Sriastradh uint8_t ThermalInterval; 3111571a7a1Sriastradh uint16_t TemperatureLimitHigh; 3121571a7a1Sriastradh 3131571a7a1Sriastradh uint16_t TemperatureLimitLow; 3141571a7a1Sriastradh uint8_t MemoryBootLevel; 3151571a7a1Sriastradh uint8_t MemoryVoltageChangeEnable; 3161571a7a1Sriastradh 3171571a7a1Sriastradh uint16_t BootMVdd; 3181571a7a1Sriastradh uint8_t MemoryInterval; 3191571a7a1Sriastradh uint8_t MemoryThermThrottleEnable; 3201571a7a1Sriastradh 3211571a7a1Sriastradh uint16_t VoltageResponseTime; 3221571a7a1Sriastradh uint16_t PhaseResponseTime; 3231571a7a1Sriastradh 3241571a7a1Sriastradh uint8_t PCIeBootLinkLevel; 3251571a7a1Sriastradh uint8_t PCIeGenInterval; 3261571a7a1Sriastradh uint8_t DTEInterval; 3271571a7a1Sriastradh uint8_t DTEMode; 3281571a7a1Sriastradh 3291571a7a1Sriastradh uint8_t SVI2Enable; 3301571a7a1Sriastradh uint8_t VRHotGpio; 3311571a7a1Sriastradh uint8_t AcDcGpio; 3321571a7a1Sriastradh uint8_t ThermGpio; 3331571a7a1Sriastradh 3341571a7a1Sriastradh uint16_t PPM_PkgPwrLimit; 3351571a7a1Sriastradh uint16_t PPM_TemperatureLimit; 3361571a7a1Sriastradh 3371571a7a1Sriastradh uint16_t DefaultTdp; 3381571a7a1Sriastradh uint16_t TargetTdp; 3391571a7a1Sriastradh 3401571a7a1Sriastradh uint16_t FpsHighThreshold; 3411571a7a1Sriastradh uint16_t FpsLowThreshold; 3421571a7a1Sriastradh 3431571a7a1Sriastradh uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS]; 3441571a7a1Sriastradh uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS]; 3451571a7a1Sriastradh 3461571a7a1Sriastradh uint16_t TemperatureLimitEdge; 3471571a7a1Sriastradh uint16_t TemperatureLimitHotspot; 3481571a7a1Sriastradh 3491571a7a1Sriastradh uint16_t BootVddc; 3501571a7a1Sriastradh uint16_t BootVddci; 3511571a7a1Sriastradh 3521571a7a1Sriastradh uint16_t FanGainEdge; 3531571a7a1Sriastradh uint16_t FanGainHotspot; 3541571a7a1Sriastradh 3551571a7a1Sriastradh uint32_t LowSclkInterruptThreshold; 3561571a7a1Sriastradh uint32_t VddGfxReChkWait; 3571571a7a1Sriastradh 3581571a7a1Sriastradh uint8_t ClockStretcherAmount; 3591571a7a1Sriastradh uint8_t Sclk_CKS_masterEn0_7; 3601571a7a1Sriastradh uint8_t Sclk_CKS_masterEn8_15; 3611571a7a1Sriastradh uint8_t DPMFreezeAndForced; 3621571a7a1Sriastradh 3631571a7a1Sriastradh uint8_t Sclk_voltageOffset[8]; 3641571a7a1Sriastradh 3651571a7a1Sriastradh SMU_ClockStretcherDataTable ClockStretcherDataTable; 3661571a7a1Sriastradh SMU_CKS_LOOKUPTable CKS_LOOKUPTable; 3671571a7a1Sriastradh 3681571a7a1Sriastradh uint32_t CurrSclkPllRange; 3691571a7a1Sriastradh sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE]; 3701571a7a1Sriastradh GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES]; 3711571a7a1Sriastradh SMU_QuadraticCoeffs AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES]; 3721571a7a1Sriastradh }; 3731571a7a1Sriastradh 3741571a7a1Sriastradh typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable; 3751571a7a1Sriastradh 3761571a7a1Sriastradh 3771571a7a1Sriastradh struct SMU74_Discrete_FanTable { 3781571a7a1Sriastradh uint16_t FdoMode; 3791571a7a1Sriastradh int16_t TempMin; 3801571a7a1Sriastradh int16_t TempMed; 3811571a7a1Sriastradh int16_t TempMax; 3821571a7a1Sriastradh int16_t Slope1; 3831571a7a1Sriastradh int16_t Slope2; 3841571a7a1Sriastradh int16_t FdoMin; 3851571a7a1Sriastradh int16_t HystUp; 3861571a7a1Sriastradh int16_t HystDown; 3871571a7a1Sriastradh int16_t HystSlope; 3881571a7a1Sriastradh int16_t TempRespLim; 3891571a7a1Sriastradh int16_t TempCurr; 3901571a7a1Sriastradh int16_t SlopeCurr; 3911571a7a1Sriastradh int16_t PwmCurr; 3921571a7a1Sriastradh uint32_t RefreshPeriod; 3931571a7a1Sriastradh int16_t FdoMax; 3941571a7a1Sriastradh uint8_t TempSrc; 3951571a7a1Sriastradh int8_t Padding; 3961571a7a1Sriastradh }; 3971571a7a1Sriastradh 3981571a7a1Sriastradh typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable; 3991571a7a1Sriastradh 4001571a7a1Sriastradh #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 4011571a7a1Sriastradh #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) 4021571a7a1Sriastradh 4031571a7a1Sriastradh 4041571a7a1Sriastradh struct SMU7_MclkDpmScoreboard { 4051571a7a1Sriastradh uint32_t PercentageBusy; 4061571a7a1Sriastradh 4071571a7a1Sriastradh int32_t PIDError; 4081571a7a1Sriastradh int32_t PIDIntegral; 4091571a7a1Sriastradh int32_t PIDOutput; 4101571a7a1Sriastradh 4111571a7a1Sriastradh uint32_t SigmaDeltaAccum; 4121571a7a1Sriastradh uint32_t SigmaDeltaOutput; 4131571a7a1Sriastradh uint32_t SigmaDeltaLevel; 4141571a7a1Sriastradh 4151571a7a1Sriastradh uint32_t UtilizationSetpoint; 4161571a7a1Sriastradh 4171571a7a1Sriastradh uint8_t TdpClampMode; 4181571a7a1Sriastradh uint8_t TdcClampMode; 4191571a7a1Sriastradh uint8_t ThermClampMode; 4201571a7a1Sriastradh uint8_t VoltageBusy; 4211571a7a1Sriastradh 4221571a7a1Sriastradh int8_t CurrLevel; 4231571a7a1Sriastradh int8_t TargLevel; 4241571a7a1Sriastradh uint8_t LevelChangeInProgress; 4251571a7a1Sriastradh uint8_t UpHyst; 4261571a7a1Sriastradh 4271571a7a1Sriastradh uint8_t DownHyst; 4281571a7a1Sriastradh uint8_t VoltageDownHyst; 4291571a7a1Sriastradh uint8_t DpmEnable; 4301571a7a1Sriastradh uint8_t DpmRunning; 4311571a7a1Sriastradh 4321571a7a1Sriastradh uint8_t DpmForce; 4331571a7a1Sriastradh uint8_t DpmForceLevel; 4341571a7a1Sriastradh uint8_t padding2; 4351571a7a1Sriastradh uint8_t McArbIndex; 4361571a7a1Sriastradh 4371571a7a1Sriastradh uint32_t MinimumPerfMclk; 4381571a7a1Sriastradh 4391571a7a1Sriastradh uint8_t AcpiReq; 4401571a7a1Sriastradh uint8_t AcpiAck; 4411571a7a1Sriastradh uint8_t MclkSwitchInProgress; 4421571a7a1Sriastradh uint8_t MclkSwitchCritical; 4431571a7a1Sriastradh 4441571a7a1Sriastradh uint8_t IgnoreVBlank; 4451571a7a1Sriastradh uint8_t TargetMclkIndex; 4461571a7a1Sriastradh uint16_t VbiFailureCount; 4471571a7a1Sriastradh uint8_t VbiWaitCounter; 4481571a7a1Sriastradh uint8_t EnabledLevelsChange; 4491571a7a1Sriastradh 4501571a7a1Sriastradh uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY]; 4511571a7a1Sriastradh uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY]; 4521571a7a1Sriastradh 4531571a7a1Sriastradh void (*TargetStateCalculator)(uint8_t); 4541571a7a1Sriastradh void (*SavedTargetStateCalculator)(uint8_t); 4551571a7a1Sriastradh 4561571a7a1Sriastradh uint16_t AutoDpmInterval; 4571571a7a1Sriastradh uint16_t AutoDpmRange; 4581571a7a1Sriastradh 4591571a7a1Sriastradh uint16_t VbiTimeoutCount; 4601571a7a1Sriastradh uint16_t MclkSwitchingTime; 4611571a7a1Sriastradh 4621571a7a1Sriastradh uint8_t fastSwitch; 4631571a7a1Sriastradh uint8_t Save_PIC_VDDGFX_EXIT; 4641571a7a1Sriastradh uint8_t Save_PIC_VDDGFX_ENTER; 4651571a7a1Sriastradh uint8_t padding; 4661571a7a1Sriastradh }; 4671571a7a1Sriastradh 4681571a7a1Sriastradh typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; 4691571a7a1Sriastradh 4701571a7a1Sriastradh struct SMU7_UlvScoreboard { 4711571a7a1Sriastradh uint8_t EnterUlv; 4721571a7a1Sriastradh uint8_t ExitUlv; 4731571a7a1Sriastradh uint8_t UlvActive; 4741571a7a1Sriastradh uint8_t WaitingForUlv; 4751571a7a1Sriastradh uint8_t UlvEnable; 4761571a7a1Sriastradh uint8_t UlvRunning; 4771571a7a1Sriastradh uint8_t UlvMasterEnable; 4781571a7a1Sriastradh uint8_t padding; 4791571a7a1Sriastradh uint32_t UlvAbortedCount; 4801571a7a1Sriastradh uint32_t UlvTimeStamp; 4811571a7a1Sriastradh }; 4821571a7a1Sriastradh 4831571a7a1Sriastradh typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; 4841571a7a1Sriastradh 4851571a7a1Sriastradh struct VddgfxSavedRegisters { 4861571a7a1Sriastradh uint32_t GPU_DBG[3]; 4871571a7a1Sriastradh uint32_t MEC_BaseAddress_Hi; 4881571a7a1Sriastradh uint32_t MEC_BaseAddress_Lo; 4891571a7a1Sriastradh uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; 4901571a7a1Sriastradh uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; 4911571a7a1Sriastradh uint32_t CP_INT_CNTL; 4921571a7a1Sriastradh }; 4931571a7a1Sriastradh 4941571a7a1Sriastradh typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; 4951571a7a1Sriastradh 4961571a7a1Sriastradh struct SMU7_VddGfxScoreboard { 4971571a7a1Sriastradh uint8_t VddGfxEnable; 4981571a7a1Sriastradh uint8_t VddGfxActive; 4991571a7a1Sriastradh uint8_t VPUResetOccured; 5001571a7a1Sriastradh uint8_t padding; 5011571a7a1Sriastradh 5021571a7a1Sriastradh uint32_t VddGfxEnteredCount; 5031571a7a1Sriastradh uint32_t VddGfxAbortedCount; 5041571a7a1Sriastradh 5051571a7a1Sriastradh uint32_t VddGfxVid; 5061571a7a1Sriastradh 5071571a7a1Sriastradh VddgfxSavedRegisters SavedRegisters; 5081571a7a1Sriastradh }; 5091571a7a1Sriastradh 5101571a7a1Sriastradh typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; 5111571a7a1Sriastradh 5121571a7a1Sriastradh struct SMU7_TdcLimitScoreboard { 5131571a7a1Sriastradh uint8_t Enable; 5141571a7a1Sriastradh uint8_t Running; 5151571a7a1Sriastradh uint16_t Alpha; 5161571a7a1Sriastradh uint32_t FilteredIddc; 5171571a7a1Sriastradh uint32_t IddcLimit; 5181571a7a1Sriastradh uint32_t IddcHyst; 5191571a7a1Sriastradh SMU7_HystController_Data HystControllerData; 5201571a7a1Sriastradh }; 5211571a7a1Sriastradh 5221571a7a1Sriastradh typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; 5231571a7a1Sriastradh 5241571a7a1Sriastradh struct SMU7_PkgPwrLimitScoreboard { 5251571a7a1Sriastradh uint8_t Enable; 5261571a7a1Sriastradh uint8_t Running; 5271571a7a1Sriastradh uint16_t Alpha; 5281571a7a1Sriastradh uint32_t FilteredPkgPwr; 5291571a7a1Sriastradh uint32_t Limit; 5301571a7a1Sriastradh uint32_t Hyst; 5311571a7a1Sriastradh uint32_t LimitFromDriver; 5321571a7a1Sriastradh SMU7_HystController_Data HystControllerData; 5331571a7a1Sriastradh }; 5341571a7a1Sriastradh 5351571a7a1Sriastradh typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; 5361571a7a1Sriastradh 5371571a7a1Sriastradh struct SMU7_BapmScoreboard { 5381571a7a1Sriastradh uint32_t source_powers[SMU74_DTE_SOURCES]; 5391571a7a1Sriastradh uint32_t source_powers_last[SMU74_DTE_SOURCES]; 5401571a7a1Sriastradh int32_t entity_temperatures[SMU74_NUM_GPU_TES]; 5411571a7a1Sriastradh int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES]; 5421571a7a1Sriastradh int32_t Limit; 5431571a7a1Sriastradh int32_t Hyst; 5441571a7a1Sriastradh int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2]; 5451571a7a1Sriastradh int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; 5461571a7a1Sriastradh uint16_t ConfigTDPPowerScalar; 5471571a7a1Sriastradh uint16_t FanSpeedPowerScalar; 5481571a7a1Sriastradh uint16_t OverDrivePowerScalar; 5491571a7a1Sriastradh uint16_t OverDriveLimitScalar; 5501571a7a1Sriastradh uint16_t FinalPowerScalar; 5511571a7a1Sriastradh uint8_t VariantID; 5521571a7a1Sriastradh uint8_t spare997; 5531571a7a1Sriastradh 5541571a7a1Sriastradh SMU7_HystController_Data HystControllerData; 5551571a7a1Sriastradh 5561571a7a1Sriastradh int32_t temperature_gradient_slope; 5571571a7a1Sriastradh int32_t temperature_gradient; 5581571a7a1Sriastradh uint32_t measured_temperature; 5591571a7a1Sriastradh }; 5601571a7a1Sriastradh 5611571a7a1Sriastradh 5621571a7a1Sriastradh typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; 5631571a7a1Sriastradh 5641571a7a1Sriastradh struct SMU7_AcpiScoreboard { 5651571a7a1Sriastradh uint32_t SavedInterruptMask[2]; 5661571a7a1Sriastradh uint8_t LastACPIRequest; 5671571a7a1Sriastradh uint8_t CgBifResp; 5681571a7a1Sriastradh uint8_t RequestType; 5691571a7a1Sriastradh uint8_t Padding; 5701571a7a1Sriastradh SMU74_Discrete_ACPILevel D0Level; 5711571a7a1Sriastradh }; 5721571a7a1Sriastradh 5731571a7a1Sriastradh typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; 5741571a7a1Sriastradh 5751571a7a1Sriastradh struct SMU74_Discrete_PmFuses { 5761571a7a1Sriastradh uint8_t BapmVddCVidHiSidd[8]; 5771571a7a1Sriastradh uint8_t BapmVddCVidLoSidd[8]; 5781571a7a1Sriastradh uint8_t VddCVid[8]; 5791571a7a1Sriastradh uint8_t SviLoadLineEn; 5801571a7a1Sriastradh uint8_t SviLoadLineVddC; 5811571a7a1Sriastradh uint8_t SviLoadLineTrimVddC; 5821571a7a1Sriastradh uint8_t SviLoadLineOffsetVddC; 5831571a7a1Sriastradh uint16_t TDC_VDDC_PkgLimit; 5841571a7a1Sriastradh uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 5851571a7a1Sriastradh uint8_t TDC_MAWt; 5861571a7a1Sriastradh uint8_t TdcWaterfallCtl; 5871571a7a1Sriastradh uint8_t LPMLTemperatureMin; 5881571a7a1Sriastradh uint8_t LPMLTemperatureMax; 5891571a7a1Sriastradh uint8_t Reserved; 5901571a7a1Sriastradh 5911571a7a1Sriastradh uint8_t LPMLTemperatureScaler[16]; 5921571a7a1Sriastradh 5931571a7a1Sriastradh int16_t FuzzyFan_ErrorSetDelta; 5941571a7a1Sriastradh int16_t FuzzyFan_ErrorRateSetDelta; 5951571a7a1Sriastradh int16_t FuzzyFan_PwmSetDelta; 5961571a7a1Sriastradh uint16_t Reserved6; 5971571a7a1Sriastradh 5981571a7a1Sriastradh uint8_t GnbLPML[16]; 5991571a7a1Sriastradh 6001571a7a1Sriastradh uint8_t GnbLPMLMaxVid; 6011571a7a1Sriastradh uint8_t GnbLPMLMinVid; 6021571a7a1Sriastradh uint8_t Reserved1[2]; 6031571a7a1Sriastradh 6041571a7a1Sriastradh uint16_t BapmVddCBaseLeakageHiSidd; 6051571a7a1Sriastradh uint16_t BapmVddCBaseLeakageLoSidd; 6061571a7a1Sriastradh 6071571a7a1Sriastradh uint16_t VFT_Temp[3]; 6081571a7a1Sriastradh uint16_t padding; 6091571a7a1Sriastradh 6101571a7a1Sriastradh SMU_QuadraticCoeffs VFT_ATE[3]; 6111571a7a1Sriastradh 6121571a7a1Sriastradh SMU_QuadraticCoeffs AVFS_GB; 6131571a7a1Sriastradh SMU_QuadraticCoeffs ATE_ACBTC_GB; 6141571a7a1Sriastradh 6151571a7a1Sriastradh SMU_QuadraticCoeffs P2V; 6161571a7a1Sriastradh 6171571a7a1Sriastradh uint32_t PsmCharzFreq; 6181571a7a1Sriastradh 6191571a7a1Sriastradh uint16_t InversionVoltage; 6201571a7a1Sriastradh uint16_t PsmCharzTemp; 6211571a7a1Sriastradh 6221571a7a1Sriastradh uint32_t EnabledAvfsModules; 6231571a7a1Sriastradh }; 6241571a7a1Sriastradh 6251571a7a1Sriastradh typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses; 6261571a7a1Sriastradh 6271571a7a1Sriastradh struct SMU7_Discrete_Log_Header_Table { 6281571a7a1Sriastradh uint32_t version; 6291571a7a1Sriastradh uint32_t asic_id; 6301571a7a1Sriastradh uint16_t flags; 6311571a7a1Sriastradh uint16_t entry_size; 6321571a7a1Sriastradh uint32_t total_size; 6331571a7a1Sriastradh uint32_t num_of_entries; 6341571a7a1Sriastradh uint8_t type; 6351571a7a1Sriastradh uint8_t mode; 6361571a7a1Sriastradh uint8_t filler_0[2]; 6371571a7a1Sriastradh uint32_t filler_1[2]; 6381571a7a1Sriastradh }; 6391571a7a1Sriastradh 6401571a7a1Sriastradh typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; 6411571a7a1Sriastradh 6421571a7a1Sriastradh struct SMU7_Discrete_Log_Cntl { 6431571a7a1Sriastradh uint8_t Enabled; 6441571a7a1Sriastradh uint8_t Type; 6451571a7a1Sriastradh uint8_t padding[2]; 6461571a7a1Sriastradh uint32_t BufferSize; 6471571a7a1Sriastradh uint32_t SamplesLogged; 6481571a7a1Sriastradh uint32_t SampleSize; 6491571a7a1Sriastradh uint32_t AddrL; 6501571a7a1Sriastradh uint32_t AddrH; 6511571a7a1Sriastradh }; 6521571a7a1Sriastradh 6531571a7a1Sriastradh typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; 6541571a7a1Sriastradh 6551571a7a1Sriastradh #if defined SMU__DGPU_ONLY 6561571a7a1Sriastradh #define CAC_ACC_NW_NUM_OF_SIGNALS 87 6571571a7a1Sriastradh #endif 6581571a7a1Sriastradh 6591571a7a1Sriastradh 6601571a7a1Sriastradh struct SMU7_Discrete_Cac_Collection_Table { 6611571a7a1Sriastradh uint32_t temperature; 6621571a7a1Sriastradh uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; 6631571a7a1Sriastradh }; 6641571a7a1Sriastradh 6651571a7a1Sriastradh typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; 6661571a7a1Sriastradh 6671571a7a1Sriastradh struct SMU7_Discrete_Cac_Verification_Table { 6681571a7a1Sriastradh uint32_t VddcTotalPower; 6691571a7a1Sriastradh uint32_t VddcLeakagePower; 6701571a7a1Sriastradh uint32_t VddcConstantPower; 6711571a7a1Sriastradh uint32_t VddcGfxDynamicPower; 6721571a7a1Sriastradh uint32_t VddcUvdDynamicPower; 6731571a7a1Sriastradh uint32_t VddcVceDynamicPower; 6741571a7a1Sriastradh uint32_t VddcAcpDynamicPower; 6751571a7a1Sriastradh uint32_t VddcPcieDynamicPower; 6761571a7a1Sriastradh uint32_t VddcDceDynamicPower; 6771571a7a1Sriastradh uint32_t VddcCurrent; 6781571a7a1Sriastradh uint32_t VddcVoltage; 6791571a7a1Sriastradh uint32_t VddciTotalPower; 6801571a7a1Sriastradh uint32_t VddciLeakagePower; 6811571a7a1Sriastradh uint32_t VddciConstantPower; 6821571a7a1Sriastradh uint32_t VddciDynamicPower; 6831571a7a1Sriastradh uint32_t Vddr1TotalPower; 6841571a7a1Sriastradh uint32_t Vddr1LeakagePower; 6851571a7a1Sriastradh uint32_t Vddr1ConstantPower; 6861571a7a1Sriastradh uint32_t Vddr1DynamicPower; 6871571a7a1Sriastradh uint32_t spare[4]; 6881571a7a1Sriastradh uint32_t temperature; 6891571a7a1Sriastradh }; 6901571a7a1Sriastradh 6911571a7a1Sriastradh typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; 6921571a7a1Sriastradh 6931571a7a1Sriastradh struct SMU7_Discrete_Pm_Status_Table { 6941571a7a1Sriastradh int32_t T_meas_max; 6951571a7a1Sriastradh int32_t T_meas_acc; 6961571a7a1Sriastradh int32_t T_calc_max; 6971571a7a1Sriastradh int32_t T_calc_acc; 6981571a7a1Sriastradh uint32_t P_scalar_acc; 6991571a7a1Sriastradh uint32_t P_calc_max; 7001571a7a1Sriastradh uint32_t P_calc_acc; 7011571a7a1Sriastradh 7021571a7a1Sriastradh uint32_t I_calc_max; 7031571a7a1Sriastradh uint32_t I_calc_acc; 7041571a7a1Sriastradh uint32_t I_calc_acc_vddci; 7051571a7a1Sriastradh uint32_t V_calc_noload_acc; 7061571a7a1Sriastradh uint32_t V_calc_load_acc; 7071571a7a1Sriastradh uint32_t V_calc_noload_acc_vddci; 7081571a7a1Sriastradh uint32_t P_meas_acc; 7091571a7a1Sriastradh uint32_t V_meas_noload_acc; 7101571a7a1Sriastradh uint32_t V_meas_load_acc; 7111571a7a1Sriastradh uint32_t I_meas_acc; 7121571a7a1Sriastradh uint32_t P_meas_acc_vddci; 7131571a7a1Sriastradh uint32_t V_meas_noload_acc_vddci; 7141571a7a1Sriastradh uint32_t V_meas_load_acc_vddci; 7151571a7a1Sriastradh uint32_t I_meas_acc_vddci; 7161571a7a1Sriastradh 7171571a7a1Sriastradh uint16_t Sclk_dpm_residency[8]; 7181571a7a1Sriastradh uint16_t Uvd_dpm_residency[8]; 7191571a7a1Sriastradh uint16_t Vce_dpm_residency[8]; 7201571a7a1Sriastradh uint16_t Mclk_dpm_residency[4]; 7211571a7a1Sriastradh 7221571a7a1Sriastradh uint32_t P_vddci_acc; 7231571a7a1Sriastradh uint32_t P_vddr1_acc; 7241571a7a1Sriastradh uint32_t P_nte1_acc; 7251571a7a1Sriastradh uint32_t PkgPwr_max; 7261571a7a1Sriastradh uint32_t PkgPwr_acc; 7271571a7a1Sriastradh uint32_t MclkSwitchingTime_max; 7281571a7a1Sriastradh uint32_t MclkSwitchingTime_acc; 7291571a7a1Sriastradh uint32_t FanPwm_acc; 7301571a7a1Sriastradh uint32_t FanRpm_acc; 7311571a7a1Sriastradh 7321571a7a1Sriastradh uint32_t AccCnt; 7331571a7a1Sriastradh }; 7341571a7a1Sriastradh 7351571a7a1Sriastradh typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; 7361571a7a1Sriastradh 7371571a7a1Sriastradh #define SMU7_MAX_GFX_CU_COUNT 16 7381571a7a1Sriastradh 7391571a7a1Sriastradh struct SMU7_GfxCuPgScoreboard { 7401571a7a1Sriastradh uint8_t Enabled; 7411571a7a1Sriastradh uint8_t WaterfallUp; 7421571a7a1Sriastradh uint8_t WaterfallDown; 7431571a7a1Sriastradh uint8_t WaterfallLimit; 7441571a7a1Sriastradh uint8_t CurrMaxCu; 7451571a7a1Sriastradh uint8_t TargMaxCu; 7461571a7a1Sriastradh uint8_t ClampMode; 7471571a7a1Sriastradh uint8_t Active; 7481571a7a1Sriastradh uint8_t MaxSupportedCu; 7491571a7a1Sriastradh uint8_t MinSupportedCu; 7501571a7a1Sriastradh uint8_t PendingGfxCuHostInterrupt; 7511571a7a1Sriastradh uint8_t LastFilteredMaxCuInteger; 7521571a7a1Sriastradh uint16_t FilteredMaxCu; 7531571a7a1Sriastradh uint16_t FilteredMaxCuAlpha; 7541571a7a1Sriastradh uint16_t FilterResetCount; 7551571a7a1Sriastradh uint16_t FilterResetCountLimit; 7561571a7a1Sriastradh uint8_t ForceCu; 7571571a7a1Sriastradh uint8_t ForceCuCount; 7581571a7a1Sriastradh uint8_t spare[2]; 7591571a7a1Sriastradh }; 7601571a7a1Sriastradh 7611571a7a1Sriastradh typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard; 7621571a7a1Sriastradh 7631571a7a1Sriastradh #define SMU7_SCLK_CAC 0x561 7641571a7a1Sriastradh #define SMU7_MCLK_CAC 0xF9 7651571a7a1Sriastradh #define SMU7_VCLK_CAC 0x2DE 7661571a7a1Sriastradh #define SMU7_DCLK_CAC 0x2DE 7671571a7a1Sriastradh #define SMU7_ECLK_CAC 0x25E 7681571a7a1Sriastradh #define SMU7_ACLK_CAC 0x25E 7691571a7a1Sriastradh #define SMU7_SAMCLK_CAC 0x25E 7701571a7a1Sriastradh #define SMU7_DISPCLK_CAC 0x100 7711571a7a1Sriastradh #define SMU7_CAC_CONSTANT 0x2EE3430 7721571a7a1Sriastradh #define SMU7_CAC_CONSTANT_SHIFT 18 7731571a7a1Sriastradh 7741571a7a1Sriastradh #define SMU7_VDDCI_MCLK_CONST 1765 7751571a7a1Sriastradh #define SMU7_VDDCI_MCLK_CONST_SHIFT 16 7761571a7a1Sriastradh #define SMU7_VDDCI_VDDCI_CONST 50958 7771571a7a1Sriastradh #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 7781571a7a1Sriastradh #define SMU7_VDDCI_CONST 11781 7791571a7a1Sriastradh #define SMU7_VDDCI_STROBE_PWR 1331 7801571a7a1Sriastradh 7811571a7a1Sriastradh #define SMU7_VDDR1_CONST 693 7821571a7a1Sriastradh #define SMU7_VDDR1_CAC_WEIGHT 20 7831571a7a1Sriastradh #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 7841571a7a1Sriastradh #define SMU7_VDDR1_STROBE_PWR 512 7851571a7a1Sriastradh 7861571a7a1Sriastradh #define SMU7_AREA_COEFF_UVD 0xA78 7871571a7a1Sriastradh #define SMU7_AREA_COEFF_VCE 0x190A 7881571a7a1Sriastradh #define SMU7_AREA_COEFF_ACP 0x22D1 7891571a7a1Sriastradh #define SMU7_AREA_COEFF_SAMU 0x534 7901571a7a1Sriastradh 7911571a7a1Sriastradh #define SMU7_THERM_OUT_MODE_DISABLE 0x0 7921571a7a1Sriastradh #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 7931571a7a1Sriastradh #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 7941571a7a1Sriastradh 7951571a7a1Sriastradh // DIDT Defines 7961571a7a1Sriastradh #define SQ_Enable_MASK 0x1 7971571a7a1Sriastradh #define SQ_IR_MASK 0x2 7981571a7a1Sriastradh #define SQ_PCC_MASK 0x4 7991571a7a1Sriastradh #define SQ_EDC_MASK 0x8 8001571a7a1Sriastradh 8011571a7a1Sriastradh #define TCP_Enable_MASK 0x100 8021571a7a1Sriastradh #define TCP_IR_MASK 0x200 8031571a7a1Sriastradh #define TCP_PCC_MASK 0x400 8041571a7a1Sriastradh #define TCP_EDC_MASK 0x800 8051571a7a1Sriastradh 8061571a7a1Sriastradh #define TD_Enable_MASK 0x10000 8071571a7a1Sriastradh #define TD_IR_MASK 0x20000 8081571a7a1Sriastradh #define TD_PCC_MASK 0x40000 8091571a7a1Sriastradh #define TD_EDC_MASK 0x80000 8101571a7a1Sriastradh 8111571a7a1Sriastradh #define DB_Enable_MASK 0x1000000 8121571a7a1Sriastradh #define DB_IR_MASK 0x2000000 8131571a7a1Sriastradh #define DB_PCC_MASK 0x4000000 8141571a7a1Sriastradh #define DB_EDC_MASK 0x8000000 8151571a7a1Sriastradh 8161571a7a1Sriastradh #define SQ_Enable_SHIFT 0 8171571a7a1Sriastradh #define SQ_IR_SHIFT 1 8181571a7a1Sriastradh #define SQ_PCC_SHIFT 2 8191571a7a1Sriastradh #define SQ_EDC_SHIFT 3 8201571a7a1Sriastradh 8211571a7a1Sriastradh #define TCP_Enable_SHIFT 8 8221571a7a1Sriastradh #define TCP_IR_SHIFT 9 8231571a7a1Sriastradh #define TCP_PCC_SHIFT 10 8241571a7a1Sriastradh #define TCP_EDC_SHIFT 11 8251571a7a1Sriastradh 8261571a7a1Sriastradh #define TD_Enable_SHIFT 16 8271571a7a1Sriastradh #define TD_IR_SHIFT 17 8281571a7a1Sriastradh #define TD_PCC_SHIFT 18 8291571a7a1Sriastradh #define TD_EDC_SHIFT 19 8301571a7a1Sriastradh 8311571a7a1Sriastradh #define DB_Enable_SHIFT 24 8321571a7a1Sriastradh #define DB_IR_SHIFT 25 8331571a7a1Sriastradh #define DB_PCC_SHIFT 26 8341571a7a1Sriastradh #define DB_EDC_SHIFT 27 8351571a7a1Sriastradh 8361571a7a1Sriastradh #define BTCGB0_Vdroop_Enable_MASK 0x1 8371571a7a1Sriastradh #define BTCGB1_Vdroop_Enable_MASK 0x2 8381571a7a1Sriastradh #define AVFSGB0_Vdroop_Enable_MASK 0x4 8391571a7a1Sriastradh #define AVFSGB1_Vdroop_Enable_MASK 0x8 8401571a7a1Sriastradh 8411571a7a1Sriastradh #define BTCGB0_Vdroop_Enable_SHIFT 0 8421571a7a1Sriastradh #define BTCGB1_Vdroop_Enable_SHIFT 1 8431571a7a1Sriastradh #define AVFSGB0_Vdroop_Enable_SHIFT 2 8441571a7a1Sriastradh #define AVFSGB1_Vdroop_Enable_SHIFT 3 8451571a7a1Sriastradh 8461571a7a1Sriastradh 8471571a7a1Sriastradh #pragma pack(pop) 8481571a7a1Sriastradh 8491571a7a1Sriastradh 8501571a7a1Sriastradh #endif 8511571a7a1Sriastradh 852