1*677dec6eSriastradh /* $NetBSD: vega12_smumgr.h,v 1.2 2021/12/18 23:45:27 riastradh Exp $ */ 21571a7a1Sriastradh 31571a7a1Sriastradh /* 41571a7a1Sriastradh * Copyright 2017 Advanced Micro Devices, Inc. 51571a7a1Sriastradh * 61571a7a1Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 71571a7a1Sriastradh * copy of this software and associated documentation files (the "Software"), 81571a7a1Sriastradh * to deal in the Software without restriction, including without limitation 91571a7a1Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 101571a7a1Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 111571a7a1Sriastradh * Software is furnished to do so, subject to the following conditions: 121571a7a1Sriastradh * 131571a7a1Sriastradh * The above copyright notice and this permission notice shall be included in 141571a7a1Sriastradh * all copies or substantial portions of the Software. 151571a7a1Sriastradh * 161571a7a1Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 171571a7a1Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 181571a7a1Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 191571a7a1Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 201571a7a1Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 211571a7a1Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 221571a7a1Sriastradh * OTHER DEALINGS IN THE SOFTWARE. 231571a7a1Sriastradh * 241571a7a1Sriastradh */ 251571a7a1Sriastradh #ifndef _VEGA12_SMUMANAGER_H_ 261571a7a1Sriastradh #define _VEGA12_SMUMANAGER_H_ 271571a7a1Sriastradh 281571a7a1Sriastradh #include "hwmgr.h" 291571a7a1Sriastradh #include "vega12/smu9_driver_if.h" 301571a7a1Sriastradh #include "vega12_hwmgr.h" 311571a7a1Sriastradh 321571a7a1Sriastradh struct smu_table_entry { 331571a7a1Sriastradh uint32_t version; 341571a7a1Sriastradh uint32_t size; 351571a7a1Sriastradh uint64_t mc_addr; 361571a7a1Sriastradh void *table; 371571a7a1Sriastradh struct amdgpu_bo *handle; 381571a7a1Sriastradh }; 391571a7a1Sriastradh 401571a7a1Sriastradh struct smu_table_array { 411571a7a1Sriastradh struct smu_table_entry entry[TABLE_COUNT]; 421571a7a1Sriastradh }; 431571a7a1Sriastradh 441571a7a1Sriastradh struct vega12_smumgr { 451571a7a1Sriastradh struct smu_table_array smu_tables; 461571a7a1Sriastradh }; 471571a7a1Sriastradh 481571a7a1Sriastradh #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF 491571a7a1Sriastradh #define SMU_FEATURES_LOW_SHIFT 0 501571a7a1Sriastradh #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 511571a7a1Sriastradh #define SMU_FEATURES_HIGH_SHIFT 32 521571a7a1Sriastradh 531571a7a1Sriastradh int vega12_enable_smc_features(struct pp_hwmgr *hwmgr, 541571a7a1Sriastradh bool enable, uint64_t feature_mask); 551571a7a1Sriastradh int vega12_get_enabled_smc_features(struct pp_hwmgr *hwmgr, 561571a7a1Sriastradh uint64_t *features_enabled); 571571a7a1Sriastradh 581571a7a1Sriastradh #endif 591571a7a1Sriastradh 60