1*9a4c85f7Sriastradh /* $NetBSD: drm_edid.c,v 1.15 2021/12/19 12:44:04 riastradh Exp $ */
24e59feabSriastradh
356053ce7Sriastradh /*
456053ce7Sriastradh * Copyright (c) 2006 Luc Verhaegen (quirks list)
556053ce7Sriastradh * Copyright (c) 2007-2008 Intel Corporation
656053ce7Sriastradh * Jesse Barnes <jesse.barnes@intel.com>
756053ce7Sriastradh * Copyright 2010 Red Hat, Inc.
856053ce7Sriastradh *
956053ce7Sriastradh * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
1056053ce7Sriastradh * FB layer.
1156053ce7Sriastradh * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
1256053ce7Sriastradh *
1356053ce7Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a
1456053ce7Sriastradh * copy of this software and associated documentation files (the "Software"),
1556053ce7Sriastradh * to deal in the Software without restriction, including without limitation
1656053ce7Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sub license,
1756053ce7Sriastradh * and/or sell copies of the Software, and to permit persons to whom the
1856053ce7Sriastradh * Software is furnished to do so, subject to the following conditions:
1956053ce7Sriastradh *
2056053ce7Sriastradh * The above copyright notice and this permission notice (including the
2156053ce7Sriastradh * next paragraph) shall be included in all copies or substantial portions
2256053ce7Sriastradh * of the Software.
2356053ce7Sriastradh *
2456053ce7Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2556053ce7Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2656053ce7Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
2756053ce7Sriastradh * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
2856053ce7Sriastradh * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2956053ce7Sriastradh * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
3056053ce7Sriastradh * DEALINGS IN THE SOFTWARE.
3156053ce7Sriastradh */
324e59feabSriastradh
33677dec6eSriastradh #include <sys/cdefs.h>
34*9a4c85f7Sriastradh __KERNEL_RCSID(0, "$NetBSD: drm_edid.c,v 1.15 2021/12/19 12:44:04 riastradh Exp $");
35677dec6eSriastradh
36a55ed7faSriastradh #include <linux/hdmi.h>
3756053ce7Sriastradh #include <linux/i2c.h>
38677dec6eSriastradh #include <linux/kernel.h>
3956053ce7Sriastradh #include <linux/module.h>
40677dec6eSriastradh #include <linux/slab.h>
41677dec6eSriastradh #include <linux/vga_switcheroo.h>
42677dec6eSriastradh
434e59feabSriastradh #include <drm/drm_displayid.h>
44677dec6eSriastradh #include <drm/drm_drv.h>
458e465d8aSriastradh #include <linux/bitmap.h>
46677dec6eSriastradh #include <drm/drm_edid.h>
47677dec6eSriastradh #include <drm/drm_encoder.h>
48677dec6eSriastradh #include <drm/drm_print.h>
49677dec6eSriastradh #include <drm/drm_scdc_helper.h>
50677dec6eSriastradh
51677dec6eSriastradh #include "drm_crtc_internal.h"
5256053ce7Sriastradh
53aa66f76bSriastradh #include <linux/nbsd-namespace.h>
54aa66f76bSriastradh
5556053ce7Sriastradh #define version_greater(edid, maj, min) \
5656053ce7Sriastradh (((edid)->version > (maj)) || \
5756053ce7Sriastradh ((edid)->version == (maj) && (edid)->revision > (min)))
5856053ce7Sriastradh
5956053ce7Sriastradh #define EDID_EST_TIMINGS 16
6056053ce7Sriastradh #define EDID_STD_TIMINGS 8
6156053ce7Sriastradh #define EDID_DETAILED_TIMINGS 4
6256053ce7Sriastradh
6356053ce7Sriastradh /*
6456053ce7Sriastradh * EDID blocks out in the wild have a variety of bugs, try to collect
6556053ce7Sriastradh * them here (note that userspace may work around broken monitors first,
6656053ce7Sriastradh * but fixes should make their way here so that the kernel "just works"
6756053ce7Sriastradh * on as many displays as possible).
6856053ce7Sriastradh */
6956053ce7Sriastradh
7056053ce7Sriastradh /* First detailed mode wrong, use largest 60Hz mode */
7156053ce7Sriastradh #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
7256053ce7Sriastradh /* Reported 135MHz pixel clock is too high, needs adjustment */
7356053ce7Sriastradh #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
7456053ce7Sriastradh /* Prefer the largest mode at 75 Hz */
7556053ce7Sriastradh #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
7656053ce7Sriastradh /* Detail timing is in cm not mm */
7756053ce7Sriastradh #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
7856053ce7Sriastradh /* Detailed timing descriptors have bogus size values, so just take the
7956053ce7Sriastradh * maximum size and use that.
8056053ce7Sriastradh */
8156053ce7Sriastradh #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
8256053ce7Sriastradh /* use +hsync +vsync for detailed mode */
8356053ce7Sriastradh #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
8456053ce7Sriastradh /* Force reduced-blanking timings for detailed modes */
8556053ce7Sriastradh #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
86a55ed7faSriastradh /* Force 8bpc */
87a55ed7faSriastradh #define EDID_QUIRK_FORCE_8BPC (1 << 8)
884e59feabSriastradh /* Force 12bpc */
894e59feabSriastradh #define EDID_QUIRK_FORCE_12BPC (1 << 9)
904e59feabSriastradh /* Force 6bpc */
914e59feabSriastradh #define EDID_QUIRK_FORCE_6BPC (1 << 10)
924e59feabSriastradh /* Force 10bpc */
934e59feabSriastradh #define EDID_QUIRK_FORCE_10BPC (1 << 11)
94677dec6eSriastradh /* Non desktop display (i.e. HMD) */
95677dec6eSriastradh #define EDID_QUIRK_NON_DESKTOP (1 << 12)
9656053ce7Sriastradh
9756053ce7Sriastradh struct detailed_mode_closure {
9856053ce7Sriastradh struct drm_connector *connector;
9956053ce7Sriastradh struct edid *edid;
10056053ce7Sriastradh bool preferred;
10156053ce7Sriastradh u32 quirks;
10256053ce7Sriastradh int modes;
10356053ce7Sriastradh };
10456053ce7Sriastradh
10556053ce7Sriastradh #define LEVEL_DMT 0
10656053ce7Sriastradh #define LEVEL_GTF 1
10756053ce7Sriastradh #define LEVEL_GTF2 2
10856053ce7Sriastradh #define LEVEL_CVT 3
10956053ce7Sriastradh
110677dec6eSriastradh static const struct edid_quirk {
11156053ce7Sriastradh char vendor[4];
11256053ce7Sriastradh int product_id;
11356053ce7Sriastradh u32 quirks;
11456053ce7Sriastradh } edid_quirk_list[] = {
11556053ce7Sriastradh /* Acer AL1706 */
11656053ce7Sriastradh { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
11756053ce7Sriastradh /* Acer F51 */
11856053ce7Sriastradh { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
11956053ce7Sriastradh
1204e59feabSriastradh /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
1214e59feabSriastradh { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
1224e59feabSriastradh
123677dec6eSriastradh /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
124677dec6eSriastradh { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
125677dec6eSriastradh
1264e59feabSriastradh /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
1274e59feabSriastradh { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
1284e59feabSriastradh
129677dec6eSriastradh /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
130677dec6eSriastradh { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
131677dec6eSriastradh
132677dec6eSriastradh /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
133677dec6eSriastradh { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
134677dec6eSriastradh
13556053ce7Sriastradh /* Belinea 10 15 55 */
13656053ce7Sriastradh { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
13756053ce7Sriastradh { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
13856053ce7Sriastradh
13956053ce7Sriastradh /* Envision Peripherals, Inc. EN-7100e */
14056053ce7Sriastradh { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
14156053ce7Sriastradh /* Envision EN2028 */
14256053ce7Sriastradh { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
14356053ce7Sriastradh
14456053ce7Sriastradh /* Funai Electronics PM36B */
14556053ce7Sriastradh { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
14656053ce7Sriastradh EDID_QUIRK_DETAILED_IN_CM },
14756053ce7Sriastradh
1484e59feabSriastradh /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
1494e59feabSriastradh { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
1504e59feabSriastradh
15156053ce7Sriastradh /* LG Philips LCD LP154W01-A5 */
15256053ce7Sriastradh { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
15356053ce7Sriastradh { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
15456053ce7Sriastradh
15556053ce7Sriastradh /* Samsung SyncMaster 205BW. Note: irony */
15656053ce7Sriastradh { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
15756053ce7Sriastradh /* Samsung SyncMaster 22[5-6]BW */
15856053ce7Sriastradh { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
15956053ce7Sriastradh { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
16056053ce7Sriastradh
1614e59feabSriastradh /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
1624e59feabSriastradh { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
1634e59feabSriastradh
16456053ce7Sriastradh /* ViewSonic VA2026w */
16556053ce7Sriastradh { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
166a55ed7faSriastradh
167a55ed7faSriastradh /* Medion MD 30217 PG */
168a55ed7faSriastradh { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
169a55ed7faSriastradh
170677dec6eSriastradh /* Lenovo G50 */
171677dec6eSriastradh { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
172677dec6eSriastradh
173a55ed7faSriastradh /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
174a55ed7faSriastradh { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
1754e59feabSriastradh
1764e59feabSriastradh /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
1774e59feabSriastradh { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
178677dec6eSriastradh
179677dec6eSriastradh /* Valve Index Headset */
180677dec6eSriastradh { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
181677dec6eSriastradh { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
182677dec6eSriastradh { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
183677dec6eSriastradh { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
184677dec6eSriastradh { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
185677dec6eSriastradh { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
186677dec6eSriastradh { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
187677dec6eSriastradh { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
188677dec6eSriastradh { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
189677dec6eSriastradh { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
190677dec6eSriastradh { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
191677dec6eSriastradh { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
192677dec6eSriastradh { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
193677dec6eSriastradh { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
194677dec6eSriastradh { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
195677dec6eSriastradh { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
196677dec6eSriastradh { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
197677dec6eSriastradh
198677dec6eSriastradh /* HTC Vive and Vive Pro VR Headsets */
199677dec6eSriastradh { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
200677dec6eSriastradh { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
201677dec6eSriastradh
202677dec6eSriastradh /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
203677dec6eSriastradh { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
204677dec6eSriastradh { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
205677dec6eSriastradh { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
206677dec6eSriastradh
207677dec6eSriastradh /* Windows Mixed Reality Headsets */
208677dec6eSriastradh { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
209677dec6eSriastradh { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
210677dec6eSriastradh { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
211677dec6eSriastradh { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
212677dec6eSriastradh { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
213677dec6eSriastradh { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
214677dec6eSriastradh { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
215677dec6eSriastradh { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
216677dec6eSriastradh
217677dec6eSriastradh /* Sony PlayStation VR Headset */
218677dec6eSriastradh { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
219677dec6eSriastradh
220677dec6eSriastradh /* Sensics VR Headsets */
221677dec6eSriastradh { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
222677dec6eSriastradh
223677dec6eSriastradh /* OSVR HDK and HDK2 VR Headsets */
224677dec6eSriastradh { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
225a55ed7faSriastradh };
226a55ed7faSriastradh
227a55ed7faSriastradh /*
228a55ed7faSriastradh * Autogenerated from the DMT spec.
229a55ed7faSriastradh * This table is copied from xfree86/modes/xf86EdidModes.c.
230a55ed7faSriastradh */
231a55ed7faSriastradh static const struct drm_display_mode drm_dmt_modes[] = {
2324e59feabSriastradh /* 0x01 - 640x350@85Hz */
233a55ed7faSriastradh { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
234a55ed7faSriastradh 736, 832, 0, 350, 382, 385, 445, 0,
235a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
2364e59feabSriastradh /* 0x02 - 640x400@85Hz */
237a55ed7faSriastradh { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
238a55ed7faSriastradh 736, 832, 0, 400, 401, 404, 445, 0,
239a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
2404e59feabSriastradh /* 0x03 - 720x400@85Hz */
241a55ed7faSriastradh { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
242a55ed7faSriastradh 828, 936, 0, 400, 401, 404, 446, 0,
243a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
2444e59feabSriastradh /* 0x04 - 640x480@60Hz */
245a55ed7faSriastradh { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
2464e59feabSriastradh 752, 800, 0, 480, 490, 492, 525, 0,
247a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
2484e59feabSriastradh /* 0x05 - 640x480@72Hz */
249a55ed7faSriastradh { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
250a55ed7faSriastradh 704, 832, 0, 480, 489, 492, 520, 0,
251a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
2524e59feabSriastradh /* 0x06 - 640x480@75Hz */
253a55ed7faSriastradh { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
254a55ed7faSriastradh 720, 840, 0, 480, 481, 484, 500, 0,
255a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
2564e59feabSriastradh /* 0x07 - 640x480@85Hz */
257a55ed7faSriastradh { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
258a55ed7faSriastradh 752, 832, 0, 480, 481, 484, 509, 0,
259a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
2604e59feabSriastradh /* 0x08 - 800x600@56Hz */
261a55ed7faSriastradh { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
262a55ed7faSriastradh 896, 1024, 0, 600, 601, 603, 625, 0,
263a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2644e59feabSriastradh /* 0x09 - 800x600@60Hz */
265a55ed7faSriastradh { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
266a55ed7faSriastradh 968, 1056, 0, 600, 601, 605, 628, 0,
267a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2684e59feabSriastradh /* 0x0a - 800x600@72Hz */
269a55ed7faSriastradh { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
270a55ed7faSriastradh 976, 1040, 0, 600, 637, 643, 666, 0,
271a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2724e59feabSriastradh /* 0x0b - 800x600@75Hz */
273a55ed7faSriastradh { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
274a55ed7faSriastradh 896, 1056, 0, 600, 601, 604, 625, 0,
275a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2764e59feabSriastradh /* 0x0c - 800x600@85Hz */
277a55ed7faSriastradh { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
278a55ed7faSriastradh 896, 1048, 0, 600, 601, 604, 631, 0,
279a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2804e59feabSriastradh /* 0x0d - 800x600@120Hz RB */
281a55ed7faSriastradh { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
282a55ed7faSriastradh 880, 960, 0, 600, 603, 607, 636, 0,
283a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
2844e59feabSriastradh /* 0x0e - 848x480@60Hz */
285a55ed7faSriastradh { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
286a55ed7faSriastradh 976, 1088, 0, 480, 486, 494, 517, 0,
287a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2884e59feabSriastradh /* 0x0f - 1024x768@43Hz, interlace */
289a55ed7faSriastradh { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
290677dec6eSriastradh 1208, 1264, 0, 768, 768, 776, 817, 0,
291a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
292a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE) },
2934e59feabSriastradh /* 0x10 - 1024x768@60Hz */
294a55ed7faSriastradh { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
295a55ed7faSriastradh 1184, 1344, 0, 768, 771, 777, 806, 0,
296a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
2974e59feabSriastradh /* 0x11 - 1024x768@70Hz */
298a55ed7faSriastradh { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
299a55ed7faSriastradh 1184, 1328, 0, 768, 771, 777, 806, 0,
300a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
3014e59feabSriastradh /* 0x12 - 1024x768@75Hz */
302a55ed7faSriastradh { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
303a55ed7faSriastradh 1136, 1312, 0, 768, 769, 772, 800, 0,
304a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
3054e59feabSriastradh /* 0x13 - 1024x768@85Hz */
306a55ed7faSriastradh { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
307a55ed7faSriastradh 1168, 1376, 0, 768, 769, 772, 808, 0,
308a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
3094e59feabSriastradh /* 0x14 - 1024x768@120Hz RB */
310a55ed7faSriastradh { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
311a55ed7faSriastradh 1104, 1184, 0, 768, 771, 775, 813, 0,
312a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
3134e59feabSriastradh /* 0x15 - 1152x864@75Hz */
314a55ed7faSriastradh { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
315a55ed7faSriastradh 1344, 1600, 0, 864, 865, 868, 900, 0,
316a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
3174e59feabSriastradh /* 0x55 - 1280x720@60Hz */
3184e59feabSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
3194e59feabSriastradh 1430, 1650, 0, 720, 725, 730, 750, 0,
3204e59feabSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
3214e59feabSriastradh /* 0x16 - 1280x768@60Hz RB */
322a55ed7faSriastradh { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
323a55ed7faSriastradh 1360, 1440, 0, 768, 771, 778, 790, 0,
324a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
3254e59feabSriastradh /* 0x17 - 1280x768@60Hz */
326a55ed7faSriastradh { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
327a55ed7faSriastradh 1472, 1664, 0, 768, 771, 778, 798, 0,
328a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
3294e59feabSriastradh /* 0x18 - 1280x768@75Hz */
330a55ed7faSriastradh { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
331a55ed7faSriastradh 1488, 1696, 0, 768, 771, 778, 805, 0,
3324e59feabSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
3334e59feabSriastradh /* 0x19 - 1280x768@85Hz */
334a55ed7faSriastradh { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
335a55ed7faSriastradh 1496, 1712, 0, 768, 771, 778, 809, 0,
336a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
3374e59feabSriastradh /* 0x1a - 1280x768@120Hz RB */
338a55ed7faSriastradh { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
339a55ed7faSriastradh 1360, 1440, 0, 768, 771, 778, 813, 0,
340a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
3414e59feabSriastradh /* 0x1b - 1280x800@60Hz RB */
342a55ed7faSriastradh { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
343a55ed7faSriastradh 1360, 1440, 0, 800, 803, 809, 823, 0,
344a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
3454e59feabSriastradh /* 0x1c - 1280x800@60Hz */
346a55ed7faSriastradh { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
347a55ed7faSriastradh 1480, 1680, 0, 800, 803, 809, 831, 0,
3484e59feabSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
3494e59feabSriastradh /* 0x1d - 1280x800@75Hz */
350a55ed7faSriastradh { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
351a55ed7faSriastradh 1488, 1696, 0, 800, 803, 809, 838, 0,
352a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
3534e59feabSriastradh /* 0x1e - 1280x800@85Hz */
354a55ed7faSriastradh { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
355a55ed7faSriastradh 1496, 1712, 0, 800, 803, 809, 843, 0,
356a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
3574e59feabSriastradh /* 0x1f - 1280x800@120Hz RB */
358a55ed7faSriastradh { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
359a55ed7faSriastradh 1360, 1440, 0, 800, 803, 809, 847, 0,
360a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
3614e59feabSriastradh /* 0x20 - 1280x960@60Hz */
362a55ed7faSriastradh { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
363a55ed7faSriastradh 1488, 1800, 0, 960, 961, 964, 1000, 0,
364a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
3654e59feabSriastradh /* 0x21 - 1280x960@85Hz */
366a55ed7faSriastradh { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
367a55ed7faSriastradh 1504, 1728, 0, 960, 961, 964, 1011, 0,
368a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
3694e59feabSriastradh /* 0x22 - 1280x960@120Hz RB */
370a55ed7faSriastradh { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
371a55ed7faSriastradh 1360, 1440, 0, 960, 963, 967, 1017, 0,
372a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
3734e59feabSriastradh /* 0x23 - 1280x1024@60Hz */
374a55ed7faSriastradh { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
375a55ed7faSriastradh 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
376a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
3774e59feabSriastradh /* 0x24 - 1280x1024@75Hz */
378a55ed7faSriastradh { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
379a55ed7faSriastradh 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
380a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
3814e59feabSriastradh /* 0x25 - 1280x1024@85Hz */
382a55ed7faSriastradh { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
383a55ed7faSriastradh 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
384a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
3854e59feabSriastradh /* 0x26 - 1280x1024@120Hz RB */
386a55ed7faSriastradh { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
387a55ed7faSriastradh 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
388a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
3894e59feabSriastradh /* 0x27 - 1360x768@60Hz */
390a55ed7faSriastradh { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
391a55ed7faSriastradh 1536, 1792, 0, 768, 771, 777, 795, 0,
392a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
3934e59feabSriastradh /* 0x28 - 1360x768@120Hz RB */
394a55ed7faSriastradh { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
395a55ed7faSriastradh 1440, 1520, 0, 768, 771, 776, 813, 0,
396a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
3974e59feabSriastradh /* 0x51 - 1366x768@60Hz */
3984e59feabSriastradh { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
3994e59feabSriastradh 1579, 1792, 0, 768, 771, 774, 798, 0,
4004e59feabSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
4014e59feabSriastradh /* 0x56 - 1366x768@60Hz */
4024e59feabSriastradh { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
4034e59feabSriastradh 1436, 1500, 0, 768, 769, 772, 800, 0,
4044e59feabSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
4054e59feabSriastradh /* 0x29 - 1400x1050@60Hz RB */
406a55ed7faSriastradh { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
407a55ed7faSriastradh 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
408a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
4094e59feabSriastradh /* 0x2a - 1400x1050@60Hz */
410a55ed7faSriastradh { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
411a55ed7faSriastradh 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
412a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
4134e59feabSriastradh /* 0x2b - 1400x1050@75Hz */
414a55ed7faSriastradh { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
415a55ed7faSriastradh 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
416a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
4174e59feabSriastradh /* 0x2c - 1400x1050@85Hz */
418a55ed7faSriastradh { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
419a55ed7faSriastradh 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
420a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
4214e59feabSriastradh /* 0x2d - 1400x1050@120Hz RB */
422a55ed7faSriastradh { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
423a55ed7faSriastradh 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
424a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
4254e59feabSriastradh /* 0x2e - 1440x900@60Hz RB */
426a55ed7faSriastradh { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
427a55ed7faSriastradh 1520, 1600, 0, 900, 903, 909, 926, 0,
428a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
4294e59feabSriastradh /* 0x2f - 1440x900@60Hz */
430a55ed7faSriastradh { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
431a55ed7faSriastradh 1672, 1904, 0, 900, 903, 909, 934, 0,
432a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
4334e59feabSriastradh /* 0x30 - 1440x900@75Hz */
434a55ed7faSriastradh { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
435a55ed7faSriastradh 1688, 1936, 0, 900, 903, 909, 942, 0,
436a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
4374e59feabSriastradh /* 0x31 - 1440x900@85Hz */
438a55ed7faSriastradh { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
439a55ed7faSriastradh 1696, 1952, 0, 900, 903, 909, 948, 0,
440a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
4414e59feabSriastradh /* 0x32 - 1440x900@120Hz RB */
442a55ed7faSriastradh { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
443a55ed7faSriastradh 1520, 1600, 0, 900, 903, 909, 953, 0,
444a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
4454e59feabSriastradh /* 0x53 - 1600x900@60Hz */
4464e59feabSriastradh { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
4474e59feabSriastradh 1704, 1800, 0, 900, 901, 904, 1000, 0,
4484e59feabSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
4494e59feabSriastradh /* 0x33 - 1600x1200@60Hz */
450a55ed7faSriastradh { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
451a55ed7faSriastradh 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
452a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
4534e59feabSriastradh /* 0x34 - 1600x1200@65Hz */
454a55ed7faSriastradh { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
455a55ed7faSriastradh 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
456a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
4574e59feabSriastradh /* 0x35 - 1600x1200@70Hz */
458a55ed7faSriastradh { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
459a55ed7faSriastradh 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
460a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
4614e59feabSriastradh /* 0x36 - 1600x1200@75Hz */
462a55ed7faSriastradh { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
463a55ed7faSriastradh 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
464a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
4654e59feabSriastradh /* 0x37 - 1600x1200@85Hz */
466a55ed7faSriastradh { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
467a55ed7faSriastradh 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
468a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
4694e59feabSriastradh /* 0x38 - 1600x1200@120Hz RB */
470a55ed7faSriastradh { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
471a55ed7faSriastradh 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
472a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
4734e59feabSriastradh /* 0x39 - 1680x1050@60Hz RB */
474a55ed7faSriastradh { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
475a55ed7faSriastradh 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
476a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
4774e59feabSriastradh /* 0x3a - 1680x1050@60Hz */
478a55ed7faSriastradh { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
479a55ed7faSriastradh 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
480a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
4814e59feabSriastradh /* 0x3b - 1680x1050@75Hz */
482a55ed7faSriastradh { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
483a55ed7faSriastradh 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
484a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
4854e59feabSriastradh /* 0x3c - 1680x1050@85Hz */
486a55ed7faSriastradh { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
487a55ed7faSriastradh 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
488a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
4894e59feabSriastradh /* 0x3d - 1680x1050@120Hz RB */
490a55ed7faSriastradh { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
491a55ed7faSriastradh 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
492a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
4934e59feabSriastradh /* 0x3e - 1792x1344@60Hz */
494a55ed7faSriastradh { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
495a55ed7faSriastradh 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
496a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
4974e59feabSriastradh /* 0x3f - 1792x1344@75Hz */
498a55ed7faSriastradh { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
499a55ed7faSriastradh 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
500a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5014e59feabSriastradh /* 0x40 - 1792x1344@120Hz RB */
502a55ed7faSriastradh { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
503a55ed7faSriastradh 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
504a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
5054e59feabSriastradh /* 0x41 - 1856x1392@60Hz */
506a55ed7faSriastradh { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
507a55ed7faSriastradh 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
508a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5094e59feabSriastradh /* 0x42 - 1856x1392@75Hz */
510a55ed7faSriastradh { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
5114e59feabSriastradh 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
512a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5134e59feabSriastradh /* 0x43 - 1856x1392@120Hz RB */
514a55ed7faSriastradh { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
515a55ed7faSriastradh 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
516a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
5174e59feabSriastradh /* 0x52 - 1920x1080@60Hz */
5184e59feabSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
5194e59feabSriastradh 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
5204e59feabSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
5214e59feabSriastradh /* 0x44 - 1920x1200@60Hz RB */
522a55ed7faSriastradh { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
523a55ed7faSriastradh 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
524a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
5254e59feabSriastradh /* 0x45 - 1920x1200@60Hz */
526a55ed7faSriastradh { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
527a55ed7faSriastradh 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
528a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5294e59feabSriastradh /* 0x46 - 1920x1200@75Hz */
530a55ed7faSriastradh { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
531a55ed7faSriastradh 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
532a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5334e59feabSriastradh /* 0x47 - 1920x1200@85Hz */
534a55ed7faSriastradh { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
535a55ed7faSriastradh 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
536a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5374e59feabSriastradh /* 0x48 - 1920x1200@120Hz RB */
538a55ed7faSriastradh { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
539a55ed7faSriastradh 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
540a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
5414e59feabSriastradh /* 0x49 - 1920x1440@60Hz */
542a55ed7faSriastradh { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
543a55ed7faSriastradh 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
544a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5454e59feabSriastradh /* 0x4a - 1920x1440@75Hz */
546a55ed7faSriastradh { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
547a55ed7faSriastradh 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
548a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5494e59feabSriastradh /* 0x4b - 1920x1440@120Hz RB */
550a55ed7faSriastradh { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
551a55ed7faSriastradh 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
552a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
5534e59feabSriastradh /* 0x54 - 2048x1152@60Hz */
5544e59feabSriastradh { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
5554e59feabSriastradh 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
5564e59feabSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
5574e59feabSriastradh /* 0x4c - 2560x1600@60Hz RB */
558a55ed7faSriastradh { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
559a55ed7faSriastradh 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
560a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
5614e59feabSriastradh /* 0x4d - 2560x1600@60Hz */
562a55ed7faSriastradh { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
563a55ed7faSriastradh 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
564a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5654e59feabSriastradh /* 0x4e - 2560x1600@75Hz */
566a55ed7faSriastradh { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
567a55ed7faSriastradh 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
568a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5694e59feabSriastradh /* 0x4f - 2560x1600@85Hz */
570a55ed7faSriastradh { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
571a55ed7faSriastradh 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
572a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
5734e59feabSriastradh /* 0x50 - 2560x1600@120Hz RB */
574a55ed7faSriastradh { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
575a55ed7faSriastradh 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
576a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
5774e59feabSriastradh /* 0x57 - 4096x2160@60Hz RB */
5784e59feabSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
5794e59feabSriastradh 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
5804e59feabSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
5814e59feabSriastradh /* 0x58 - 4096x2160@59.94Hz RB */
5824e59feabSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
5834e59feabSriastradh 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
5844e59feabSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
585a55ed7faSriastradh };
586a55ed7faSriastradh
587a55ed7faSriastradh /*
588a55ed7faSriastradh * These more or less come from the DMT spec. The 720x400 modes are
589a55ed7faSriastradh * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
590a55ed7faSriastradh * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
591a55ed7faSriastradh * should be 1152x870, again for the Mac, but instead we use the x864 DMT
592a55ed7faSriastradh * mode.
593a55ed7faSriastradh *
594a55ed7faSriastradh * The DMT modes have been fact-checked; the rest are mild guesses.
595a55ed7faSriastradh */
596a55ed7faSriastradh static const struct drm_display_mode edid_est_modes[] = {
597a55ed7faSriastradh { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
598a55ed7faSriastradh 968, 1056, 0, 600, 601, 605, 628, 0,
599a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
600a55ed7faSriastradh { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
601a55ed7faSriastradh 896, 1024, 0, 600, 601, 603, 625, 0,
602a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
603a55ed7faSriastradh { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
604a55ed7faSriastradh 720, 840, 0, 480, 481, 484, 500, 0,
605a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
606a55ed7faSriastradh { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
607677dec6eSriastradh 704, 832, 0, 480, 489, 492, 520, 0,
608a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
609a55ed7faSriastradh { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
610a55ed7faSriastradh 768, 864, 0, 480, 483, 486, 525, 0,
611a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
612677dec6eSriastradh { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
613a55ed7faSriastradh 752, 800, 0, 480, 490, 492, 525, 0,
614a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
615a55ed7faSriastradh { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
616a55ed7faSriastradh 846, 900, 0, 400, 421, 423, 449, 0,
617a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
618a55ed7faSriastradh { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
619a55ed7faSriastradh 846, 900, 0, 400, 412, 414, 449, 0,
620a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
621a55ed7faSriastradh { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
622a55ed7faSriastradh 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
623a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
624677dec6eSriastradh { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
625a55ed7faSriastradh 1136, 1312, 0, 768, 769, 772, 800, 0,
626a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
627a55ed7faSriastradh { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
628a55ed7faSriastradh 1184, 1328, 0, 768, 771, 777, 806, 0,
629a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
630a55ed7faSriastradh { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
631a55ed7faSriastradh 1184, 1344, 0, 768, 771, 777, 806, 0,
632a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
633a55ed7faSriastradh { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
634a55ed7faSriastradh 1208, 1264, 0, 768, 768, 776, 817, 0,
635a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
636a55ed7faSriastradh { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
637a55ed7faSriastradh 928, 1152, 0, 624, 625, 628, 667, 0,
638a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
639a55ed7faSriastradh { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
640a55ed7faSriastradh 896, 1056, 0, 600, 601, 604, 625, 0,
641a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
642a55ed7faSriastradh { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
643a55ed7faSriastradh 976, 1040, 0, 600, 637, 643, 666, 0,
644a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
645a55ed7faSriastradh { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
646a55ed7faSriastradh 1344, 1600, 0, 864, 865, 868, 900, 0,
647a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
648a55ed7faSriastradh };
649a55ed7faSriastradh
650a55ed7faSriastradh struct minimode {
651a55ed7faSriastradh short w;
652a55ed7faSriastradh short h;
653a55ed7faSriastradh short r;
654a55ed7faSriastradh short rb;
655a55ed7faSriastradh };
656a55ed7faSriastradh
657a55ed7faSriastradh static const struct minimode est3_modes[] = {
658a55ed7faSriastradh /* byte 6 */
659a55ed7faSriastradh { 640, 350, 85, 0 },
660a55ed7faSriastradh { 640, 400, 85, 0 },
661a55ed7faSriastradh { 720, 400, 85, 0 },
662a55ed7faSriastradh { 640, 480, 85, 0 },
663a55ed7faSriastradh { 848, 480, 60, 0 },
664a55ed7faSriastradh { 800, 600, 85, 0 },
665a55ed7faSriastradh { 1024, 768, 85, 0 },
666a55ed7faSriastradh { 1152, 864, 75, 0 },
667a55ed7faSriastradh /* byte 7 */
668a55ed7faSriastradh { 1280, 768, 60, 1 },
669a55ed7faSriastradh { 1280, 768, 60, 0 },
670a55ed7faSriastradh { 1280, 768, 75, 0 },
671a55ed7faSriastradh { 1280, 768, 85, 0 },
672a55ed7faSriastradh { 1280, 960, 60, 0 },
673a55ed7faSriastradh { 1280, 960, 85, 0 },
674a55ed7faSriastradh { 1280, 1024, 60, 0 },
675a55ed7faSriastradh { 1280, 1024, 85, 0 },
676a55ed7faSriastradh /* byte 8 */
677a55ed7faSriastradh { 1360, 768, 60, 0 },
678a55ed7faSriastradh { 1440, 900, 60, 1 },
679a55ed7faSriastradh { 1440, 900, 60, 0 },
680a55ed7faSriastradh { 1440, 900, 75, 0 },
681a55ed7faSriastradh { 1440, 900, 85, 0 },
682a55ed7faSriastradh { 1400, 1050, 60, 1 },
683a55ed7faSriastradh { 1400, 1050, 60, 0 },
684a55ed7faSriastradh { 1400, 1050, 75, 0 },
685a55ed7faSriastradh /* byte 9 */
686a55ed7faSriastradh { 1400, 1050, 85, 0 },
687a55ed7faSriastradh { 1680, 1050, 60, 1 },
688a55ed7faSriastradh { 1680, 1050, 60, 0 },
689a55ed7faSriastradh { 1680, 1050, 75, 0 },
690a55ed7faSriastradh { 1680, 1050, 85, 0 },
691a55ed7faSriastradh { 1600, 1200, 60, 0 },
692a55ed7faSriastradh { 1600, 1200, 65, 0 },
693a55ed7faSriastradh { 1600, 1200, 70, 0 },
694a55ed7faSriastradh /* byte 10 */
695a55ed7faSriastradh { 1600, 1200, 75, 0 },
696a55ed7faSriastradh { 1600, 1200, 85, 0 },
697a55ed7faSriastradh { 1792, 1344, 60, 0 },
698a55ed7faSriastradh { 1792, 1344, 75, 0 },
699a55ed7faSriastradh { 1856, 1392, 60, 0 },
700a55ed7faSriastradh { 1856, 1392, 75, 0 },
701a55ed7faSriastradh { 1920, 1200, 60, 1 },
702a55ed7faSriastradh { 1920, 1200, 60, 0 },
703a55ed7faSriastradh /* byte 11 */
704a55ed7faSriastradh { 1920, 1200, 75, 0 },
705a55ed7faSriastradh { 1920, 1200, 85, 0 },
706a55ed7faSriastradh { 1920, 1440, 60, 0 },
707a55ed7faSriastradh { 1920, 1440, 75, 0 },
708a55ed7faSriastradh };
709a55ed7faSriastradh
710a55ed7faSriastradh static const struct minimode extra_modes[] = {
711a55ed7faSriastradh { 1024, 576, 60, 0 },
712a55ed7faSriastradh { 1366, 768, 60, 0 },
713a55ed7faSriastradh { 1600, 900, 60, 0 },
714a55ed7faSriastradh { 1680, 945, 60, 0 },
715a55ed7faSriastradh { 1920, 1080, 60, 0 },
716a55ed7faSriastradh { 2048, 1152, 60, 0 },
717a55ed7faSriastradh { 2048, 1536, 60, 0 },
718a55ed7faSriastradh };
719a55ed7faSriastradh
720a55ed7faSriastradh /*
721677dec6eSriastradh * From CEA/CTA-861 spec.
722677dec6eSriastradh *
723677dec6eSriastradh * Do not access directly, instead always use cea_mode_for_vic().
724a55ed7faSriastradh */
725677dec6eSriastradh static const struct drm_display_mode edid_cea_modes_1[] = {
726677dec6eSriastradh /* 1 - 640x480@60Hz 4:3 */
727a55ed7faSriastradh { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
728a55ed7faSriastradh 752, 800, 0, 480, 490, 492, 525, 0,
729a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
730a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
731677dec6eSriastradh /* 2 - 720x480@60Hz 4:3 */
732a55ed7faSriastradh { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
733a55ed7faSriastradh 798, 858, 0, 480, 489, 495, 525, 0,
734a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
735a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
736677dec6eSriastradh /* 3 - 720x480@60Hz 16:9 */
737a55ed7faSriastradh { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
738a55ed7faSriastradh 798, 858, 0, 480, 489, 495, 525, 0,
739a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
740a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
741677dec6eSriastradh /* 4 - 1280x720@60Hz 16:9 */
742a55ed7faSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
743a55ed7faSriastradh 1430, 1650, 0, 720, 725, 730, 750, 0,
744a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
745a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
746677dec6eSriastradh /* 5 - 1920x1080i@60Hz 16:9 */
747a55ed7faSriastradh { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
748a55ed7faSriastradh 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
749a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
750a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE),
751a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
752677dec6eSriastradh /* 6 - 720(1440)x480i@60Hz 4:3 */
7534e59feabSriastradh { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
7544e59feabSriastradh 801, 858, 0, 480, 488, 494, 525, 0,
755a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
756a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
757a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
758677dec6eSriastradh /* 7 - 720(1440)x480i@60Hz 16:9 */
7594e59feabSriastradh { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
7604e59feabSriastradh 801, 858, 0, 480, 488, 494, 525, 0,
761a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
762a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
763a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
764677dec6eSriastradh /* 8 - 720(1440)x240@60Hz 4:3 */
7654e59feabSriastradh { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
7664e59feabSriastradh 801, 858, 0, 240, 244, 247, 262, 0,
767a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
768a55ed7faSriastradh DRM_MODE_FLAG_DBLCLK),
769a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
770677dec6eSriastradh /* 9 - 720(1440)x240@60Hz 16:9 */
7714e59feabSriastradh { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
7724e59feabSriastradh 801, 858, 0, 240, 244, 247, 262, 0,
773a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
774a55ed7faSriastradh DRM_MODE_FLAG_DBLCLK),
775a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776677dec6eSriastradh /* 10 - 2880x480i@60Hz 4:3 */
777a55ed7faSriastradh { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
778a55ed7faSriastradh 3204, 3432, 0, 480, 488, 494, 525, 0,
779a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
780a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE),
781a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
782677dec6eSriastradh /* 11 - 2880x480i@60Hz 16:9 */
783a55ed7faSriastradh { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784a55ed7faSriastradh 3204, 3432, 0, 480, 488, 494, 525, 0,
785a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
786a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE),
787a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
788677dec6eSriastradh /* 12 - 2880x240@60Hz 4:3 */
789a55ed7faSriastradh { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
790a55ed7faSriastradh 3204, 3432, 0, 240, 244, 247, 262, 0,
791a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
792a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
793677dec6eSriastradh /* 13 - 2880x240@60Hz 16:9 */
794a55ed7faSriastradh { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
795a55ed7faSriastradh 3204, 3432, 0, 240, 244, 247, 262, 0,
796a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
797a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
798677dec6eSriastradh /* 14 - 1440x480@60Hz 4:3 */
799a55ed7faSriastradh { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
800a55ed7faSriastradh 1596, 1716, 0, 480, 489, 495, 525, 0,
801a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
802a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
803677dec6eSriastradh /* 15 - 1440x480@60Hz 16:9 */
804a55ed7faSriastradh { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
805a55ed7faSriastradh 1596, 1716, 0, 480, 489, 495, 525, 0,
806a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
808677dec6eSriastradh /* 16 - 1920x1080@60Hz 16:9 */
809a55ed7faSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
810a55ed7faSriastradh 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
811a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
812a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
813677dec6eSriastradh /* 17 - 720x576@50Hz 4:3 */
814a55ed7faSriastradh { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
815a55ed7faSriastradh 796, 864, 0, 576, 581, 586, 625, 0,
816a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
818677dec6eSriastradh /* 18 - 720x576@50Hz 16:9 */
819a55ed7faSriastradh { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
820a55ed7faSriastradh 796, 864, 0, 576, 581, 586, 625, 0,
821a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
822a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823677dec6eSriastradh /* 19 - 1280x720@50Hz 16:9 */
824a55ed7faSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
825a55ed7faSriastradh 1760, 1980, 0, 720, 725, 730, 750, 0,
826a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
827a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
828677dec6eSriastradh /* 20 - 1920x1080i@50Hz 16:9 */
829a55ed7faSriastradh { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
830a55ed7faSriastradh 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
831a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
832a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE),
833a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
834677dec6eSriastradh /* 21 - 720(1440)x576i@50Hz 4:3 */
8354e59feabSriastradh { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
8364e59feabSriastradh 795, 864, 0, 576, 580, 586, 625, 0,
837a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
838a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
839a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
840677dec6eSriastradh /* 22 - 720(1440)x576i@50Hz 16:9 */
8414e59feabSriastradh { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
8424e59feabSriastradh 795, 864, 0, 576, 580, 586, 625, 0,
843a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
844a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
845a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
846677dec6eSriastradh /* 23 - 720(1440)x288@50Hz 4:3 */
8474e59feabSriastradh { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
8484e59feabSriastradh 795, 864, 0, 288, 290, 293, 312, 0,
849a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
850a55ed7faSriastradh DRM_MODE_FLAG_DBLCLK),
851a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
852677dec6eSriastradh /* 24 - 720(1440)x288@50Hz 16:9 */
8534e59feabSriastradh { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
8544e59feabSriastradh 795, 864, 0, 288, 290, 293, 312, 0,
855a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
856a55ed7faSriastradh DRM_MODE_FLAG_DBLCLK),
857a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858677dec6eSriastradh /* 25 - 2880x576i@50Hz 4:3 */
859a55ed7faSriastradh { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
860a55ed7faSriastradh 3180, 3456, 0, 576, 580, 586, 625, 0,
861a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
862a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE),
863a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
864677dec6eSriastradh /* 26 - 2880x576i@50Hz 16:9 */
865a55ed7faSriastradh { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866a55ed7faSriastradh 3180, 3456, 0, 576, 580, 586, 625, 0,
867a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
868a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE),
869a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870677dec6eSriastradh /* 27 - 2880x288@50Hz 4:3 */
871a55ed7faSriastradh { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
872a55ed7faSriastradh 3180, 3456, 0, 288, 290, 293, 312, 0,
873a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
874a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
875677dec6eSriastradh /* 28 - 2880x288@50Hz 16:9 */
876a55ed7faSriastradh { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
877a55ed7faSriastradh 3180, 3456, 0, 288, 290, 293, 312, 0,
878a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
879a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
880677dec6eSriastradh /* 29 - 1440x576@50Hz 4:3 */
881a55ed7faSriastradh { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
882a55ed7faSriastradh 1592, 1728, 0, 576, 581, 586, 625, 0,
883a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
884a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
885677dec6eSriastradh /* 30 - 1440x576@50Hz 16:9 */
886a55ed7faSriastradh { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
887a55ed7faSriastradh 1592, 1728, 0, 576, 581, 586, 625, 0,
888a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
889a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
890677dec6eSriastradh /* 31 - 1920x1080@50Hz 16:9 */
891a55ed7faSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
892a55ed7faSriastradh 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
893a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
894a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
895677dec6eSriastradh /* 32 - 1920x1080@24Hz 16:9 */
896a55ed7faSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
897a55ed7faSriastradh 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
898a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
899a55ed7faSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900677dec6eSriastradh /* 33 - 1920x1080@25Hz 16:9 */
901a55ed7faSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
902a55ed7faSriastradh 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
903a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
904a55ed7faSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
905677dec6eSriastradh /* 34 - 1920x1080@30Hz 16:9 */
906a55ed7faSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
907a55ed7faSriastradh 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
908a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
909a55ed7faSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910677dec6eSriastradh /* 35 - 2880x480@60Hz 4:3 */
911a55ed7faSriastradh { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
912a55ed7faSriastradh 3192, 3432, 0, 480, 489, 495, 525, 0,
913a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
914a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
915677dec6eSriastradh /* 36 - 2880x480@60Hz 16:9 */
916a55ed7faSriastradh { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
917a55ed7faSriastradh 3192, 3432, 0, 480, 489, 495, 525, 0,
918a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
919a55ed7faSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
920677dec6eSriastradh /* 37 - 2880x576@50Hz 4:3 */
921a55ed7faSriastradh { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
922a55ed7faSriastradh 3184, 3456, 0, 576, 581, 586, 625, 0,
923a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
924a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
925677dec6eSriastradh /* 38 - 2880x576@50Hz 16:9 */
926a55ed7faSriastradh { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
927a55ed7faSriastradh 3184, 3456, 0, 576, 581, 586, 625, 0,
928a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
929a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
930677dec6eSriastradh /* 39 - 1920x1080i@50Hz 16:9 */
931a55ed7faSriastradh { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
932a55ed7faSriastradh 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
933a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
934a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE),
935a55ed7faSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
936677dec6eSriastradh /* 40 - 1920x1080i@100Hz 16:9 */
937a55ed7faSriastradh { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
938a55ed7faSriastradh 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
939a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
940a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE),
941a55ed7faSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
942677dec6eSriastradh /* 41 - 1280x720@100Hz 16:9 */
943a55ed7faSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
944a55ed7faSriastradh 1760, 1980, 0, 720, 725, 730, 750, 0,
945a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
946a55ed7faSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
947677dec6eSriastradh /* 42 - 720x576@100Hz 4:3 */
948a55ed7faSriastradh { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
949a55ed7faSriastradh 796, 864, 0, 576, 581, 586, 625, 0,
950a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
951a55ed7faSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
952677dec6eSriastradh /* 43 - 720x576@100Hz 16:9 */
953a55ed7faSriastradh { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
954a55ed7faSriastradh 796, 864, 0, 576, 581, 586, 625, 0,
955a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
956a55ed7faSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
957677dec6eSriastradh /* 44 - 720(1440)x576i@100Hz 4:3 */
9584e59feabSriastradh { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
9594e59feabSriastradh 795, 864, 0, 576, 580, 586, 625, 0,
960a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
9614e59feabSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
962a55ed7faSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
963677dec6eSriastradh /* 45 - 720(1440)x576i@100Hz 16:9 */
9644e59feabSriastradh { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
9654e59feabSriastradh 795, 864, 0, 576, 580, 586, 625, 0,
966a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
9674e59feabSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
968a55ed7faSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
969677dec6eSriastradh /* 46 - 1920x1080i@120Hz 16:9 */
970a55ed7faSriastradh { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
971a55ed7faSriastradh 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
972a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
973a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE),
974a55ed7faSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
975677dec6eSriastradh /* 47 - 1280x720@120Hz 16:9 */
976a55ed7faSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
977a55ed7faSriastradh 1430, 1650, 0, 720, 725, 730, 750, 0,
978a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
979a55ed7faSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
980677dec6eSriastradh /* 48 - 720x480@120Hz 4:3 */
981a55ed7faSriastradh { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
982a55ed7faSriastradh 798, 858, 0, 480, 489, 495, 525, 0,
983a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
984a55ed7faSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
985677dec6eSriastradh /* 49 - 720x480@120Hz 16:9 */
986a55ed7faSriastradh { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
987a55ed7faSriastradh 798, 858, 0, 480, 489, 495, 525, 0,
988a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
989a55ed7faSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
990677dec6eSriastradh /* 50 - 720(1440)x480i@120Hz 4:3 */
9914e59feabSriastradh { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
9924e59feabSriastradh 801, 858, 0, 480, 488, 494, 525, 0,
993a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
994a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
995a55ed7faSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
996677dec6eSriastradh /* 51 - 720(1440)x480i@120Hz 16:9 */
9974e59feabSriastradh { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
9984e59feabSriastradh 801, 858, 0, 480, 488, 494, 525, 0,
999a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1000a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1001a55ed7faSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1002677dec6eSriastradh /* 52 - 720x576@200Hz 4:3 */
1003a55ed7faSriastradh { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1004a55ed7faSriastradh 796, 864, 0, 576, 581, 586, 625, 0,
1005a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1006a55ed7faSriastradh .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1007677dec6eSriastradh /* 53 - 720x576@200Hz 16:9 */
1008a55ed7faSriastradh { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1009a55ed7faSriastradh 796, 864, 0, 576, 581, 586, 625, 0,
1010a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1011a55ed7faSriastradh .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1012677dec6eSriastradh /* 54 - 720(1440)x576i@200Hz 4:3 */
10134e59feabSriastradh { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
10144e59feabSriastradh 795, 864, 0, 576, 580, 586, 625, 0,
1015a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1016a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1017a55ed7faSriastradh .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1018677dec6eSriastradh /* 55 - 720(1440)x576i@200Hz 16:9 */
10194e59feabSriastradh { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
10204e59feabSriastradh 795, 864, 0, 576, 580, 586, 625, 0,
1021a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1022a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1023a55ed7faSriastradh .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1024677dec6eSriastradh /* 56 - 720x480@240Hz 4:3 */
1025a55ed7faSriastradh { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1026a55ed7faSriastradh 798, 858, 0, 480, 489, 495, 525, 0,
1027a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1028a55ed7faSriastradh .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1029677dec6eSriastradh /* 57 - 720x480@240Hz 16:9 */
1030a55ed7faSriastradh { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1031a55ed7faSriastradh 798, 858, 0, 480, 489, 495, 525, 0,
1032a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1033a55ed7faSriastradh .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1034677dec6eSriastradh /* 58 - 720(1440)x480i@240Hz 4:3 */
10354e59feabSriastradh { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
10364e59feabSriastradh 801, 858, 0, 480, 488, 494, 525, 0,
1037a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1038a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1039a55ed7faSriastradh .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1040677dec6eSriastradh /* 59 - 720(1440)x480i@240Hz 16:9 */
10414e59feabSriastradh { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
10424e59feabSriastradh 801, 858, 0, 480, 488, 494, 525, 0,
1043a55ed7faSriastradh DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1044a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1045a55ed7faSriastradh .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1046677dec6eSriastradh /* 60 - 1280x720@24Hz 16:9 */
1047a55ed7faSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1048a55ed7faSriastradh 3080, 3300, 0, 720, 725, 730, 750, 0,
1049a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1050a55ed7faSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1051677dec6eSriastradh /* 61 - 1280x720@25Hz 16:9 */
1052a55ed7faSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1053a55ed7faSriastradh 3740, 3960, 0, 720, 725, 730, 750, 0,
1054a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1055a55ed7faSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1056677dec6eSriastradh /* 62 - 1280x720@30Hz 16:9 */
1057a55ed7faSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1058a55ed7faSriastradh 3080, 3300, 0, 720, 725, 730, 750, 0,
1059a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1060a55ed7faSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1061677dec6eSriastradh /* 63 - 1920x1080@120Hz 16:9 */
1062a55ed7faSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1063a55ed7faSriastradh 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1064a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065a55ed7faSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1066677dec6eSriastradh /* 64 - 1920x1080@100Hz 16:9 */
1067a55ed7faSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1068677dec6eSriastradh 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1069a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070a55ed7faSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1071677dec6eSriastradh /* 65 - 1280x720@24Hz 64:27 */
1072677dec6eSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1073677dec6eSriastradh 3080, 3300, 0, 720, 725, 730, 750, 0,
1074677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1076677dec6eSriastradh /* 66 - 1280x720@25Hz 64:27 */
1077677dec6eSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1078677dec6eSriastradh 3740, 3960, 0, 720, 725, 730, 750, 0,
1079677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1081677dec6eSriastradh /* 67 - 1280x720@30Hz 64:27 */
1082677dec6eSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1083677dec6eSriastradh 3080, 3300, 0, 720, 725, 730, 750, 0,
1084677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1086677dec6eSriastradh /* 68 - 1280x720@50Hz 64:27 */
1087677dec6eSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1088677dec6eSriastradh 1760, 1980, 0, 720, 725, 730, 750, 0,
1089677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091677dec6eSriastradh /* 69 - 1280x720@60Hz 64:27 */
1092677dec6eSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1093677dec6eSriastradh 1430, 1650, 0, 720, 725, 730, 750, 0,
1094677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096677dec6eSriastradh /* 70 - 1280x720@100Hz 64:27 */
1097677dec6eSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1098677dec6eSriastradh 1760, 1980, 0, 720, 725, 730, 750, 0,
1099677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101677dec6eSriastradh /* 71 - 1280x720@120Hz 64:27 */
1102677dec6eSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1103677dec6eSriastradh 1430, 1650, 0, 720, 725, 730, 750, 0,
1104677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106677dec6eSriastradh /* 72 - 1920x1080@24Hz 64:27 */
1107677dec6eSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1108677dec6eSriastradh 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1109677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111677dec6eSriastradh /* 73 - 1920x1080@25Hz 64:27 */
1112677dec6eSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1113677dec6eSriastradh 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1114677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116677dec6eSriastradh /* 74 - 1920x1080@30Hz 64:27 */
1117677dec6eSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1118677dec6eSriastradh 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1119677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121677dec6eSriastradh /* 75 - 1920x1080@50Hz 64:27 */
1122677dec6eSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1123677dec6eSriastradh 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1124677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126677dec6eSriastradh /* 76 - 1920x1080@60Hz 64:27 */
1127677dec6eSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1128677dec6eSriastradh 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1129677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131677dec6eSriastradh /* 77 - 1920x1080@100Hz 64:27 */
1132677dec6eSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1133677dec6eSriastradh 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1134677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136677dec6eSriastradh /* 78 - 1920x1080@120Hz 64:27 */
1137677dec6eSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1138677dec6eSriastradh 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1139677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141677dec6eSriastradh /* 79 - 1680x720@24Hz 64:27 */
1142677dec6eSriastradh { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1143677dec6eSriastradh 3080, 3300, 0, 720, 725, 730, 750, 0,
1144677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146677dec6eSriastradh /* 80 - 1680x720@25Hz 64:27 */
1147677dec6eSriastradh { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1148677dec6eSriastradh 2948, 3168, 0, 720, 725, 730, 750, 0,
1149677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151677dec6eSriastradh /* 81 - 1680x720@30Hz 64:27 */
1152677dec6eSriastradh { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1153677dec6eSriastradh 2420, 2640, 0, 720, 725, 730, 750, 0,
1154677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1156677dec6eSriastradh /* 82 - 1680x720@50Hz 64:27 */
1157677dec6eSriastradh { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1158677dec6eSriastradh 1980, 2200, 0, 720, 725, 730, 750, 0,
1159677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1161677dec6eSriastradh /* 83 - 1680x720@60Hz 64:27 */
1162677dec6eSriastradh { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1163677dec6eSriastradh 1980, 2200, 0, 720, 725, 730, 750, 0,
1164677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1166677dec6eSriastradh /* 84 - 1680x720@100Hz 64:27 */
1167677dec6eSriastradh { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1168677dec6eSriastradh 1780, 2000, 0, 720, 725, 730, 825, 0,
1169677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1171677dec6eSriastradh /* 85 - 1680x720@120Hz 64:27 */
1172677dec6eSriastradh { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1173677dec6eSriastradh 1780, 2000, 0, 720, 725, 730, 825, 0,
1174677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1176677dec6eSriastradh /* 86 - 2560x1080@24Hz 64:27 */
1177677dec6eSriastradh { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1178677dec6eSriastradh 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1179677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1181677dec6eSriastradh /* 87 - 2560x1080@25Hz 64:27 */
1182677dec6eSriastradh { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1183677dec6eSriastradh 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1184677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1186677dec6eSriastradh /* 88 - 2560x1080@30Hz 64:27 */
1187677dec6eSriastradh { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1188677dec6eSriastradh 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1189677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1191677dec6eSriastradh /* 89 - 2560x1080@50Hz 64:27 */
1192677dec6eSriastradh { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1193677dec6eSriastradh 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1194677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1196677dec6eSriastradh /* 90 - 2560x1080@60Hz 64:27 */
1197677dec6eSriastradh { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1198677dec6eSriastradh 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1199677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1201677dec6eSriastradh /* 91 - 2560x1080@100Hz 64:27 */
1202677dec6eSriastradh { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1203677dec6eSriastradh 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1204677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1206677dec6eSriastradh /* 92 - 2560x1080@120Hz 64:27 */
1207677dec6eSriastradh { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1208677dec6eSriastradh 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1209677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1211677dec6eSriastradh /* 93 - 3840x2160@24Hz 16:9 */
1212677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1213677dec6eSriastradh 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1214677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1216677dec6eSriastradh /* 94 - 3840x2160@25Hz 16:9 */
1217677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1218677dec6eSriastradh 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1219677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1221677dec6eSriastradh /* 95 - 3840x2160@30Hz 16:9 */
1222677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1223677dec6eSriastradh 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1224677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1226677dec6eSriastradh /* 96 - 3840x2160@50Hz 16:9 */
1227677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1228677dec6eSriastradh 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1229677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1230677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1231677dec6eSriastradh /* 97 - 3840x2160@60Hz 16:9 */
1232677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1233677dec6eSriastradh 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1234677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1235677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1236677dec6eSriastradh /* 98 - 4096x2160@24Hz 256:135 */
1237677dec6eSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1238677dec6eSriastradh 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1239677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1241677dec6eSriastradh /* 99 - 4096x2160@25Hz 256:135 */
1242677dec6eSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1243677dec6eSriastradh 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1244677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1246677dec6eSriastradh /* 100 - 4096x2160@30Hz 256:135 */
1247677dec6eSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1248677dec6eSriastradh 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1249677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1251677dec6eSriastradh /* 101 - 4096x2160@50Hz 256:135 */
1252677dec6eSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1253677dec6eSriastradh 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1254677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1256677dec6eSriastradh /* 102 - 4096x2160@60Hz 256:135 */
1257677dec6eSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1258677dec6eSriastradh 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1259677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1261677dec6eSriastradh /* 103 - 3840x2160@24Hz 64:27 */
1262677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1263677dec6eSriastradh 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1264677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1266677dec6eSriastradh /* 104 - 3840x2160@25Hz 64:27 */
1267677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1268677dec6eSriastradh 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1269677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1271677dec6eSriastradh /* 105 - 3840x2160@30Hz 64:27 */
1272677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1273677dec6eSriastradh 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1274677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1276677dec6eSriastradh /* 106 - 3840x2160@50Hz 64:27 */
1277677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1278677dec6eSriastradh 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1279677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1281677dec6eSriastradh /* 107 - 3840x2160@60Hz 64:27 */
1282677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1283677dec6eSriastradh 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1284677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1285677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1286677dec6eSriastradh /* 108 - 1280x720@48Hz 16:9 */
1287677dec6eSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1288677dec6eSriastradh 2280, 2500, 0, 720, 725, 730, 750, 0,
1289677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1290677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1291677dec6eSriastradh /* 109 - 1280x720@48Hz 64:27 */
1292677dec6eSriastradh { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1293677dec6eSriastradh 2280, 2500, 0, 720, 725, 730, 750, 0,
1294677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1295677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1296677dec6eSriastradh /* 110 - 1680x720@48Hz 64:27 */
1297677dec6eSriastradh { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1298677dec6eSriastradh 2530, 2750, 0, 720, 725, 730, 750, 0,
1299677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1301677dec6eSriastradh /* 111 - 1920x1080@48Hz 16:9 */
1302677dec6eSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1303677dec6eSriastradh 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1304677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1305677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1306677dec6eSriastradh /* 112 - 1920x1080@48Hz 64:27 */
1307677dec6eSriastradh { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1308677dec6eSriastradh 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1309677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1310677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1311677dec6eSriastradh /* 113 - 2560x1080@48Hz 64:27 */
1312677dec6eSriastradh { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1313677dec6eSriastradh 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1314677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1315677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1316677dec6eSriastradh /* 114 - 3840x2160@48Hz 16:9 */
1317677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1318677dec6eSriastradh 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1319677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1320677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1321677dec6eSriastradh /* 115 - 4096x2160@48Hz 256:135 */
1322677dec6eSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1323677dec6eSriastradh 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1324677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1325677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1326677dec6eSriastradh /* 116 - 3840x2160@48Hz 64:27 */
1327677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1328677dec6eSriastradh 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1329677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1330677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1331677dec6eSriastradh /* 117 - 3840x2160@100Hz 16:9 */
1332677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1333677dec6eSriastradh 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1334677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1335677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1336677dec6eSriastradh /* 118 - 3840x2160@120Hz 16:9 */
1337677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1338677dec6eSriastradh 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1339677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1340677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1341677dec6eSriastradh /* 119 - 3840x2160@100Hz 64:27 */
1342677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1343677dec6eSriastradh 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1344677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1345677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1346677dec6eSriastradh /* 120 - 3840x2160@120Hz 64:27 */
1347677dec6eSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1348677dec6eSriastradh 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1349677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1350677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1351677dec6eSriastradh /* 121 - 5120x2160@24Hz 64:27 */
1352677dec6eSriastradh { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1353677dec6eSriastradh 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1354677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1355677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1356677dec6eSriastradh /* 122 - 5120x2160@25Hz 64:27 */
1357677dec6eSriastradh { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1358677dec6eSriastradh 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1359677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1360677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1361677dec6eSriastradh /* 123 - 5120x2160@30Hz 64:27 */
1362677dec6eSriastradh { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1363677dec6eSriastradh 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1364677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1365677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1366677dec6eSriastradh /* 124 - 5120x2160@48Hz 64:27 */
1367677dec6eSriastradh { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1368677dec6eSriastradh 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1369677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1370677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1371677dec6eSriastradh /* 125 - 5120x2160@50Hz 64:27 */
1372677dec6eSriastradh { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1373677dec6eSriastradh 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1374677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1375677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1376677dec6eSriastradh /* 126 - 5120x2160@60Hz 64:27 */
1377677dec6eSriastradh { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1378677dec6eSriastradh 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1379677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1380677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1381677dec6eSriastradh /* 127 - 5120x2160@100Hz 64:27 */
1382677dec6eSriastradh { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1383677dec6eSriastradh 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1384677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1385677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1386a55ed7faSriastradh };
1387a55ed7faSriastradh
1388a55ed7faSriastradh /*
1389677dec6eSriastradh * From CEA/CTA-861 spec.
1390677dec6eSriastradh *
1391677dec6eSriastradh * Do not access directly, instead always use cea_mode_for_vic().
1392677dec6eSriastradh */
1393677dec6eSriastradh static const struct drm_display_mode edid_cea_modes_193[] = {
1394677dec6eSriastradh /* 193 - 5120x2160@120Hz 64:27 */
1395677dec6eSriastradh { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1396677dec6eSriastradh 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1397677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1398677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1399677dec6eSriastradh /* 194 - 7680x4320@24Hz 16:9 */
1400677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1401677dec6eSriastradh 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1402677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1403677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1404677dec6eSriastradh /* 195 - 7680x4320@25Hz 16:9 */
1405677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1406677dec6eSriastradh 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1407677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1408677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1409677dec6eSriastradh /* 196 - 7680x4320@30Hz 16:9 */
1410677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1411677dec6eSriastradh 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1412677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1413677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1414677dec6eSriastradh /* 197 - 7680x4320@48Hz 16:9 */
1415677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1416677dec6eSriastradh 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1417677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1418677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1419677dec6eSriastradh /* 198 - 7680x4320@50Hz 16:9 */
1420677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1421677dec6eSriastradh 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1422677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1423677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1424677dec6eSriastradh /* 199 - 7680x4320@60Hz 16:9 */
1425677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1426677dec6eSriastradh 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1427677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1428677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1429677dec6eSriastradh /* 200 - 7680x4320@100Hz 16:9 */
1430677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1431677dec6eSriastradh 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1432677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1433677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1434677dec6eSriastradh /* 201 - 7680x4320@120Hz 16:9 */
1435677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1436677dec6eSriastradh 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1437677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1438677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1439677dec6eSriastradh /* 202 - 7680x4320@24Hz 64:27 */
1440677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1441677dec6eSriastradh 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1442677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1443677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1444677dec6eSriastradh /* 203 - 7680x4320@25Hz 64:27 */
1445677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1446677dec6eSriastradh 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1447677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1448677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1449677dec6eSriastradh /* 204 - 7680x4320@30Hz 64:27 */
1450677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1451677dec6eSriastradh 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1452677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1453677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1454677dec6eSriastradh /* 205 - 7680x4320@48Hz 64:27 */
1455677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1456677dec6eSriastradh 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1457677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1458677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1459677dec6eSriastradh /* 206 - 7680x4320@50Hz 64:27 */
1460677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1461677dec6eSriastradh 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1462677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1463677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1464677dec6eSriastradh /* 207 - 7680x4320@60Hz 64:27 */
1465677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1466677dec6eSriastradh 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1467677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1468677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1469677dec6eSriastradh /* 208 - 7680x4320@100Hz 64:27 */
1470677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1471677dec6eSriastradh 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1472677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1473677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1474677dec6eSriastradh /* 209 - 7680x4320@120Hz 64:27 */
1475677dec6eSriastradh { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1476677dec6eSriastradh 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1477677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1478677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1479677dec6eSriastradh /* 210 - 10240x4320@24Hz 64:27 */
1480677dec6eSriastradh { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1481677dec6eSriastradh 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1482677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1483677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1484677dec6eSriastradh /* 211 - 10240x4320@25Hz 64:27 */
1485677dec6eSriastradh { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1486677dec6eSriastradh 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1487677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1488677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1489677dec6eSriastradh /* 212 - 10240x4320@30Hz 64:27 */
1490677dec6eSriastradh { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1491677dec6eSriastradh 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1492677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1493677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1494677dec6eSriastradh /* 213 - 10240x4320@48Hz 64:27 */
1495677dec6eSriastradh { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1496677dec6eSriastradh 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1497677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1498677dec6eSriastradh .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1499677dec6eSriastradh /* 214 - 10240x4320@50Hz 64:27 */
1500677dec6eSriastradh { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1501677dec6eSriastradh 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1502677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1503677dec6eSriastradh .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1504677dec6eSriastradh /* 215 - 10240x4320@60Hz 64:27 */
1505677dec6eSriastradh { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1506677dec6eSriastradh 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1507677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1508677dec6eSriastradh .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1509677dec6eSriastradh /* 216 - 10240x4320@100Hz 64:27 */
1510677dec6eSriastradh { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1511677dec6eSriastradh 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1512677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1513677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1514677dec6eSriastradh /* 217 - 10240x4320@120Hz 64:27 */
1515677dec6eSriastradh { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1516677dec6eSriastradh 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1517677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1518677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1519677dec6eSriastradh /* 218 - 4096x2160@100Hz 256:135 */
1520677dec6eSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1521677dec6eSriastradh 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1522677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1523677dec6eSriastradh .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1524677dec6eSriastradh /* 219 - 4096x2160@120Hz 256:135 */
1525677dec6eSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1526677dec6eSriastradh 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1527677dec6eSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1528677dec6eSriastradh .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1529677dec6eSriastradh };
1530677dec6eSriastradh
1531677dec6eSriastradh /*
1532677dec6eSriastradh * HDMI 1.4 4k modes. Index using the VIC.
1533a55ed7faSriastradh */
1534a55ed7faSriastradh static const struct drm_display_mode edid_4k_modes[] = {
1535677dec6eSriastradh /* 0 - dummy, VICs start at 1 */
1536677dec6eSriastradh { },
1537a55ed7faSriastradh /* 1 - 3840x2160@30Hz */
1538a55ed7faSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1539a55ed7faSriastradh 3840, 4016, 4104, 4400, 0,
1540a55ed7faSriastradh 2160, 2168, 2178, 2250, 0,
1541a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1542677dec6eSriastradh .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1543a55ed7faSriastradh /* 2 - 3840x2160@25Hz */
1544a55ed7faSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1545a55ed7faSriastradh 3840, 4896, 4984, 5280, 0,
1546a55ed7faSriastradh 2160, 2168, 2178, 2250, 0,
1547a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1548677dec6eSriastradh .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1549a55ed7faSriastradh /* 3 - 3840x2160@24Hz */
1550a55ed7faSriastradh { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551a55ed7faSriastradh 3840, 5116, 5204, 5500, 0,
1552a55ed7faSriastradh 2160, 2168, 2178, 2250, 0,
1553a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1554677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1555a55ed7faSriastradh /* 4 - 4096x2160@24Hz (SMPTE) */
1556a55ed7faSriastradh { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1557a55ed7faSriastradh 4096, 5116, 5204, 5500, 0,
1558a55ed7faSriastradh 2160, 2168, 2178, 2250, 0,
1559a55ed7faSriastradh DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1560677dec6eSriastradh .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
156156053ce7Sriastradh };
156256053ce7Sriastradh
156356053ce7Sriastradh /*** DDC fetch and block validation ***/
156456053ce7Sriastradh
156556053ce7Sriastradh static const u8 edid_header[] = {
156656053ce7Sriastradh 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
156756053ce7Sriastradh };
156856053ce7Sriastradh
15694e59feabSriastradh /**
15704e59feabSriastradh * drm_edid_header_is_valid - sanity check the header of the base EDID block
15714e59feabSriastradh * @raw_edid: pointer to raw base EDID block
15724e59feabSriastradh *
15734e59feabSriastradh * Sanity check the header of the base EDID block.
15744e59feabSriastradh *
15754e59feabSriastradh * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
157656053ce7Sriastradh */
drm_edid_header_is_valid(const u8 * raw_edid)157756053ce7Sriastradh int drm_edid_header_is_valid(const u8 *raw_edid)
157856053ce7Sriastradh {
157956053ce7Sriastradh int i, score = 0;
158056053ce7Sriastradh
158156053ce7Sriastradh for (i = 0; i < sizeof(edid_header); i++)
158256053ce7Sriastradh if (raw_edid[i] == edid_header[i])
158356053ce7Sriastradh score++;
158456053ce7Sriastradh
158556053ce7Sriastradh return score;
158656053ce7Sriastradh }
158756053ce7Sriastradh EXPORT_SYMBOL(drm_edid_header_is_valid);
158856053ce7Sriastradh
158956053ce7Sriastradh static int edid_fixup __read_mostly = 6;
159056053ce7Sriastradh module_param_named(edid_fixup, edid_fixup, int, 0400);
159156053ce7Sriastradh MODULE_PARM_DESC(edid_fixup,
159256053ce7Sriastradh "Minimum number of valid EDID header bytes (0-8, default 6)");
159356053ce7Sriastradh
15944e59feabSriastradh static void drm_get_displayid(struct drm_connector *connector,
15954e59feabSriastradh struct edid *edid);
159657b58161Sriastradh static int validate_displayid(const u8 *displayid, int length, int idx);
15974e59feabSriastradh
drm_edid_block_checksum(const u8 * raw_edid)15984e59feabSriastradh static int drm_edid_block_checksum(const u8 *raw_edid)
159956053ce7Sriastradh {
160056053ce7Sriastradh int i;
160156053ce7Sriastradh u8 csum = 0;
16024e59feabSriastradh for (i = 0; i < EDID_LENGTH; i++)
16034e59feabSriastradh csum += raw_edid[i];
16044e59feabSriastradh
16054e59feabSriastradh return csum;
16064e59feabSriastradh }
16074e59feabSriastradh
drm_edid_is_zero(const u8 * in_edid,int length)16084e59feabSriastradh static bool drm_edid_is_zero(const u8 *in_edid, int length)
16094e59feabSriastradh {
16104e59feabSriastradh if (memchr_inv(in_edid, 0, length))
16114e59feabSriastradh return false;
16124e59feabSriastradh
16134e59feabSriastradh return true;
16144e59feabSriastradh }
16154e59feabSriastradh
16164e59feabSriastradh /**
16174e59feabSriastradh * drm_edid_block_valid - Sanity check the EDID block (base or extension)
16184e59feabSriastradh * @raw_edid: pointer to raw EDID block
16194e59feabSriastradh * @block: type of block to validate (0 for base, extension otherwise)
16204e59feabSriastradh * @print_bad_edid: if true, dump bad EDID blocks to the console
16214e59feabSriastradh * @edid_corrupt: if true, the header or checksum is invalid
16224e59feabSriastradh *
16234e59feabSriastradh * Validate a base or extension EDID block and optionally dump bad blocks to
16244e59feabSriastradh * the console.
16254e59feabSriastradh *
16264e59feabSriastradh * Return: True if the block is valid, false otherwise.
16274e59feabSriastradh */
drm_edid_block_valid(u8 * raw_edid,int block,bool print_bad_edid,bool * edid_corrupt)16284e59feabSriastradh bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
16294e59feabSriastradh bool *edid_corrupt)
16304e59feabSriastradh {
16314e59feabSriastradh u8 csum;
163256053ce7Sriastradh struct edid *edid = (struct edid *)raw_edid;
163356053ce7Sriastradh
1634a55ed7faSriastradh if (WARN_ON(!raw_edid))
1635a55ed7faSriastradh return false;
1636a55ed7faSriastradh
163756053ce7Sriastradh if (edid_fixup > 8 || edid_fixup < 0)
163856053ce7Sriastradh edid_fixup = 6;
163956053ce7Sriastradh
164056053ce7Sriastradh if (block == 0) {
164156053ce7Sriastradh int score = drm_edid_header_is_valid(raw_edid);
16424e59feabSriastradh if (score == 8) {
16434e59feabSriastradh if (edid_corrupt)
16444e59feabSriastradh *edid_corrupt = false;
16454e59feabSriastradh } else if (score >= edid_fixup) {
16464e59feabSriastradh /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
16474e59feabSriastradh * The corrupt flag needs to be set here otherwise, the
16484e59feabSriastradh * fix-up code here will correct the problem, the
16494e59feabSriastradh * checksum is correct and the test fails
16504e59feabSriastradh */
16514e59feabSriastradh if (edid_corrupt)
16524e59feabSriastradh *edid_corrupt = true;
165356053ce7Sriastradh DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
165456053ce7Sriastradh memcpy(raw_edid, edid_header, sizeof(edid_header));
165556053ce7Sriastradh } else {
16564e59feabSriastradh if (edid_corrupt)
16574e59feabSriastradh *edid_corrupt = true;
165856053ce7Sriastradh goto bad;
165956053ce7Sriastradh }
166056053ce7Sriastradh }
166156053ce7Sriastradh
16624e59feabSriastradh csum = drm_edid_block_checksum(raw_edid);
166356053ce7Sriastradh if (csum) {
16644e59feabSriastradh if (edid_corrupt)
16654e59feabSriastradh *edid_corrupt = true;
16664e59feabSriastradh
166756053ce7Sriastradh /* allow CEA to slide through, switches mangle this */
1668677dec6eSriastradh if (raw_edid[0] == CEA_EXT) {
1669677dec6eSriastradh DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1670677dec6eSriastradh DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1671677dec6eSriastradh } else {
1672677dec6eSriastradh if (print_bad_edid)
1673677dec6eSriastradh DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1674677dec6eSriastradh
167556053ce7Sriastradh goto bad;
167656053ce7Sriastradh }
1677677dec6eSriastradh }
167856053ce7Sriastradh
167956053ce7Sriastradh /* per-block-type checks */
168056053ce7Sriastradh switch (raw_edid[0]) {
168156053ce7Sriastradh case 0: /* base */
168256053ce7Sriastradh if (edid->version != 1) {
1683677dec6eSriastradh DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
168456053ce7Sriastradh goto bad;
168556053ce7Sriastradh }
168656053ce7Sriastradh
168756053ce7Sriastradh if (edid->revision > 4)
168856053ce7Sriastradh DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
168956053ce7Sriastradh break;
169056053ce7Sriastradh
169156053ce7Sriastradh default:
169256053ce7Sriastradh break;
169356053ce7Sriastradh }
169456053ce7Sriastradh
1695a55ed7faSriastradh return true;
169656053ce7Sriastradh
169756053ce7Sriastradh bad:
1698a55ed7faSriastradh if (print_bad_edid) {
16994e59feabSriastradh if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1700677dec6eSriastradh pr_notice("EDID block is all zeroes\n");
17014e59feabSriastradh } else {
1702677dec6eSriastradh pr_notice("Raw EDID:\n");
1703677dec6eSriastradh print_hex_dump(KERN_NOTICE,
1704677dec6eSriastradh " \t", DUMP_PREFIX_NONE, 16, 1,
170556053ce7Sriastradh raw_edid, EDID_LENGTH, false);
170656053ce7Sriastradh }
17074e59feabSriastradh }
1708a55ed7faSriastradh return false;
170956053ce7Sriastradh }
171056053ce7Sriastradh EXPORT_SYMBOL(drm_edid_block_valid);
171156053ce7Sriastradh
171256053ce7Sriastradh /**
171356053ce7Sriastradh * drm_edid_is_valid - sanity check EDID data
171456053ce7Sriastradh * @edid: EDID data
171556053ce7Sriastradh *
171656053ce7Sriastradh * Sanity-check an entire EDID record (including extensions)
17174e59feabSriastradh *
17184e59feabSriastradh * Return: True if the EDID data is valid, false otherwise.
171956053ce7Sriastradh */
drm_edid_is_valid(struct edid * edid)172056053ce7Sriastradh bool drm_edid_is_valid(struct edid *edid)
172156053ce7Sriastradh {
172256053ce7Sriastradh int i;
172356053ce7Sriastradh u8 *raw = (u8 *)edid;
172456053ce7Sriastradh
172556053ce7Sriastradh if (!edid)
172656053ce7Sriastradh return false;
172756053ce7Sriastradh
172856053ce7Sriastradh for (i = 0; i <= edid->extensions; i++)
17294e59feabSriastradh if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
173056053ce7Sriastradh return false;
173156053ce7Sriastradh
173256053ce7Sriastradh return true;
173356053ce7Sriastradh }
173456053ce7Sriastradh EXPORT_SYMBOL(drm_edid_is_valid);
173556053ce7Sriastradh
173656053ce7Sriastradh #define DDC_SEGMENT_ADDR 0x30
173756053ce7Sriastradh /**
17384e59feabSriastradh * drm_do_probe_ddc_edid() - get EDID information via I2C
17394e59feabSriastradh * @data: I2C device adapter
1740a55ed7faSriastradh * @buf: EDID data buffer to be filled
1741a55ed7faSriastradh * @block: 128 byte EDID block to start fetching from
1742a55ed7faSriastradh * @len: EDID data buffer length to fetch
1743a55ed7faSriastradh *
17444e59feabSriastradh * Try to fetch EDID information by calling I2C driver functions.
1745a55ed7faSriastradh *
17464e59feabSriastradh * Return: 0 on success or -1 on failure.
174756053ce7Sriastradh */
174856053ce7Sriastradh static int
drm_do_probe_ddc_edid(void * data,u8 * buf,unsigned int block,size_t len)17494e59feabSriastradh drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
175056053ce7Sriastradh {
17514e59feabSriastradh struct i2c_adapter *adapter = data;
175256053ce7Sriastradh unsigned char start = block * EDID_LENGTH;
175356053ce7Sriastradh unsigned char segment = block >> 1;
175456053ce7Sriastradh unsigned char xfers = segment ? 3 : 2;
175556053ce7Sriastradh int ret, retries = 5;
175656053ce7Sriastradh
17574e59feabSriastradh /*
17584e59feabSriastradh * The core I2C driver will automatically retry the transfer if the
175956053ce7Sriastradh * adapter reports EAGAIN. However, we find that bit-banging transfers
176056053ce7Sriastradh * are susceptible to errors under a heavily loaded machine and
176156053ce7Sriastradh * generate spurious NAKs and timeouts. Retrying the transfer
176256053ce7Sriastradh * of the individual block a few times seems to overcome this.
176356053ce7Sriastradh */
176456053ce7Sriastradh do {
176556053ce7Sriastradh struct i2c_msg msgs[] = {
176656053ce7Sriastradh {
176756053ce7Sriastradh .addr = DDC_SEGMENT_ADDR,
176856053ce7Sriastradh .flags = 0,
176956053ce7Sriastradh .len = 1,
177056053ce7Sriastradh .buf = &segment,
177156053ce7Sriastradh }, {
177256053ce7Sriastradh .addr = DDC_ADDR,
177356053ce7Sriastradh .flags = 0,
177456053ce7Sriastradh .len = 1,
177556053ce7Sriastradh .buf = &start,
177656053ce7Sriastradh }, {
177756053ce7Sriastradh .addr = DDC_ADDR,
177856053ce7Sriastradh .flags = I2C_M_RD,
177956053ce7Sriastradh .len = len,
178056053ce7Sriastradh .buf = buf,
178156053ce7Sriastradh }
178256053ce7Sriastradh };
178356053ce7Sriastradh
178456053ce7Sriastradh /*
17854e59feabSriastradh * Avoid sending the segment addr to not upset non-compliant
17864e59feabSriastradh * DDC monitors.
178756053ce7Sriastradh */
178856053ce7Sriastradh ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
178956053ce7Sriastradh
179056053ce7Sriastradh if (ret == -ENXIO) {
179156053ce7Sriastradh DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
179256053ce7Sriastradh adapter->name);
179356053ce7Sriastradh break;
179456053ce7Sriastradh }
179556053ce7Sriastradh } while (ret != xfers && --retries);
179656053ce7Sriastradh
179756053ce7Sriastradh return ret == xfers ? 0 : -1;
179856053ce7Sriastradh }
179956053ce7Sriastradh
connector_bad_edid(struct drm_connector * connector,u8 * edid,int num_blocks)1800677dec6eSriastradh static void connector_bad_edid(struct drm_connector *connector,
1801677dec6eSriastradh u8 *edid, int num_blocks)
1802677dec6eSriastradh {
1803677dec6eSriastradh int i;
1804677dec6eSriastradh
1805677dec6eSriastradh if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1806677dec6eSriastradh return;
1807677dec6eSriastradh
1808677dec6eSriastradh dev_warn(connector->dev->dev,
1809677dec6eSriastradh "%s: EDID is invalid:\n",
1810677dec6eSriastradh connector->name);
1811677dec6eSriastradh for (i = 0; i < num_blocks; i++) {
1812677dec6eSriastradh u8 *block = edid + i * EDID_LENGTH;
1813677dec6eSriastradh char prefix[20];
1814677dec6eSriastradh
1815677dec6eSriastradh if (drm_edid_is_zero(block, EDID_LENGTH))
18168e465d8aSriastradh snprintf(prefix, sizeof prefix, "\t[%02x] ZERO ", i);
1817677dec6eSriastradh else if (!drm_edid_block_valid(block, i, false, NULL))
18188e465d8aSriastradh snprintf(prefix, sizeof prefix, "\t[%02x] BAD ", i);
1819677dec6eSriastradh else
18208e465d8aSriastradh snprintf(prefix, sizeof prefix, "\t[%02x] GOOD ", i);
1821677dec6eSriastradh
1822677dec6eSriastradh print_hex_dump(KERN_WARNING,
1823677dec6eSriastradh prefix, DUMP_PREFIX_NONE, 16, 1,
1824677dec6eSriastradh block, EDID_LENGTH, false);
1825677dec6eSriastradh }
1826677dec6eSriastradh }
1827677dec6eSriastradh
1828677dec6eSriastradh /* Get override or firmware EDID */
drm_get_override_edid(struct drm_connector * connector)1829677dec6eSriastradh static struct edid *drm_get_override_edid(struct drm_connector *connector)
1830677dec6eSriastradh {
1831677dec6eSriastradh struct edid *override = NULL;
1832677dec6eSriastradh
1833677dec6eSriastradh if (connector->override_edid)
1834677dec6eSriastradh override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1835677dec6eSriastradh
1836677dec6eSriastradh if (!override)
1837677dec6eSriastradh override = drm_load_edid_firmware(connector);
1838677dec6eSriastradh
1839677dec6eSriastradh return IS_ERR(override) ? NULL : override;
1840677dec6eSriastradh }
1841677dec6eSriastradh
1842677dec6eSriastradh /**
1843677dec6eSriastradh * drm_add_override_edid_modes - add modes from override/firmware EDID
1844677dec6eSriastradh * @connector: connector we're probing
1845677dec6eSriastradh *
1846677dec6eSriastradh * Add modes from the override/firmware EDID, if available. Only to be used from
1847677dec6eSriastradh * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1848677dec6eSriastradh * failed during drm_get_edid() and caused the override/firmware EDID to be
1849677dec6eSriastradh * skipped.
1850677dec6eSriastradh *
1851677dec6eSriastradh * Return: The number of modes added or 0 if we couldn't find any.
1852677dec6eSriastradh */
drm_add_override_edid_modes(struct drm_connector * connector)1853677dec6eSriastradh int drm_add_override_edid_modes(struct drm_connector *connector)
1854677dec6eSriastradh {
1855677dec6eSriastradh struct edid *override;
1856677dec6eSriastradh int num_modes = 0;
1857677dec6eSriastradh
1858677dec6eSriastradh override = drm_get_override_edid(connector);
1859677dec6eSriastradh if (override) {
1860677dec6eSriastradh drm_connector_update_edid_property(connector, override);
1861677dec6eSriastradh num_modes = drm_add_edid_modes(connector, override);
1862677dec6eSriastradh kfree(override);
1863677dec6eSriastradh
1864677dec6eSriastradh DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1865677dec6eSriastradh connector->base.id, connector->name, num_modes);
1866677dec6eSriastradh }
1867677dec6eSriastradh
1868677dec6eSriastradh return num_modes;
1869677dec6eSriastradh }
1870677dec6eSriastradh EXPORT_SYMBOL(drm_add_override_edid_modes);
1871677dec6eSriastradh
18724e59feabSriastradh /**
18734e59feabSriastradh * drm_do_get_edid - get EDID data using a custom EDID block read function
18744e59feabSriastradh * @connector: connector we're probing
18754e59feabSriastradh * @get_edid_block: EDID block read function
18764e59feabSriastradh * @data: private data passed to the block read function
18774e59feabSriastradh *
18784e59feabSriastradh * When the I2C adapter connected to the DDC bus is hidden behind a device that
18794e59feabSriastradh * exposes a different interface to read EDID blocks this function can be used
18804e59feabSriastradh * to get EDID data using a custom block read function.
18814e59feabSriastradh *
18824e59feabSriastradh * As in the general case the DDC bus is accessible by the kernel at the I2C
18834e59feabSriastradh * level, drivers must make all reasonable efforts to expose it as an I2C
18844e59feabSriastradh * adapter and use drm_get_edid() instead of abusing this function.
18854e59feabSriastradh *
1886677dec6eSriastradh * The EDID may be overridden using debugfs override_edid or firmare EDID
1887677dec6eSriastradh * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1888677dec6eSriastradh * order. Having either of them bypasses actual EDID reads.
1889677dec6eSriastradh *
18904e59feabSriastradh * Return: Pointer to valid EDID or NULL if we couldn't find any.
18914e59feabSriastradh */
drm_do_get_edid(struct drm_connector * connector,int (* get_edid_block)(void * data,u8 * buf,unsigned int block,size_t len),void * data)18924e59feabSriastradh struct edid *drm_do_get_edid(struct drm_connector *connector,
18934e59feabSriastradh int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
18944e59feabSriastradh size_t len),
18954e59feabSriastradh void *data)
189656053ce7Sriastradh {
189756053ce7Sriastradh int i, j = 0, valid_extensions = 0;
1898677dec6eSriastradh u8 *edid, *new;
1899677dec6eSriastradh struct edid *override;
190056053ce7Sriastradh
1901677dec6eSriastradh override = drm_get_override_edid(connector);
1902677dec6eSriastradh if (override)
1903677dec6eSriastradh return override;
1904677dec6eSriastradh
1905677dec6eSriastradh if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
190656053ce7Sriastradh return NULL;
190756053ce7Sriastradh
190856053ce7Sriastradh /* base block fetch */
190956053ce7Sriastradh for (i = 0; i < 4; i++) {
1910677dec6eSriastradh if (get_edid_block(data, edid, 0, EDID_LENGTH))
191156053ce7Sriastradh goto out;
1912677dec6eSriastradh if (drm_edid_block_valid(edid, 0, false,
19134e59feabSriastradh &connector->edid_corrupt))
191456053ce7Sriastradh break;
1915677dec6eSriastradh if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
191656053ce7Sriastradh connector->null_edid_counter++;
191756053ce7Sriastradh goto carp;
191856053ce7Sriastradh }
191956053ce7Sriastradh }
192056053ce7Sriastradh if (i == 4)
192156053ce7Sriastradh goto carp;
192256053ce7Sriastradh
192356053ce7Sriastradh /* if there's no extensions, we're done */
1924677dec6eSriastradh valid_extensions = edid[0x7e];
1925677dec6eSriastradh if (valid_extensions == 0)
1926677dec6eSriastradh return (struct edid *)edid;
192756053ce7Sriastradh
1928677dec6eSriastradh new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
192956053ce7Sriastradh if (!new)
193056053ce7Sriastradh goto out;
1931677dec6eSriastradh edid = new;
193256053ce7Sriastradh
1933677dec6eSriastradh for (j = 1; j <= edid[0x7e]; j++) {
1934677dec6eSriastradh u8 *block = edid + j * EDID_LENGTH;
1935677dec6eSriastradh
193656053ce7Sriastradh for (i = 0; i < 4; i++) {
1937677dec6eSriastradh if (get_edid_block(data, block, j, EDID_LENGTH))
193856053ce7Sriastradh goto out;
1939677dec6eSriastradh if (drm_edid_block_valid(block, j, false, NULL))
194056053ce7Sriastradh break;
194156053ce7Sriastradh }
1942677dec6eSriastradh
1943677dec6eSriastradh if (i == 4)
1944677dec6eSriastradh valid_extensions--;
194556053ce7Sriastradh }
1946a55ed7faSriastradh
1947677dec6eSriastradh if (valid_extensions != edid[0x7e]) {
1948677dec6eSriastradh u8 *base;
1949a55ed7faSriastradh
1950677dec6eSriastradh connector_bad_edid(connector, edid, edid[0x7e] + 1);
195156053ce7Sriastradh
1952677dec6eSriastradh edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1953677dec6eSriastradh edid[0x7e] = valid_extensions;
1954677dec6eSriastradh
1955677dec6eSriastradh new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1956677dec6eSriastradh GFP_KERNEL);
195756053ce7Sriastradh if (!new)
195856053ce7Sriastradh goto out;
1959677dec6eSriastradh
1960677dec6eSriastradh base = new;
1961677dec6eSriastradh for (i = 0; i <= edid[0x7e]; i++) {
1962677dec6eSriastradh u8 *block = edid + i * EDID_LENGTH;
1963677dec6eSriastradh
1964677dec6eSriastradh if (!drm_edid_block_valid(block, i, false, NULL))
1965677dec6eSriastradh continue;
1966677dec6eSriastradh
1967677dec6eSriastradh memcpy(base, block, EDID_LENGTH);
1968677dec6eSriastradh base += EDID_LENGTH;
196956053ce7Sriastradh }
197056053ce7Sriastradh
1971677dec6eSriastradh kfree(edid);
1972677dec6eSriastradh edid = new;
1973677dec6eSriastradh }
1974677dec6eSriastradh
1975677dec6eSriastradh return (struct edid *)edid;
197656053ce7Sriastradh
197756053ce7Sriastradh carp:
1978677dec6eSriastradh connector_bad_edid(connector, edid, 1);
197956053ce7Sriastradh out:
1980677dec6eSriastradh kfree(edid);
198156053ce7Sriastradh return NULL;
198256053ce7Sriastradh }
19834e59feabSriastradh EXPORT_SYMBOL_GPL(drm_do_get_edid);
198456053ce7Sriastradh
198556053ce7Sriastradh /**
19864e59feabSriastradh * drm_probe_ddc() - probe DDC presence
19874e59feabSriastradh * @adapter: I2C adapter to probe
198856053ce7Sriastradh *
19894e59feabSriastradh * Return: True on success, false on failure.
199056053ce7Sriastradh */
199156053ce7Sriastradh bool
drm_probe_ddc(struct i2c_adapter * adapter)199256053ce7Sriastradh drm_probe_ddc(struct i2c_adapter *adapter)
199356053ce7Sriastradh {
199456053ce7Sriastradh unsigned char out;
199556053ce7Sriastradh
199656053ce7Sriastradh return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
199756053ce7Sriastradh }
199856053ce7Sriastradh EXPORT_SYMBOL(drm_probe_ddc);
199956053ce7Sriastradh
200056053ce7Sriastradh /**
200156053ce7Sriastradh * drm_get_edid - get EDID data, if available
200256053ce7Sriastradh * @connector: connector we're probing
20034e59feabSriastradh * @adapter: I2C adapter to use for DDC
200456053ce7Sriastradh *
20054e59feabSriastradh * Poke the given I2C channel to grab EDID data if possible. If found,
200656053ce7Sriastradh * attach it to the connector.
200756053ce7Sriastradh *
20084e59feabSriastradh * Return: Pointer to valid EDID or NULL if we couldn't find any.
200956053ce7Sriastradh */
drm_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)201056053ce7Sriastradh struct edid *drm_get_edid(struct drm_connector *connector,
201156053ce7Sriastradh struct i2c_adapter *adapter)
201256053ce7Sriastradh {
20134e59feabSriastradh struct edid *edid;
201456053ce7Sriastradh
2015677dec6eSriastradh if (connector->force == DRM_FORCE_OFF)
2016677dec6eSriastradh return NULL;
2017677dec6eSriastradh
2018677dec6eSriastradh if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
20194e59feabSriastradh return NULL;
202056053ce7Sriastradh
20214e59feabSriastradh edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
20224e59feabSriastradh if (edid)
20234e59feabSriastradh drm_get_displayid(connector, edid);
202456053ce7Sriastradh return edid;
202556053ce7Sriastradh }
202656053ce7Sriastradh EXPORT_SYMBOL(drm_get_edid);
202756053ce7Sriastradh
2028a55ed7faSriastradh /**
2029677dec6eSriastradh * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2030677dec6eSriastradh * @connector: connector we're probing
2031677dec6eSriastradh * @adapter: I2C adapter to use for DDC
2032677dec6eSriastradh *
2033677dec6eSriastradh * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2034677dec6eSriastradh * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2035677dec6eSriastradh * switch DDC to the GPU which is retrieving EDID.
2036677dec6eSriastradh *
2037677dec6eSriastradh * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2038677dec6eSriastradh */
drm_get_edid_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2039677dec6eSriastradh struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2040677dec6eSriastradh struct i2c_adapter *adapter)
2041677dec6eSriastradh {
20420589344aSriastradh #ifndef __NetBSD__ /* XXX vga switcheroo */
2043677dec6eSriastradh struct pci_dev *pdev = connector->dev->pdev;
20440589344aSriastradh #endif
2045677dec6eSriastradh struct edid *edid;
2046677dec6eSriastradh
20470589344aSriastradh #ifndef __NetBSD__ /* XXX vga switcheroo */
2048677dec6eSriastradh vga_switcheroo_lock_ddc(pdev);
20490589344aSriastradh #endif
2050677dec6eSriastradh edid = drm_get_edid(connector, adapter);
20510589344aSriastradh #ifndef __NetBSD__ /* XXX vga switcheroo */
2052677dec6eSriastradh vga_switcheroo_unlock_ddc(pdev);
20530589344aSriastradh #endif
2054677dec6eSriastradh
2055677dec6eSriastradh return edid;
2056677dec6eSriastradh }
2057677dec6eSriastradh EXPORT_SYMBOL(drm_get_edid_switcheroo);
2058677dec6eSriastradh
2059677dec6eSriastradh /**
2060a55ed7faSriastradh * drm_edid_duplicate - duplicate an EDID and the extensions
2061a55ed7faSriastradh * @edid: EDID to duplicate
2062a55ed7faSriastradh *
20634e59feabSriastradh * Return: Pointer to duplicated EDID or NULL on allocation failure.
2064a55ed7faSriastradh */
drm_edid_duplicate(const struct edid * edid)2065a55ed7faSriastradh struct edid *drm_edid_duplicate(const struct edid *edid)
2066a55ed7faSriastradh {
2067a55ed7faSriastradh return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2068a55ed7faSriastradh }
2069a55ed7faSriastradh EXPORT_SYMBOL(drm_edid_duplicate);
2070a55ed7faSriastradh
207156053ce7Sriastradh /*** EDID parsing ***/
207256053ce7Sriastradh
207356053ce7Sriastradh /**
207456053ce7Sriastradh * edid_vendor - match a string against EDID's obfuscated vendor field
207556053ce7Sriastradh * @edid: EDID to match
207656053ce7Sriastradh * @vendor: vendor string
207756053ce7Sriastradh *
207856053ce7Sriastradh * Returns true if @vendor is in @edid, false otherwise
207956053ce7Sriastradh */
edid_vendor(const struct edid * edid,const char * vendor)2080677dec6eSriastradh static bool edid_vendor(const struct edid *edid, const char *vendor)
208156053ce7Sriastradh {
208256053ce7Sriastradh char edid_vendor[3];
208356053ce7Sriastradh
208456053ce7Sriastradh edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
208556053ce7Sriastradh edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
208656053ce7Sriastradh ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
208756053ce7Sriastradh edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
208856053ce7Sriastradh
208956053ce7Sriastradh return !strncmp(edid_vendor, vendor, 3);
209056053ce7Sriastradh }
209156053ce7Sriastradh
209256053ce7Sriastradh /**
209356053ce7Sriastradh * edid_get_quirks - return quirk flags for a given EDID
209456053ce7Sriastradh * @edid: EDID to process
209556053ce7Sriastradh *
209656053ce7Sriastradh * This tells subsequent routines what fixes they need to apply.
209756053ce7Sriastradh */
edid_get_quirks(const struct edid * edid)2098677dec6eSriastradh static u32 edid_get_quirks(const struct edid *edid)
209956053ce7Sriastradh {
2100677dec6eSriastradh const struct edid_quirk *quirk;
210156053ce7Sriastradh int i;
210256053ce7Sriastradh
210356053ce7Sriastradh for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
210456053ce7Sriastradh quirk = &edid_quirk_list[i];
210556053ce7Sriastradh
210656053ce7Sriastradh if (edid_vendor(edid, quirk->vendor) &&
210756053ce7Sriastradh (EDID_PRODUCT_ID(edid) == quirk->product_id))
210856053ce7Sriastradh return quirk->quirks;
210956053ce7Sriastradh }
211056053ce7Sriastradh
211156053ce7Sriastradh return 0;
211256053ce7Sriastradh }
211356053ce7Sriastradh
211456053ce7Sriastradh #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2115a55ed7faSriastradh #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
211656053ce7Sriastradh
211756053ce7Sriastradh /**
211856053ce7Sriastradh * edid_fixup_preferred - set preferred modes based on quirk list
211956053ce7Sriastradh * @connector: has mode list to fix up
212056053ce7Sriastradh * @quirks: quirks list
212156053ce7Sriastradh *
212256053ce7Sriastradh * Walk the mode list for @connector, clearing the preferred status
212356053ce7Sriastradh * on existing modes and setting it anew for the right mode ala @quirks.
212456053ce7Sriastradh */
edid_fixup_preferred(struct drm_connector * connector,u32 quirks)212556053ce7Sriastradh static void edid_fixup_preferred(struct drm_connector *connector,
212656053ce7Sriastradh u32 quirks)
212756053ce7Sriastradh {
212856053ce7Sriastradh struct drm_display_mode *t, *cur_mode, *preferred_mode;
212956053ce7Sriastradh int target_refresh = 0;
2130a55ed7faSriastradh int cur_vrefresh, preferred_vrefresh;
213156053ce7Sriastradh
213256053ce7Sriastradh if (list_empty(&connector->probed_modes))
213356053ce7Sriastradh return;
213456053ce7Sriastradh
213556053ce7Sriastradh if (quirks & EDID_QUIRK_PREFER_LARGE_60)
213656053ce7Sriastradh target_refresh = 60;
213756053ce7Sriastradh if (quirks & EDID_QUIRK_PREFER_LARGE_75)
213856053ce7Sriastradh target_refresh = 75;
213956053ce7Sriastradh
214056053ce7Sriastradh preferred_mode = list_first_entry(&connector->probed_modes,
214156053ce7Sriastradh struct drm_display_mode, head);
214256053ce7Sriastradh
214356053ce7Sriastradh list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
214456053ce7Sriastradh cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
214556053ce7Sriastradh
214656053ce7Sriastradh if (cur_mode == preferred_mode)
214756053ce7Sriastradh continue;
214856053ce7Sriastradh
214956053ce7Sriastradh /* Largest mode is preferred */
215056053ce7Sriastradh if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
215156053ce7Sriastradh preferred_mode = cur_mode;
215256053ce7Sriastradh
2153a55ed7faSriastradh cur_vrefresh = cur_mode->vrefresh ?
2154a55ed7faSriastradh cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
2155a55ed7faSriastradh preferred_vrefresh = preferred_mode->vrefresh ?
2156a55ed7faSriastradh preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
215756053ce7Sriastradh /* At a given size, try to get closest to target refresh */
215856053ce7Sriastradh if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2159a55ed7faSriastradh MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2160a55ed7faSriastradh MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
216156053ce7Sriastradh preferred_mode = cur_mode;
216256053ce7Sriastradh }
216356053ce7Sriastradh }
216456053ce7Sriastradh
216556053ce7Sriastradh preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
216656053ce7Sriastradh }
216756053ce7Sriastradh
216856053ce7Sriastradh static bool
mode_is_rb(const struct drm_display_mode * mode)216956053ce7Sriastradh mode_is_rb(const struct drm_display_mode *mode)
217056053ce7Sriastradh {
217156053ce7Sriastradh return (mode->htotal - mode->hdisplay == 160) &&
217256053ce7Sriastradh (mode->hsync_end - mode->hdisplay == 80) &&
217356053ce7Sriastradh (mode->hsync_end - mode->hsync_start == 32) &&
217456053ce7Sriastradh (mode->vsync_start - mode->vdisplay == 3);
217556053ce7Sriastradh }
217656053ce7Sriastradh
217756053ce7Sriastradh /*
217856053ce7Sriastradh * drm_mode_find_dmt - Create a copy of a mode if present in DMT
217956053ce7Sriastradh * @dev: Device to duplicate against
218056053ce7Sriastradh * @hsize: Mode width
218156053ce7Sriastradh * @vsize: Mode height
218256053ce7Sriastradh * @fresh: Mode refresh rate
218356053ce7Sriastradh * @rb: Mode reduced-blanking-ness
218456053ce7Sriastradh *
218556053ce7Sriastradh * Walk the DMT mode list looking for a match for the given parameters.
21864e59feabSriastradh *
21874e59feabSriastradh * Return: A newly allocated copy of the mode, or NULL if not found.
218856053ce7Sriastradh */
drm_mode_find_dmt(struct drm_device * dev,int hsize,int vsize,int fresh,bool rb)218956053ce7Sriastradh struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
219056053ce7Sriastradh int hsize, int vsize, int fresh,
219156053ce7Sriastradh bool rb)
219256053ce7Sriastradh {
219356053ce7Sriastradh int i;
219456053ce7Sriastradh
2195a55ed7faSriastradh for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
219656053ce7Sriastradh const struct drm_display_mode *ptr = &drm_dmt_modes[i];
219756053ce7Sriastradh if (hsize != ptr->hdisplay)
219856053ce7Sriastradh continue;
219956053ce7Sriastradh if (vsize != ptr->vdisplay)
220056053ce7Sriastradh continue;
220156053ce7Sriastradh if (fresh != drm_mode_vrefresh(ptr))
220256053ce7Sriastradh continue;
220356053ce7Sriastradh if (rb != mode_is_rb(ptr))
220456053ce7Sriastradh continue;
220556053ce7Sriastradh
220656053ce7Sriastradh return drm_mode_duplicate(dev, ptr);
220756053ce7Sriastradh }
220856053ce7Sriastradh
220956053ce7Sriastradh return NULL;
221056053ce7Sriastradh }
221156053ce7Sriastradh EXPORT_SYMBOL(drm_mode_find_dmt);
221256053ce7Sriastradh
221356053ce7Sriastradh typedef void detailed_cb(struct detailed_timing *timing, void *closure);
221456053ce7Sriastradh
221556053ce7Sriastradh static void
cea_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)221656053ce7Sriastradh cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
221756053ce7Sriastradh {
221856053ce7Sriastradh int i, n = 0;
221956053ce7Sriastradh u8 d = ext[0x02];
222056053ce7Sriastradh u8 *det_base = ext + d;
222156053ce7Sriastradh
222256053ce7Sriastradh n = (127 - d) / 18;
222356053ce7Sriastradh for (i = 0; i < n; i++)
222456053ce7Sriastradh cb((struct detailed_timing *)(det_base + 18 * i), closure);
222556053ce7Sriastradh }
222656053ce7Sriastradh
222756053ce7Sriastradh static void
vtb_for_each_detailed_block(u8 * ext,detailed_cb * cb,void * closure)222856053ce7Sriastradh vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
222956053ce7Sriastradh {
223056053ce7Sriastradh unsigned int i, n = min((int)ext[0x02], 6);
223156053ce7Sriastradh u8 *det_base = ext + 5;
223256053ce7Sriastradh
223356053ce7Sriastradh if (ext[0x01] != 1)
223456053ce7Sriastradh return; /* unknown version */
223556053ce7Sriastradh
223656053ce7Sriastradh for (i = 0; i < n; i++)
223756053ce7Sriastradh cb((struct detailed_timing *)(det_base + 18 * i), closure);
223856053ce7Sriastradh }
223956053ce7Sriastradh
224056053ce7Sriastradh static void
drm_for_each_detailed_block(u8 * raw_edid,detailed_cb * cb,void * closure)224156053ce7Sriastradh drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
224256053ce7Sriastradh {
224356053ce7Sriastradh int i;
224456053ce7Sriastradh struct edid *edid = (struct edid *)raw_edid;
224556053ce7Sriastradh
224656053ce7Sriastradh if (edid == NULL)
224756053ce7Sriastradh return;
224856053ce7Sriastradh
224956053ce7Sriastradh for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
225056053ce7Sriastradh cb(&(edid->detailed_timings[i]), closure);
225156053ce7Sriastradh
225256053ce7Sriastradh for (i = 1; i <= raw_edid[0x7e]; i++) {
225356053ce7Sriastradh u8 *ext = raw_edid + (i * EDID_LENGTH);
225456053ce7Sriastradh switch (*ext) {
225556053ce7Sriastradh case CEA_EXT:
225656053ce7Sriastradh cea_for_each_detailed_block(ext, cb, closure);
225756053ce7Sriastradh break;
225856053ce7Sriastradh case VTB_EXT:
225956053ce7Sriastradh vtb_for_each_detailed_block(ext, cb, closure);
226056053ce7Sriastradh break;
226156053ce7Sriastradh default:
226256053ce7Sriastradh break;
226356053ce7Sriastradh }
226456053ce7Sriastradh }
226556053ce7Sriastradh }
226656053ce7Sriastradh
226756053ce7Sriastradh static void
is_rb(struct detailed_timing * t,void * data)226856053ce7Sriastradh is_rb(struct detailed_timing *t, void *data)
226956053ce7Sriastradh {
227056053ce7Sriastradh u8 *r = (u8 *)t;
227156053ce7Sriastradh if (r[3] == EDID_DETAIL_MONITOR_RANGE)
227256053ce7Sriastradh if (r[15] & 0x10)
227356053ce7Sriastradh *(bool *)data = true;
227456053ce7Sriastradh }
227556053ce7Sriastradh
227656053ce7Sriastradh /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
227756053ce7Sriastradh static bool
drm_monitor_supports_rb(struct edid * edid)227856053ce7Sriastradh drm_monitor_supports_rb(struct edid *edid)
227956053ce7Sriastradh {
228056053ce7Sriastradh if (edid->revision >= 4) {
228156053ce7Sriastradh bool ret = false;
228256053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
228356053ce7Sriastradh return ret;
228456053ce7Sriastradh }
228556053ce7Sriastradh
228656053ce7Sriastradh return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
228756053ce7Sriastradh }
228856053ce7Sriastradh
228956053ce7Sriastradh static void
find_gtf2(struct detailed_timing * t,void * data)229056053ce7Sriastradh find_gtf2(struct detailed_timing *t, void *data)
229156053ce7Sriastradh {
229256053ce7Sriastradh u8 *r = (u8 *)t;
229356053ce7Sriastradh if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
229456053ce7Sriastradh *(u8 **)data = r;
229556053ce7Sriastradh }
229656053ce7Sriastradh
229756053ce7Sriastradh /* Secondary GTF curve kicks in above some break frequency */
229856053ce7Sriastradh static int
drm_gtf2_hbreak(struct edid * edid)229956053ce7Sriastradh drm_gtf2_hbreak(struct edid *edid)
230056053ce7Sriastradh {
230156053ce7Sriastradh u8 *r = NULL;
230256053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
230356053ce7Sriastradh return r ? (r[12] * 2) : 0;
230456053ce7Sriastradh }
230556053ce7Sriastradh
230656053ce7Sriastradh static int
drm_gtf2_2c(struct edid * edid)230756053ce7Sriastradh drm_gtf2_2c(struct edid *edid)
230856053ce7Sriastradh {
230956053ce7Sriastradh u8 *r = NULL;
231056053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
231156053ce7Sriastradh return r ? r[13] : 0;
231256053ce7Sriastradh }
231356053ce7Sriastradh
231456053ce7Sriastradh static int
drm_gtf2_m(struct edid * edid)231556053ce7Sriastradh drm_gtf2_m(struct edid *edid)
231656053ce7Sriastradh {
231756053ce7Sriastradh u8 *r = NULL;
231856053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
231956053ce7Sriastradh return r ? (r[15] << 8) + r[14] : 0;
232056053ce7Sriastradh }
232156053ce7Sriastradh
232256053ce7Sriastradh static int
drm_gtf2_k(struct edid * edid)232356053ce7Sriastradh drm_gtf2_k(struct edid *edid)
232456053ce7Sriastradh {
232556053ce7Sriastradh u8 *r = NULL;
232656053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
232756053ce7Sriastradh return r ? r[16] : 0;
232856053ce7Sriastradh }
232956053ce7Sriastradh
233056053ce7Sriastradh static int
drm_gtf2_2j(struct edid * edid)233156053ce7Sriastradh drm_gtf2_2j(struct edid *edid)
233256053ce7Sriastradh {
233356053ce7Sriastradh u8 *r = NULL;
233456053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
233556053ce7Sriastradh return r ? r[17] : 0;
233656053ce7Sriastradh }
233756053ce7Sriastradh
233856053ce7Sriastradh /**
233956053ce7Sriastradh * standard_timing_level - get std. timing level(CVT/GTF/DMT)
234056053ce7Sriastradh * @edid: EDID block to scan
234156053ce7Sriastradh */
standard_timing_level(struct edid * edid)234256053ce7Sriastradh static int standard_timing_level(struct edid *edid)
234356053ce7Sriastradh {
234456053ce7Sriastradh if (edid->revision >= 2) {
234556053ce7Sriastradh if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
234656053ce7Sriastradh return LEVEL_CVT;
234756053ce7Sriastradh if (drm_gtf2_hbreak(edid))
234856053ce7Sriastradh return LEVEL_GTF2;
2349677dec6eSriastradh if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
235056053ce7Sriastradh return LEVEL_GTF;
235156053ce7Sriastradh }
235256053ce7Sriastradh return LEVEL_DMT;
235356053ce7Sriastradh }
235456053ce7Sriastradh
235556053ce7Sriastradh /*
235656053ce7Sriastradh * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
235756053ce7Sriastradh * monitors fill with ascii space (0x20) instead.
235856053ce7Sriastradh */
235956053ce7Sriastradh static int
bad_std_timing(u8 a,u8 b)236056053ce7Sriastradh bad_std_timing(u8 a, u8 b)
236156053ce7Sriastradh {
236256053ce7Sriastradh return (a == 0x00 && b == 0x00) ||
236356053ce7Sriastradh (a == 0x01 && b == 0x01) ||
236456053ce7Sriastradh (a == 0x20 && b == 0x20);
236556053ce7Sriastradh }
236656053ce7Sriastradh
236756053ce7Sriastradh /**
236856053ce7Sriastradh * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2369a55ed7faSriastradh * @connector: connector of for the EDID block
2370a55ed7faSriastradh * @edid: EDID block to scan
237156053ce7Sriastradh * @t: standard timing params
237256053ce7Sriastradh *
237356053ce7Sriastradh * Take the standard timing params (in this case width, aspect, and refresh)
237456053ce7Sriastradh * and convert them into a real mode using CVT/GTF/DMT.
237556053ce7Sriastradh */
237656053ce7Sriastradh static struct drm_display_mode *
drm_mode_std(struct drm_connector * connector,struct edid * edid,struct std_timing * t)237756053ce7Sriastradh drm_mode_std(struct drm_connector *connector, struct edid *edid,
23784e59feabSriastradh struct std_timing *t)
237956053ce7Sriastradh {
238056053ce7Sriastradh struct drm_device *dev = connector->dev;
238156053ce7Sriastradh struct drm_display_mode *m, *mode = NULL;
238256053ce7Sriastradh int hsize, vsize;
238356053ce7Sriastradh int vrefresh_rate;
238456053ce7Sriastradh unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
238556053ce7Sriastradh >> EDID_TIMING_ASPECT_SHIFT;
238656053ce7Sriastradh unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
238756053ce7Sriastradh >> EDID_TIMING_VFREQ_SHIFT;
238856053ce7Sriastradh int timing_level = standard_timing_level(edid);
238956053ce7Sriastradh
239056053ce7Sriastradh if (bad_std_timing(t->hsize, t->vfreq_aspect))
239156053ce7Sriastradh return NULL;
239256053ce7Sriastradh
239356053ce7Sriastradh /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
239456053ce7Sriastradh hsize = t->hsize * 8 + 248;
239556053ce7Sriastradh /* vrefresh_rate = vfreq + 60 */
239656053ce7Sriastradh vrefresh_rate = vfreq + 60;
239756053ce7Sriastradh /* the vdisplay is calculated based on the aspect ratio */
239856053ce7Sriastradh if (aspect_ratio == 0) {
23994e59feabSriastradh if (edid->revision < 3)
240056053ce7Sriastradh vsize = hsize;
240156053ce7Sriastradh else
240256053ce7Sriastradh vsize = (hsize * 10) / 16;
240356053ce7Sriastradh } else if (aspect_ratio == 1)
240456053ce7Sriastradh vsize = (hsize * 3) / 4;
240556053ce7Sriastradh else if (aspect_ratio == 2)
240656053ce7Sriastradh vsize = (hsize * 4) / 5;
240756053ce7Sriastradh else
240856053ce7Sriastradh vsize = (hsize * 9) / 16;
240956053ce7Sriastradh
241056053ce7Sriastradh /* HDTV hack, part 1 */
241156053ce7Sriastradh if (vrefresh_rate == 60 &&
241256053ce7Sriastradh ((hsize == 1360 && vsize == 765) ||
241356053ce7Sriastradh (hsize == 1368 && vsize == 769))) {
241456053ce7Sriastradh hsize = 1366;
241556053ce7Sriastradh vsize = 768;
241656053ce7Sriastradh }
241756053ce7Sriastradh
241856053ce7Sriastradh /*
241956053ce7Sriastradh * If this connector already has a mode for this size and refresh
242056053ce7Sriastradh * rate (because it came from detailed or CVT info), use that
242156053ce7Sriastradh * instead. This way we don't have to guess at interlace or
242256053ce7Sriastradh * reduced blanking.
242356053ce7Sriastradh */
242456053ce7Sriastradh list_for_each_entry(m, &connector->probed_modes, head)
242556053ce7Sriastradh if (m->hdisplay == hsize && m->vdisplay == vsize &&
242656053ce7Sriastradh drm_mode_vrefresh(m) == vrefresh_rate)
242756053ce7Sriastradh return NULL;
242856053ce7Sriastradh
242956053ce7Sriastradh /* HDTV hack, part 2 */
243056053ce7Sriastradh if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
243156053ce7Sriastradh mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
243256053ce7Sriastradh false);
2433677dec6eSriastradh if (!mode)
2434677dec6eSriastradh return NULL;
243556053ce7Sriastradh mode->hdisplay = 1366;
243656053ce7Sriastradh mode->hsync_start = mode->hsync_start - 1;
243756053ce7Sriastradh mode->hsync_end = mode->hsync_end - 1;
243856053ce7Sriastradh return mode;
243956053ce7Sriastradh }
244056053ce7Sriastradh
244156053ce7Sriastradh /* check whether it can be found in default mode table */
244256053ce7Sriastradh if (drm_monitor_supports_rb(edid)) {
244356053ce7Sriastradh mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
244456053ce7Sriastradh true);
244556053ce7Sriastradh if (mode)
244656053ce7Sriastradh return mode;
244756053ce7Sriastradh }
244856053ce7Sriastradh mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
244956053ce7Sriastradh if (mode)
245056053ce7Sriastradh return mode;
245156053ce7Sriastradh
245256053ce7Sriastradh /* okay, generate it */
245356053ce7Sriastradh switch (timing_level) {
245456053ce7Sriastradh case LEVEL_DMT:
245556053ce7Sriastradh break;
245656053ce7Sriastradh case LEVEL_GTF:
245756053ce7Sriastradh mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
245856053ce7Sriastradh break;
245956053ce7Sriastradh case LEVEL_GTF2:
246056053ce7Sriastradh /*
246156053ce7Sriastradh * This is potentially wrong if there's ever a monitor with
246256053ce7Sriastradh * more than one ranges section, each claiming a different
246356053ce7Sriastradh * secondary GTF curve. Please don't do that.
246456053ce7Sriastradh */
246556053ce7Sriastradh mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
246656053ce7Sriastradh if (!mode)
246756053ce7Sriastradh return NULL;
246856053ce7Sriastradh if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
246956053ce7Sriastradh drm_mode_destroy(dev, mode);
247056053ce7Sriastradh mode = drm_gtf_mode_complex(dev, hsize, vsize,
247156053ce7Sriastradh vrefresh_rate, 0, 0,
247256053ce7Sriastradh drm_gtf2_m(edid),
247356053ce7Sriastradh drm_gtf2_2c(edid),
247456053ce7Sriastradh drm_gtf2_k(edid),
247556053ce7Sriastradh drm_gtf2_2j(edid));
247656053ce7Sriastradh }
247756053ce7Sriastradh break;
247856053ce7Sriastradh case LEVEL_CVT:
247956053ce7Sriastradh mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
248056053ce7Sriastradh false);
248156053ce7Sriastradh break;
248256053ce7Sriastradh }
248356053ce7Sriastradh return mode;
248456053ce7Sriastradh }
248556053ce7Sriastradh
248656053ce7Sriastradh /*
248756053ce7Sriastradh * EDID is delightfully ambiguous about how interlaced modes are to be
248856053ce7Sriastradh * encoded. Our internal representation is of frame height, but some
248956053ce7Sriastradh * HDTV detailed timings are encoded as field height.
249056053ce7Sriastradh *
249156053ce7Sriastradh * The format list here is from CEA, in frame size. Technically we
249256053ce7Sriastradh * should be checking refresh rate too. Whatever.
249356053ce7Sriastradh */
249456053ce7Sriastradh static void
drm_mode_do_interlace_quirk(struct drm_display_mode * mode,struct detailed_pixel_timing * pt)249556053ce7Sriastradh drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
249656053ce7Sriastradh struct detailed_pixel_timing *pt)
249756053ce7Sriastradh {
249856053ce7Sriastradh int i;
249956053ce7Sriastradh static const struct {
250056053ce7Sriastradh int w, h;
250156053ce7Sriastradh } cea_interlaced[] = {
250256053ce7Sriastradh { 1920, 1080 },
250356053ce7Sriastradh { 720, 480 },
250456053ce7Sriastradh { 1440, 480 },
250556053ce7Sriastradh { 2880, 480 },
250656053ce7Sriastradh { 720, 576 },
250756053ce7Sriastradh { 1440, 576 },
250856053ce7Sriastradh { 2880, 576 },
250956053ce7Sriastradh };
251056053ce7Sriastradh
251156053ce7Sriastradh if (!(pt->misc & DRM_EDID_PT_INTERLACED))
251256053ce7Sriastradh return;
251356053ce7Sriastradh
251456053ce7Sriastradh for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
251556053ce7Sriastradh if ((mode->hdisplay == cea_interlaced[i].w) &&
251656053ce7Sriastradh (mode->vdisplay == cea_interlaced[i].h / 2)) {
251756053ce7Sriastradh mode->vdisplay *= 2;
251856053ce7Sriastradh mode->vsync_start *= 2;
251956053ce7Sriastradh mode->vsync_end *= 2;
252056053ce7Sriastradh mode->vtotal *= 2;
252156053ce7Sriastradh mode->vtotal |= 1;
252256053ce7Sriastradh }
252356053ce7Sriastradh }
252456053ce7Sriastradh
252556053ce7Sriastradh mode->flags |= DRM_MODE_FLAG_INTERLACE;
252656053ce7Sriastradh }
252756053ce7Sriastradh
252856053ce7Sriastradh /**
252956053ce7Sriastradh * drm_mode_detailed - create a new mode from an EDID detailed timing section
253056053ce7Sriastradh * @dev: DRM device (needed to create new mode)
253156053ce7Sriastradh * @edid: EDID block
253256053ce7Sriastradh * @timing: EDID detailed timing info
253356053ce7Sriastradh * @quirks: quirks to apply
253456053ce7Sriastradh *
253556053ce7Sriastradh * An EDID detailed timing block contains enough info for us to create and
253656053ce7Sriastradh * return a new struct drm_display_mode.
253756053ce7Sriastradh */
drm_mode_detailed(struct drm_device * dev,struct edid * edid,struct detailed_timing * timing,u32 quirks)253856053ce7Sriastradh static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
253956053ce7Sriastradh struct edid *edid,
254056053ce7Sriastradh struct detailed_timing *timing,
254156053ce7Sriastradh u32 quirks)
254256053ce7Sriastradh {
254356053ce7Sriastradh struct drm_display_mode *mode;
254456053ce7Sriastradh struct detailed_pixel_timing *pt = &timing->data.pixel_data;
254556053ce7Sriastradh unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
254656053ce7Sriastradh unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
254756053ce7Sriastradh unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
254856053ce7Sriastradh unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
254956053ce7Sriastradh unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
255056053ce7Sriastradh unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2551a55ed7faSriastradh unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
255256053ce7Sriastradh unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
255356053ce7Sriastradh
255456053ce7Sriastradh /* ignore tiny modes */
255556053ce7Sriastradh if (hactive < 64 || vactive < 64)
255656053ce7Sriastradh return NULL;
255756053ce7Sriastradh
255856053ce7Sriastradh if (pt->misc & DRM_EDID_PT_STEREO) {
2559a55ed7faSriastradh DRM_DEBUG_KMS("stereo mode not supported\n");
256056053ce7Sriastradh return NULL;
256156053ce7Sriastradh }
256256053ce7Sriastradh if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2563a55ed7faSriastradh DRM_DEBUG_KMS("composite sync not supported\n");
256456053ce7Sriastradh }
256556053ce7Sriastradh
256656053ce7Sriastradh /* it is incorrect if hsync/vsync width is zero */
256756053ce7Sriastradh if (!hsync_pulse_width || !vsync_pulse_width) {
256856053ce7Sriastradh DRM_DEBUG_KMS("Incorrect Detailed timing. "
256956053ce7Sriastradh "Wrong Hsync/Vsync pulse width\n");
257056053ce7Sriastradh return NULL;
257156053ce7Sriastradh }
257256053ce7Sriastradh
257356053ce7Sriastradh if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
257456053ce7Sriastradh mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
257556053ce7Sriastradh if (!mode)
257656053ce7Sriastradh return NULL;
257756053ce7Sriastradh
257856053ce7Sriastradh goto set_size;
257956053ce7Sriastradh }
258056053ce7Sriastradh
258156053ce7Sriastradh mode = drm_mode_create(dev);
258256053ce7Sriastradh if (!mode)
258356053ce7Sriastradh return NULL;
258456053ce7Sriastradh
258556053ce7Sriastradh if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
258656053ce7Sriastradh timing->pixel_clock = cpu_to_le16(1088);
258756053ce7Sriastradh
258856053ce7Sriastradh mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
258956053ce7Sriastradh
259056053ce7Sriastradh mode->hdisplay = hactive;
259156053ce7Sriastradh mode->hsync_start = mode->hdisplay + hsync_offset;
259256053ce7Sriastradh mode->hsync_end = mode->hsync_start + hsync_pulse_width;
259356053ce7Sriastradh mode->htotal = mode->hdisplay + hblank;
259456053ce7Sriastradh
259556053ce7Sriastradh mode->vdisplay = vactive;
259656053ce7Sriastradh mode->vsync_start = mode->vdisplay + vsync_offset;
259756053ce7Sriastradh mode->vsync_end = mode->vsync_start + vsync_pulse_width;
259856053ce7Sriastradh mode->vtotal = mode->vdisplay + vblank;
259956053ce7Sriastradh
260056053ce7Sriastradh /* Some EDIDs have bogus h/vtotal values */
260156053ce7Sriastradh if (mode->hsync_end > mode->htotal)
260256053ce7Sriastradh mode->htotal = mode->hsync_end + 1;
260356053ce7Sriastradh if (mode->vsync_end > mode->vtotal)
260456053ce7Sriastradh mode->vtotal = mode->vsync_end + 1;
260556053ce7Sriastradh
260656053ce7Sriastradh drm_mode_do_interlace_quirk(mode, pt);
260756053ce7Sriastradh
260856053ce7Sriastradh if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
260956053ce7Sriastradh pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
261056053ce7Sriastradh }
261156053ce7Sriastradh
261256053ce7Sriastradh mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
261356053ce7Sriastradh DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
261456053ce7Sriastradh mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
261556053ce7Sriastradh DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
261656053ce7Sriastradh
261756053ce7Sriastradh set_size:
261856053ce7Sriastradh mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
261956053ce7Sriastradh mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
262056053ce7Sriastradh
262156053ce7Sriastradh if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
262256053ce7Sriastradh mode->width_mm *= 10;
262356053ce7Sriastradh mode->height_mm *= 10;
262456053ce7Sriastradh }
262556053ce7Sriastradh
262656053ce7Sriastradh if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
262756053ce7Sriastradh mode->width_mm = edid->width_cm * 10;
262856053ce7Sriastradh mode->height_mm = edid->height_cm * 10;
262956053ce7Sriastradh }
263056053ce7Sriastradh
263156053ce7Sriastradh mode->type = DRM_MODE_TYPE_DRIVER;
2632a55ed7faSriastradh mode->vrefresh = drm_mode_vrefresh(mode);
263356053ce7Sriastradh drm_mode_set_name(mode);
263456053ce7Sriastradh
263556053ce7Sriastradh return mode;
263656053ce7Sriastradh }
263756053ce7Sriastradh
263856053ce7Sriastradh static bool
mode_in_hsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)263956053ce7Sriastradh mode_in_hsync_range(const struct drm_display_mode *mode,
264056053ce7Sriastradh struct edid *edid, u8 *t)
264156053ce7Sriastradh {
264256053ce7Sriastradh int hsync, hmin, hmax;
264356053ce7Sriastradh
264456053ce7Sriastradh hmin = t[7];
264556053ce7Sriastradh if (edid->revision >= 4)
264656053ce7Sriastradh hmin += ((t[4] & 0x04) ? 255 : 0);
264756053ce7Sriastradh hmax = t[8];
264856053ce7Sriastradh if (edid->revision >= 4)
264956053ce7Sriastradh hmax += ((t[4] & 0x08) ? 255 : 0);
265056053ce7Sriastradh hsync = drm_mode_hsync(mode);
265156053ce7Sriastradh
265256053ce7Sriastradh return (hsync <= hmax && hsync >= hmin);
265356053ce7Sriastradh }
265456053ce7Sriastradh
265556053ce7Sriastradh static bool
mode_in_vsync_range(const struct drm_display_mode * mode,struct edid * edid,u8 * t)265656053ce7Sriastradh mode_in_vsync_range(const struct drm_display_mode *mode,
265756053ce7Sriastradh struct edid *edid, u8 *t)
265856053ce7Sriastradh {
265956053ce7Sriastradh int vsync, vmin, vmax;
266056053ce7Sriastradh
266156053ce7Sriastradh vmin = t[5];
266256053ce7Sriastradh if (edid->revision >= 4)
266356053ce7Sriastradh vmin += ((t[4] & 0x01) ? 255 : 0);
266456053ce7Sriastradh vmax = t[6];
266556053ce7Sriastradh if (edid->revision >= 4)
266656053ce7Sriastradh vmax += ((t[4] & 0x02) ? 255 : 0);
266756053ce7Sriastradh vsync = drm_mode_vrefresh(mode);
266856053ce7Sriastradh
266956053ce7Sriastradh return (vsync <= vmax && vsync >= vmin);
267056053ce7Sriastradh }
267156053ce7Sriastradh
267256053ce7Sriastradh static u32
range_pixel_clock(struct edid * edid,u8 * t)267356053ce7Sriastradh range_pixel_clock(struct edid *edid, u8 *t)
267456053ce7Sriastradh {
267556053ce7Sriastradh /* unspecified */
267656053ce7Sriastradh if (t[9] == 0 || t[9] == 255)
267756053ce7Sriastradh return 0;
267856053ce7Sriastradh
267956053ce7Sriastradh /* 1.4 with CVT support gives us real precision, yay */
268056053ce7Sriastradh if (edid->revision >= 4 && t[10] == 0x04)
268156053ce7Sriastradh return (t[9] * 10000) - ((t[12] >> 2) * 250);
268256053ce7Sriastradh
268356053ce7Sriastradh /* 1.3 is pathetic, so fuzz up a bit */
268456053ce7Sriastradh return t[9] * 10000 + 5001;
268556053ce7Sriastradh }
268656053ce7Sriastradh
268756053ce7Sriastradh static bool
mode_in_range(const struct drm_display_mode * mode,struct edid * edid,struct detailed_timing * timing)268856053ce7Sriastradh mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
268956053ce7Sriastradh struct detailed_timing *timing)
269056053ce7Sriastradh {
269156053ce7Sriastradh u32 max_clock;
269256053ce7Sriastradh u8 *t = (u8 *)timing;
269356053ce7Sriastradh
269456053ce7Sriastradh if (!mode_in_hsync_range(mode, edid, t))
269556053ce7Sriastradh return false;
269656053ce7Sriastradh
269756053ce7Sriastradh if (!mode_in_vsync_range(mode, edid, t))
269856053ce7Sriastradh return false;
269956053ce7Sriastradh
270056053ce7Sriastradh if ((max_clock = range_pixel_clock(edid, t)))
270156053ce7Sriastradh if (mode->clock > max_clock)
270256053ce7Sriastradh return false;
270356053ce7Sriastradh
270456053ce7Sriastradh /* 1.4 max horizontal check */
270556053ce7Sriastradh if (edid->revision >= 4 && t[10] == 0x04)
270656053ce7Sriastradh if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
270756053ce7Sriastradh return false;
270856053ce7Sriastradh
270956053ce7Sriastradh if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
271056053ce7Sriastradh return false;
271156053ce7Sriastradh
271256053ce7Sriastradh return true;
271356053ce7Sriastradh }
271456053ce7Sriastradh
valid_inferred_mode(const struct drm_connector * connector,const struct drm_display_mode * mode)271556053ce7Sriastradh static bool valid_inferred_mode(const struct drm_connector *connector,
271656053ce7Sriastradh const struct drm_display_mode *mode)
271756053ce7Sriastradh {
27184e59feabSriastradh const struct drm_display_mode *m;
271956053ce7Sriastradh bool ok = false;
272056053ce7Sriastradh
272156053ce7Sriastradh list_for_each_entry(m, &connector->probed_modes, head) {
272256053ce7Sriastradh if (mode->hdisplay == m->hdisplay &&
272356053ce7Sriastradh mode->vdisplay == m->vdisplay &&
272456053ce7Sriastradh drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
272556053ce7Sriastradh return false; /* duplicated */
272656053ce7Sriastradh if (mode->hdisplay <= m->hdisplay &&
272756053ce7Sriastradh mode->vdisplay <= m->vdisplay)
272856053ce7Sriastradh ok = true;
272956053ce7Sriastradh }
273056053ce7Sriastradh return ok;
273156053ce7Sriastradh }
273256053ce7Sriastradh
273356053ce7Sriastradh static int
drm_dmt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)273456053ce7Sriastradh drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
273556053ce7Sriastradh struct detailed_timing *timing)
273656053ce7Sriastradh {
273756053ce7Sriastradh int i, modes = 0;
273856053ce7Sriastradh struct drm_display_mode *newmode;
273956053ce7Sriastradh struct drm_device *dev = connector->dev;
274056053ce7Sriastradh
2741a55ed7faSriastradh for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
274256053ce7Sriastradh if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
274356053ce7Sriastradh valid_inferred_mode(connector, drm_dmt_modes + i)) {
274456053ce7Sriastradh newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
274556053ce7Sriastradh if (newmode) {
274656053ce7Sriastradh drm_mode_probed_add(connector, newmode);
274756053ce7Sriastradh modes++;
274856053ce7Sriastradh }
274956053ce7Sriastradh }
275056053ce7Sriastradh }
275156053ce7Sriastradh
275256053ce7Sriastradh return modes;
275356053ce7Sriastradh }
275456053ce7Sriastradh
275556053ce7Sriastradh /* fix up 1366x768 mode from 1368x768;
275656053ce7Sriastradh * GFT/CVT can't express 1366 width which isn't dividable by 8
275756053ce7Sriastradh */
drm_mode_fixup_1366x768(struct drm_display_mode * mode)2758677dec6eSriastradh void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
275956053ce7Sriastradh {
276056053ce7Sriastradh if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
276156053ce7Sriastradh mode->hdisplay = 1366;
276256053ce7Sriastradh mode->hsync_start--;
276356053ce7Sriastradh mode->hsync_end--;
276456053ce7Sriastradh drm_mode_set_name(mode);
276556053ce7Sriastradh }
276656053ce7Sriastradh }
276756053ce7Sriastradh
276856053ce7Sriastradh static int
drm_gtf_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)276956053ce7Sriastradh drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
277056053ce7Sriastradh struct detailed_timing *timing)
277156053ce7Sriastradh {
277256053ce7Sriastradh int i, modes = 0;
277356053ce7Sriastradh struct drm_display_mode *newmode;
277456053ce7Sriastradh struct drm_device *dev = connector->dev;
277556053ce7Sriastradh
2776a55ed7faSriastradh for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
277756053ce7Sriastradh const struct minimode *m = &extra_modes[i];
277856053ce7Sriastradh newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
277956053ce7Sriastradh if (!newmode)
278056053ce7Sriastradh return modes;
278156053ce7Sriastradh
2782677dec6eSriastradh drm_mode_fixup_1366x768(newmode);
278356053ce7Sriastradh if (!mode_in_range(newmode, edid, timing) ||
278456053ce7Sriastradh !valid_inferred_mode(connector, newmode)) {
278556053ce7Sriastradh drm_mode_destroy(dev, newmode);
278656053ce7Sriastradh continue;
278756053ce7Sriastradh }
278856053ce7Sriastradh
278956053ce7Sriastradh drm_mode_probed_add(connector, newmode);
279056053ce7Sriastradh modes++;
279156053ce7Sriastradh }
279256053ce7Sriastradh
279356053ce7Sriastradh return modes;
279456053ce7Sriastradh }
279556053ce7Sriastradh
279656053ce7Sriastradh static int
drm_cvt_modes_for_range(struct drm_connector * connector,struct edid * edid,struct detailed_timing * timing)279756053ce7Sriastradh drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
279856053ce7Sriastradh struct detailed_timing *timing)
279956053ce7Sriastradh {
280056053ce7Sriastradh int i, modes = 0;
280156053ce7Sriastradh struct drm_display_mode *newmode;
280256053ce7Sriastradh struct drm_device *dev = connector->dev;
280356053ce7Sriastradh bool rb = drm_monitor_supports_rb(edid);
280456053ce7Sriastradh
2805a55ed7faSriastradh for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
280656053ce7Sriastradh const struct minimode *m = &extra_modes[i];
280756053ce7Sriastradh newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
280856053ce7Sriastradh if (!newmode)
280956053ce7Sriastradh return modes;
281056053ce7Sriastradh
2811677dec6eSriastradh drm_mode_fixup_1366x768(newmode);
281256053ce7Sriastradh if (!mode_in_range(newmode, edid, timing) ||
281356053ce7Sriastradh !valid_inferred_mode(connector, newmode)) {
281456053ce7Sriastradh drm_mode_destroy(dev, newmode);
281556053ce7Sriastradh continue;
281656053ce7Sriastradh }
281756053ce7Sriastradh
281856053ce7Sriastradh drm_mode_probed_add(connector, newmode);
281956053ce7Sriastradh modes++;
282056053ce7Sriastradh }
282156053ce7Sriastradh
282256053ce7Sriastradh return modes;
282356053ce7Sriastradh }
282456053ce7Sriastradh
282556053ce7Sriastradh static void
do_inferred_modes(struct detailed_timing * timing,void * c)282656053ce7Sriastradh do_inferred_modes(struct detailed_timing *timing, void *c)
282756053ce7Sriastradh {
282856053ce7Sriastradh struct detailed_mode_closure *closure = c;
282956053ce7Sriastradh struct detailed_non_pixel *data = &timing->data.other_data;
283056053ce7Sriastradh struct detailed_data_monitor_range *range = &data->data.range;
283156053ce7Sriastradh
283256053ce7Sriastradh if (data->type != EDID_DETAIL_MONITOR_RANGE)
283356053ce7Sriastradh return;
283456053ce7Sriastradh
283556053ce7Sriastradh closure->modes += drm_dmt_modes_for_range(closure->connector,
283656053ce7Sriastradh closure->edid,
283756053ce7Sriastradh timing);
283856053ce7Sriastradh
283956053ce7Sriastradh if (!version_greater(closure->edid, 1, 1))
284056053ce7Sriastradh return; /* GTF not defined yet */
284156053ce7Sriastradh
284256053ce7Sriastradh switch (range->flags) {
284356053ce7Sriastradh case 0x02: /* secondary gtf, XXX could do more */
284456053ce7Sriastradh case 0x00: /* default gtf */
284556053ce7Sriastradh closure->modes += drm_gtf_modes_for_range(closure->connector,
284656053ce7Sriastradh closure->edid,
284756053ce7Sriastradh timing);
284856053ce7Sriastradh break;
284956053ce7Sriastradh case 0x04: /* cvt, only in 1.4+ */
285056053ce7Sriastradh if (!version_greater(closure->edid, 1, 3))
285156053ce7Sriastradh break;
285256053ce7Sriastradh
285356053ce7Sriastradh closure->modes += drm_cvt_modes_for_range(closure->connector,
285456053ce7Sriastradh closure->edid,
285556053ce7Sriastradh timing);
285656053ce7Sriastradh break;
285756053ce7Sriastradh case 0x01: /* just the ranges, no formula */
285856053ce7Sriastradh default:
285956053ce7Sriastradh break;
286056053ce7Sriastradh }
286156053ce7Sriastradh }
286256053ce7Sriastradh
286356053ce7Sriastradh static int
add_inferred_modes(struct drm_connector * connector,struct edid * edid)286456053ce7Sriastradh add_inferred_modes(struct drm_connector *connector, struct edid *edid)
286556053ce7Sriastradh {
286656053ce7Sriastradh struct detailed_mode_closure closure = {
28674e59feabSriastradh .connector = connector,
28684e59feabSriastradh .edid = edid,
286956053ce7Sriastradh };
287056053ce7Sriastradh
287156053ce7Sriastradh if (version_greater(edid, 1, 0))
287256053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
287356053ce7Sriastradh &closure);
287456053ce7Sriastradh
287556053ce7Sriastradh return closure.modes;
287656053ce7Sriastradh }
287756053ce7Sriastradh
287856053ce7Sriastradh static int
drm_est3_modes(struct drm_connector * connector,struct detailed_timing * timing)287956053ce7Sriastradh drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
288056053ce7Sriastradh {
288156053ce7Sriastradh int i, j, m, modes = 0;
288256053ce7Sriastradh struct drm_display_mode *mode;
2883677dec6eSriastradh u8 *est = ((u8 *)timing) + 6;
288456053ce7Sriastradh
288556053ce7Sriastradh for (i = 0; i < 6; i++) {
2886a55ed7faSriastradh for (j = 7; j >= 0; j--) {
288756053ce7Sriastradh m = (i * 8) + (7 - j);
288856053ce7Sriastradh if (m >= ARRAY_SIZE(est3_modes))
288956053ce7Sriastradh break;
289056053ce7Sriastradh if (est[i] & (1 << j)) {
289156053ce7Sriastradh mode = drm_mode_find_dmt(connector->dev,
289256053ce7Sriastradh est3_modes[m].w,
289356053ce7Sriastradh est3_modes[m].h,
289456053ce7Sriastradh est3_modes[m].r,
289556053ce7Sriastradh est3_modes[m].rb);
289656053ce7Sriastradh if (mode) {
289756053ce7Sriastradh drm_mode_probed_add(connector, mode);
289856053ce7Sriastradh modes++;
289956053ce7Sriastradh }
290056053ce7Sriastradh }
290156053ce7Sriastradh }
290256053ce7Sriastradh }
290356053ce7Sriastradh
290456053ce7Sriastradh return modes;
290556053ce7Sriastradh }
290656053ce7Sriastradh
290756053ce7Sriastradh static void
do_established_modes(struct detailed_timing * timing,void * c)290856053ce7Sriastradh do_established_modes(struct detailed_timing *timing, void *c)
290956053ce7Sriastradh {
291056053ce7Sriastradh struct detailed_mode_closure *closure = c;
291156053ce7Sriastradh struct detailed_non_pixel *data = &timing->data.other_data;
291256053ce7Sriastradh
291356053ce7Sriastradh if (data->type == EDID_DETAIL_EST_TIMINGS)
291456053ce7Sriastradh closure->modes += drm_est3_modes(closure->connector, timing);
291556053ce7Sriastradh }
291656053ce7Sriastradh
291756053ce7Sriastradh /**
291856053ce7Sriastradh * add_established_modes - get est. modes from EDID and add them
29194e59feabSriastradh * @connector: connector to add mode(s) to
292056053ce7Sriastradh * @edid: EDID block to scan
292156053ce7Sriastradh *
292256053ce7Sriastradh * Each EDID block contains a bitmap of the supported "established modes" list
292356053ce7Sriastradh * (defined above). Tease them out and add them to the global modes list.
292456053ce7Sriastradh */
292556053ce7Sriastradh static int
add_established_modes(struct drm_connector * connector,struct edid * edid)292656053ce7Sriastradh add_established_modes(struct drm_connector *connector, struct edid *edid)
292756053ce7Sriastradh {
292856053ce7Sriastradh struct drm_device *dev = connector->dev;
292956053ce7Sriastradh unsigned long est_bits = edid->established_timings.t1 |
293056053ce7Sriastradh (edid->established_timings.t2 << 8) |
293156053ce7Sriastradh ((edid->established_timings.mfg_rsvd & 0x80) << 9);
293256053ce7Sriastradh int i, modes = 0;
293356053ce7Sriastradh struct detailed_mode_closure closure = {
29344e59feabSriastradh .connector = connector,
29354e59feabSriastradh .edid = edid,
293656053ce7Sriastradh };
293756053ce7Sriastradh
293856053ce7Sriastradh for (i = 0; i <= EDID_EST_TIMINGS; i++) {
293956053ce7Sriastradh if (est_bits & (1<<i)) {
294056053ce7Sriastradh struct drm_display_mode *newmode;
294156053ce7Sriastradh newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
294256053ce7Sriastradh if (newmode) {
294356053ce7Sriastradh drm_mode_probed_add(connector, newmode);
294456053ce7Sriastradh modes++;
294556053ce7Sriastradh }
294656053ce7Sriastradh }
294756053ce7Sriastradh }
294856053ce7Sriastradh
294956053ce7Sriastradh if (version_greater(edid, 1, 0))
295056053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid,
295156053ce7Sriastradh do_established_modes, &closure);
295256053ce7Sriastradh
295356053ce7Sriastradh return modes + closure.modes;
295456053ce7Sriastradh }
295556053ce7Sriastradh
295656053ce7Sriastradh static void
do_standard_modes(struct detailed_timing * timing,void * c)295756053ce7Sriastradh do_standard_modes(struct detailed_timing *timing, void *c)
295856053ce7Sriastradh {
295956053ce7Sriastradh struct detailed_mode_closure *closure = c;
296056053ce7Sriastradh struct detailed_non_pixel *data = &timing->data.other_data;
296156053ce7Sriastradh struct drm_connector *connector = closure->connector;
296256053ce7Sriastradh struct edid *edid = closure->edid;
296356053ce7Sriastradh
296456053ce7Sriastradh if (data->type == EDID_DETAIL_STD_MODES) {
296556053ce7Sriastradh int i;
296656053ce7Sriastradh for (i = 0; i < 6; i++) {
296756053ce7Sriastradh struct std_timing *std;
296856053ce7Sriastradh struct drm_display_mode *newmode;
296956053ce7Sriastradh
297056053ce7Sriastradh std = &data->data.timings[i];
29714e59feabSriastradh newmode = drm_mode_std(connector, edid, std);
297256053ce7Sriastradh if (newmode) {
297356053ce7Sriastradh drm_mode_probed_add(connector, newmode);
297456053ce7Sriastradh closure->modes++;
297556053ce7Sriastradh }
297656053ce7Sriastradh }
297756053ce7Sriastradh }
297856053ce7Sriastradh }
297956053ce7Sriastradh
298056053ce7Sriastradh /**
298156053ce7Sriastradh * add_standard_modes - get std. modes from EDID and add them
29824e59feabSriastradh * @connector: connector to add mode(s) to
298356053ce7Sriastradh * @edid: EDID block to scan
298456053ce7Sriastradh *
298556053ce7Sriastradh * Standard modes can be calculated using the appropriate standard (DMT,
298656053ce7Sriastradh * GTF or CVT. Grab them from @edid and add them to the list.
298756053ce7Sriastradh */
298856053ce7Sriastradh static int
add_standard_modes(struct drm_connector * connector,struct edid * edid)298956053ce7Sriastradh add_standard_modes(struct drm_connector *connector, struct edid *edid)
299056053ce7Sriastradh {
299156053ce7Sriastradh int i, modes = 0;
299256053ce7Sriastradh struct detailed_mode_closure closure = {
29934e59feabSriastradh .connector = connector,
29944e59feabSriastradh .edid = edid,
299556053ce7Sriastradh };
299656053ce7Sriastradh
299756053ce7Sriastradh for (i = 0; i < EDID_STD_TIMINGS; i++) {
299856053ce7Sriastradh struct drm_display_mode *newmode;
299956053ce7Sriastradh
300056053ce7Sriastradh newmode = drm_mode_std(connector, edid,
30014e59feabSriastradh &edid->standard_timings[i]);
300256053ce7Sriastradh if (newmode) {
300356053ce7Sriastradh drm_mode_probed_add(connector, newmode);
300456053ce7Sriastradh modes++;
300556053ce7Sriastradh }
300656053ce7Sriastradh }
300756053ce7Sriastradh
300856053ce7Sriastradh if (version_greater(edid, 1, 0))
300956053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
301056053ce7Sriastradh &closure);
301156053ce7Sriastradh
301256053ce7Sriastradh /* XXX should also look for standard codes in VTB blocks */
301356053ce7Sriastradh
301456053ce7Sriastradh return modes + closure.modes;
301556053ce7Sriastradh }
301656053ce7Sriastradh
drm_cvt_modes(struct drm_connector * connector,struct detailed_timing * timing)301756053ce7Sriastradh static int drm_cvt_modes(struct drm_connector *connector,
301856053ce7Sriastradh struct detailed_timing *timing)
301956053ce7Sriastradh {
302056053ce7Sriastradh int i, j, modes = 0;
302156053ce7Sriastradh struct drm_display_mode *newmode;
302256053ce7Sriastradh struct drm_device *dev = connector->dev;
302356053ce7Sriastradh struct cvt_timing *cvt;
302456053ce7Sriastradh const int rates[] = { 60, 85, 75, 60, 50 };
302556053ce7Sriastradh const u8 empty[3] = { 0, 0, 0 };
302656053ce7Sriastradh
302756053ce7Sriastradh for (i = 0; i < 4; i++) {
302856053ce7Sriastradh int uninitialized_var(width), height;
302956053ce7Sriastradh cvt = &(timing->data.other_data.data.cvt[i]);
303056053ce7Sriastradh
303156053ce7Sriastradh if (!memcmp(cvt->code, empty, 3))
303256053ce7Sriastradh continue;
303356053ce7Sriastradh
303456053ce7Sriastradh height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
303556053ce7Sriastradh switch (cvt->code[1] & 0x0c) {
303656053ce7Sriastradh case 0x00:
303756053ce7Sriastradh width = height * 4 / 3;
303856053ce7Sriastradh break;
303956053ce7Sriastradh case 0x04:
304056053ce7Sriastradh width = height * 16 / 9;
304156053ce7Sriastradh break;
304256053ce7Sriastradh case 0x08:
304356053ce7Sriastradh width = height * 16 / 10;
304456053ce7Sriastradh break;
304556053ce7Sriastradh case 0x0c:
304656053ce7Sriastradh width = height * 15 / 9;
304756053ce7Sriastradh break;
304856053ce7Sriastradh }
304956053ce7Sriastradh
305056053ce7Sriastradh for (j = 1; j < 5; j++) {
305156053ce7Sriastradh if (cvt->code[2] & (1 << j)) {
305256053ce7Sriastradh newmode = drm_cvt_mode(dev, width, height,
305356053ce7Sriastradh rates[j], j == 0,
305456053ce7Sriastradh false, false);
305556053ce7Sriastradh if (newmode) {
305656053ce7Sriastradh drm_mode_probed_add(connector, newmode);
305756053ce7Sriastradh modes++;
305856053ce7Sriastradh }
305956053ce7Sriastradh }
306056053ce7Sriastradh }
306156053ce7Sriastradh }
306256053ce7Sriastradh
306356053ce7Sriastradh return modes;
306456053ce7Sriastradh }
306556053ce7Sriastradh
306656053ce7Sriastradh static void
do_cvt_mode(struct detailed_timing * timing,void * c)306756053ce7Sriastradh do_cvt_mode(struct detailed_timing *timing, void *c)
306856053ce7Sriastradh {
306956053ce7Sriastradh struct detailed_mode_closure *closure = c;
307056053ce7Sriastradh struct detailed_non_pixel *data = &timing->data.other_data;
307156053ce7Sriastradh
307256053ce7Sriastradh if (data->type == EDID_DETAIL_CVT_3BYTE)
307356053ce7Sriastradh closure->modes += drm_cvt_modes(closure->connector, timing);
307456053ce7Sriastradh }
307556053ce7Sriastradh
307656053ce7Sriastradh static int
add_cvt_modes(struct drm_connector * connector,struct edid * edid)307756053ce7Sriastradh add_cvt_modes(struct drm_connector *connector, struct edid *edid)
307856053ce7Sriastradh {
307956053ce7Sriastradh struct detailed_mode_closure closure = {
30804e59feabSriastradh .connector = connector,
30814e59feabSriastradh .edid = edid,
308256053ce7Sriastradh };
308356053ce7Sriastradh
308456053ce7Sriastradh if (version_greater(edid, 1, 2))
308556053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
308656053ce7Sriastradh
308756053ce7Sriastradh /* XXX should also look for CVT codes in VTB blocks */
308856053ce7Sriastradh
308956053ce7Sriastradh return closure.modes;
309056053ce7Sriastradh }
309156053ce7Sriastradh
30924e59feabSriastradh static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
30934e59feabSriastradh
309456053ce7Sriastradh static void
do_detailed_mode(struct detailed_timing * timing,void * c)309556053ce7Sriastradh do_detailed_mode(struct detailed_timing *timing, void *c)
309656053ce7Sriastradh {
309756053ce7Sriastradh struct detailed_mode_closure *closure = c;
309856053ce7Sriastradh struct drm_display_mode *newmode;
309956053ce7Sriastradh
310056053ce7Sriastradh if (timing->pixel_clock) {
310156053ce7Sriastradh newmode = drm_mode_detailed(closure->connector->dev,
310256053ce7Sriastradh closure->edid, timing,
310356053ce7Sriastradh closure->quirks);
310456053ce7Sriastradh if (!newmode)
310556053ce7Sriastradh return;
310656053ce7Sriastradh
310756053ce7Sriastradh if (closure->preferred)
310856053ce7Sriastradh newmode->type |= DRM_MODE_TYPE_PREFERRED;
310956053ce7Sriastradh
31104e59feabSriastradh /*
31114e59feabSriastradh * Detailed modes are limited to 10kHz pixel clock resolution,
31124e59feabSriastradh * so fix up anything that looks like CEA/HDMI mode, but the clock
31134e59feabSriastradh * is just slightly off.
31144e59feabSriastradh */
31154e59feabSriastradh fixup_detailed_cea_mode_clock(newmode);
31164e59feabSriastradh
311756053ce7Sriastradh drm_mode_probed_add(closure->connector, newmode);
311856053ce7Sriastradh closure->modes++;
3119677dec6eSriastradh closure->preferred = false;
312056053ce7Sriastradh }
312156053ce7Sriastradh }
312256053ce7Sriastradh
312356053ce7Sriastradh /*
312456053ce7Sriastradh * add_detailed_modes - Add modes from detailed timings
312556053ce7Sriastradh * @connector: attached connector
312656053ce7Sriastradh * @edid: EDID block to scan
312756053ce7Sriastradh * @quirks: quirks to apply
312856053ce7Sriastradh */
312956053ce7Sriastradh static int
add_detailed_modes(struct drm_connector * connector,struct edid * edid,u32 quirks)313056053ce7Sriastradh add_detailed_modes(struct drm_connector *connector, struct edid *edid,
313156053ce7Sriastradh u32 quirks)
313256053ce7Sriastradh {
313356053ce7Sriastradh struct detailed_mode_closure closure = {
31344e59feabSriastradh .connector = connector,
31354e59feabSriastradh .edid = edid,
3136677dec6eSriastradh .preferred = true,
31374e59feabSriastradh .quirks = quirks,
313856053ce7Sriastradh };
313956053ce7Sriastradh
314056053ce7Sriastradh if (closure.preferred && !version_greater(edid, 1, 3))
314156053ce7Sriastradh closure.preferred =
314256053ce7Sriastradh (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
314356053ce7Sriastradh
314456053ce7Sriastradh drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
314556053ce7Sriastradh
314656053ce7Sriastradh return closure.modes;
314756053ce7Sriastradh }
314856053ce7Sriastradh
314956053ce7Sriastradh #define AUDIO_BLOCK 0x01
315056053ce7Sriastradh #define VIDEO_BLOCK 0x02
315156053ce7Sriastradh #define VENDOR_BLOCK 0x03
315256053ce7Sriastradh #define SPEAKER_BLOCK 0x04
3153677dec6eSriastradh #define HDR_STATIC_METADATA_BLOCK 0x6
3154677dec6eSriastradh #define USE_EXTENDED_TAG 0x07
3155677dec6eSriastradh #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3156677dec6eSriastradh #define EXT_VIDEO_DATA_BLOCK_420 0x0E
3157677dec6eSriastradh #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
315856053ce7Sriastradh #define EDID_BASIC_AUDIO (1 << 6)
315956053ce7Sriastradh #define EDID_CEA_YCRCB444 (1 << 5)
316056053ce7Sriastradh #define EDID_CEA_YCRCB422 (1 << 4)
3161a55ed7faSriastradh #define EDID_CEA_VCDB_QS (1 << 6)
316256053ce7Sriastradh
3163a55ed7faSriastradh /*
316456053ce7Sriastradh * Search EDID for CEA extension block.
316556053ce7Sriastradh */
drm_find_edid_extension(const struct edid * edid,int ext_id)31662cbe17a3Sriastradh static const u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
316756053ce7Sriastradh {
31689a10ff95Sriastradh const u8 *edid_ext = NULL;
316956053ce7Sriastradh int i;
317056053ce7Sriastradh
317156053ce7Sriastradh /* No EDID or EDID extensions */
317256053ce7Sriastradh if (edid == NULL || edid->extensions == 0)
317356053ce7Sriastradh return NULL;
317456053ce7Sriastradh
317556053ce7Sriastradh /* Find CEA extension */
317656053ce7Sriastradh for (i = 0; i < edid->extensions; i++) {
31778e465d8aSriastradh edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1);
31784e59feabSriastradh if (edid_ext[0] == ext_id)
317956053ce7Sriastradh break;
318056053ce7Sriastradh }
318156053ce7Sriastradh
318256053ce7Sriastradh if (i == edid->extensions)
318356053ce7Sriastradh return NULL;
318456053ce7Sriastradh
318556053ce7Sriastradh return edid_ext;
318656053ce7Sriastradh }
318756053ce7Sriastradh
31884e59feabSriastradh
drm_find_displayid_extension(const struct edid * edid)318957b58161Sriastradh static const u8 *drm_find_displayid_extension(const struct edid *edid)
31904e59feabSriastradh {
31914e59feabSriastradh return drm_find_edid_extension(edid, DISPLAYID_EXT);
31924e59feabSriastradh }
31934e59feabSriastradh
drm_find_cea_extension(const struct edid * edid)31942cbe17a3Sriastradh static const u8 *drm_find_cea_extension(const struct edid *edid)
3195677dec6eSriastradh {
3196677dec6eSriastradh int ret;
3197677dec6eSriastradh int idx = 1;
3198677dec6eSriastradh int length = EDID_LENGTH;
319957b58161Sriastradh const struct displayid_block *block;
320057b58161Sriastradh const u8 *cea;
320157b58161Sriastradh const u8 *displayid;
3202677dec6eSriastradh
3203677dec6eSriastradh /* Look for a top level CEA extension block */
3204677dec6eSriastradh cea = drm_find_edid_extension(edid, CEA_EXT);
3205677dec6eSriastradh if (cea)
3206677dec6eSriastradh return cea;
3207677dec6eSriastradh
3208677dec6eSriastradh /* CEA blocks can also be found embedded in a DisplayID block */
3209677dec6eSriastradh displayid = drm_find_displayid_extension(edid);
3210677dec6eSriastradh if (!displayid)
3211677dec6eSriastradh return NULL;
3212677dec6eSriastradh
3213677dec6eSriastradh ret = validate_displayid(displayid, length, idx);
3214677dec6eSriastradh if (ret)
3215677dec6eSriastradh return NULL;
3216677dec6eSriastradh
3217677dec6eSriastradh idx += sizeof(struct displayid_hdr);
3218677dec6eSriastradh for_each_displayid_db(displayid, block, idx, length) {
3219677dec6eSriastradh if (block->tag == DATA_BLOCK_CTA) {
322057b58161Sriastradh cea = (const u8 *)block;
3221677dec6eSriastradh break;
3222677dec6eSriastradh }
3223677dec6eSriastradh }
3224677dec6eSriastradh
3225677dec6eSriastradh return cea;
3226677dec6eSriastradh }
3227677dec6eSriastradh
cea_mode_for_vic(u8 vic)3228677dec6eSriastradh static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3229677dec6eSriastradh {
3230677dec6eSriastradh BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3231677dec6eSriastradh BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3232677dec6eSriastradh
3233677dec6eSriastradh if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3234677dec6eSriastradh return &edid_cea_modes_1[vic - 1];
3235677dec6eSriastradh if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3236677dec6eSriastradh return &edid_cea_modes_193[vic - 193];
3237677dec6eSriastradh return NULL;
3238677dec6eSriastradh }
3239677dec6eSriastradh
cea_num_vics(void)3240677dec6eSriastradh static u8 cea_num_vics(void)
3241677dec6eSriastradh {
3242677dec6eSriastradh return 193 + ARRAY_SIZE(edid_cea_modes_193);
3243677dec6eSriastradh }
3244677dec6eSriastradh
cea_next_vic(u8 vic)3245677dec6eSriastradh static u8 cea_next_vic(u8 vic)
3246677dec6eSriastradh {
3247677dec6eSriastradh if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3248677dec6eSriastradh vic = 193;
3249677dec6eSriastradh return vic;
3250677dec6eSriastradh }
3251677dec6eSriastradh
325256053ce7Sriastradh /*
3253a55ed7faSriastradh * Calculate the alternate clock for the CEA mode
3254a55ed7faSriastradh * (60Hz vs. 59.94Hz etc.)
325556053ce7Sriastradh */
3256a55ed7faSriastradh static unsigned int
cea_mode_alternate_clock(const struct drm_display_mode * cea_mode)3257a55ed7faSriastradh cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
325856053ce7Sriastradh {
3259a55ed7faSriastradh unsigned int clock = cea_mode->clock;
3260a55ed7faSriastradh
3261a55ed7faSriastradh if (cea_mode->vrefresh % 6 != 0)
3262a55ed7faSriastradh return clock;
3263a55ed7faSriastradh
3264a55ed7faSriastradh /*
3265a55ed7faSriastradh * edid_cea_modes contains the 59.94Hz
3266a55ed7faSriastradh * variant for 240 and 480 line modes,
3267a55ed7faSriastradh * and the 60Hz variant otherwise.
3268a55ed7faSriastradh */
3269a55ed7faSriastradh if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
32704e59feabSriastradh clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3271a55ed7faSriastradh else
32724e59feabSriastradh clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3273a55ed7faSriastradh
3274a55ed7faSriastradh return clock;
3275a55ed7faSriastradh }
3276a55ed7faSriastradh
3277677dec6eSriastradh static bool
cea_mode_alternate_timings(u8 vic,struct drm_display_mode * mode)3278677dec6eSriastradh cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3279677dec6eSriastradh {
3280677dec6eSriastradh /*
3281677dec6eSriastradh * For certain VICs the spec allows the vertical
3282677dec6eSriastradh * front porch to vary by one or two lines.
3283677dec6eSriastradh *
3284677dec6eSriastradh * cea_modes[] stores the variant with the shortest
3285677dec6eSriastradh * vertical front porch. We can adjust the mode to
3286677dec6eSriastradh * get the other variants by simply increasing the
3287677dec6eSriastradh * vertical front porch length.
3288677dec6eSriastradh */
3289677dec6eSriastradh BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3290677dec6eSriastradh cea_mode_for_vic(9)->vtotal != 262 ||
3291677dec6eSriastradh cea_mode_for_vic(12)->vtotal != 262 ||
3292677dec6eSriastradh cea_mode_for_vic(13)->vtotal != 262 ||
3293677dec6eSriastradh cea_mode_for_vic(23)->vtotal != 312 ||
3294677dec6eSriastradh cea_mode_for_vic(24)->vtotal != 312 ||
3295677dec6eSriastradh cea_mode_for_vic(27)->vtotal != 312 ||
3296677dec6eSriastradh cea_mode_for_vic(28)->vtotal != 312);
3297677dec6eSriastradh
3298677dec6eSriastradh if (((vic == 8 || vic == 9 ||
3299677dec6eSriastradh vic == 12 || vic == 13) && mode->vtotal < 263) ||
3300677dec6eSriastradh ((vic == 23 || vic == 24 ||
3301677dec6eSriastradh vic == 27 || vic == 28) && mode->vtotal < 314)) {
3302677dec6eSriastradh mode->vsync_start++;
3303677dec6eSriastradh mode->vsync_end++;
3304677dec6eSriastradh mode->vtotal++;
3305677dec6eSriastradh
3306677dec6eSriastradh return true;
3307677dec6eSriastradh }
3308677dec6eSriastradh
3309677dec6eSriastradh return false;
3310677dec6eSriastradh }
3311677dec6eSriastradh
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3312677dec6eSriastradh static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3313677dec6eSriastradh unsigned int clock_tolerance)
3314677dec6eSriastradh {
3315677dec6eSriastradh unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3316677dec6eSriastradh u8 vic;
3317677dec6eSriastradh
3318677dec6eSriastradh if (!to_match->clock)
3319677dec6eSriastradh return 0;
3320677dec6eSriastradh
3321677dec6eSriastradh if (to_match->picture_aspect_ratio)
3322677dec6eSriastradh match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3323677dec6eSriastradh
3324677dec6eSriastradh for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3325677dec6eSriastradh struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3326677dec6eSriastradh unsigned int clock1, clock2;
3327677dec6eSriastradh
3328677dec6eSriastradh /* Check both 60Hz and 59.94Hz */
3329677dec6eSriastradh clock1 = cea_mode.clock;
3330677dec6eSriastradh clock2 = cea_mode_alternate_clock(&cea_mode);
3331677dec6eSriastradh
3332677dec6eSriastradh if (abs(to_match->clock - clock1) > clock_tolerance &&
3333677dec6eSriastradh abs(to_match->clock - clock2) > clock_tolerance)
3334677dec6eSriastradh continue;
3335677dec6eSriastradh
3336677dec6eSriastradh do {
3337677dec6eSriastradh if (drm_mode_match(to_match, &cea_mode, match_flags))
3338677dec6eSriastradh return vic;
3339677dec6eSriastradh } while (cea_mode_alternate_timings(vic, &cea_mode));
3340677dec6eSriastradh }
3341677dec6eSriastradh
3342677dec6eSriastradh return 0;
3343677dec6eSriastradh }
3344677dec6eSriastradh
3345a55ed7faSriastradh /**
3346a55ed7faSriastradh * drm_match_cea_mode - look for a CEA mode matching given mode
3347a55ed7faSriastradh * @to_match: display mode
3348a55ed7faSriastradh *
33494e59feabSriastradh * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3350a55ed7faSriastradh * mode.
3351a55ed7faSriastradh */
drm_match_cea_mode(const struct drm_display_mode * to_match)3352a55ed7faSriastradh u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3353a55ed7faSriastradh {
3354677dec6eSriastradh unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3355677dec6eSriastradh u8 vic;
335656053ce7Sriastradh
3357a55ed7faSriastradh if (!to_match->clock)
3358a55ed7faSriastradh return 0;
335956053ce7Sriastradh
3360677dec6eSriastradh if (to_match->picture_aspect_ratio)
3361677dec6eSriastradh match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3362677dec6eSriastradh
3363677dec6eSriastradh for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3364677dec6eSriastradh struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3365a55ed7faSriastradh unsigned int clock1, clock2;
3366a55ed7faSriastradh
3367a55ed7faSriastradh /* Check both 60Hz and 59.94Hz */
3368677dec6eSriastradh clock1 = cea_mode.clock;
3369677dec6eSriastradh clock2 = cea_mode_alternate_clock(&cea_mode);
3370a55ed7faSriastradh
3371677dec6eSriastradh if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3372677dec6eSriastradh KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3373677dec6eSriastradh continue;
3374677dec6eSriastradh
3375677dec6eSriastradh do {
3376677dec6eSriastradh if (drm_mode_match(to_match, &cea_mode, match_flags))
3377677dec6eSriastradh return vic;
3378677dec6eSriastradh } while (cea_mode_alternate_timings(vic, &cea_mode));
337956053ce7Sriastradh }
3380677dec6eSriastradh
338156053ce7Sriastradh return 0;
338256053ce7Sriastradh }
338356053ce7Sriastradh EXPORT_SYMBOL(drm_match_cea_mode);
338456053ce7Sriastradh
drm_valid_cea_vic(u8 vic)3385677dec6eSriastradh static bool drm_valid_cea_vic(u8 vic)
33864e59feabSriastradh {
3387677dec6eSriastradh return cea_mode_for_vic(vic) != NULL;
33884e59feabSriastradh }
3389677dec6eSriastradh
drm_get_cea_aspect_ratio(const u8 video_code)3390677dec6eSriastradh static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3391677dec6eSriastradh {
3392677dec6eSriastradh const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3393677dec6eSriastradh
3394677dec6eSriastradh if (mode)
3395677dec6eSriastradh return mode->picture_aspect_ratio;
3396677dec6eSriastradh
3397677dec6eSriastradh return HDMI_PICTURE_ASPECT_NONE;
3398677dec6eSriastradh }
3399677dec6eSriastradh
drm_get_hdmi_aspect_ratio(const u8 video_code)3400677dec6eSriastradh static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3401677dec6eSriastradh {
3402677dec6eSriastradh return edid_4k_modes[video_code].picture_aspect_ratio;
3403677dec6eSriastradh }
34044e59feabSriastradh
3405a55ed7faSriastradh /*
3406a55ed7faSriastradh * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3407a55ed7faSriastradh * specific block).
3408a55ed7faSriastradh */
3409a55ed7faSriastradh static unsigned int
hdmi_mode_alternate_clock(const struct drm_display_mode * hdmi_mode)3410a55ed7faSriastradh hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3411a55ed7faSriastradh {
3412a55ed7faSriastradh return cea_mode_alternate_clock(hdmi_mode);
3413a55ed7faSriastradh }
3414a55ed7faSriastradh
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)3415677dec6eSriastradh static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3416677dec6eSriastradh unsigned int clock_tolerance)
3417677dec6eSriastradh {
3418677dec6eSriastradh unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3419677dec6eSriastradh u8 vic;
3420677dec6eSriastradh
3421677dec6eSriastradh if (!to_match->clock)
3422677dec6eSriastradh return 0;
3423677dec6eSriastradh
3424677dec6eSriastradh if (to_match->picture_aspect_ratio)
3425677dec6eSriastradh match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3426677dec6eSriastradh
3427677dec6eSriastradh for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3428677dec6eSriastradh const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3429677dec6eSriastradh unsigned int clock1, clock2;
3430677dec6eSriastradh
3431677dec6eSriastradh /* Make sure to also match alternate clocks */
3432677dec6eSriastradh clock1 = hdmi_mode->clock;
3433677dec6eSriastradh clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3434677dec6eSriastradh
3435677dec6eSriastradh if (abs(to_match->clock - clock1) > clock_tolerance &&
3436677dec6eSriastradh abs(to_match->clock - clock2) > clock_tolerance)
3437677dec6eSriastradh continue;
3438677dec6eSriastradh
3439677dec6eSriastradh if (drm_mode_match(to_match, hdmi_mode, match_flags))
3440677dec6eSriastradh return vic;
3441677dec6eSriastradh }
3442677dec6eSriastradh
3443677dec6eSriastradh return 0;
3444677dec6eSriastradh }
3445677dec6eSriastradh
3446a55ed7faSriastradh /*
3447a55ed7faSriastradh * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3448a55ed7faSriastradh * @to_match: display mode
3449a55ed7faSriastradh *
3450a55ed7faSriastradh * An HDMI mode is one defined in the HDMI vendor specific block.
3451a55ed7faSriastradh *
3452a55ed7faSriastradh * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3453a55ed7faSriastradh */
drm_match_hdmi_mode(const struct drm_display_mode * to_match)3454a55ed7faSriastradh static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3455a55ed7faSriastradh {
3456677dec6eSriastradh unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3457677dec6eSriastradh u8 vic;
3458a55ed7faSriastradh
3459a55ed7faSriastradh if (!to_match->clock)
3460a55ed7faSriastradh return 0;
3461a55ed7faSriastradh
3462677dec6eSriastradh if (to_match->picture_aspect_ratio)
3463677dec6eSriastradh match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3464677dec6eSriastradh
3465677dec6eSriastradh for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3466677dec6eSriastradh const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3467a55ed7faSriastradh unsigned int clock1, clock2;
3468a55ed7faSriastradh
3469a55ed7faSriastradh /* Make sure to also match alternate clocks */
3470a55ed7faSriastradh clock1 = hdmi_mode->clock;
3471a55ed7faSriastradh clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3472a55ed7faSriastradh
3473a55ed7faSriastradh if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3474a55ed7faSriastradh KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3475677dec6eSriastradh drm_mode_match(to_match, hdmi_mode, match_flags))
3476677dec6eSriastradh return vic;
3477a55ed7faSriastradh }
3478a55ed7faSriastradh return 0;
3479a55ed7faSriastradh }
348056053ce7Sriastradh
drm_valid_hdmi_vic(u8 vic)3481677dec6eSriastradh static bool drm_valid_hdmi_vic(u8 vic)
3482677dec6eSriastradh {
3483677dec6eSriastradh return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3484677dec6eSriastradh }
3485677dec6eSriastradh
348656053ce7Sriastradh static int
add_alternate_cea_modes(struct drm_connector * connector,struct edid * edid)3487a55ed7faSriastradh add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
348856053ce7Sriastradh {
348956053ce7Sriastradh struct drm_device *dev = connector->dev;
3490a55ed7faSriastradh struct drm_display_mode *mode, *tmp;
3491aa66f76bSriastradh LIST_HEAD(list);
349256053ce7Sriastradh int modes = 0;
349356053ce7Sriastradh
3494a55ed7faSriastradh /* Don't add CEA modes if the CEA extension block is missing */
3495a55ed7faSriastradh if (!drm_find_cea_extension(edid))
3496a55ed7faSriastradh return 0;
3497a55ed7faSriastradh
3498a55ed7faSriastradh /*
3499a55ed7faSriastradh * Go through all probed modes and create a new mode
3500a55ed7faSriastradh * with the alternate clock for certain CEA modes.
3501a55ed7faSriastradh */
3502a55ed7faSriastradh list_for_each_entry(mode, &connector->probed_modes, head) {
3503a55ed7faSriastradh const struct drm_display_mode *cea_mode = NULL;
350456053ce7Sriastradh struct drm_display_mode *newmode;
3505677dec6eSriastradh u8 vic = drm_match_cea_mode(mode);
3506a55ed7faSriastradh unsigned int clock1, clock2;
3507a55ed7faSriastradh
3508677dec6eSriastradh if (drm_valid_cea_vic(vic)) {
3509677dec6eSriastradh cea_mode = cea_mode_for_vic(vic);
3510a55ed7faSriastradh clock2 = cea_mode_alternate_clock(cea_mode);
3511a55ed7faSriastradh } else {
3512677dec6eSriastradh vic = drm_match_hdmi_mode(mode);
3513677dec6eSriastradh if (drm_valid_hdmi_vic(vic)) {
3514677dec6eSriastradh cea_mode = &edid_4k_modes[vic];
3515a55ed7faSriastradh clock2 = hdmi_mode_alternate_clock(cea_mode);
3516a55ed7faSriastradh }
3517a55ed7faSriastradh }
3518a55ed7faSriastradh
3519a55ed7faSriastradh if (!cea_mode)
3520a55ed7faSriastradh continue;
3521a55ed7faSriastradh
3522a55ed7faSriastradh clock1 = cea_mode->clock;
3523a55ed7faSriastradh
3524a55ed7faSriastradh if (clock1 == clock2)
3525a55ed7faSriastradh continue;
3526a55ed7faSriastradh
3527a55ed7faSriastradh if (mode->clock != clock1 && mode->clock != clock2)
3528a55ed7faSriastradh continue;
3529a55ed7faSriastradh
3530a55ed7faSriastradh newmode = drm_mode_duplicate(dev, cea_mode);
3531a55ed7faSriastradh if (!newmode)
3532a55ed7faSriastradh continue;
3533a55ed7faSriastradh
3534a55ed7faSriastradh /* Carry over the stereo flags */
3535a55ed7faSriastradh newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3536a55ed7faSriastradh
3537a55ed7faSriastradh /*
3538a55ed7faSriastradh * The current mode could be either variant. Make
3539a55ed7faSriastradh * sure to pick the "other" clock for the new mode.
3540a55ed7faSriastradh */
3541a55ed7faSriastradh if (mode->clock != clock1)
3542a55ed7faSriastradh newmode->clock = clock1;
3543a55ed7faSriastradh else
3544a55ed7faSriastradh newmode->clock = clock2;
3545a55ed7faSriastradh
3546a55ed7faSriastradh list_add_tail(&newmode->head, &list);
3547a55ed7faSriastradh }
3548a55ed7faSriastradh
3549a55ed7faSriastradh list_for_each_entry_safe(mode, tmp, &list, head) {
3550a55ed7faSriastradh list_del(&mode->head);
3551a55ed7faSriastradh drm_mode_probed_add(connector, mode);
3552a55ed7faSriastradh modes++;
3553a55ed7faSriastradh }
3554a55ed7faSriastradh
3555a55ed7faSriastradh return modes;
3556a55ed7faSriastradh }
3557a55ed7faSriastradh
svd_to_vic(u8 svd)3558677dec6eSriastradh static u8 svd_to_vic(u8 svd)
3559677dec6eSriastradh {
3560677dec6eSriastradh /* 0-6 bit vic, 7th bit native mode indicator */
3561677dec6eSriastradh if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3562677dec6eSriastradh return svd & 127;
3563677dec6eSriastradh
3564677dec6eSriastradh return svd;
3565677dec6eSriastradh }
3566677dec6eSriastradh
3567a55ed7faSriastradh static struct drm_display_mode *
drm_display_mode_from_vic_index(struct drm_connector * connector,const u8 * video_db,u8 video_len,u8 video_index)3568a55ed7faSriastradh drm_display_mode_from_vic_index(struct drm_connector *connector,
3569a55ed7faSriastradh const u8 *video_db, u8 video_len,
3570a55ed7faSriastradh u8 video_index)
3571a55ed7faSriastradh {
3572a55ed7faSriastradh struct drm_device *dev = connector->dev;
3573a55ed7faSriastradh struct drm_display_mode *newmode;
3574677dec6eSriastradh u8 vic;
3575a55ed7faSriastradh
3576a55ed7faSriastradh if (video_db == NULL || video_index >= video_len)
3577a55ed7faSriastradh return NULL;
3578a55ed7faSriastradh
3579a55ed7faSriastradh /* CEA modes are numbered 1..127 */
3580677dec6eSriastradh vic = svd_to_vic(video_db[video_index]);
3581677dec6eSriastradh if (!drm_valid_cea_vic(vic))
3582a55ed7faSriastradh return NULL;
3583a55ed7faSriastradh
3584677dec6eSriastradh newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3585a55ed7faSriastradh if (!newmode)
3586a55ed7faSriastradh return NULL;
3587a55ed7faSriastradh
3588a55ed7faSriastradh newmode->vrefresh = 0;
3589a55ed7faSriastradh
3590a55ed7faSriastradh return newmode;
3591a55ed7faSriastradh }
3592a55ed7faSriastradh
3593677dec6eSriastradh /*
3594677dec6eSriastradh * do_y420vdb_modes - Parse YCBCR 420 only modes
3595677dec6eSriastradh * @connector: connector corresponding to the HDMI sink
3596677dec6eSriastradh * @svds: start of the data block of CEA YCBCR 420 VDB
3597677dec6eSriastradh * @len: length of the CEA YCBCR 420 VDB
3598677dec6eSriastradh *
3599677dec6eSriastradh * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3600677dec6eSriastradh * which contains modes which can be supported in YCBCR 420
3601677dec6eSriastradh * output format only.
3602677dec6eSriastradh */
do_y420vdb_modes(struct drm_connector * connector,const u8 * svds,u8 svds_len)3603677dec6eSriastradh static int do_y420vdb_modes(struct drm_connector *connector,
3604677dec6eSriastradh const u8 *svds, u8 svds_len)
3605677dec6eSriastradh {
3606677dec6eSriastradh int modes = 0, i;
3607677dec6eSriastradh struct drm_device *dev = connector->dev;
3608677dec6eSriastradh struct drm_display_info *info = &connector->display_info;
3609677dec6eSriastradh struct drm_hdmi_info *hdmi = &info->hdmi;
3610677dec6eSriastradh
3611677dec6eSriastradh for (i = 0; i < svds_len; i++) {
3612677dec6eSriastradh u8 vic = svd_to_vic(svds[i]);
3613677dec6eSriastradh struct drm_display_mode *newmode;
3614677dec6eSriastradh
3615677dec6eSriastradh if (!drm_valid_cea_vic(vic))
3616677dec6eSriastradh continue;
3617677dec6eSriastradh
3618677dec6eSriastradh newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3619677dec6eSriastradh if (!newmode)
3620677dec6eSriastradh break;
3621677dec6eSriastradh bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3622677dec6eSriastradh drm_mode_probed_add(connector, newmode);
3623677dec6eSriastradh modes++;
3624677dec6eSriastradh }
3625677dec6eSriastradh
3626677dec6eSriastradh if (modes > 0)
3627677dec6eSriastradh info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3628677dec6eSriastradh return modes;
3629677dec6eSriastradh }
3630677dec6eSriastradh
3631677dec6eSriastradh /*
3632677dec6eSriastradh * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3633677dec6eSriastradh * @connector: connector corresponding to the HDMI sink
3634677dec6eSriastradh * @vic: CEA vic for the video mode to be added in the map
3635677dec6eSriastradh *
3636677dec6eSriastradh * Makes an entry for a videomode in the YCBCR 420 bitmap
3637677dec6eSriastradh */
3638677dec6eSriastradh static void
drm_add_cmdb_modes(struct drm_connector * connector,u8 svd)3639677dec6eSriastradh drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3640677dec6eSriastradh {
3641677dec6eSriastradh u8 vic = svd_to_vic(svd);
3642677dec6eSriastradh struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3643677dec6eSriastradh
3644677dec6eSriastradh if (!drm_valid_cea_vic(vic))
3645677dec6eSriastradh return;
3646677dec6eSriastradh
3647677dec6eSriastradh bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3648677dec6eSriastradh }
3649677dec6eSriastradh
3650a55ed7faSriastradh static int
do_cea_modes(struct drm_connector * connector,const u8 * db,u8 len)3651a55ed7faSriastradh do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3652a55ed7faSriastradh {
3653a55ed7faSriastradh int i, modes = 0;
3654677dec6eSriastradh struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3655a55ed7faSriastradh
3656a55ed7faSriastradh for (i = 0; i < len; i++) {
3657a55ed7faSriastradh struct drm_display_mode *mode;
3658a55ed7faSriastradh mode = drm_display_mode_from_vic_index(connector, db, len, i);
3659a55ed7faSriastradh if (mode) {
3660677dec6eSriastradh /*
3661677dec6eSriastradh * YCBCR420 capability block contains a bitmap which
3662677dec6eSriastradh * gives the index of CEA modes from CEA VDB, which
3663677dec6eSriastradh * can support YCBCR 420 sampling output also (apart
3664677dec6eSriastradh * from RGB/YCBCR444 etc).
3665677dec6eSriastradh * For example, if the bit 0 in bitmap is set,
3666677dec6eSriastradh * first mode in VDB can support YCBCR420 output too.
3667677dec6eSriastradh * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3668677dec6eSriastradh */
3669677dec6eSriastradh if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3670677dec6eSriastradh drm_add_cmdb_modes(connector, db[i]);
3671677dec6eSriastradh
3672a55ed7faSriastradh drm_mode_probed_add(connector, mode);
3673a55ed7faSriastradh modes++;
3674a55ed7faSriastradh }
3675a55ed7faSriastradh }
3676a55ed7faSriastradh
3677a55ed7faSriastradh return modes;
3678a55ed7faSriastradh }
3679a55ed7faSriastradh
3680a55ed7faSriastradh struct stereo_mandatory_mode {
3681a55ed7faSriastradh int width, height, vrefresh;
3682a55ed7faSriastradh unsigned int flags;
3683a55ed7faSriastradh };
3684a55ed7faSriastradh
3685a55ed7faSriastradh static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3686a55ed7faSriastradh { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3687a55ed7faSriastradh { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3688a55ed7faSriastradh { 1920, 1080, 50,
3689a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3690a55ed7faSriastradh { 1920, 1080, 60,
3691a55ed7faSriastradh DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3692a55ed7faSriastradh { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3693a55ed7faSriastradh { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3694a55ed7faSriastradh { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3695a55ed7faSriastradh { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3696a55ed7faSriastradh };
3697a55ed7faSriastradh
3698a55ed7faSriastradh static bool
stereo_match_mandatory(const struct drm_display_mode * mode,const struct stereo_mandatory_mode * stereo_mode)3699a55ed7faSriastradh stereo_match_mandatory(const struct drm_display_mode *mode,
3700a55ed7faSriastradh const struct stereo_mandatory_mode *stereo_mode)
3701a55ed7faSriastradh {
3702a55ed7faSriastradh unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3703a55ed7faSriastradh
3704a55ed7faSriastradh return mode->hdisplay == stereo_mode->width &&
3705a55ed7faSriastradh mode->vdisplay == stereo_mode->height &&
3706a55ed7faSriastradh interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3707a55ed7faSriastradh drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3708a55ed7faSriastradh }
3709a55ed7faSriastradh
add_hdmi_mandatory_stereo_modes(struct drm_connector * connector)3710a55ed7faSriastradh static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3711a55ed7faSriastradh {
3712a55ed7faSriastradh struct drm_device *dev = connector->dev;
3713a55ed7faSriastradh const struct drm_display_mode *mode;
3714a55ed7faSriastradh struct list_head stereo_modes;
3715a55ed7faSriastradh int modes = 0, i;
3716a55ed7faSriastradh
3717a55ed7faSriastradh INIT_LIST_HEAD(&stereo_modes);
3718a55ed7faSriastradh
3719a55ed7faSriastradh list_for_each_entry(mode, &connector->probed_modes, head) {
3720a55ed7faSriastradh for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3721a55ed7faSriastradh const struct stereo_mandatory_mode *mandatory;
3722a55ed7faSriastradh struct drm_display_mode *new_mode;
3723a55ed7faSriastradh
3724a55ed7faSriastradh if (!stereo_match_mandatory(mode,
3725a55ed7faSriastradh &stereo_mandatory_modes[i]))
3726a55ed7faSriastradh continue;
3727a55ed7faSriastradh
3728a55ed7faSriastradh mandatory = &stereo_mandatory_modes[i];
3729a55ed7faSriastradh new_mode = drm_mode_duplicate(dev, mode);
3730a55ed7faSriastradh if (!new_mode)
3731a55ed7faSriastradh continue;
3732a55ed7faSriastradh
3733a55ed7faSriastradh new_mode->flags |= mandatory->flags;
3734a55ed7faSriastradh list_add_tail(&new_mode->head, &stereo_modes);
3735a55ed7faSriastradh modes++;
3736a55ed7faSriastradh }
3737a55ed7faSriastradh }
3738a55ed7faSriastradh
3739a55ed7faSriastradh list_splice_tail(&stereo_modes, &connector->probed_modes);
3740a55ed7faSriastradh
3741a55ed7faSriastradh return modes;
3742a55ed7faSriastradh }
3743a55ed7faSriastradh
add_hdmi_mode(struct drm_connector * connector,u8 vic)3744a55ed7faSriastradh static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3745a55ed7faSriastradh {
3746a55ed7faSriastradh struct drm_device *dev = connector->dev;
3747a55ed7faSriastradh struct drm_display_mode *newmode;
3748a55ed7faSriastradh
3749677dec6eSriastradh if (!drm_valid_hdmi_vic(vic)) {
3750a55ed7faSriastradh DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3751a55ed7faSriastradh return 0;
3752a55ed7faSriastradh }
3753a55ed7faSriastradh
3754a55ed7faSriastradh newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3755a55ed7faSriastradh if (!newmode)
3756a55ed7faSriastradh return 0;
3757a55ed7faSriastradh
3758a55ed7faSriastradh drm_mode_probed_add(connector, newmode);
3759a55ed7faSriastradh
3760a55ed7faSriastradh return 1;
3761a55ed7faSriastradh }
3762a55ed7faSriastradh
add_3d_struct_modes(struct drm_connector * connector,u16 structure,const u8 * video_db,u8 video_len,u8 video_index)3763a55ed7faSriastradh static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3764a55ed7faSriastradh const u8 *video_db, u8 video_len, u8 video_index)
3765a55ed7faSriastradh {
3766a55ed7faSriastradh struct drm_display_mode *newmode;
3767a55ed7faSriastradh int modes = 0;
3768a55ed7faSriastradh
3769a55ed7faSriastradh if (structure & (1 << 0)) {
3770a55ed7faSriastradh newmode = drm_display_mode_from_vic_index(connector, video_db,
3771a55ed7faSriastradh video_len,
3772a55ed7faSriastradh video_index);
377356053ce7Sriastradh if (newmode) {
3774a55ed7faSriastradh newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
377556053ce7Sriastradh drm_mode_probed_add(connector, newmode);
377656053ce7Sriastradh modes++;
377756053ce7Sriastradh }
377856053ce7Sriastradh }
3779a55ed7faSriastradh if (structure & (1 << 6)) {
3780a55ed7faSriastradh newmode = drm_display_mode_from_vic_index(connector, video_db,
3781a55ed7faSriastradh video_len,
3782a55ed7faSriastradh video_index);
3783a55ed7faSriastradh if (newmode) {
3784a55ed7faSriastradh newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3785a55ed7faSriastradh drm_mode_probed_add(connector, newmode);
3786a55ed7faSriastradh modes++;
3787a55ed7faSriastradh }
3788a55ed7faSriastradh }
3789a55ed7faSriastradh if (structure & (1 << 8)) {
3790a55ed7faSriastradh newmode = drm_display_mode_from_vic_index(connector, video_db,
3791a55ed7faSriastradh video_len,
3792a55ed7faSriastradh video_index);
3793a55ed7faSriastradh if (newmode) {
3794a55ed7faSriastradh newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3795a55ed7faSriastradh drm_mode_probed_add(connector, newmode);
3796a55ed7faSriastradh modes++;
3797a55ed7faSriastradh }
379856053ce7Sriastradh }
379956053ce7Sriastradh
380056053ce7Sriastradh return modes;
380156053ce7Sriastradh }
380256053ce7Sriastradh
3803a55ed7faSriastradh /*
3804a55ed7faSriastradh * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3805a55ed7faSriastradh * @connector: connector corresponding to the HDMI sink
3806a55ed7faSriastradh * @db: start of the CEA vendor specific block
3807a55ed7faSriastradh * @len: length of the CEA block payload, ie. one can access up to db[len]
3808a55ed7faSriastradh *
3809a55ed7faSriastradh * Parses the HDMI VSDB looking for modes to add to @connector. This function
3810a55ed7faSriastradh * also adds the stereo 3d modes when applicable.
3811a55ed7faSriastradh */
3812a55ed7faSriastradh static int
do_hdmi_vsdb_modes(struct drm_connector * connector,const u8 * db,u8 len,const u8 * video_db,u8 video_len)3813a55ed7faSriastradh do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3814a55ed7faSriastradh const u8 *video_db, u8 video_len)
3815a55ed7faSriastradh {
3816677dec6eSriastradh struct drm_display_info *info = &connector->display_info;
3817a55ed7faSriastradh int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3818a55ed7faSriastradh u8 vic_len, hdmi_3d_len = 0;
3819a55ed7faSriastradh u16 mask;
3820a55ed7faSriastradh u16 structure_all;
3821a55ed7faSriastradh
3822a55ed7faSriastradh if (len < 8)
3823a55ed7faSriastradh goto out;
3824a55ed7faSriastradh
3825a55ed7faSriastradh /* no HDMI_Video_Present */
3826a55ed7faSriastradh if (!(db[8] & (1 << 5)))
3827a55ed7faSriastradh goto out;
3828a55ed7faSriastradh
3829a55ed7faSriastradh /* Latency_Fields_Present */
3830a55ed7faSriastradh if (db[8] & (1 << 7))
3831a55ed7faSriastradh offset += 2;
3832a55ed7faSriastradh
3833a55ed7faSriastradh /* I_Latency_Fields_Present */
3834a55ed7faSriastradh if (db[8] & (1 << 6))
3835a55ed7faSriastradh offset += 2;
3836a55ed7faSriastradh
3837a55ed7faSriastradh /* the declared length is not long enough for the 2 first bytes
3838a55ed7faSriastradh * of additional video format capabilities */
3839a55ed7faSriastradh if (len < (8 + offset + 2))
3840a55ed7faSriastradh goto out;
3841a55ed7faSriastradh
3842a55ed7faSriastradh /* 3D_Present */
3843a55ed7faSriastradh offset++;
3844a55ed7faSriastradh if (db[8 + offset] & (1 << 7)) {
3845a55ed7faSriastradh modes += add_hdmi_mandatory_stereo_modes(connector);
3846a55ed7faSriastradh
3847a55ed7faSriastradh /* 3D_Multi_present */
3848a55ed7faSriastradh multi_present = (db[8 + offset] & 0x60) >> 5;
3849a55ed7faSriastradh }
3850a55ed7faSriastradh
3851a55ed7faSriastradh offset++;
3852a55ed7faSriastradh vic_len = db[8 + offset] >> 5;
3853a55ed7faSriastradh hdmi_3d_len = db[8 + offset] & 0x1f;
3854a55ed7faSriastradh
3855a55ed7faSriastradh for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3856a55ed7faSriastradh u8 vic;
3857a55ed7faSriastradh
3858a55ed7faSriastradh vic = db[9 + offset + i];
3859a55ed7faSriastradh modes += add_hdmi_mode(connector, vic);
3860a55ed7faSriastradh }
3861a55ed7faSriastradh offset += 1 + vic_len;
3862a55ed7faSriastradh
3863a55ed7faSriastradh if (multi_present == 1)
3864a55ed7faSriastradh multi_len = 2;
3865a55ed7faSriastradh else if (multi_present == 2)
3866a55ed7faSriastradh multi_len = 4;
3867a55ed7faSriastradh else
3868a55ed7faSriastradh multi_len = 0;
3869a55ed7faSriastradh
3870a55ed7faSriastradh if (len < (8 + offset + hdmi_3d_len - 1))
3871a55ed7faSriastradh goto out;
3872a55ed7faSriastradh
3873a55ed7faSriastradh if (hdmi_3d_len < multi_len)
3874a55ed7faSriastradh goto out;
3875a55ed7faSriastradh
3876a55ed7faSriastradh if (multi_present == 1 || multi_present == 2) {
3877a55ed7faSriastradh /* 3D_Structure_ALL */
3878a55ed7faSriastradh structure_all = (db[8 + offset] << 8) | db[9 + offset];
3879a55ed7faSriastradh
3880a55ed7faSriastradh /* check if 3D_MASK is present */
3881a55ed7faSriastradh if (multi_present == 2)
3882a55ed7faSriastradh mask = (db[10 + offset] << 8) | db[11 + offset];
3883a55ed7faSriastradh else
3884a55ed7faSriastradh mask = 0xffff;
3885a55ed7faSriastradh
3886a55ed7faSriastradh for (i = 0; i < 16; i++) {
3887a55ed7faSriastradh if (mask & (1 << i))
3888a55ed7faSriastradh modes += add_3d_struct_modes(connector,
3889a55ed7faSriastradh structure_all,
3890a55ed7faSriastradh video_db,
3891a55ed7faSriastradh video_len, i);
3892a55ed7faSriastradh }
3893a55ed7faSriastradh }
3894a55ed7faSriastradh
3895a55ed7faSriastradh offset += multi_len;
3896a55ed7faSriastradh
3897a55ed7faSriastradh for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3898a55ed7faSriastradh int vic_index;
3899a55ed7faSriastradh struct drm_display_mode *newmode = NULL;
3900a55ed7faSriastradh unsigned int newflag = 0;
3901a55ed7faSriastradh bool detail_present;
3902a55ed7faSriastradh
3903a55ed7faSriastradh detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3904a55ed7faSriastradh
3905a55ed7faSriastradh if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3906a55ed7faSriastradh break;
3907a55ed7faSriastradh
3908a55ed7faSriastradh /* 2D_VIC_order_X */
3909a55ed7faSriastradh vic_index = db[8 + offset + i] >> 4;
3910a55ed7faSriastradh
3911a55ed7faSriastradh /* 3D_Structure_X */
3912a55ed7faSriastradh switch (db[8 + offset + i] & 0x0f) {
3913a55ed7faSriastradh case 0:
3914a55ed7faSriastradh newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3915a55ed7faSriastradh break;
3916a55ed7faSriastradh case 6:
3917a55ed7faSriastradh newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3918a55ed7faSriastradh break;
3919a55ed7faSriastradh case 8:
3920a55ed7faSriastradh /* 3D_Detail_X */
3921a55ed7faSriastradh if ((db[9 + offset + i] >> 4) == 1)
3922a55ed7faSriastradh newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3923a55ed7faSriastradh break;
3924a55ed7faSriastradh }
3925a55ed7faSriastradh
3926a55ed7faSriastradh if (newflag != 0) {
3927a55ed7faSriastradh newmode = drm_display_mode_from_vic_index(connector,
3928a55ed7faSriastradh video_db,
3929a55ed7faSriastradh video_len,
3930a55ed7faSriastradh vic_index);
3931a55ed7faSriastradh
3932a55ed7faSriastradh if (newmode) {
3933a55ed7faSriastradh newmode->flags |= newflag;
3934a55ed7faSriastradh drm_mode_probed_add(connector, newmode);
3935a55ed7faSriastradh modes++;
3936a55ed7faSriastradh }
3937a55ed7faSriastradh }
3938a55ed7faSriastradh
3939a55ed7faSriastradh if (detail_present)
3940a55ed7faSriastradh i++;
3941a55ed7faSriastradh }
3942a55ed7faSriastradh
3943a55ed7faSriastradh out:
3944677dec6eSriastradh if (modes > 0)
3945677dec6eSriastradh info->has_hdmi_infoframe = true;
3946a55ed7faSriastradh return modes;
3947a55ed7faSriastradh }
3948a55ed7faSriastradh
394956053ce7Sriastradh static int
cea_db_payload_len(const u8 * db)395056053ce7Sriastradh cea_db_payload_len(const u8 *db)
395156053ce7Sriastradh {
395256053ce7Sriastradh return db[0] & 0x1f;
395356053ce7Sriastradh }
395456053ce7Sriastradh
395556053ce7Sriastradh static int
cea_db_extended_tag(const u8 * db)3956677dec6eSriastradh cea_db_extended_tag(const u8 *db)
3957677dec6eSriastradh {
3958677dec6eSriastradh return db[1];
3959677dec6eSriastradh }
3960677dec6eSriastradh
3961677dec6eSriastradh static int
cea_db_tag(const u8 * db)396256053ce7Sriastradh cea_db_tag(const u8 *db)
396356053ce7Sriastradh {
396456053ce7Sriastradh return db[0] >> 5;
396556053ce7Sriastradh }
396656053ce7Sriastradh
396756053ce7Sriastradh static int
cea_revision(const u8 * cea)396856053ce7Sriastradh cea_revision(const u8 *cea)
396956053ce7Sriastradh {
397056053ce7Sriastradh return cea[1];
397156053ce7Sriastradh }
397256053ce7Sriastradh
397356053ce7Sriastradh static int
cea_db_offsets(const u8 * cea,int * start,int * end)397456053ce7Sriastradh cea_db_offsets(const u8 *cea, int *start, int *end)
397556053ce7Sriastradh {
3976677dec6eSriastradh /* DisplayID CTA extension blocks and top-level CEA EDID
3977677dec6eSriastradh * block header definitions differ in the following bytes:
3978677dec6eSriastradh * 1) Byte 2 of the header specifies length differently,
3979677dec6eSriastradh * 2) Byte 3 is only present in the CEA top level block.
3980677dec6eSriastradh *
3981677dec6eSriastradh * The different definitions for byte 2 follow.
3982677dec6eSriastradh *
3983677dec6eSriastradh * DisplayID CTA extension block defines byte 2 as:
3984677dec6eSriastradh * Number of payload bytes
3985677dec6eSriastradh *
3986677dec6eSriastradh * CEA EDID block defines byte 2 as:
3987677dec6eSriastradh * Byte number (decimal) within this block where the 18-byte
3988677dec6eSriastradh * DTDs begin. If no non-DTD data is present in this extension
3989677dec6eSriastradh * block, the value should be set to 04h (the byte after next).
3990677dec6eSriastradh * If set to 00h, there are no DTDs present in this block and
3991677dec6eSriastradh * no non-DTD data.
3992677dec6eSriastradh */
3993677dec6eSriastradh if (cea[0] == DATA_BLOCK_CTA) {
3994677dec6eSriastradh *start = 3;
3995677dec6eSriastradh *end = *start + cea[2];
3996677dec6eSriastradh } else if (cea[0] == CEA_EXT) {
399756053ce7Sriastradh /* Data block offset in CEA extension block */
399856053ce7Sriastradh *start = 4;
399956053ce7Sriastradh *end = cea[2];
400056053ce7Sriastradh if (*end == 0)
400156053ce7Sriastradh *end = 127;
400256053ce7Sriastradh if (*end < 4 || *end > 127)
400356053ce7Sriastradh return -ERANGE;
4004677dec6eSriastradh } else {
4005677dec6eSriastradh return -EOPNOTSUPP;
4006677dec6eSriastradh }
4007677dec6eSriastradh
400856053ce7Sriastradh return 0;
400956053ce7Sriastradh }
401056053ce7Sriastradh
cea_db_is_hdmi_vsdb(const u8 * db)4011a55ed7faSriastradh static bool cea_db_is_hdmi_vsdb(const u8 *db)
4012a55ed7faSriastradh {
4013a55ed7faSriastradh int hdmi_id;
4014a55ed7faSriastradh
4015a55ed7faSriastradh if (cea_db_tag(db) != VENDOR_BLOCK)
4016a55ed7faSriastradh return false;
4017a55ed7faSriastradh
4018a55ed7faSriastradh if (cea_db_payload_len(db) < 5)
4019a55ed7faSriastradh return false;
4020a55ed7faSriastradh
4021a55ed7faSriastradh hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4022a55ed7faSriastradh
4023a55ed7faSriastradh return hdmi_id == HDMI_IEEE_OUI;
4024a55ed7faSriastradh }
4025a55ed7faSriastradh
cea_db_is_hdmi_forum_vsdb(const u8 * db)4026677dec6eSriastradh static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4027677dec6eSriastradh {
4028677dec6eSriastradh unsigned int oui;
4029677dec6eSriastradh
4030677dec6eSriastradh if (cea_db_tag(db) != VENDOR_BLOCK)
4031677dec6eSriastradh return false;
4032677dec6eSriastradh
4033677dec6eSriastradh if (cea_db_payload_len(db) < 7)
4034677dec6eSriastradh return false;
4035677dec6eSriastradh
4036677dec6eSriastradh oui = db[3] << 16 | db[2] << 8 | db[1];
4037677dec6eSriastradh
4038677dec6eSriastradh return oui == HDMI_FORUM_IEEE_OUI;
4039677dec6eSriastradh }
4040677dec6eSriastradh
cea_db_is_vcdb(const u8 * db)4041677dec6eSriastradh static bool cea_db_is_vcdb(const u8 *db)
4042677dec6eSriastradh {
4043677dec6eSriastradh if (cea_db_tag(db) != USE_EXTENDED_TAG)
4044677dec6eSriastradh return false;
4045677dec6eSriastradh
4046677dec6eSriastradh if (cea_db_payload_len(db) != 2)
4047677dec6eSriastradh return false;
4048677dec6eSriastradh
4049677dec6eSriastradh if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4050677dec6eSriastradh return false;
4051677dec6eSriastradh
4052677dec6eSriastradh return true;
4053677dec6eSriastradh }
4054677dec6eSriastradh
cea_db_is_y420cmdb(const u8 * db)4055677dec6eSriastradh static bool cea_db_is_y420cmdb(const u8 *db)
4056677dec6eSriastradh {
4057677dec6eSriastradh if (cea_db_tag(db) != USE_EXTENDED_TAG)
4058677dec6eSriastradh return false;
4059677dec6eSriastradh
4060677dec6eSriastradh if (!cea_db_payload_len(db))
4061677dec6eSriastradh return false;
4062677dec6eSriastradh
4063677dec6eSriastradh if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4064677dec6eSriastradh return false;
4065677dec6eSriastradh
4066677dec6eSriastradh return true;
4067677dec6eSriastradh }
4068677dec6eSriastradh
cea_db_is_y420vdb(const u8 * db)4069677dec6eSriastradh static bool cea_db_is_y420vdb(const u8 *db)
4070677dec6eSriastradh {
4071677dec6eSriastradh if (cea_db_tag(db) != USE_EXTENDED_TAG)
4072677dec6eSriastradh return false;
4073677dec6eSriastradh
4074677dec6eSriastradh if (!cea_db_payload_len(db))
4075677dec6eSriastradh return false;
4076677dec6eSriastradh
4077677dec6eSriastradh if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4078677dec6eSriastradh return false;
4079677dec6eSriastradh
4080677dec6eSriastradh return true;
4081677dec6eSriastradh }
4082677dec6eSriastradh
408356053ce7Sriastradh #define for_each_cea_db(cea, i, start, end) \
408456053ce7Sriastradh for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
408556053ce7Sriastradh
drm_parse_y420cmdb_bitmap(struct drm_connector * connector,const u8 * db)4086677dec6eSriastradh static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4087677dec6eSriastradh const u8 *db)
4088677dec6eSriastradh {
4089677dec6eSriastradh struct drm_display_info *info = &connector->display_info;
4090677dec6eSriastradh struct drm_hdmi_info *hdmi = &info->hdmi;
4091677dec6eSriastradh u8 map_len = cea_db_payload_len(db) - 1;
4092677dec6eSriastradh u8 count;
4093677dec6eSriastradh u64 map = 0;
4094677dec6eSriastradh
4095677dec6eSriastradh if (map_len == 0) {
4096677dec6eSriastradh /* All CEA modes support ycbcr420 sampling also.*/
4097677dec6eSriastradh hdmi->y420_cmdb_map = U64_MAX;
4098677dec6eSriastradh info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4099677dec6eSriastradh return;
4100677dec6eSriastradh }
4101677dec6eSriastradh
4102677dec6eSriastradh /*
4103677dec6eSriastradh * This map indicates which of the existing CEA block modes
4104677dec6eSriastradh * from VDB can support YCBCR420 output too. So if bit=0 is
4105677dec6eSriastradh * set, first mode from VDB can support YCBCR420 output too.
4106677dec6eSriastradh * We will parse and keep this map, before parsing VDB itself
4107677dec6eSriastradh * to avoid going through the same block again and again.
4108677dec6eSriastradh *
4109677dec6eSriastradh * Spec is not clear about max possible size of this block.
4110677dec6eSriastradh * Clamping max bitmap block size at 8 bytes. Every byte can
4111677dec6eSriastradh * address 8 CEA modes, in this way this map can address
4112677dec6eSriastradh * 8*8 = first 64 SVDs.
4113677dec6eSriastradh */
4114677dec6eSriastradh if (WARN_ON_ONCE(map_len > 8))
4115677dec6eSriastradh map_len = 8;
4116677dec6eSriastradh
4117677dec6eSriastradh for (count = 0; count < map_len; count++)
4118677dec6eSriastradh map |= (u64)db[2 + count] << (8 * count);
4119677dec6eSriastradh
4120677dec6eSriastradh if (map)
4121677dec6eSriastradh info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4122677dec6eSriastradh
4123677dec6eSriastradh hdmi->y420_cmdb_map = map;
4124677dec6eSriastradh }
4125677dec6eSriastradh
412656053ce7Sriastradh static int
add_cea_modes(struct drm_connector * connector,struct edid * edid)412756053ce7Sriastradh add_cea_modes(struct drm_connector *connector, struct edid *edid)
412856053ce7Sriastradh {
4129a55ed7faSriastradh const u8 *cea = drm_find_cea_extension(edid);
4130a55ed7faSriastradh const u8 *db, *hdmi = NULL, *video = NULL;
4131a55ed7faSriastradh u8 dbl, hdmi_len, video_len = 0;
413256053ce7Sriastradh int modes = 0;
413356053ce7Sriastradh
413456053ce7Sriastradh if (cea && cea_revision(cea) >= 3) {
413556053ce7Sriastradh int i, start, end;
413656053ce7Sriastradh
413756053ce7Sriastradh if (cea_db_offsets(cea, &start, &end))
413856053ce7Sriastradh return 0;
413956053ce7Sriastradh
414056053ce7Sriastradh for_each_cea_db(cea, i, start, end) {
414156053ce7Sriastradh db = &cea[i];
414256053ce7Sriastradh dbl = cea_db_payload_len(db);
414356053ce7Sriastradh
4144a55ed7faSriastradh if (cea_db_tag(db) == VIDEO_BLOCK) {
4145a55ed7faSriastradh video = db + 1;
4146a55ed7faSriastradh video_len = dbl;
4147a55ed7faSriastradh modes += do_cea_modes(connector, video, dbl);
4148677dec6eSriastradh } else if (cea_db_is_hdmi_vsdb(db)) {
4149a55ed7faSriastradh hdmi = db;
4150a55ed7faSriastradh hdmi_len = dbl;
4151677dec6eSriastradh } else if (cea_db_is_y420vdb(db)) {
4152677dec6eSriastradh const u8 *vdb420 = &db[2];
4153677dec6eSriastradh
4154677dec6eSriastradh /* Add 4:2:0(only) modes present in EDID */
4155677dec6eSriastradh modes += do_y420vdb_modes(connector,
4156677dec6eSriastradh vdb420,
4157677dec6eSriastradh dbl - 1);
415856053ce7Sriastradh }
415956053ce7Sriastradh }
4160a55ed7faSriastradh }
4161a55ed7faSriastradh
4162a55ed7faSriastradh /*
4163a55ed7faSriastradh * We parse the HDMI VSDB after having added the cea modes as we will
4164a55ed7faSriastradh * be patching their flags when the sink supports stereo 3D.
4165a55ed7faSriastradh */
4166a55ed7faSriastradh if (hdmi)
4167a55ed7faSriastradh modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4168a55ed7faSriastradh video_len);
416956053ce7Sriastradh
417056053ce7Sriastradh return modes;
417156053ce7Sriastradh }
417256053ce7Sriastradh
fixup_detailed_cea_mode_clock(struct drm_display_mode * mode)41734e59feabSriastradh static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
41744e59feabSriastradh {
41754e59feabSriastradh const struct drm_display_mode *cea_mode;
41764e59feabSriastradh int clock1, clock2, clock;
4177677dec6eSriastradh u8 vic;
41784e59feabSriastradh const char *type;
41794e59feabSriastradh
4180677dec6eSriastradh /*
4181677dec6eSriastradh * allow 5kHz clock difference either way to account for
4182677dec6eSriastradh * the 10kHz clock resolution limit of detailed timings.
4183677dec6eSriastradh */
4184677dec6eSriastradh vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4185677dec6eSriastradh if (drm_valid_cea_vic(vic)) {
41864e59feabSriastradh type = "CEA";
4187677dec6eSriastradh cea_mode = cea_mode_for_vic(vic);
41884e59feabSriastradh clock1 = cea_mode->clock;
41894e59feabSriastradh clock2 = cea_mode_alternate_clock(cea_mode);
41904e59feabSriastradh } else {
4191677dec6eSriastradh vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4192677dec6eSriastradh if (drm_valid_hdmi_vic(vic)) {
41934e59feabSriastradh type = "HDMI";
4194677dec6eSriastradh cea_mode = &edid_4k_modes[vic];
41954e59feabSriastradh clock1 = cea_mode->clock;
41964e59feabSriastradh clock2 = hdmi_mode_alternate_clock(cea_mode);
41974e59feabSriastradh } else {
41984e59feabSriastradh return;
41994e59feabSriastradh }
42004e59feabSriastradh }
42014e59feabSriastradh
42024e59feabSriastradh /* pick whichever is closest */
42034e59feabSriastradh if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
42044e59feabSriastradh clock = clock1;
42054e59feabSriastradh else
42064e59feabSriastradh clock = clock2;
42074e59feabSriastradh
42084e59feabSriastradh if (mode->clock == clock)
42094e59feabSriastradh return;
42104e59feabSriastradh
42114e59feabSriastradh DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4212677dec6eSriastradh type, vic, mode->clock, clock);
42134e59feabSriastradh mode->clock = clock;
42144e59feabSriastradh }
42154e59feabSriastradh
cea_db_is_hdmi_hdr_metadata_block(const u8 * db)4216677dec6eSriastradh static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4217677dec6eSriastradh {
4218677dec6eSriastradh if (cea_db_tag(db) != USE_EXTENDED_TAG)
4219677dec6eSriastradh return false;
4220677dec6eSriastradh
4221677dec6eSriastradh if (db[1] != HDR_STATIC_METADATA_BLOCK)
4222677dec6eSriastradh return false;
4223677dec6eSriastradh
4224677dec6eSriastradh if (cea_db_payload_len(db) < 3)
4225677dec6eSriastradh return false;
4226677dec6eSriastradh
4227677dec6eSriastradh return true;
4228677dec6eSriastradh }
4229677dec6eSriastradh
eotf_supported(const u8 * edid_ext)4230677dec6eSriastradh static uint8_t eotf_supported(const u8 *edid_ext)
4231677dec6eSriastradh {
4232677dec6eSriastradh return edid_ext[2] &
4233677dec6eSriastradh (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4234677dec6eSriastradh BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4235677dec6eSriastradh BIT(HDMI_EOTF_SMPTE_ST2084) |
4236677dec6eSriastradh BIT(HDMI_EOTF_BT_2100_HLG));
4237677dec6eSriastradh }
4238677dec6eSriastradh
hdr_metadata_type(const u8 * edid_ext)4239677dec6eSriastradh static uint8_t hdr_metadata_type(const u8 *edid_ext)
4240677dec6eSriastradh {
4241677dec6eSriastradh return edid_ext[3] &
4242677dec6eSriastradh BIT(HDMI_STATIC_METADATA_TYPE1);
4243677dec6eSriastradh }
4244677dec6eSriastradh
424556053ce7Sriastradh static void
drm_parse_hdr_metadata_block(struct drm_connector * connector,const u8 * db)4246677dec6eSriastradh drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4247677dec6eSriastradh {
4248677dec6eSriastradh u16 len;
4249677dec6eSriastradh
4250677dec6eSriastradh len = cea_db_payload_len(db);
4251677dec6eSriastradh
4252677dec6eSriastradh connector->hdr_sink_metadata.hdmi_type1.eotf =
4253677dec6eSriastradh eotf_supported(db);
4254677dec6eSriastradh connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4255677dec6eSriastradh hdr_metadata_type(db);
4256677dec6eSriastradh
4257677dec6eSriastradh if (len >= 4)
4258677dec6eSriastradh connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4259677dec6eSriastradh if (len >= 5)
4260677dec6eSriastradh connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4261677dec6eSriastradh if (len >= 6)
4262677dec6eSriastradh connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4263677dec6eSriastradh }
4264677dec6eSriastradh
4265677dec6eSriastradh static void
drm_parse_hdmi_vsdb_audio(struct drm_connector * connector,const u8 * db)4266677dec6eSriastradh drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
426756053ce7Sriastradh {
426856053ce7Sriastradh u8 len = cea_db_payload_len(db);
426956053ce7Sriastradh
4270*9a4c85f7Sriastradh if (len >= 5) {
4271*9a4c85f7Sriastradh connector->physical_address = (db[4] << 8) | db[5];
4272*9a4c85f7Sriastradh }
4273677dec6eSriastradh if (len >= 6 && (db[6] & (1 << 7)))
4274677dec6eSriastradh connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
427556053ce7Sriastradh if (len >= 8) {
427656053ce7Sriastradh connector->latency_present[0] = db[8] >> 7;
427756053ce7Sriastradh connector->latency_present[1] = (db[8] >> 6) & 1;
427856053ce7Sriastradh }
427956053ce7Sriastradh if (len >= 9)
428056053ce7Sriastradh connector->video_latency[0] = db[9];
428156053ce7Sriastradh if (len >= 10)
428256053ce7Sriastradh connector->audio_latency[0] = db[10];
428356053ce7Sriastradh if (len >= 11)
428456053ce7Sriastradh connector->video_latency[1] = db[11];
428556053ce7Sriastradh if (len >= 12)
428656053ce7Sriastradh connector->audio_latency[1] = db[12];
428756053ce7Sriastradh
4288677dec6eSriastradh DRM_DEBUG_KMS("HDMI: latency present %d %d, "
428956053ce7Sriastradh "video latency %d %d, "
429056053ce7Sriastradh "audio latency %d %d\n",
4291677dec6eSriastradh connector->latency_present[0],
4292677dec6eSriastradh connector->latency_present[1],
429356053ce7Sriastradh connector->video_latency[0],
429456053ce7Sriastradh connector->video_latency[1],
429556053ce7Sriastradh connector->audio_latency[0],
429656053ce7Sriastradh connector->audio_latency[1]);
429756053ce7Sriastradh }
429856053ce7Sriastradh
429956053ce7Sriastradh static void
monitor_name(struct detailed_timing * t,void * data)430056053ce7Sriastradh monitor_name(struct detailed_timing *t, void *data)
430156053ce7Sriastradh {
430256053ce7Sriastradh if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
430356053ce7Sriastradh *(u8 **)data = t->data.other_data.data.str.str;
430456053ce7Sriastradh }
430556053ce7Sriastradh
get_monitor_name(struct edid * edid,char name[13])4306677dec6eSriastradh static int get_monitor_name(struct edid *edid, char name[13])
4307677dec6eSriastradh {
4308677dec6eSriastradh char *edid_name = NULL;
4309677dec6eSriastradh int mnl;
4310677dec6eSriastradh
4311677dec6eSriastradh if (!edid || !name)
4312677dec6eSriastradh return 0;
4313677dec6eSriastradh
4314677dec6eSriastradh drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4315677dec6eSriastradh for (mnl = 0; edid_name && mnl < 13; mnl++) {
4316677dec6eSriastradh if (edid_name[mnl] == 0x0a)
4317677dec6eSriastradh break;
4318677dec6eSriastradh
4319677dec6eSriastradh name[mnl] = edid_name[mnl];
4320677dec6eSriastradh }
4321677dec6eSriastradh
4322677dec6eSriastradh return mnl;
4323677dec6eSriastradh }
4324677dec6eSriastradh
432556053ce7Sriastradh /**
4326677dec6eSriastradh * drm_edid_get_monitor_name - fetch the monitor name from the edid
4327677dec6eSriastradh * @edid: monitor EDID information
4328677dec6eSriastradh * @name: pointer to a character array to hold the name of the monitor
4329677dec6eSriastradh * @bufsize: The size of the name buffer (should be at least 14 chars.)
4330677dec6eSriastradh *
4331677dec6eSriastradh */
drm_edid_get_monitor_name(struct edid * edid,char * name,int bufsize)4332677dec6eSriastradh void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4333677dec6eSriastradh {
4334677dec6eSriastradh int name_length;
4335677dec6eSriastradh char buf[13];
4336677dec6eSriastradh
4337677dec6eSriastradh if (bufsize <= 0)
4338677dec6eSriastradh return;
4339677dec6eSriastradh
4340677dec6eSriastradh name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4341677dec6eSriastradh memcpy(name, buf, name_length);
4342677dec6eSriastradh name[name_length] = '\0';
4343677dec6eSriastradh }
4344677dec6eSriastradh EXPORT_SYMBOL(drm_edid_get_monitor_name);
4345677dec6eSriastradh
clear_eld(struct drm_connector * connector)4346677dec6eSriastradh static void clear_eld(struct drm_connector *connector)
4347677dec6eSriastradh {
4348677dec6eSriastradh memset(connector->eld, 0, sizeof(connector->eld));
4349677dec6eSriastradh
4350677dec6eSriastradh connector->latency_present[0] = false;
4351677dec6eSriastradh connector->latency_present[1] = false;
4352677dec6eSriastradh connector->video_latency[0] = 0;
4353677dec6eSriastradh connector->audio_latency[0] = 0;
4354677dec6eSriastradh connector->video_latency[1] = 0;
4355677dec6eSriastradh connector->audio_latency[1] = 0;
4356677dec6eSriastradh }
4357677dec6eSriastradh
4358677dec6eSriastradh /*
435956053ce7Sriastradh * drm_edid_to_eld - build ELD from EDID
436056053ce7Sriastradh * @connector: connector corresponding to the HDMI/DP sink
436156053ce7Sriastradh * @edid: EDID to parse
436256053ce7Sriastradh *
43634e59feabSriastradh * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
43644e59feabSriastradh * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
436556053ce7Sriastradh */
drm_edid_to_eld(struct drm_connector * connector,struct edid * edid)4366677dec6eSriastradh static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
436756053ce7Sriastradh {
436856053ce7Sriastradh uint8_t *eld = connector->eld;
43692cbe17a3Sriastradh const u8 *cea;
43702cbe17a3Sriastradh const u8 *db;
4371677dec6eSriastradh int total_sad_count = 0;
437256053ce7Sriastradh int mnl;
437356053ce7Sriastradh int dbl;
437456053ce7Sriastradh
4375677dec6eSriastradh clear_eld(connector);
4376677dec6eSriastradh
4377677dec6eSriastradh if (!edid)
4378677dec6eSriastradh return;
437956053ce7Sriastradh
438056053ce7Sriastradh cea = drm_find_cea_extension(edid);
438156053ce7Sriastradh if (!cea) {
438256053ce7Sriastradh DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
438356053ce7Sriastradh return;
438456053ce7Sriastradh }
438556053ce7Sriastradh
4386677dec6eSriastradh mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4387677dec6eSriastradh DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
438856053ce7Sriastradh
4389677dec6eSriastradh eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4390677dec6eSriastradh eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
439156053ce7Sriastradh
4392677dec6eSriastradh eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4393677dec6eSriastradh
4394677dec6eSriastradh eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4395677dec6eSriastradh eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4396677dec6eSriastradh eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4397677dec6eSriastradh eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
439856053ce7Sriastradh
439956053ce7Sriastradh if (cea_revision(cea) >= 3) {
440056053ce7Sriastradh int i, start, end;
440156053ce7Sriastradh
440256053ce7Sriastradh if (cea_db_offsets(cea, &start, &end)) {
440356053ce7Sriastradh start = 0;
440456053ce7Sriastradh end = 0;
440556053ce7Sriastradh }
440656053ce7Sriastradh
440756053ce7Sriastradh for_each_cea_db(cea, i, start, end) {
440856053ce7Sriastradh db = &cea[i];
440956053ce7Sriastradh dbl = cea_db_payload_len(db);
441056053ce7Sriastradh
441156053ce7Sriastradh switch (cea_db_tag(db)) {
4412677dec6eSriastradh int sad_count;
4413677dec6eSriastradh
441456053ce7Sriastradh case AUDIO_BLOCK:
441556053ce7Sriastradh /* Audio Data Block, contains SADs */
4416677dec6eSriastradh sad_count = min(dbl / 3, 15 - total_sad_count);
4417677dec6eSriastradh if (sad_count >= 1)
4418677dec6eSriastradh memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4419677dec6eSriastradh &db[1], sad_count * 3);
4420677dec6eSriastradh total_sad_count += sad_count;
442156053ce7Sriastradh break;
442256053ce7Sriastradh case SPEAKER_BLOCK:
442356053ce7Sriastradh /* Speaker Allocation Data Block */
442456053ce7Sriastradh if (dbl >= 1)
4425677dec6eSriastradh eld[DRM_ELD_SPEAKER] = db[1];
442656053ce7Sriastradh break;
442756053ce7Sriastradh case VENDOR_BLOCK:
442856053ce7Sriastradh /* HDMI Vendor-Specific Data Block */
442956053ce7Sriastradh if (cea_db_is_hdmi_vsdb(db))
4430677dec6eSriastradh drm_parse_hdmi_vsdb_audio(connector, db);
443156053ce7Sriastradh break;
443256053ce7Sriastradh default:
443356053ce7Sriastradh break;
443456053ce7Sriastradh }
443556053ce7Sriastradh }
443656053ce7Sriastradh }
4437677dec6eSriastradh eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
443856053ce7Sriastradh
44394e59feabSriastradh if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
44404e59feabSriastradh connector->connector_type == DRM_MODE_CONNECTOR_eDP)
44414e59feabSriastradh eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
44424e59feabSriastradh else
44434e59feabSriastradh eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
44444e59feabSriastradh
44454e59feabSriastradh eld[DRM_ELD_BASELINE_ELD_LEN] =
44464e59feabSriastradh DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
44474e59feabSriastradh
44484e59feabSriastradh DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4449677dec6eSriastradh drm_eld_size(eld), total_sad_count);
445056053ce7Sriastradh }
445156053ce7Sriastradh
445256053ce7Sriastradh /**
4453a55ed7faSriastradh * drm_edid_to_sad - extracts SADs from EDID
4454a55ed7faSriastradh * @edid: EDID to parse
4455a55ed7faSriastradh * @sads: pointer that will be set to the extracted SADs
4456a55ed7faSriastradh *
4457a55ed7faSriastradh * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4458a55ed7faSriastradh *
44594e59feabSriastradh * Note: The returned pointer needs to be freed using kfree().
44604e59feabSriastradh *
44614e59feabSriastradh * Return: The number of found SADs or negative number on error.
4462a55ed7faSriastradh */
drm_edid_to_sad(struct edid * edid,struct cea_sad ** sads)4463a55ed7faSriastradh int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4464a55ed7faSriastradh {
4465a55ed7faSriastradh int count = 0;
4466a55ed7faSriastradh int i, start, end, dbl;
44672cbe17a3Sriastradh const u8 *cea;
4468a55ed7faSriastradh
4469a55ed7faSriastradh cea = drm_find_cea_extension(edid);
4470a55ed7faSriastradh if (!cea) {
4471a55ed7faSriastradh DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4472677dec6eSriastradh return 0;
4473a55ed7faSriastradh }
4474a55ed7faSriastradh
4475a55ed7faSriastradh if (cea_revision(cea) < 3) {
4476a55ed7faSriastradh DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4477677dec6eSriastradh return 0;
4478a55ed7faSriastradh }
4479a55ed7faSriastradh
4480a55ed7faSriastradh if (cea_db_offsets(cea, &start, &end)) {
4481a55ed7faSriastradh DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4482a55ed7faSriastradh return -EPROTO;
4483a55ed7faSriastradh }
4484a55ed7faSriastradh
4485a55ed7faSriastradh for_each_cea_db(cea, i, start, end) {
44862cbe17a3Sriastradh const u8 *db = &cea[i];
4487a55ed7faSriastradh
4488a55ed7faSriastradh if (cea_db_tag(db) == AUDIO_BLOCK) {
4489a55ed7faSriastradh int j;
4490a55ed7faSriastradh dbl = cea_db_payload_len(db);
4491a55ed7faSriastradh
4492a55ed7faSriastradh count = dbl / 3; /* SAD is 3B */
4493a55ed7faSriastradh *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4494a55ed7faSriastradh if (!*sads)
4495a55ed7faSriastradh return -ENOMEM;
4496a55ed7faSriastradh for (j = 0; j < count; j++) {
44972cbe17a3Sriastradh const u8 *sad = &db[1 + j * 3];
4498a55ed7faSriastradh
4499a55ed7faSriastradh (*sads)[j].format = (sad[0] & 0x78) >> 3;
4500a55ed7faSriastradh (*sads)[j].channels = sad[0] & 0x7;
4501a55ed7faSriastradh (*sads)[j].freq = sad[1] & 0x7F;
4502a55ed7faSriastradh (*sads)[j].byte2 = sad[2];
4503a55ed7faSriastradh }
4504a55ed7faSriastradh break;
4505a55ed7faSriastradh }
4506a55ed7faSriastradh }
4507a55ed7faSriastradh
4508a55ed7faSriastradh return count;
4509a55ed7faSriastradh }
4510a55ed7faSriastradh EXPORT_SYMBOL(drm_edid_to_sad);
4511a55ed7faSriastradh
4512a55ed7faSriastradh /**
4513a55ed7faSriastradh * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4514a55ed7faSriastradh * @edid: EDID to parse
4515a55ed7faSriastradh * @sadb: pointer to the speaker block
4516a55ed7faSriastradh *
4517a55ed7faSriastradh * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4518a55ed7faSriastradh *
45194e59feabSriastradh * Note: The returned pointer needs to be freed using kfree().
45204e59feabSriastradh *
45214e59feabSriastradh * Return: The number of found Speaker Allocation Blocks or negative number on
45224e59feabSriastradh * error.
4523a55ed7faSriastradh */
drm_edid_to_speaker_allocation(struct edid * edid,u8 ** sadb)4524a55ed7faSriastradh int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4525a55ed7faSriastradh {
4526a55ed7faSriastradh int count = 0;
4527a55ed7faSriastradh int i, start, end, dbl;
4528a55ed7faSriastradh const u8 *cea;
4529a55ed7faSriastradh
4530a55ed7faSriastradh cea = drm_find_cea_extension(edid);
4531a55ed7faSriastradh if (!cea) {
4532a55ed7faSriastradh DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4533677dec6eSriastradh return 0;
4534a55ed7faSriastradh }
4535a55ed7faSriastradh
4536a55ed7faSriastradh if (cea_revision(cea) < 3) {
4537a55ed7faSriastradh DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4538677dec6eSriastradh return 0;
4539a55ed7faSriastradh }
4540a55ed7faSriastradh
4541a55ed7faSriastradh if (cea_db_offsets(cea, &start, &end)) {
4542a55ed7faSriastradh DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4543a55ed7faSriastradh return -EPROTO;
4544a55ed7faSriastradh }
4545a55ed7faSriastradh
4546a55ed7faSriastradh for_each_cea_db(cea, i, start, end) {
4547a55ed7faSriastradh const u8 *db = &cea[i];
4548a55ed7faSriastradh
4549a55ed7faSriastradh if (cea_db_tag(db) == SPEAKER_BLOCK) {
4550a55ed7faSriastradh dbl = cea_db_payload_len(db);
4551a55ed7faSriastradh
4552a55ed7faSriastradh /* Speaker Allocation Data Block */
4553a55ed7faSriastradh if (dbl == 3) {
45544e59feabSriastradh *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4555a55ed7faSriastradh if (!*sadb)
4556a55ed7faSriastradh return -ENOMEM;
4557a55ed7faSriastradh count = dbl;
4558a55ed7faSriastradh break;
4559a55ed7faSriastradh }
4560a55ed7faSriastradh }
4561a55ed7faSriastradh }
4562a55ed7faSriastradh
4563a55ed7faSriastradh return count;
4564a55ed7faSriastradh }
4565a55ed7faSriastradh EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4566a55ed7faSriastradh
4567a55ed7faSriastradh /**
45684e59feabSriastradh * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
456956053ce7Sriastradh * @connector: connector associated with the HDMI/DP sink
457056053ce7Sriastradh * @mode: the display mode
45714e59feabSriastradh *
45724e59feabSriastradh * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
45734e59feabSriastradh * the sink doesn't support audio or video.
457456053ce7Sriastradh */
drm_av_sync_delay(struct drm_connector * connector,const struct drm_display_mode * mode)457556053ce7Sriastradh int drm_av_sync_delay(struct drm_connector *connector,
45764e59feabSriastradh const struct drm_display_mode *mode)
457756053ce7Sriastradh {
457856053ce7Sriastradh int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
457956053ce7Sriastradh int a, v;
458056053ce7Sriastradh
458156053ce7Sriastradh if (!connector->latency_present[0])
458256053ce7Sriastradh return 0;
458356053ce7Sriastradh if (!connector->latency_present[1])
458456053ce7Sriastradh i = 0;
458556053ce7Sriastradh
458656053ce7Sriastradh a = connector->audio_latency[i];
458756053ce7Sriastradh v = connector->video_latency[i];
458856053ce7Sriastradh
458956053ce7Sriastradh /*
459056053ce7Sriastradh * HDMI/DP sink doesn't support audio or video?
459156053ce7Sriastradh */
459256053ce7Sriastradh if (a == 255 || v == 255)
459356053ce7Sriastradh return 0;
459456053ce7Sriastradh
459556053ce7Sriastradh /*
459656053ce7Sriastradh * Convert raw EDID values to millisecond.
459756053ce7Sriastradh * Treat unknown latency as 0ms.
459856053ce7Sriastradh */
459956053ce7Sriastradh if (a)
460056053ce7Sriastradh a = min(2 * (a - 1), 500);
460156053ce7Sriastradh if (v)
460256053ce7Sriastradh v = min(2 * (v - 1), 500);
460356053ce7Sriastradh
460456053ce7Sriastradh return max(v - a, 0);
460556053ce7Sriastradh }
460656053ce7Sriastradh EXPORT_SYMBOL(drm_av_sync_delay);
460756053ce7Sriastradh
460856053ce7Sriastradh /**
46094e59feabSriastradh * drm_detect_hdmi_monitor - detect whether monitor is HDMI
461056053ce7Sriastradh * @edid: monitor EDID information
461156053ce7Sriastradh *
461256053ce7Sriastradh * Parse the CEA extension according to CEA-861-B.
46134e59feabSriastradh *
46144e59feabSriastradh * Return: True if the monitor is HDMI, false if not or unknown.
461556053ce7Sriastradh */
drm_detect_hdmi_monitor(struct edid * edid)461656053ce7Sriastradh bool drm_detect_hdmi_monitor(struct edid *edid)
461756053ce7Sriastradh {
46182cbe17a3Sriastradh const u8 *edid_ext;
461956053ce7Sriastradh int i;
462056053ce7Sriastradh int start_offset, end_offset;
462156053ce7Sriastradh
462256053ce7Sriastradh edid_ext = drm_find_cea_extension(edid);
462356053ce7Sriastradh if (!edid_ext)
462456053ce7Sriastradh return false;
462556053ce7Sriastradh
462656053ce7Sriastradh if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
462756053ce7Sriastradh return false;
462856053ce7Sriastradh
462956053ce7Sriastradh /*
463056053ce7Sriastradh * Because HDMI identifier is in Vendor Specific Block,
463156053ce7Sriastradh * search it from all data blocks of CEA extension.
463256053ce7Sriastradh */
463356053ce7Sriastradh for_each_cea_db(edid_ext, i, start_offset, end_offset) {
463456053ce7Sriastradh if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
463556053ce7Sriastradh return true;
463656053ce7Sriastradh }
463756053ce7Sriastradh
463856053ce7Sriastradh return false;
463956053ce7Sriastradh }
464056053ce7Sriastradh EXPORT_SYMBOL(drm_detect_hdmi_monitor);
464156053ce7Sriastradh
464256053ce7Sriastradh /**
464356053ce7Sriastradh * drm_detect_monitor_audio - check monitor audio capability
4644a55ed7faSriastradh * @edid: EDID block to scan
464556053ce7Sriastradh *
464656053ce7Sriastradh * Monitor should have CEA extension block.
464756053ce7Sriastradh * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
464856053ce7Sriastradh * audio' only. If there is any audio extension block and supported
464956053ce7Sriastradh * audio format, assume at least 'basic audio' support, even if 'basic
465056053ce7Sriastradh * audio' is not defined in EDID.
465156053ce7Sriastradh *
46524e59feabSriastradh * Return: True if the monitor supports audio, false otherwise.
465356053ce7Sriastradh */
drm_detect_monitor_audio(struct edid * edid)465456053ce7Sriastradh bool drm_detect_monitor_audio(struct edid *edid)
465556053ce7Sriastradh {
46562cbe17a3Sriastradh const u8 *edid_ext;
465756053ce7Sriastradh int i, j;
465856053ce7Sriastradh bool has_audio = false;
465956053ce7Sriastradh int start_offset, end_offset;
466056053ce7Sriastradh
466156053ce7Sriastradh edid_ext = drm_find_cea_extension(edid);
466256053ce7Sriastradh if (!edid_ext)
466356053ce7Sriastradh goto end;
466456053ce7Sriastradh
466556053ce7Sriastradh has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
466656053ce7Sriastradh
466756053ce7Sriastradh if (has_audio) {
466856053ce7Sriastradh DRM_DEBUG_KMS("Monitor has basic audio support\n");
466956053ce7Sriastradh goto end;
467056053ce7Sriastradh }
467156053ce7Sriastradh
467256053ce7Sriastradh if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
467356053ce7Sriastradh goto end;
467456053ce7Sriastradh
467556053ce7Sriastradh for_each_cea_db(edid_ext, i, start_offset, end_offset) {
467656053ce7Sriastradh if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
467756053ce7Sriastradh has_audio = true;
467856053ce7Sriastradh for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
467956053ce7Sriastradh DRM_DEBUG_KMS("CEA audio format %d\n",
468056053ce7Sriastradh (edid_ext[i + j] >> 3) & 0xf);
468156053ce7Sriastradh goto end;
468256053ce7Sriastradh }
468356053ce7Sriastradh }
468456053ce7Sriastradh end:
468556053ce7Sriastradh return has_audio;
468656053ce7Sriastradh }
468756053ce7Sriastradh EXPORT_SYMBOL(drm_detect_monitor_audio);
468856053ce7Sriastradh
4689a55ed7faSriastradh
4690a55ed7faSriastradh /**
4691677dec6eSriastradh * drm_default_rgb_quant_range - default RGB quantization range
4692677dec6eSriastradh * @mode: display mode
46934e59feabSriastradh *
4694677dec6eSriastradh * Determine the default RGB quantization range for the mode,
4695677dec6eSriastradh * as specified in CEA-861.
4696677dec6eSriastradh *
4697677dec6eSriastradh * Return: The default RGB quantization range for the mode
46984e59feabSriastradh */
4699677dec6eSriastradh enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode * mode)4700677dec6eSriastradh drm_default_rgb_quant_range(const struct drm_display_mode *mode)
47014e59feabSriastradh {
4702677dec6eSriastradh /* All CEA modes other than VIC 1 use limited quantization range. */
4703677dec6eSriastradh return drm_match_cea_mode(mode) > 1 ?
4704677dec6eSriastradh HDMI_QUANTIZATION_RANGE_LIMITED :
4705677dec6eSriastradh HDMI_QUANTIZATION_RANGE_FULL;
4706677dec6eSriastradh }
4707677dec6eSriastradh EXPORT_SYMBOL(drm_default_rgb_quant_range);
47084e59feabSriastradh
drm_parse_vcdb(struct drm_connector * connector,const u8 * db)4709677dec6eSriastradh static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4710677dec6eSriastradh {
4711677dec6eSriastradh struct drm_display_info *info = &connector->display_info;
47124e59feabSriastradh
4713677dec6eSriastradh DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4714677dec6eSriastradh
4715677dec6eSriastradh if (db[2] & EDID_CEA_VCDB_QS)
4716677dec6eSriastradh info->rgb_quant_range_selectable = true;
4717677dec6eSriastradh }
4718677dec6eSriastradh
drm_parse_ycbcr420_deep_color_info(struct drm_connector * connector,const u8 * db)4719677dec6eSriastradh static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4720677dec6eSriastradh const u8 *db)
4721677dec6eSriastradh {
4722677dec6eSriastradh u8 dc_mask;
4723677dec6eSriastradh struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4724677dec6eSriastradh
4725677dec6eSriastradh dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4726677dec6eSriastradh hdmi->y420_dc_modes = dc_mask;
4727677dec6eSriastradh }
4728677dec6eSriastradh
drm_parse_hdmi_forum_vsdb(struct drm_connector * connector,const u8 * hf_vsdb)4729677dec6eSriastradh static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4730677dec6eSriastradh const u8 *hf_vsdb)
4731677dec6eSriastradh {
4732677dec6eSriastradh struct drm_display_info *display = &connector->display_info;
4733677dec6eSriastradh struct drm_hdmi_info *hdmi = &display->hdmi;
4734677dec6eSriastradh
4735677dec6eSriastradh display->has_hdmi_infoframe = true;
4736677dec6eSriastradh
4737677dec6eSriastradh if (hf_vsdb[6] & 0x80) {
4738677dec6eSriastradh hdmi->scdc.supported = true;
4739677dec6eSriastradh if (hf_vsdb[6] & 0x40)
4740677dec6eSriastradh hdmi->scdc.read_request = true;
4741677dec6eSriastradh }
47424e59feabSriastradh
47434e59feabSriastradh /*
4744677dec6eSriastradh * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4745677dec6eSriastradh * And as per the spec, three factors confirm this:
4746677dec6eSriastradh * * Availability of a HF-VSDB block in EDID (check)
4747677dec6eSriastradh * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4748677dec6eSriastradh * * SCDC support available (let's check)
4749677dec6eSriastradh * Lets check it out.
47504e59feabSriastradh */
4751677dec6eSriastradh
4752677dec6eSriastradh if (hf_vsdb[5]) {
4753677dec6eSriastradh /* max clock is 5000 KHz times block value */
4754677dec6eSriastradh u32 max_tmds_clock = hf_vsdb[5] * 5000;
4755677dec6eSriastradh struct drm_scdc *scdc = &hdmi->scdc;
4756677dec6eSriastradh
4757677dec6eSriastradh if (max_tmds_clock > 340000) {
4758677dec6eSriastradh display->max_tmds_clock = max_tmds_clock;
4759677dec6eSriastradh DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4760677dec6eSriastradh display->max_tmds_clock);
4761677dec6eSriastradh }
4762677dec6eSriastradh
4763677dec6eSriastradh if (scdc->supported) {
4764677dec6eSriastradh scdc->scrambling.supported = true;
4765677dec6eSriastradh
4766677dec6eSriastradh /* Few sinks support scrambling for clocks < 340M */
4767677dec6eSriastradh if ((hf_vsdb[6] & 0x8))
4768677dec6eSriastradh scdc->scrambling.low_rates = true;
4769677dec6eSriastradh }
4770677dec6eSriastradh }
4771677dec6eSriastradh
4772677dec6eSriastradh drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4773677dec6eSriastradh }
4774677dec6eSriastradh
drm_parse_hdmi_deep_color_info(struct drm_connector * connector,const u8 * hdmi)4775677dec6eSriastradh static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4776677dec6eSriastradh const u8 *hdmi)
4777677dec6eSriastradh {
4778677dec6eSriastradh struct drm_display_info *info = &connector->display_info;
4779677dec6eSriastradh unsigned int dc_bpc = 0;
4780677dec6eSriastradh
47814e59feabSriastradh /* HDMI supports at least 8 bpc */
47824e59feabSriastradh info->bpc = 8;
47834e59feabSriastradh
47844e59feabSriastradh if (cea_db_payload_len(hdmi) < 6)
4785677dec6eSriastradh return;
47864e59feabSriastradh
47874e59feabSriastradh if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
47884e59feabSriastradh dc_bpc = 10;
47894e59feabSriastradh info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
47904e59feabSriastradh DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
47914e59feabSriastradh connector->name);
47924e59feabSriastradh }
47934e59feabSriastradh
47944e59feabSriastradh if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
47954e59feabSriastradh dc_bpc = 12;
47964e59feabSriastradh info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
47974e59feabSriastradh DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
47984e59feabSriastradh connector->name);
47994e59feabSriastradh }
48004e59feabSriastradh
48014e59feabSriastradh if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
48024e59feabSriastradh dc_bpc = 16;
48034e59feabSriastradh info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
48044e59feabSriastradh DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
48054e59feabSriastradh connector->name);
48064e59feabSriastradh }
48074e59feabSriastradh
4808677dec6eSriastradh if (dc_bpc == 0) {
4809677dec6eSriastradh DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4810677dec6eSriastradh connector->name);
4811677dec6eSriastradh return;
4812677dec6eSriastradh }
4813677dec6eSriastradh
48144e59feabSriastradh DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
48154e59feabSriastradh connector->name, dc_bpc);
48164e59feabSriastradh info->bpc = dc_bpc;
48174e59feabSriastradh
48184e59feabSriastradh /*
48194e59feabSriastradh * Deep color support mandates RGB444 support for all video
48204e59feabSriastradh * modes and forbids YCRCB422 support for all video modes per
48214e59feabSriastradh * HDMI 1.3 spec.
48224e59feabSriastradh */
48234e59feabSriastradh info->color_formats = DRM_COLOR_FORMAT_RGB444;
48244e59feabSriastradh
48254e59feabSriastradh /* YCRCB444 is optional according to spec. */
48264e59feabSriastradh if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
48274e59feabSriastradh info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
48284e59feabSriastradh DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
48294e59feabSriastradh connector->name);
48304e59feabSriastradh }
48314e59feabSriastradh
48324e59feabSriastradh /*
48334e59feabSriastradh * Spec says that if any deep color mode is supported at all,
48344e59feabSriastradh * then deep color 36 bit must be supported.
48354e59feabSriastradh */
48364e59feabSriastradh if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
48374e59feabSriastradh DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
48384e59feabSriastradh connector->name);
48394e59feabSriastradh }
48404e59feabSriastradh }
48414e59feabSriastradh
4842677dec6eSriastradh static void
drm_parse_hdmi_vsdb_video(struct drm_connector * connector,const u8 * db)4843677dec6eSriastradh drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
484456053ce7Sriastradh {
4845677dec6eSriastradh struct drm_display_info *info = &connector->display_info;
4846677dec6eSriastradh u8 len = cea_db_payload_len(db);
484756053ce7Sriastradh
4848677dec6eSriastradh if (len >= 6)
4849677dec6eSriastradh info->dvi_dual = db[6] & 1;
4850677dec6eSriastradh if (len >= 7)
4851677dec6eSriastradh info->max_tmds_clock = db[7] * 5000;
485256053ce7Sriastradh
4853677dec6eSriastradh DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4854677dec6eSriastradh "max TMDS clock %d kHz\n",
4855677dec6eSriastradh info->dvi_dual,
4856677dec6eSriastradh info->max_tmds_clock);
485756053ce7Sriastradh
4858677dec6eSriastradh drm_parse_hdmi_deep_color_info(connector, db);
4859677dec6eSriastradh }
486056053ce7Sriastradh
drm_parse_cea_ext(struct drm_connector * connector,const struct edid * edid)4861677dec6eSriastradh static void drm_parse_cea_ext(struct drm_connector *connector,
4862677dec6eSriastradh const struct edid *edid)
4863677dec6eSriastradh {
4864677dec6eSriastradh struct drm_display_info *info = &connector->display_info;
4865677dec6eSriastradh const u8 *edid_ext;
4866677dec6eSriastradh int i, start, end;
486756053ce7Sriastradh
486856053ce7Sriastradh edid_ext = drm_find_cea_extension(edid);
4869677dec6eSriastradh if (!edid_ext)
4870677dec6eSriastradh return;
4871677dec6eSriastradh
487256053ce7Sriastradh info->cea_rev = edid_ext[1];
487356053ce7Sriastradh
487456053ce7Sriastradh /* The existence of a CEA block should imply RGB support */
487556053ce7Sriastradh info->color_formats = DRM_COLOR_FORMAT_RGB444;
487656053ce7Sriastradh if (edid_ext[3] & EDID_CEA_YCRCB444)
487756053ce7Sriastradh info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
487856053ce7Sriastradh if (edid_ext[3] & EDID_CEA_YCRCB422)
487956053ce7Sriastradh info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4880677dec6eSriastradh
4881677dec6eSriastradh if (cea_db_offsets(edid_ext, &start, &end))
4882677dec6eSriastradh return;
4883677dec6eSriastradh
4884677dec6eSriastradh for_each_cea_db(edid_ext, i, start, end) {
4885677dec6eSriastradh const u8 *db = &edid_ext[i];
4886677dec6eSriastradh
4887677dec6eSriastradh if (cea_db_is_hdmi_vsdb(db))
4888677dec6eSriastradh drm_parse_hdmi_vsdb_video(connector, db);
4889677dec6eSriastradh if (cea_db_is_hdmi_forum_vsdb(db))
4890677dec6eSriastradh drm_parse_hdmi_forum_vsdb(connector, db);
4891677dec6eSriastradh if (cea_db_is_y420cmdb(db))
4892677dec6eSriastradh drm_parse_y420cmdb_bitmap(connector, db);
4893677dec6eSriastradh if (cea_db_is_vcdb(db))
4894677dec6eSriastradh drm_parse_vcdb(connector, db);
4895677dec6eSriastradh if (cea_db_is_hdmi_hdr_metadata_block(db))
4896677dec6eSriastradh drm_parse_hdr_metadata_block(connector, db);
4897677dec6eSriastradh }
489856053ce7Sriastradh }
489956053ce7Sriastradh
4900677dec6eSriastradh /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4901677dec6eSriastradh * all of the values which would have been set from EDID
4902677dec6eSriastradh */
4903677dec6eSriastradh void
drm_reset_display_info(struct drm_connector * connector)4904677dec6eSriastradh drm_reset_display_info(struct drm_connector *connector)
4905677dec6eSriastradh {
4906677dec6eSriastradh struct drm_display_info *info = &connector->display_info;
4907677dec6eSriastradh
4908677dec6eSriastradh info->width_mm = 0;
4909677dec6eSriastradh info->height_mm = 0;
4910677dec6eSriastradh
4911677dec6eSriastradh info->bpc = 0;
4912677dec6eSriastradh info->color_formats = 0;
4913677dec6eSriastradh info->cea_rev = 0;
4914677dec6eSriastradh info->max_tmds_clock = 0;
4915677dec6eSriastradh info->dvi_dual = false;
4916677dec6eSriastradh info->has_hdmi_infoframe = false;
4917677dec6eSriastradh info->rgb_quant_range_selectable = false;
4918677dec6eSriastradh memset(&info->hdmi, 0, sizeof(info->hdmi));
4919677dec6eSriastradh
4920677dec6eSriastradh info->non_desktop = 0;
4921677dec6eSriastradh }
4922677dec6eSriastradh
drm_add_display_info(struct drm_connector * connector,const struct edid * edid)4923677dec6eSriastradh u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4924677dec6eSriastradh {
4925677dec6eSriastradh struct drm_display_info *info = &connector->display_info;
4926677dec6eSriastradh
4927677dec6eSriastradh u32 quirks = edid_get_quirks(edid);
4928677dec6eSriastradh
4929677dec6eSriastradh drm_reset_display_info(connector);
4930677dec6eSriastradh
4931677dec6eSriastradh info->width_mm = edid->width_cm * 10;
4932677dec6eSriastradh info->height_mm = edid->height_cm * 10;
4933677dec6eSriastradh
4934677dec6eSriastradh info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4935677dec6eSriastradh
4936677dec6eSriastradh DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4937677dec6eSriastradh
4938677dec6eSriastradh if (edid->revision < 3)
4939677dec6eSriastradh return quirks;
4940677dec6eSriastradh
4941677dec6eSriastradh if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4942677dec6eSriastradh return quirks;
4943677dec6eSriastradh
4944677dec6eSriastradh drm_parse_cea_ext(connector, edid);
4945677dec6eSriastradh
4946677dec6eSriastradh /*
4947677dec6eSriastradh * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4948677dec6eSriastradh *
4949677dec6eSriastradh * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4950677dec6eSriastradh * tells us to assume 8 bpc color depth if the EDID doesn't have
4951677dec6eSriastradh * extensions which tell otherwise.
4952677dec6eSriastradh */
4953677dec6eSriastradh if (info->bpc == 0 && edid->revision == 3 &&
4954677dec6eSriastradh edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
4955677dec6eSriastradh info->bpc = 8;
4956677dec6eSriastradh DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4957677dec6eSriastradh connector->name, info->bpc);
4958677dec6eSriastradh }
49594e59feabSriastradh
496056053ce7Sriastradh /* Only defined for 1.4 with digital displays */
496156053ce7Sriastradh if (edid->revision < 4)
4962677dec6eSriastradh return quirks;
496356053ce7Sriastradh
496456053ce7Sriastradh switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
496556053ce7Sriastradh case DRM_EDID_DIGITAL_DEPTH_6:
496656053ce7Sriastradh info->bpc = 6;
496756053ce7Sriastradh break;
496856053ce7Sriastradh case DRM_EDID_DIGITAL_DEPTH_8:
496956053ce7Sriastradh info->bpc = 8;
497056053ce7Sriastradh break;
497156053ce7Sriastradh case DRM_EDID_DIGITAL_DEPTH_10:
497256053ce7Sriastradh info->bpc = 10;
497356053ce7Sriastradh break;
497456053ce7Sriastradh case DRM_EDID_DIGITAL_DEPTH_12:
497556053ce7Sriastradh info->bpc = 12;
497656053ce7Sriastradh break;
497756053ce7Sriastradh case DRM_EDID_DIGITAL_DEPTH_14:
497856053ce7Sriastradh info->bpc = 14;
497956053ce7Sriastradh break;
498056053ce7Sriastradh case DRM_EDID_DIGITAL_DEPTH_16:
498156053ce7Sriastradh info->bpc = 16;
498256053ce7Sriastradh break;
498356053ce7Sriastradh case DRM_EDID_DIGITAL_DEPTH_UNDEF:
498456053ce7Sriastradh default:
498556053ce7Sriastradh info->bpc = 0;
498656053ce7Sriastradh break;
498756053ce7Sriastradh }
498856053ce7Sriastradh
49894e59feabSriastradh DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
49904e59feabSriastradh connector->name, info->bpc);
49914e59feabSriastradh
499256053ce7Sriastradh info->color_formats |= DRM_COLOR_FORMAT_RGB444;
499356053ce7Sriastradh if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
499456053ce7Sriastradh info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
499556053ce7Sriastradh if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
499656053ce7Sriastradh info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4997677dec6eSriastradh return quirks;
4998677dec6eSriastradh }
4999677dec6eSriastradh
validate_displayid(const u8 * displayid,int length,int idx)50002cbe17a3Sriastradh static int validate_displayid(const u8 *displayid, int length, int idx)
5001677dec6eSriastradh {
5002677dec6eSriastradh int i;
5003677dec6eSriastradh u8 csum = 0;
50042cbe17a3Sriastradh const struct displayid_hdr *base;
5005677dec6eSriastradh
50062cbe17a3Sriastradh base = (const struct displayid_hdr *)&displayid[idx];
5007677dec6eSriastradh
5008677dec6eSriastradh DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
5009677dec6eSriastradh base->rev, base->bytes, base->prod_id, base->ext_count);
5010677dec6eSriastradh
5011677dec6eSriastradh if (base->bytes + 5 > length - idx)
5012677dec6eSriastradh return -EINVAL;
5013677dec6eSriastradh for (i = idx; i <= base->bytes + 5; i++) {
5014677dec6eSriastradh csum += displayid[i];
5015677dec6eSriastradh }
5016677dec6eSriastradh if (csum) {
5017677dec6eSriastradh DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
5018677dec6eSriastradh return -EINVAL;
5019677dec6eSriastradh }
5020677dec6eSriastradh return 0;
5021677dec6eSriastradh }
5022677dec6eSriastradh
drm_mode_displayid_detailed(struct drm_device * dev,const struct displayid_detailed_timings_1 * timings)5023677dec6eSriastradh static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
50242cbe17a3Sriastradh const struct displayid_detailed_timings_1 *timings)
5025677dec6eSriastradh {
5026677dec6eSriastradh struct drm_display_mode *mode;
5027677dec6eSriastradh unsigned pixel_clock = (timings->pixel_clock[0] |
5028677dec6eSriastradh (timings->pixel_clock[1] << 8) |
5029677dec6eSriastradh (timings->pixel_clock[2] << 16));
5030677dec6eSriastradh unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5031677dec6eSriastradh unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5032677dec6eSriastradh unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5033677dec6eSriastradh unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5034677dec6eSriastradh unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5035677dec6eSriastradh unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5036677dec6eSriastradh unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5037677dec6eSriastradh unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5038677dec6eSriastradh bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5039677dec6eSriastradh bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5040677dec6eSriastradh mode = drm_mode_create(dev);
5041677dec6eSriastradh if (!mode)
5042677dec6eSriastradh return NULL;
5043677dec6eSriastradh
5044677dec6eSriastradh mode->clock = pixel_clock * 10;
5045677dec6eSriastradh mode->hdisplay = hactive;
5046677dec6eSriastradh mode->hsync_start = mode->hdisplay + hsync;
5047677dec6eSriastradh mode->hsync_end = mode->hsync_start + hsync_width;
5048677dec6eSriastradh mode->htotal = mode->hdisplay + hblank;
5049677dec6eSriastradh
5050677dec6eSriastradh mode->vdisplay = vactive;
5051677dec6eSriastradh mode->vsync_start = mode->vdisplay + vsync;
5052677dec6eSriastradh mode->vsync_end = mode->vsync_start + vsync_width;
5053677dec6eSriastradh mode->vtotal = mode->vdisplay + vblank;
5054677dec6eSriastradh
5055677dec6eSriastradh mode->flags = 0;
5056677dec6eSriastradh mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5057677dec6eSriastradh mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5058677dec6eSriastradh mode->type = DRM_MODE_TYPE_DRIVER;
5059677dec6eSriastradh
5060677dec6eSriastradh if (timings->flags & 0x80)
5061677dec6eSriastradh mode->type |= DRM_MODE_TYPE_PREFERRED;
5062677dec6eSriastradh mode->vrefresh = drm_mode_vrefresh(mode);
5063677dec6eSriastradh drm_mode_set_name(mode);
5064677dec6eSriastradh
5065677dec6eSriastradh return mode;
5066677dec6eSriastradh }
5067677dec6eSriastradh
add_displayid_detailed_1_modes(struct drm_connector * connector,const struct displayid_block * block)5068677dec6eSriastradh static int add_displayid_detailed_1_modes(struct drm_connector *connector,
50692cbe17a3Sriastradh const struct displayid_block *block)
5070677dec6eSriastradh {
50712cbe17a3Sriastradh const struct displayid_detailed_timing_block *det = (const struct displayid_detailed_timing_block *)block;
5072677dec6eSriastradh int i;
5073677dec6eSriastradh int num_timings;
5074677dec6eSriastradh struct drm_display_mode *newmode;
5075677dec6eSriastradh int num_modes = 0;
5076677dec6eSriastradh /* blocks must be multiple of 20 bytes length */
5077677dec6eSriastradh if (block->num_bytes % 20)
5078677dec6eSriastradh return 0;
5079677dec6eSriastradh
5080677dec6eSriastradh num_timings = block->num_bytes / 20;
5081677dec6eSriastradh for (i = 0; i < num_timings; i++) {
50822cbe17a3Sriastradh const struct displayid_detailed_timings_1 *timings = &det->timings[i];
5083677dec6eSriastradh
5084677dec6eSriastradh newmode = drm_mode_displayid_detailed(connector->dev, timings);
5085677dec6eSriastradh if (!newmode)
5086677dec6eSriastradh continue;
5087677dec6eSriastradh
5088677dec6eSriastradh drm_mode_probed_add(connector, newmode);
5089677dec6eSriastradh num_modes++;
5090677dec6eSriastradh }
5091677dec6eSriastradh return num_modes;
5092677dec6eSriastradh }
5093677dec6eSriastradh
add_displayid_detailed_modes(struct drm_connector * connector,struct edid * edid)5094677dec6eSriastradh static int add_displayid_detailed_modes(struct drm_connector *connector,
5095677dec6eSriastradh struct edid *edid)
5096677dec6eSriastradh {
50972cbe17a3Sriastradh const u8 *displayid;
5098677dec6eSriastradh int ret;
5099677dec6eSriastradh int idx = 1;
5100677dec6eSriastradh int length = EDID_LENGTH;
51012cbe17a3Sriastradh const struct displayid_block *block;
5102677dec6eSriastradh int num_modes = 0;
5103677dec6eSriastradh
5104677dec6eSriastradh displayid = drm_find_displayid_extension(edid);
5105677dec6eSriastradh if (!displayid)
5106677dec6eSriastradh return 0;
5107677dec6eSriastradh
5108677dec6eSriastradh ret = validate_displayid(displayid, length, idx);
5109677dec6eSriastradh if (ret)
5110677dec6eSriastradh return 0;
5111677dec6eSriastradh
5112677dec6eSriastradh idx += sizeof(struct displayid_hdr);
5113677dec6eSriastradh for_each_displayid_db(displayid, block, idx, length) {
5114677dec6eSriastradh switch (block->tag) {
5115677dec6eSriastradh case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5116677dec6eSriastradh num_modes += add_displayid_detailed_1_modes(connector, block);
5117677dec6eSriastradh break;
5118677dec6eSriastradh }
5119677dec6eSriastradh }
5120677dec6eSriastradh return num_modes;
512156053ce7Sriastradh }
512256053ce7Sriastradh
512356053ce7Sriastradh /**
512456053ce7Sriastradh * drm_add_edid_modes - add modes from EDID data, if available
512556053ce7Sriastradh * @connector: connector we're probing
51264e59feabSriastradh * @edid: EDID data
512756053ce7Sriastradh *
5128677dec6eSriastradh * Add the specified modes to the connector's mode list. Also fills out the
5129677dec6eSriastradh * &drm_display_info structure and ELD in @connector with any information which
5130677dec6eSriastradh * can be derived from the edid.
513156053ce7Sriastradh *
51324e59feabSriastradh * Return: The number of modes added or 0 if we couldn't find any.
513356053ce7Sriastradh */
drm_add_edid_modes(struct drm_connector * connector,struct edid * edid)513456053ce7Sriastradh int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
513556053ce7Sriastradh {
513656053ce7Sriastradh int num_modes = 0;
513756053ce7Sriastradh u32 quirks;
513856053ce7Sriastradh
513956053ce7Sriastradh if (edid == NULL) {
5140677dec6eSriastradh clear_eld(connector);
514156053ce7Sriastradh return 0;
514256053ce7Sriastradh }
514356053ce7Sriastradh if (!drm_edid_is_valid(edid)) {
5144677dec6eSriastradh clear_eld(connector);
514556053ce7Sriastradh dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
51464e59feabSriastradh connector->name);
514756053ce7Sriastradh return 0;
514856053ce7Sriastradh }
514956053ce7Sriastradh
5150677dec6eSriastradh drm_edid_to_eld(connector, edid);
5151677dec6eSriastradh
5152677dec6eSriastradh /*
5153677dec6eSriastradh * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5154677dec6eSriastradh * To avoid multiple parsing of same block, lets parse that map
5155677dec6eSriastradh * from sink info, before parsing CEA modes.
5156677dec6eSriastradh */
5157677dec6eSriastradh quirks = drm_add_display_info(connector, edid);
515856053ce7Sriastradh
515956053ce7Sriastradh /*
516056053ce7Sriastradh * EDID spec says modes should be preferred in this order:
516156053ce7Sriastradh * - preferred detailed mode
516256053ce7Sriastradh * - other detailed modes from base block
516356053ce7Sriastradh * - detailed modes from extension blocks
516456053ce7Sriastradh * - CVT 3-byte code modes
516556053ce7Sriastradh * - standard timing codes
516656053ce7Sriastradh * - established timing codes
516756053ce7Sriastradh * - modes inferred from GTF or CVT range information
516856053ce7Sriastradh *
516956053ce7Sriastradh * We get this pretty much right.
517056053ce7Sriastradh *
517156053ce7Sriastradh * XXX order for additional mode types in extension blocks?
517256053ce7Sriastradh */
517356053ce7Sriastradh num_modes += add_detailed_modes(connector, edid, quirks);
517456053ce7Sriastradh num_modes += add_cvt_modes(connector, edid);
517556053ce7Sriastradh num_modes += add_standard_modes(connector, edid);
517656053ce7Sriastradh num_modes += add_established_modes(connector, edid);
517756053ce7Sriastradh num_modes += add_cea_modes(connector, edid);
5178a55ed7faSriastradh num_modes += add_alternate_cea_modes(connector, edid);
5179677dec6eSriastradh num_modes += add_displayid_detailed_modes(connector, edid);
51804e59feabSriastradh if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
51814e59feabSriastradh num_modes += add_inferred_modes(connector, edid);
518256053ce7Sriastradh
518356053ce7Sriastradh if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
518456053ce7Sriastradh edid_fixup_preferred(connector, quirks);
518556053ce7Sriastradh
51864e59feabSriastradh if (quirks & EDID_QUIRK_FORCE_6BPC)
51874e59feabSriastradh connector->display_info.bpc = 6;
518856053ce7Sriastradh
5189a55ed7faSriastradh if (quirks & EDID_QUIRK_FORCE_8BPC)
5190a55ed7faSriastradh connector->display_info.bpc = 8;
5191a55ed7faSriastradh
51924e59feabSriastradh if (quirks & EDID_QUIRK_FORCE_10BPC)
51934e59feabSriastradh connector->display_info.bpc = 10;
51944e59feabSriastradh
51954e59feabSriastradh if (quirks & EDID_QUIRK_FORCE_12BPC)
51964e59feabSriastradh connector->display_info.bpc = 12;
51974e59feabSriastradh
519856053ce7Sriastradh return num_modes;
519956053ce7Sriastradh }
520056053ce7Sriastradh EXPORT_SYMBOL(drm_add_edid_modes);
520156053ce7Sriastradh
520256053ce7Sriastradh /**
520356053ce7Sriastradh * drm_add_modes_noedid - add modes for the connectors without EDID
520456053ce7Sriastradh * @connector: connector we're probing
520556053ce7Sriastradh * @hdisplay: the horizontal display limit
520656053ce7Sriastradh * @vdisplay: the vertical display limit
520756053ce7Sriastradh *
520856053ce7Sriastradh * Add the specified modes to the connector's mode list. Only when the
520956053ce7Sriastradh * hdisplay/vdisplay is not beyond the given limit, it will be added.
521056053ce7Sriastradh *
52114e59feabSriastradh * Return: The number of modes added or 0 if we couldn't find any.
521256053ce7Sriastradh */
drm_add_modes_noedid(struct drm_connector * connector,int hdisplay,int vdisplay)521356053ce7Sriastradh int drm_add_modes_noedid(struct drm_connector *connector,
521456053ce7Sriastradh int hdisplay, int vdisplay)
521556053ce7Sriastradh {
521656053ce7Sriastradh int i, count, num_modes = 0;
521756053ce7Sriastradh struct drm_display_mode *mode;
521856053ce7Sriastradh struct drm_device *dev = connector->dev;
521956053ce7Sriastradh
52204e59feabSriastradh count = ARRAY_SIZE(drm_dmt_modes);
522156053ce7Sriastradh if (hdisplay < 0)
522256053ce7Sriastradh hdisplay = 0;
522356053ce7Sriastradh if (vdisplay < 0)
522456053ce7Sriastradh vdisplay = 0;
522556053ce7Sriastradh
522656053ce7Sriastradh for (i = 0; i < count; i++) {
522756053ce7Sriastradh const struct drm_display_mode *ptr = &drm_dmt_modes[i];
522856053ce7Sriastradh if (hdisplay && vdisplay) {
522956053ce7Sriastradh /*
523056053ce7Sriastradh * Only when two are valid, they will be used to check
523156053ce7Sriastradh * whether the mode should be added to the mode list of
523256053ce7Sriastradh * the connector.
523356053ce7Sriastradh */
523456053ce7Sriastradh if (ptr->hdisplay > hdisplay ||
523556053ce7Sriastradh ptr->vdisplay > vdisplay)
523656053ce7Sriastradh continue;
523756053ce7Sriastradh }
523856053ce7Sriastradh if (drm_mode_vrefresh(ptr) > 61)
523956053ce7Sriastradh continue;
524056053ce7Sriastradh mode = drm_mode_duplicate(dev, ptr);
524156053ce7Sriastradh if (mode) {
524256053ce7Sriastradh drm_mode_probed_add(connector, mode);
524356053ce7Sriastradh num_modes++;
524456053ce7Sriastradh }
524556053ce7Sriastradh }
524656053ce7Sriastradh return num_modes;
524756053ce7Sriastradh }
524856053ce7Sriastradh EXPORT_SYMBOL(drm_add_modes_noedid);
524956053ce7Sriastradh
52504e59feabSriastradh /**
52514e59feabSriastradh * drm_set_preferred_mode - Sets the preferred mode of a connector
52524e59feabSriastradh * @connector: connector whose mode list should be processed
52534e59feabSriastradh * @hpref: horizontal resolution of preferred mode
52544e59feabSriastradh * @vpref: vertical resolution of preferred mode
52554e59feabSriastradh *
52564e59feabSriastradh * Marks a mode as preferred if it matches the resolution specified by @hpref
52574e59feabSriastradh * and @vpref.
52584e59feabSriastradh */
drm_set_preferred_mode(struct drm_connector * connector,int hpref,int vpref)5259a55ed7faSriastradh void drm_set_preferred_mode(struct drm_connector *connector,
5260a55ed7faSriastradh int hpref, int vpref)
526156053ce7Sriastradh {
5262a55ed7faSriastradh struct drm_display_mode *mode;
526356053ce7Sriastradh
5264a55ed7faSriastradh list_for_each_entry(mode, &connector->probed_modes, head) {
5265a55ed7faSriastradh if (mode->hdisplay == hpref &&
5266a55ed7faSriastradh mode->vdisplay == vpref)
5267a55ed7faSriastradh mode->type |= DRM_MODE_TYPE_PREFERRED;
5268a55ed7faSriastradh }
5269a55ed7faSriastradh }
5270a55ed7faSriastradh EXPORT_SYMBOL(drm_set_preferred_mode);
5271a55ed7faSriastradh
is_hdmi2_sink(struct drm_connector * connector)5272677dec6eSriastradh static bool is_hdmi2_sink(struct drm_connector *connector)
5273677dec6eSriastradh {
5274677dec6eSriastradh /*
5275677dec6eSriastradh * FIXME: sil-sii8620 doesn't have a connector around when
5276677dec6eSriastradh * we need one, so we have to be prepared for a NULL connector.
5277677dec6eSriastradh */
5278677dec6eSriastradh if (!connector)
5279677dec6eSriastradh return true;
5280677dec6eSriastradh
5281677dec6eSriastradh return connector->display_info.hdmi.scdc.supported ||
5282677dec6eSriastradh connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5283677dec6eSriastradh }
5284677dec6eSriastradh
is_eotf_supported(u8 output_eotf,u8 sink_eotf)5285677dec6eSriastradh static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5286677dec6eSriastradh {
5287677dec6eSriastradh return sink_eotf & BIT(output_eotf);
5288677dec6eSriastradh }
5289677dec6eSriastradh
5290677dec6eSriastradh /**
5291677dec6eSriastradh * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5292677dec6eSriastradh * HDR metadata from userspace
5293677dec6eSriastradh * @frame: HDMI DRM infoframe
5294677dec6eSriastradh * @conn_state: Connector state containing HDR metadata
5295677dec6eSriastradh *
5296677dec6eSriastradh * Return: 0 on success or a negative error code on failure.
5297677dec6eSriastradh */
5298677dec6eSriastradh int
drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe * frame,const struct drm_connector_state * conn_state)5299677dec6eSriastradh drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5300677dec6eSriastradh const struct drm_connector_state *conn_state)
5301677dec6eSriastradh {
5302677dec6eSriastradh struct drm_connector *connector;
5303677dec6eSriastradh struct hdr_output_metadata *hdr_metadata;
5304677dec6eSriastradh int err;
5305677dec6eSriastradh
5306677dec6eSriastradh if (!frame || !conn_state)
5307677dec6eSriastradh return -EINVAL;
5308677dec6eSriastradh
5309677dec6eSriastradh connector = conn_state->connector;
5310677dec6eSriastradh
5311677dec6eSriastradh if (!conn_state->hdr_output_metadata)
5312677dec6eSriastradh return -EINVAL;
5313677dec6eSriastradh
5314677dec6eSriastradh hdr_metadata = conn_state->hdr_output_metadata->data;
5315677dec6eSriastradh
5316677dec6eSriastradh if (!hdr_metadata || !connector)
5317677dec6eSriastradh return -EINVAL;
5318677dec6eSriastradh
5319677dec6eSriastradh /* Sink EOTF is Bit map while infoframe is absolute values */
5320677dec6eSriastradh if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5321677dec6eSriastradh connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5322677dec6eSriastradh DRM_DEBUG_KMS("EOTF Not Supported\n");
5323677dec6eSriastradh return -EINVAL;
5324677dec6eSriastradh }
5325677dec6eSriastradh
5326677dec6eSriastradh err = hdmi_drm_infoframe_init(frame);
5327677dec6eSriastradh if (err < 0)
5328677dec6eSriastradh return err;
5329677dec6eSriastradh
5330677dec6eSriastradh frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5331677dec6eSriastradh frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5332677dec6eSriastradh
5333677dec6eSriastradh BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5334677dec6eSriastradh sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5335677dec6eSriastradh BUILD_BUG_ON(sizeof(frame->white_point) !=
5336677dec6eSriastradh sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5337677dec6eSriastradh
5338677dec6eSriastradh memcpy(&frame->display_primaries,
5339677dec6eSriastradh &hdr_metadata->hdmi_metadata_type1.display_primaries,
5340677dec6eSriastradh sizeof(frame->display_primaries));
5341677dec6eSriastradh
5342677dec6eSriastradh memcpy(&frame->white_point,
5343677dec6eSriastradh &hdr_metadata->hdmi_metadata_type1.white_point,
5344677dec6eSriastradh sizeof(frame->white_point));
5345677dec6eSriastradh
5346677dec6eSriastradh frame->max_display_mastering_luminance =
5347677dec6eSriastradh hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5348677dec6eSriastradh frame->min_display_mastering_luminance =
5349677dec6eSriastradh hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5350677dec6eSriastradh frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5351677dec6eSriastradh frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5352677dec6eSriastradh
5353677dec6eSriastradh return 0;
5354677dec6eSriastradh }
5355677dec6eSriastradh EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5356677dec6eSriastradh
drm_mode_hdmi_vic(struct drm_connector * connector,const struct drm_display_mode * mode)5357677dec6eSriastradh static u8 drm_mode_hdmi_vic(struct drm_connector *connector,
5358677dec6eSriastradh const struct drm_display_mode *mode)
5359677dec6eSriastradh {
5360677dec6eSriastradh bool has_hdmi_infoframe = connector ?
5361677dec6eSriastradh connector->display_info.has_hdmi_infoframe : false;
5362677dec6eSriastradh
5363677dec6eSriastradh if (!has_hdmi_infoframe)
5364677dec6eSriastradh return 0;
5365677dec6eSriastradh
5366677dec6eSriastradh /* No HDMI VIC when signalling 3D video format */
5367677dec6eSriastradh if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5368677dec6eSriastradh return 0;
5369677dec6eSriastradh
5370677dec6eSriastradh return drm_match_hdmi_mode(mode);
5371677dec6eSriastradh }
5372677dec6eSriastradh
drm_mode_cea_vic(struct drm_connector * connector,const struct drm_display_mode * mode)5373677dec6eSriastradh static u8 drm_mode_cea_vic(struct drm_connector *connector,
5374677dec6eSriastradh const struct drm_display_mode *mode)
5375677dec6eSriastradh {
5376677dec6eSriastradh u8 vic;
5377677dec6eSriastradh
5378677dec6eSriastradh /*
5379677dec6eSriastradh * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5380677dec6eSriastradh * we should send its VIC in vendor infoframes, else send the
5381677dec6eSriastradh * VIC in AVI infoframes. Lets check if this mode is present in
5382677dec6eSriastradh * HDMI 1.4b 4K modes
5383677dec6eSriastradh */
5384677dec6eSriastradh if (drm_mode_hdmi_vic(connector, mode))
5385677dec6eSriastradh return 0;
5386677dec6eSriastradh
5387677dec6eSriastradh vic = drm_match_cea_mode(mode);
5388677dec6eSriastradh
5389677dec6eSriastradh /*
5390677dec6eSriastradh * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5391677dec6eSriastradh * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5392677dec6eSriastradh * have to make sure we dont break HDMI 1.4 sinks.
5393677dec6eSriastradh */
5394677dec6eSriastradh if (!is_hdmi2_sink(connector) && vic > 64)
5395677dec6eSriastradh return 0;
5396677dec6eSriastradh
5397677dec6eSriastradh return vic;
5398677dec6eSriastradh }
5399677dec6eSriastradh
5400a55ed7faSriastradh /**
5401a55ed7faSriastradh * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5402a55ed7faSriastradh * data from a DRM display mode
5403a55ed7faSriastradh * @frame: HDMI AVI infoframe
5404677dec6eSriastradh * @connector: the connector
5405a55ed7faSriastradh * @mode: DRM display mode
5406a55ed7faSriastradh *
54074e59feabSriastradh * Return: 0 on success or a negative error code on failure.
5408a55ed7faSriastradh */
5409a55ed7faSriastradh int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe * frame,struct drm_connector * connector,const struct drm_display_mode * mode)5410a55ed7faSriastradh drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5411677dec6eSriastradh struct drm_connector *connector,
5412a55ed7faSriastradh const struct drm_display_mode *mode)
5413a55ed7faSriastradh {
5414677dec6eSriastradh enum hdmi_picture_aspect picture_aspect;
5415677dec6eSriastradh u8 vic, hdmi_vic;
5416a55ed7faSriastradh int err;
5417a55ed7faSriastradh
5418a55ed7faSriastradh if (!frame || !mode)
5419a55ed7faSriastradh return -EINVAL;
5420a55ed7faSriastradh
5421a55ed7faSriastradh err = hdmi_avi_infoframe_init(frame);
5422a55ed7faSriastradh if (err < 0)
5423a55ed7faSriastradh return err;
5424a55ed7faSriastradh
5425a55ed7faSriastradh if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5426a55ed7faSriastradh frame->pixel_repeat = 1;
5427a55ed7faSriastradh
5428677dec6eSriastradh vic = drm_mode_cea_vic(connector, mode);
5429677dec6eSriastradh hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5430a55ed7faSriastradh
5431a55ed7faSriastradh frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
54324e59feabSriastradh
54334e59feabSriastradh /*
5434677dec6eSriastradh * As some drivers don't support atomic, we can't use connector state.
5435677dec6eSriastradh * So just initialize the frame with default values, just the same way
5436677dec6eSriastradh * as it's done with other properties here.
54374e59feabSriastradh */
5438677dec6eSriastradh frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5439677dec6eSriastradh frame->itc = 0;
54404e59feabSriastradh
5441677dec6eSriastradh /*
5442677dec6eSriastradh * Populate picture aspect ratio from either
5443677dec6eSriastradh * user input (if specified) or from the CEA/HDMI mode lists.
5444677dec6eSriastradh */
5445677dec6eSriastradh picture_aspect = mode->picture_aspect_ratio;
5446677dec6eSriastradh if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5447677dec6eSriastradh if (vic)
5448677dec6eSriastradh picture_aspect = drm_get_cea_aspect_ratio(vic);
5449677dec6eSriastradh else if (hdmi_vic)
5450677dec6eSriastradh picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5451677dec6eSriastradh }
5452677dec6eSriastradh
5453677dec6eSriastradh /*
5454677dec6eSriastradh * The infoframe can't convey anything but none, 4:3
5455677dec6eSriastradh * and 16:9, so if the user has asked for anything else
5456677dec6eSriastradh * we can only satisfy it by specifying the right VIC.
5457677dec6eSriastradh */
5458677dec6eSriastradh if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5459677dec6eSriastradh if (vic) {
5460677dec6eSriastradh if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5461677dec6eSriastradh return -EINVAL;
5462677dec6eSriastradh } else if (hdmi_vic) {
5463677dec6eSriastradh if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5464677dec6eSriastradh return -EINVAL;
5465677dec6eSriastradh } else {
5466677dec6eSriastradh return -EINVAL;
5467677dec6eSriastradh }
5468677dec6eSriastradh
5469677dec6eSriastradh picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5470677dec6eSriastradh }
5471677dec6eSriastradh
5472677dec6eSriastradh frame->video_code = vic;
5473677dec6eSriastradh frame->picture_aspect = picture_aspect;
5474a55ed7faSriastradh frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5475a55ed7faSriastradh frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
547656053ce7Sriastradh
547756053ce7Sriastradh return 0;
547856053ce7Sriastradh }
5479a55ed7faSriastradh EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5480a55ed7faSriastradh
5481677dec6eSriastradh /* HDMI Colorspace Spec Definitions */
5482677dec6eSriastradh #define FULL_COLORIMETRY_MASK 0x1FF
5483677dec6eSriastradh #define NORMAL_COLORIMETRY_MASK 0x3
5484677dec6eSriastradh #define EXTENDED_COLORIMETRY_MASK 0x7
5485677dec6eSriastradh #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5486677dec6eSriastradh
5487677dec6eSriastradh #define C(x) ((x) << 0)
5488677dec6eSriastradh #define EC(x) ((x) << 2)
5489677dec6eSriastradh #define ACE(x) ((x) << 5)
5490677dec6eSriastradh
5491677dec6eSriastradh #define HDMI_COLORIMETRY_NO_DATA 0x0
5492677dec6eSriastradh #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5493677dec6eSriastradh #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5494677dec6eSriastradh #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5495677dec6eSriastradh #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5496677dec6eSriastradh #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5497677dec6eSriastradh #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5498677dec6eSriastradh #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5499677dec6eSriastradh #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5500677dec6eSriastradh #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5501677dec6eSriastradh #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5502677dec6eSriastradh #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5503677dec6eSriastradh #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5504677dec6eSriastradh
5505677dec6eSriastradh static const u32 hdmi_colorimetry_val[] = {
5506677dec6eSriastradh [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5507677dec6eSriastradh [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5508677dec6eSriastradh [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5509677dec6eSriastradh [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5510677dec6eSriastradh [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5511677dec6eSriastradh [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5512677dec6eSriastradh [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5513677dec6eSriastradh [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5514677dec6eSriastradh [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5515677dec6eSriastradh [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5516677dec6eSriastradh [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5517677dec6eSriastradh };
5518677dec6eSriastradh
5519677dec6eSriastradh #undef C
5520677dec6eSriastradh #undef EC
5521677dec6eSriastradh #undef ACE
5522677dec6eSriastradh
5523677dec6eSriastradh /**
5524677dec6eSriastradh * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5525677dec6eSriastradh * colorspace information
5526677dec6eSriastradh * @frame: HDMI AVI infoframe
5527677dec6eSriastradh * @conn_state: connector state
5528677dec6eSriastradh */
5529677dec6eSriastradh void
drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe * frame,const struct drm_connector_state * conn_state)5530677dec6eSriastradh drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5531677dec6eSriastradh const struct drm_connector_state *conn_state)
5532677dec6eSriastradh {
5533677dec6eSriastradh u32 colorimetry_val;
5534677dec6eSriastradh u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5535677dec6eSriastradh
5536677dec6eSriastradh if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5537677dec6eSriastradh colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5538677dec6eSriastradh else
5539677dec6eSriastradh colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5540677dec6eSriastradh
5541677dec6eSriastradh frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5542677dec6eSriastradh /*
5543677dec6eSriastradh * ToDo: Extend it for ACE formats as well. Modify the infoframe
5544677dec6eSriastradh * structure and extend it in drivers/video/hdmi
5545677dec6eSriastradh */
5546677dec6eSriastradh frame->extended_colorimetry = (colorimetry_val >> 2) &
5547677dec6eSriastradh EXTENDED_COLORIMETRY_MASK;
5548677dec6eSriastradh }
5549677dec6eSriastradh EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5550677dec6eSriastradh
5551677dec6eSriastradh /**
5552677dec6eSriastradh * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5553677dec6eSriastradh * quantization range information
5554677dec6eSriastradh * @frame: HDMI AVI infoframe
5555677dec6eSriastradh * @connector: the connector
5556677dec6eSriastradh * @mode: DRM display mode
5557677dec6eSriastradh * @rgb_quant_range: RGB quantization range (Q)
5558677dec6eSriastradh */
5559677dec6eSriastradh void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe * frame,struct drm_connector * connector,const struct drm_display_mode * mode,enum hdmi_quantization_range rgb_quant_range)5560677dec6eSriastradh drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5561677dec6eSriastradh struct drm_connector *connector,
5562677dec6eSriastradh const struct drm_display_mode *mode,
5563677dec6eSriastradh enum hdmi_quantization_range rgb_quant_range)
5564677dec6eSriastradh {
5565677dec6eSriastradh const struct drm_display_info *info = &connector->display_info;
5566677dec6eSriastradh
5567677dec6eSriastradh /*
5568677dec6eSriastradh * CEA-861:
5569677dec6eSriastradh * "A Source shall not send a non-zero Q value that does not correspond
5570677dec6eSriastradh * to the default RGB Quantization Range for the transmitted Picture
5571677dec6eSriastradh * unless the Sink indicates support for the Q bit in a Video
5572677dec6eSriastradh * Capabilities Data Block."
5573677dec6eSriastradh *
5574677dec6eSriastradh * HDMI 2.0 recommends sending non-zero Q when it does match the
5575677dec6eSriastradh * default RGB quantization range for the mode, even when QS=0.
5576677dec6eSriastradh */
5577677dec6eSriastradh if (info->rgb_quant_range_selectable ||
5578677dec6eSriastradh rgb_quant_range == drm_default_rgb_quant_range(mode))
5579677dec6eSriastradh frame->quantization_range = rgb_quant_range;
5580677dec6eSriastradh else
5581677dec6eSriastradh frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5582677dec6eSriastradh
5583677dec6eSriastradh /*
5584677dec6eSriastradh * CEA-861-F:
5585677dec6eSriastradh * "When transmitting any RGB colorimetry, the Source should set the
5586677dec6eSriastradh * YQ-field to match the RGB Quantization Range being transmitted
5587677dec6eSriastradh * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5588677dec6eSriastradh * set YQ=1) and the Sink shall ignore the YQ-field."
5589677dec6eSriastradh *
5590677dec6eSriastradh * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5591677dec6eSriastradh * by non-zero YQ when receiving RGB. There doesn't seem to be any
5592677dec6eSriastradh * good way to tell which version of CEA-861 the sink supports, so
5593677dec6eSriastradh * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5594677dec6eSriastradh * on on CEA-861-F.
5595677dec6eSriastradh */
5596677dec6eSriastradh if (!is_hdmi2_sink(connector) ||
5597677dec6eSriastradh rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5598677dec6eSriastradh frame->ycc_quantization_range =
5599677dec6eSriastradh HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5600677dec6eSriastradh else
5601677dec6eSriastradh frame->ycc_quantization_range =
5602677dec6eSriastradh HDMI_YCC_QUANTIZATION_RANGE_FULL;
5603677dec6eSriastradh }
5604677dec6eSriastradh EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5605677dec6eSriastradh
5606677dec6eSriastradh /**
5607677dec6eSriastradh * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5608677dec6eSriastradh * bar information
5609677dec6eSriastradh * @frame: HDMI AVI infoframe
5610677dec6eSriastradh * @conn_state: connector state
5611677dec6eSriastradh */
5612677dec6eSriastradh void
drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe * frame,const struct drm_connector_state * conn_state)5613677dec6eSriastradh drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5614677dec6eSriastradh const struct drm_connector_state *conn_state)
5615677dec6eSriastradh {
5616677dec6eSriastradh frame->right_bar = conn_state->tv.margins.right;
5617677dec6eSriastradh frame->left_bar = conn_state->tv.margins.left;
5618677dec6eSriastradh frame->top_bar = conn_state->tv.margins.top;
5619677dec6eSriastradh frame->bottom_bar = conn_state->tv.margins.bottom;
5620677dec6eSriastradh }
5621677dec6eSriastradh EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5622677dec6eSriastradh
5623a55ed7faSriastradh static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode * mode)5624a55ed7faSriastradh s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5625a55ed7faSriastradh {
5626a55ed7faSriastradh u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5627a55ed7faSriastradh
5628a55ed7faSriastradh switch (layout) {
5629a55ed7faSriastradh case DRM_MODE_FLAG_3D_FRAME_PACKING:
5630a55ed7faSriastradh return HDMI_3D_STRUCTURE_FRAME_PACKING;
5631a55ed7faSriastradh case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5632a55ed7faSriastradh return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5633a55ed7faSriastradh case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5634a55ed7faSriastradh return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5635a55ed7faSriastradh case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5636a55ed7faSriastradh return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5637a55ed7faSriastradh case DRM_MODE_FLAG_3D_L_DEPTH:
5638a55ed7faSriastradh return HDMI_3D_STRUCTURE_L_DEPTH;
5639a55ed7faSriastradh case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5640a55ed7faSriastradh return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5641a55ed7faSriastradh case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5642a55ed7faSriastradh return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5643a55ed7faSriastradh case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5644a55ed7faSriastradh return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5645a55ed7faSriastradh default:
5646a55ed7faSriastradh return HDMI_3D_STRUCTURE_INVALID;
5647a55ed7faSriastradh }
5648a55ed7faSriastradh }
5649a55ed7faSriastradh
5650a55ed7faSriastradh /**
5651a55ed7faSriastradh * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5652a55ed7faSriastradh * data from a DRM display mode
5653a55ed7faSriastradh * @frame: HDMI vendor infoframe
5654677dec6eSriastradh * @connector: the connector
5655a55ed7faSriastradh * @mode: DRM display mode
5656a55ed7faSriastradh *
5657a55ed7faSriastradh * Note that there's is a need to send HDMI vendor infoframes only when using a
5658a55ed7faSriastradh * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5659a55ed7faSriastradh * function will return -EINVAL, error that can be safely ignored.
5660a55ed7faSriastradh *
56614e59feabSriastradh * Return: 0 on success or a negative error code on failure.
5662a55ed7faSriastradh */
5663a55ed7faSriastradh int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe * frame,struct drm_connector * connector,const struct drm_display_mode * mode)5664a55ed7faSriastradh drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5665677dec6eSriastradh struct drm_connector *connector,
5666a55ed7faSriastradh const struct drm_display_mode *mode)
5667a55ed7faSriastradh {
5668677dec6eSriastradh /*
5669677dec6eSriastradh * FIXME: sil-sii8620 doesn't have a connector around when
5670677dec6eSriastradh * we need one, so we have to be prepared for a NULL connector.
5671677dec6eSriastradh */
5672677dec6eSriastradh bool has_hdmi_infoframe = connector ?
5673677dec6eSriastradh connector->display_info.has_hdmi_infoframe : false;
5674a55ed7faSriastradh int err;
5675a55ed7faSriastradh
5676a55ed7faSriastradh if (!frame || !mode)
5677a55ed7faSriastradh return -EINVAL;
5678a55ed7faSriastradh
5679677dec6eSriastradh if (!has_hdmi_infoframe)
5680a55ed7faSriastradh return -EINVAL;
5681a55ed7faSriastradh
5682a55ed7faSriastradh err = hdmi_vendor_infoframe_init(frame);
5683a55ed7faSriastradh if (err < 0)
5684a55ed7faSriastradh return err;
5685a55ed7faSriastradh
5686677dec6eSriastradh /*
5687677dec6eSriastradh * Even if it's not absolutely necessary to send the infoframe
5688677dec6eSriastradh * (ie.vic==0 and s3d_struct==0) we will still send it if we
5689677dec6eSriastradh * know that the sink can handle it. This is based on a
5690677dec6eSriastradh * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5691677dec6eSriastradh * have trouble realizing that they shuld switch from 3D to 2D
5692677dec6eSriastradh * mode if the source simply stops sending the infoframe when
5693677dec6eSriastradh * it wants to switch from 3D to 2D.
5694677dec6eSriastradh */
5695677dec6eSriastradh frame->vic = drm_mode_hdmi_vic(connector, mode);
5696a55ed7faSriastradh frame->s3d_struct = s3d_structure_from_display_mode(mode);
5697a55ed7faSriastradh
5698a55ed7faSriastradh return 0;
5699a55ed7faSriastradh }
5700a55ed7faSriastradh EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
57014e59feabSriastradh
drm_parse_tiled_block(struct drm_connector * connector,const struct displayid_block * block)5702677dec6eSriastradh static int drm_parse_tiled_block(struct drm_connector *connector,
57032cbe17a3Sriastradh const struct displayid_block *block)
57044e59feabSriastradh {
57052cbe17a3Sriastradh const struct displayid_tiled_block *tile = (const struct displayid_tiled_block *)block;
57064e59feabSriastradh u16 w, h;
57074e59feabSriastradh u8 tile_v_loc, tile_h_loc;
57084e59feabSriastradh u8 num_v_tile, num_h_tile;
57094e59feabSriastradh struct drm_tile_group *tg;
57104e59feabSriastradh
57114e59feabSriastradh w = tile->tile_size[0] | tile->tile_size[1] << 8;
57124e59feabSriastradh h = tile->tile_size[2] | tile->tile_size[3] << 8;
57134e59feabSriastradh
57144e59feabSriastradh num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
57154e59feabSriastradh num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
57164e59feabSriastradh tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
57174e59feabSriastradh tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
57184e59feabSriastradh
57194e59feabSriastradh connector->has_tile = true;
57204e59feabSriastradh if (tile->tile_cap & 0x80)
57214e59feabSriastradh connector->tile_is_single_monitor = true;
57224e59feabSriastradh
57234e59feabSriastradh connector->num_h_tile = num_h_tile + 1;
57244e59feabSriastradh connector->num_v_tile = num_v_tile + 1;
57254e59feabSriastradh connector->tile_h_loc = tile_h_loc;
57264e59feabSriastradh connector->tile_v_loc = tile_v_loc;
57274e59feabSriastradh connector->tile_h_size = w + 1;
57284e59feabSriastradh connector->tile_v_size = h + 1;
57294e59feabSriastradh
57304e59feabSriastradh DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
57314e59feabSriastradh DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
57324e59feabSriastradh DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
57334e59feabSriastradh num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
57344e59feabSriastradh DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
57354e59feabSriastradh
57364e59feabSriastradh tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
57374e59feabSriastradh if (!tg) {
57384e59feabSriastradh tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
57394e59feabSriastradh }
57404e59feabSriastradh if (!tg)
57414e59feabSriastradh return -ENOMEM;
57424e59feabSriastradh
57434e59feabSriastradh if (connector->tile_group != tg) {
57444e59feabSriastradh /* if we haven't got a pointer,
57454e59feabSriastradh take the reference, drop ref to old tile group */
57464e59feabSriastradh if (connector->tile_group) {
57474e59feabSriastradh drm_mode_put_tile_group(connector->dev, connector->tile_group);
57484e59feabSriastradh }
57494e59feabSriastradh connector->tile_group = tg;
57504e59feabSriastradh } else
57514e59feabSriastradh /* if same tile group, then release the ref we just took. */
57524e59feabSriastradh drm_mode_put_tile_group(connector->dev, tg);
5753677dec6eSriastradh return 0;
57544e59feabSriastradh }
5755677dec6eSriastradh
drm_parse_display_id(struct drm_connector * connector,const u8 * displayid,int length,bool is_edid_extension)5756677dec6eSriastradh static int drm_parse_display_id(struct drm_connector *connector,
57572cbe17a3Sriastradh const u8 *displayid, int length,
5758677dec6eSriastradh bool is_edid_extension)
5759677dec6eSriastradh {
5760677dec6eSriastradh /* if this is an EDID extension the first byte will be 0x70 */
5761677dec6eSriastradh int idx = 0;
57622cbe17a3Sriastradh const struct displayid_block *block;
5763677dec6eSriastradh int ret;
5764677dec6eSriastradh
5765677dec6eSriastradh if (is_edid_extension)
5766677dec6eSriastradh idx = 1;
5767677dec6eSriastradh
5768677dec6eSriastradh ret = validate_displayid(displayid, length, idx);
5769677dec6eSriastradh if (ret)
5770677dec6eSriastradh return ret;
5771677dec6eSriastradh
5772677dec6eSriastradh idx += sizeof(struct displayid_hdr);
5773677dec6eSriastradh for_each_displayid_db(displayid, block, idx, length) {
5774677dec6eSriastradh DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5775677dec6eSriastradh block->tag, block->rev, block->num_bytes);
5776677dec6eSriastradh
5777677dec6eSriastradh switch (block->tag) {
5778677dec6eSriastradh case DATA_BLOCK_TILED_DISPLAY:
5779677dec6eSriastradh ret = drm_parse_tiled_block(connector, block);
5780677dec6eSriastradh if (ret)
5781677dec6eSriastradh return ret;
5782677dec6eSriastradh break;
5783677dec6eSriastradh case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5784677dec6eSriastradh /* handled in mode gathering code. */
5785677dec6eSriastradh break;
5786677dec6eSriastradh case DATA_BLOCK_CTA:
5787677dec6eSriastradh /* handled in the cea parser code. */
57884e59feabSriastradh break;
57894e59feabSriastradh default:
5790677dec6eSriastradh DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
57914e59feabSriastradh break;
57924e59feabSriastradh }
5793677dec6eSriastradh }
57944e59feabSriastradh return 0;
57954e59feabSriastradh }
57964e59feabSriastradh
drm_get_displayid(struct drm_connector * connector,struct edid * edid)57974e59feabSriastradh static void drm_get_displayid(struct drm_connector *connector,
57984e59feabSriastradh struct edid *edid)
57994e59feabSriastradh {
58002cbe17a3Sriastradh const void *displayid = NULL;
58014e59feabSriastradh int ret;
58024e59feabSriastradh connector->has_tile = false;
58034e59feabSriastradh displayid = drm_find_displayid_extension(edid);
58044e59feabSriastradh if (!displayid) {
58054e59feabSriastradh /* drop reference to any tile group we had */
58064e59feabSriastradh goto out_drop_ref;
58074e59feabSriastradh }
58084e59feabSriastradh
58094e59feabSriastradh ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
58104e59feabSriastradh if (ret < 0)
58114e59feabSriastradh goto out_drop_ref;
58124e59feabSriastradh if (!connector->has_tile)
58134e59feabSriastradh goto out_drop_ref;
58144e59feabSriastradh return;
58154e59feabSriastradh out_drop_ref:
58164e59feabSriastradh if (connector->tile_group) {
58174e59feabSriastradh drm_mode_put_tile_group(connector->dev, connector->tile_group);
58184e59feabSriastradh connector->tile_group = NULL;
58194e59feabSriastradh }
58204e59feabSriastradh return;
58214e59feabSriastradh }
5822