1 /* $NetBSD: drm_edid.c,v 1.8 2020/02/14 14:34:57 maya Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Luc Verhaegen (quirks list) 5 * Copyright (c) 2007-2008 Intel Corporation 6 * Jesse Barnes <jesse.barnes@intel.com> 7 * Copyright 2010 Red Hat, Inc. 8 * 9 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 10 * FB layer. 11 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a 14 * copy of this software and associated documentation files (the "Software"), 15 * to deal in the Software without restriction, including without limitation 16 * the rights to use, copy, modify, merge, publish, distribute, sub license, 17 * and/or sell copies of the Software, and to permit persons to whom the 18 * Software is furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 26 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 27 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 28 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 29 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 30 * DEALINGS IN THE SOFTWARE. 31 */ 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: drm_edid.c,v 1.8 2020/02/14 14:34:57 maya Exp $"); 34 35 #include <linux/kernel.h> 36 #include <linux/slab.h> 37 #include <linux/hdmi.h> 38 #include <linux/i2c.h> 39 #include <linux/module.h> 40 #include <drm/drmP.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_displayid.h> 43 44 #include <linux/nbsd-namespace.h> 45 46 #define version_greater(edid, maj, min) \ 47 (((edid)->version > (maj)) || \ 48 ((edid)->version == (maj) && (edid)->revision > (min))) 49 50 #define EDID_EST_TIMINGS 16 51 #define EDID_STD_TIMINGS 8 52 #define EDID_DETAILED_TIMINGS 4 53 54 /* 55 * EDID blocks out in the wild have a variety of bugs, try to collect 56 * them here (note that userspace may work around broken monitors first, 57 * but fixes should make their way here so that the kernel "just works" 58 * on as many displays as possible). 59 */ 60 61 /* First detailed mode wrong, use largest 60Hz mode */ 62 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 63 /* Reported 135MHz pixel clock is too high, needs adjustment */ 64 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 65 /* Prefer the largest mode at 75 Hz */ 66 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 67 /* Detail timing is in cm not mm */ 68 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 69 /* Detailed timing descriptors have bogus size values, so just take the 70 * maximum size and use that. 71 */ 72 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 73 /* Monitor forgot to set the first detailed is preferred bit. */ 74 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 75 /* use +hsync +vsync for detailed mode */ 76 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 77 /* Force reduced-blanking timings for detailed modes */ 78 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 79 /* Force 8bpc */ 80 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 81 /* Force 12bpc */ 82 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 83 /* Force 6bpc */ 84 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 85 /* Force 10bpc */ 86 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 87 88 struct detailed_mode_closure { 89 struct drm_connector *connector; 90 struct edid *edid; 91 bool preferred; 92 u32 quirks; 93 int modes; 94 }; 95 96 #define LEVEL_DMT 0 97 #define LEVEL_GTF 1 98 #define LEVEL_GTF2 2 99 #define LEVEL_CVT 3 100 101 static struct edid_quirk { 102 char vendor[4]; 103 int product_id; 104 u32 quirks; 105 } edid_quirk_list[] = { 106 /* Acer AL1706 */ 107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 108 /* Acer F51 */ 109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 110 /* Unknown Acer */ 111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 112 113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 115 116 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 117 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 118 119 /* Belinea 10 15 55 */ 120 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 121 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 122 123 /* Envision Peripherals, Inc. EN-7100e */ 124 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 125 /* Envision EN2028 */ 126 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 127 128 /* Funai Electronics PM36B */ 129 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 130 EDID_QUIRK_DETAILED_IN_CM }, 131 132 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 133 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 134 135 /* LG Philips LCD LP154W01-A5 */ 136 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 137 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 138 139 /* Philips 107p5 CRT */ 140 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 141 142 /* Proview AY765C */ 143 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 144 145 /* Samsung SyncMaster 205BW. Note: irony */ 146 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 147 /* Samsung SyncMaster 22[5-6]BW */ 148 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 149 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 150 151 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 152 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 153 154 /* ViewSonic VA2026w */ 155 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 156 157 /* Medion MD 30217 PG */ 158 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 159 160 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 161 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 162 163 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 164 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 165 }; 166 167 /* 168 * Autogenerated from the DMT spec. 169 * This table is copied from xfree86/modes/xf86EdidModes.c. 170 */ 171 static const struct drm_display_mode drm_dmt_modes[] = { 172 /* 0x01 - 640x350@85Hz */ 173 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 174 736, 832, 0, 350, 382, 385, 445, 0, 175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 176 /* 0x02 - 640x400@85Hz */ 177 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 178 736, 832, 0, 400, 401, 404, 445, 0, 179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 180 /* 0x03 - 720x400@85Hz */ 181 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 182 828, 936, 0, 400, 401, 404, 446, 0, 183 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 184 /* 0x04 - 640x480@60Hz */ 185 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 186 752, 800, 0, 480, 490, 492, 525, 0, 187 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 188 /* 0x05 - 640x480@72Hz */ 189 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 190 704, 832, 0, 480, 489, 492, 520, 0, 191 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 192 /* 0x06 - 640x480@75Hz */ 193 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 194 720, 840, 0, 480, 481, 484, 500, 0, 195 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 196 /* 0x07 - 640x480@85Hz */ 197 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 198 752, 832, 0, 480, 481, 484, 509, 0, 199 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 200 /* 0x08 - 800x600@56Hz */ 201 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 202 896, 1024, 0, 600, 601, 603, 625, 0, 203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 204 /* 0x09 - 800x600@60Hz */ 205 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 206 968, 1056, 0, 600, 601, 605, 628, 0, 207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 208 /* 0x0a - 800x600@72Hz */ 209 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 210 976, 1040, 0, 600, 637, 643, 666, 0, 211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 212 /* 0x0b - 800x600@75Hz */ 213 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 214 896, 1056, 0, 600, 601, 604, 625, 0, 215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 216 /* 0x0c - 800x600@85Hz */ 217 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 218 896, 1048, 0, 600, 601, 604, 631, 0, 219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 220 /* 0x0d - 800x600@120Hz RB */ 221 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 222 880, 960, 0, 600, 603, 607, 636, 0, 223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 224 /* 0x0e - 848x480@60Hz */ 225 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 226 976, 1088, 0, 480, 486, 494, 517, 0, 227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 228 /* 0x0f - 1024x768@43Hz, interlace */ 229 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 230 1208, 1264, 0, 768, 768, 772, 817, 0, 231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 232 DRM_MODE_FLAG_INTERLACE) }, 233 /* 0x10 - 1024x768@60Hz */ 234 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 235 1184, 1344, 0, 768, 771, 777, 806, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 237 /* 0x11 - 1024x768@70Hz */ 238 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 239 1184, 1328, 0, 768, 771, 777, 806, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x12 - 1024x768@75Hz */ 242 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 243 1136, 1312, 0, 768, 769, 772, 800, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 245 /* 0x13 - 1024x768@85Hz */ 246 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 247 1168, 1376, 0, 768, 769, 772, 808, 0, 248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 0x14 - 1024x768@120Hz RB */ 250 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 251 1104, 1184, 0, 768, 771, 775, 813, 0, 252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x15 - 1152x864@75Hz */ 254 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 255 1344, 1600, 0, 864, 865, 868, 900, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x55 - 1280x720@60Hz */ 258 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 259 1430, 1650, 0, 720, 725, 730, 750, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x16 - 1280x768@60Hz RB */ 262 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 263 1360, 1440, 0, 768, 771, 778, 790, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 265 /* 0x17 - 1280x768@60Hz */ 266 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 267 1472, 1664, 0, 768, 771, 778, 798, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x18 - 1280x768@75Hz */ 270 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 271 1488, 1696, 0, 768, 771, 778, 805, 0, 272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x19 - 1280x768@85Hz */ 274 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 275 1496, 1712, 0, 768, 771, 778, 809, 0, 276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x1a - 1280x768@120Hz RB */ 278 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 279 1360, 1440, 0, 768, 771, 778, 813, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 281 /* 0x1b - 1280x800@60Hz RB */ 282 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 283 1360, 1440, 0, 800, 803, 809, 823, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 285 /* 0x1c - 1280x800@60Hz */ 286 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 287 1480, 1680, 0, 800, 803, 809, 831, 0, 288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x1d - 1280x800@75Hz */ 290 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 291 1488, 1696, 0, 800, 803, 809, 838, 0, 292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 293 /* 0x1e - 1280x800@85Hz */ 294 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 295 1496, 1712, 0, 800, 803, 809, 843, 0, 296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x1f - 1280x800@120Hz RB */ 298 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 299 1360, 1440, 0, 800, 803, 809, 847, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 301 /* 0x20 - 1280x960@60Hz */ 302 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 303 1488, 1800, 0, 960, 961, 964, 1000, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 305 /* 0x21 - 1280x960@85Hz */ 306 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 307 1504, 1728, 0, 960, 961, 964, 1011, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 309 /* 0x22 - 1280x960@120Hz RB */ 310 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 311 1360, 1440, 0, 960, 963, 967, 1017, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 313 /* 0x23 - 1280x1024@60Hz */ 314 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 315 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 317 /* 0x24 - 1280x1024@75Hz */ 318 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 319 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x25 - 1280x1024@85Hz */ 322 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 323 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x26 - 1280x1024@120Hz RB */ 326 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 327 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 329 /* 0x27 - 1360x768@60Hz */ 330 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 331 1536, 1792, 0, 768, 771, 777, 795, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x28 - 1360x768@120Hz RB */ 334 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 335 1440, 1520, 0, 768, 771, 776, 813, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x51 - 1366x768@60Hz */ 338 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 339 1579, 1792, 0, 768, 771, 774, 798, 0, 340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x56 - 1366x768@60Hz */ 342 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 343 1436, 1500, 0, 768, 769, 772, 800, 0, 344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x29 - 1400x1050@60Hz RB */ 346 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 347 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 349 /* 0x2a - 1400x1050@60Hz */ 350 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 351 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 353 /* 0x2b - 1400x1050@75Hz */ 354 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 355 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x2c - 1400x1050@85Hz */ 358 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 359 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x2d - 1400x1050@120Hz RB */ 362 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 363 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 365 /* 0x2e - 1440x900@60Hz RB */ 366 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 367 1520, 1600, 0, 900, 903, 909, 926, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 369 /* 0x2f - 1440x900@60Hz */ 370 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 371 1672, 1904, 0, 900, 903, 909, 934, 0, 372 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x30 - 1440x900@75Hz */ 374 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 375 1688, 1936, 0, 900, 903, 909, 942, 0, 376 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x31 - 1440x900@85Hz */ 378 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 379 1696, 1952, 0, 900, 903, 909, 948, 0, 380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x32 - 1440x900@120Hz RB */ 382 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 383 1520, 1600, 0, 900, 903, 909, 953, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 385 /* 0x53 - 1600x900@60Hz */ 386 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 387 1704, 1800, 0, 900, 901, 904, 1000, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x33 - 1600x1200@60Hz */ 390 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 391 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x34 - 1600x1200@65Hz */ 394 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 395 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 0x35 - 1600x1200@70Hz */ 398 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 399 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 401 /* 0x36 - 1600x1200@75Hz */ 402 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 403 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x37 - 1600x1200@85Hz */ 406 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 407 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x38 - 1600x1200@120Hz RB */ 410 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 411 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 413 /* 0x39 - 1680x1050@60Hz RB */ 414 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 415 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 417 /* 0x3a - 1680x1050@60Hz */ 418 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 419 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 421 /* 0x3b - 1680x1050@75Hz */ 422 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 423 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x3c - 1680x1050@85Hz */ 426 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 427 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x3d - 1680x1050@120Hz RB */ 430 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 431 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 433 /* 0x3e - 1792x1344@60Hz */ 434 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 435 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 437 /* 0x3f - 1792x1344@75Hz */ 438 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 439 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 441 /* 0x40 - 1792x1344@120Hz RB */ 442 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 443 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 445 /* 0x41 - 1856x1392@60Hz */ 446 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 447 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x42 - 1856x1392@75Hz */ 450 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 451 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x43 - 1856x1392@120Hz RB */ 454 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 455 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 457 /* 0x52 - 1920x1080@60Hz */ 458 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 459 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 461 /* 0x44 - 1920x1200@60Hz RB */ 462 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 463 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 465 /* 0x45 - 1920x1200@60Hz */ 466 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 467 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 469 /* 0x46 - 1920x1200@75Hz */ 470 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 471 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x47 - 1920x1200@85Hz */ 474 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 475 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x48 - 1920x1200@120Hz RB */ 478 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 479 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 481 /* 0x49 - 1920x1440@60Hz */ 482 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 483 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 485 /* 0x4a - 1920x1440@75Hz */ 486 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 487 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x4b - 1920x1440@120Hz RB */ 490 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 491 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 493 /* 0x54 - 2048x1152@60Hz */ 494 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 495 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 497 /* 0x4c - 2560x1600@60Hz RB */ 498 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 499 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 501 /* 0x4d - 2560x1600@60Hz */ 502 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 503 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 505 /* 0x4e - 2560x1600@75Hz */ 506 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 507 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 509 /* 0x4f - 2560x1600@85Hz */ 510 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 511 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 513 /* 0x50 - 2560x1600@120Hz RB */ 514 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 515 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x57 - 4096x2160@60Hz RB */ 518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 519 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 521 /* 0x58 - 4096x2160@59.94Hz RB */ 522 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 523 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 525 }; 526 527 /* 528 * These more or less come from the DMT spec. The 720x400 modes are 529 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 530 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 531 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 532 * mode. 533 * 534 * The DMT modes have been fact-checked; the rest are mild guesses. 535 */ 536 static const struct drm_display_mode edid_est_modes[] = { 537 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 538 968, 1056, 0, 600, 601, 605, 628, 0, 539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 540 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 541 896, 1024, 0, 600, 601, 603, 625, 0, 542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 543 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 544 720, 840, 0, 480, 481, 484, 500, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 546 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 547 704, 832, 0, 480, 489, 491, 520, 0, 548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 549 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 550 768, 864, 0, 480, 483, 486, 525, 0, 551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 552 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 553 752, 800, 0, 480, 490, 492, 525, 0, 554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 555 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 556 846, 900, 0, 400, 421, 423, 449, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 558 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 559 846, 900, 0, 400, 412, 414, 449, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 561 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 562 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 564 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 565 1136, 1312, 0, 768, 769, 772, 800, 0, 566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 567 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 568 1184, 1328, 0, 768, 771, 777, 806, 0, 569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 570 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 571 1184, 1344, 0, 768, 771, 777, 806, 0, 572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 573 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 574 1208, 1264, 0, 768, 768, 776, 817, 0, 575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 576 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 577 928, 1152, 0, 624, 625, 628, 667, 0, 578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 579 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 580 896, 1056, 0, 600, 601, 604, 625, 0, 581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 582 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 583 976, 1040, 0, 600, 637, 643, 666, 0, 584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 585 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 586 1344, 1600, 0, 864, 865, 868, 900, 0, 587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 588 }; 589 590 struct minimode { 591 short w; 592 short h; 593 short r; 594 short rb; 595 }; 596 597 static const struct minimode est3_modes[] = { 598 /* byte 6 */ 599 { 640, 350, 85, 0 }, 600 { 640, 400, 85, 0 }, 601 { 720, 400, 85, 0 }, 602 { 640, 480, 85, 0 }, 603 { 848, 480, 60, 0 }, 604 { 800, 600, 85, 0 }, 605 { 1024, 768, 85, 0 }, 606 { 1152, 864, 75, 0 }, 607 /* byte 7 */ 608 { 1280, 768, 60, 1 }, 609 { 1280, 768, 60, 0 }, 610 { 1280, 768, 75, 0 }, 611 { 1280, 768, 85, 0 }, 612 { 1280, 960, 60, 0 }, 613 { 1280, 960, 85, 0 }, 614 { 1280, 1024, 60, 0 }, 615 { 1280, 1024, 85, 0 }, 616 /* byte 8 */ 617 { 1360, 768, 60, 0 }, 618 { 1440, 900, 60, 1 }, 619 { 1440, 900, 60, 0 }, 620 { 1440, 900, 75, 0 }, 621 { 1440, 900, 85, 0 }, 622 { 1400, 1050, 60, 1 }, 623 { 1400, 1050, 60, 0 }, 624 { 1400, 1050, 75, 0 }, 625 /* byte 9 */ 626 { 1400, 1050, 85, 0 }, 627 { 1680, 1050, 60, 1 }, 628 { 1680, 1050, 60, 0 }, 629 { 1680, 1050, 75, 0 }, 630 { 1680, 1050, 85, 0 }, 631 { 1600, 1200, 60, 0 }, 632 { 1600, 1200, 65, 0 }, 633 { 1600, 1200, 70, 0 }, 634 /* byte 10 */ 635 { 1600, 1200, 75, 0 }, 636 { 1600, 1200, 85, 0 }, 637 { 1792, 1344, 60, 0 }, 638 { 1792, 1344, 75, 0 }, 639 { 1856, 1392, 60, 0 }, 640 { 1856, 1392, 75, 0 }, 641 { 1920, 1200, 60, 1 }, 642 { 1920, 1200, 60, 0 }, 643 /* byte 11 */ 644 { 1920, 1200, 75, 0 }, 645 { 1920, 1200, 85, 0 }, 646 { 1920, 1440, 60, 0 }, 647 { 1920, 1440, 75, 0 }, 648 }; 649 650 static const struct minimode extra_modes[] = { 651 { 1024, 576, 60, 0 }, 652 { 1366, 768, 60, 0 }, 653 { 1600, 900, 60, 0 }, 654 { 1680, 945, 60, 0 }, 655 { 1920, 1080, 60, 0 }, 656 { 2048, 1152, 60, 0 }, 657 { 2048, 1536, 60, 0 }, 658 }; 659 660 /* 661 * Probably taken from CEA-861 spec. 662 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 663 */ 664 static const struct drm_display_mode edid_cea_modes[] = { 665 /* 1 - 640x480@60Hz */ 666 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 667 752, 800, 0, 480, 490, 492, 525, 0, 668 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 669 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 670 /* 2 - 720x480@60Hz */ 671 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 672 798, 858, 0, 480, 489, 495, 525, 0, 673 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 674 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 675 /* 3 - 720x480@60Hz */ 676 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 677 798, 858, 0, 480, 489, 495, 525, 0, 678 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 679 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 680 /* 4 - 1280x720@60Hz */ 681 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 682 1430, 1650, 0, 720, 725, 730, 750, 0, 683 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 684 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 685 /* 5 - 1920x1080i@60Hz */ 686 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 687 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 688 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 689 DRM_MODE_FLAG_INTERLACE), 690 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 691 /* 6 - 720(1440)x480i@60Hz */ 692 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 693 801, 858, 0, 480, 488, 494, 525, 0, 694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 695 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 696 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 697 /* 7 - 720(1440)x480i@60Hz */ 698 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 699 801, 858, 0, 480, 488, 494, 525, 0, 700 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 701 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 702 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 703 /* 8 - 720(1440)x240@60Hz */ 704 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 705 801, 858, 0, 240, 244, 247, 262, 0, 706 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 707 DRM_MODE_FLAG_DBLCLK), 708 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 709 /* 9 - 720(1440)x240@60Hz */ 710 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 711 801, 858, 0, 240, 244, 247, 262, 0, 712 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 713 DRM_MODE_FLAG_DBLCLK), 714 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 715 /* 10 - 2880x480i@60Hz */ 716 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 717 3204, 3432, 0, 480, 488, 494, 525, 0, 718 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 719 DRM_MODE_FLAG_INTERLACE), 720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 721 /* 11 - 2880x480i@60Hz */ 722 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 723 3204, 3432, 0, 480, 488, 494, 525, 0, 724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 725 DRM_MODE_FLAG_INTERLACE), 726 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 727 /* 12 - 2880x240@60Hz */ 728 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 729 3204, 3432, 0, 240, 244, 247, 262, 0, 730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 732 /* 13 - 2880x240@60Hz */ 733 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 734 3204, 3432, 0, 240, 244, 247, 262, 0, 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 736 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 737 /* 14 - 1440x480@60Hz */ 738 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 739 1596, 1716, 0, 480, 489, 495, 525, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 741 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 742 /* 15 - 1440x480@60Hz */ 743 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 744 1596, 1716, 0, 480, 489, 495, 525, 0, 745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 746 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 747 /* 16 - 1920x1080@60Hz */ 748 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 749 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 751 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 752 /* 17 - 720x576@50Hz */ 753 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 754 796, 864, 0, 576, 581, 586, 625, 0, 755 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 756 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 757 /* 18 - 720x576@50Hz */ 758 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 759 796, 864, 0, 576, 581, 586, 625, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 761 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 762 /* 19 - 1280x720@50Hz */ 763 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 764 1760, 1980, 0, 720, 725, 730, 750, 0, 765 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 766 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 767 /* 20 - 1920x1080i@50Hz */ 768 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 769 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 770 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 771 DRM_MODE_FLAG_INTERLACE), 772 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 773 /* 21 - 720(1440)x576i@50Hz */ 774 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 775 795, 864, 0, 576, 580, 586, 625, 0, 776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 777 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 778 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 779 /* 22 - 720(1440)x576i@50Hz */ 780 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 781 795, 864, 0, 576, 580, 586, 625, 0, 782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 783 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 784 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 785 /* 23 - 720(1440)x288@50Hz */ 786 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 787 795, 864, 0, 288, 290, 293, 312, 0, 788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 789 DRM_MODE_FLAG_DBLCLK), 790 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 791 /* 24 - 720(1440)x288@50Hz */ 792 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 793 795, 864, 0, 288, 290, 293, 312, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 795 DRM_MODE_FLAG_DBLCLK), 796 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 797 /* 25 - 2880x576i@50Hz */ 798 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 799 3180, 3456, 0, 576, 580, 586, 625, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 801 DRM_MODE_FLAG_INTERLACE), 802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 803 /* 26 - 2880x576i@50Hz */ 804 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 805 3180, 3456, 0, 576, 580, 586, 625, 0, 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 807 DRM_MODE_FLAG_INTERLACE), 808 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 809 /* 27 - 2880x288@50Hz */ 810 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 811 3180, 3456, 0, 288, 290, 293, 312, 0, 812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 814 /* 28 - 2880x288@50Hz */ 815 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 816 3180, 3456, 0, 288, 290, 293, 312, 0, 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 818 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 819 /* 29 - 1440x576@50Hz */ 820 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 821 1592, 1728, 0, 576, 581, 586, 625, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 823 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 824 /* 30 - 1440x576@50Hz */ 825 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 826 1592, 1728, 0, 576, 581, 586, 625, 0, 827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 828 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 31 - 1920x1080@50Hz */ 830 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 831 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 833 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 834 /* 32 - 1920x1080@24Hz */ 835 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 836 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 838 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 33 - 1920x1080@25Hz */ 840 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 841 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 843 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 844 /* 34 - 1920x1080@30Hz */ 845 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 846 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 847 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 848 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 35 - 2880x480@60Hz */ 850 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 851 3192, 3432, 0, 480, 489, 495, 525, 0, 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 853 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 854 /* 36 - 2880x480@60Hz */ 855 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 856 3192, 3432, 0, 480, 489, 495, 525, 0, 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 858 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 37 - 2880x576@50Hz */ 860 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 861 3184, 3456, 0, 576, 581, 586, 625, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 864 /* 38 - 2880x576@50Hz */ 865 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 866 3184, 3456, 0, 576, 581, 586, 625, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 868 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 869 /* 39 - 1920x1080i@50Hz */ 870 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 871 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 873 DRM_MODE_FLAG_INTERLACE), 874 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 875 /* 40 - 1920x1080i@100Hz */ 876 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 877 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 878 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 879 DRM_MODE_FLAG_INTERLACE), 880 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 881 /* 41 - 1280x720@100Hz */ 882 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 883 1760, 1980, 0, 720, 725, 730, 750, 0, 884 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 885 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 886 /* 42 - 720x576@100Hz */ 887 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 888 796, 864, 0, 576, 581, 586, 625, 0, 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 890 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 891 /* 43 - 720x576@100Hz */ 892 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 893 796, 864, 0, 576, 581, 586, 625, 0, 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 895 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 896 /* 44 - 720(1440)x576i@100Hz */ 897 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 898 795, 864, 0, 576, 580, 586, 625, 0, 899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 900 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 901 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 902 /* 45 - 720(1440)x576i@100Hz */ 903 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 904 795, 864, 0, 576, 580, 586, 625, 0, 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 906 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 907 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 908 /* 46 - 1920x1080i@120Hz */ 909 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 910 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 911 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 912 DRM_MODE_FLAG_INTERLACE), 913 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 914 /* 47 - 1280x720@120Hz */ 915 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 916 1430, 1650, 0, 720, 725, 730, 750, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 918 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 48 - 720x480@120Hz */ 920 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 921 798, 858, 0, 480, 489, 495, 525, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 923 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 924 /* 49 - 720x480@120Hz */ 925 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 926 798, 858, 0, 480, 489, 495, 525, 0, 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 928 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 50 - 720(1440)x480i@120Hz */ 930 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 931 801, 858, 0, 480, 488, 494, 525, 0, 932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 933 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 934 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 935 /* 51 - 720(1440)x480i@120Hz */ 936 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 937 801, 858, 0, 480, 488, 494, 525, 0, 938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 939 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 940 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 941 /* 52 - 720x576@200Hz */ 942 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 943 796, 864, 0, 576, 581, 586, 625, 0, 944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 945 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 946 /* 53 - 720x576@200Hz */ 947 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 948 796, 864, 0, 576, 581, 586, 625, 0, 949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 950 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 951 /* 54 - 720(1440)x576i@200Hz */ 952 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 953 795, 864, 0, 576, 580, 586, 625, 0, 954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 955 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 956 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 957 /* 55 - 720(1440)x576i@200Hz */ 958 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 959 795, 864, 0, 576, 580, 586, 625, 0, 960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 961 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 962 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 963 /* 56 - 720x480@240Hz */ 964 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 965 798, 858, 0, 480, 489, 495, 525, 0, 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 967 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 968 /* 57 - 720x480@240Hz */ 969 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 970 798, 858, 0, 480, 489, 495, 525, 0, 971 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 972 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 58 - 720(1440)x480i@240 */ 974 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 975 801, 858, 0, 480, 488, 494, 525, 0, 976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 977 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 978 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 979 /* 59 - 720(1440)x480i@240 */ 980 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 981 801, 858, 0, 480, 488, 494, 525, 0, 982 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 983 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 984 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 60 - 1280x720@24Hz */ 986 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 987 3080, 3300, 0, 720, 725, 730, 750, 0, 988 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 989 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 990 /* 61 - 1280x720@25Hz */ 991 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 992 3740, 3960, 0, 720, 725, 730, 750, 0, 993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 994 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 62 - 1280x720@30Hz */ 996 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 997 3080, 3300, 0, 720, 725, 730, 750, 0, 998 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 999 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1000 /* 63 - 1920x1080@120Hz */ 1001 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1002 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1003 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1004 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 64 - 1920x1080@100Hz */ 1006 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1007 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 1008 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1009 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1010 }; 1011 1012 /* 1013 * HDMI 1.4 4k modes. 1014 */ 1015 static const struct drm_display_mode edid_4k_modes[] = { 1016 /* 1 - 3840x2160@30Hz */ 1017 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1018 3840, 4016, 4104, 4400, 0, 1019 2160, 2168, 2178, 2250, 0, 1020 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1021 .vrefresh = 30, }, 1022 /* 2 - 3840x2160@25Hz */ 1023 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1024 3840, 4896, 4984, 5280, 0, 1025 2160, 2168, 2178, 2250, 0, 1026 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1027 .vrefresh = 25, }, 1028 /* 3 - 3840x2160@24Hz */ 1029 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1030 3840, 5116, 5204, 5500, 0, 1031 2160, 2168, 2178, 2250, 0, 1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1033 .vrefresh = 24, }, 1034 /* 4 - 4096x2160@24Hz (SMPTE) */ 1035 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1036 4096, 5116, 5204, 5500, 0, 1037 2160, 2168, 2178, 2250, 0, 1038 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1039 .vrefresh = 24, }, 1040 }; 1041 1042 /*** DDC fetch and block validation ***/ 1043 1044 static const u8 edid_header[] = { 1045 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1046 }; 1047 1048 /** 1049 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1050 * @raw_edid: pointer to raw base EDID block 1051 * 1052 * Sanity check the header of the base EDID block. 1053 * 1054 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1055 */ 1056 int drm_edid_header_is_valid(const u8 *raw_edid) 1057 { 1058 int i, score = 0; 1059 1060 for (i = 0; i < sizeof(edid_header); i++) 1061 if (raw_edid[i] == edid_header[i]) 1062 score++; 1063 1064 return score; 1065 } 1066 EXPORT_SYMBOL(drm_edid_header_is_valid); 1067 1068 static int edid_fixup __read_mostly = 6; 1069 module_param_named(edid_fixup, edid_fixup, int, 0400); 1070 MODULE_PARM_DESC(edid_fixup, 1071 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1072 1073 static void drm_get_displayid(struct drm_connector *connector, 1074 struct edid *edid); 1075 1076 static int drm_edid_block_checksum(const u8 *raw_edid) 1077 { 1078 int i; 1079 u8 csum = 0; 1080 for (i = 0; i < EDID_LENGTH; i++) 1081 csum += raw_edid[i]; 1082 1083 return csum; 1084 } 1085 1086 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1087 { 1088 if (memchr_inv(in_edid, 0, length)) 1089 return false; 1090 1091 return true; 1092 } 1093 1094 /** 1095 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1096 * @raw_edid: pointer to raw EDID block 1097 * @block: type of block to validate (0 for base, extension otherwise) 1098 * @print_bad_edid: if true, dump bad EDID blocks to the console 1099 * @edid_corrupt: if true, the header or checksum is invalid 1100 * 1101 * Validate a base or extension EDID block and optionally dump bad blocks to 1102 * the console. 1103 * 1104 * Return: True if the block is valid, false otherwise. 1105 */ 1106 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1107 bool *edid_corrupt) 1108 { 1109 u8 csum; 1110 struct edid *edid = (struct edid *)raw_edid; 1111 1112 if (WARN_ON(!raw_edid)) 1113 return false; 1114 1115 if (edid_fixup > 8 || edid_fixup < 0) 1116 edid_fixup = 6; 1117 1118 if (block == 0) { 1119 int score = drm_edid_header_is_valid(raw_edid); 1120 if (score == 8) { 1121 if (edid_corrupt) 1122 *edid_corrupt = false; 1123 } else if (score >= edid_fixup) { 1124 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1125 * The corrupt flag needs to be set here otherwise, the 1126 * fix-up code here will correct the problem, the 1127 * checksum is correct and the test fails 1128 */ 1129 if (edid_corrupt) 1130 *edid_corrupt = true; 1131 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1132 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1133 } else { 1134 if (edid_corrupt) 1135 *edid_corrupt = true; 1136 goto bad; 1137 } 1138 } 1139 1140 csum = drm_edid_block_checksum(raw_edid); 1141 if (csum) { 1142 if (print_bad_edid) { 1143 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1144 } 1145 1146 if (edid_corrupt) 1147 *edid_corrupt = true; 1148 1149 /* allow CEA to slide through, switches mangle this */ 1150 if (raw_edid[0] != 0x02) 1151 goto bad; 1152 } 1153 1154 /* per-block-type checks */ 1155 switch (raw_edid[0]) { 1156 case 0: /* base */ 1157 if (edid->version != 1) { 1158 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1159 goto bad; 1160 } 1161 1162 if (edid->revision > 4) 1163 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1164 break; 1165 1166 default: 1167 break; 1168 } 1169 1170 return true; 1171 1172 bad: 1173 if (print_bad_edid) { 1174 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1175 printk(KERN_ERR "EDID block is all zeroes\n"); 1176 } else { 1177 printk(KERN_ERR "Raw EDID:\n"); 1178 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1179 raw_edid, EDID_LENGTH, false); 1180 } 1181 } 1182 return false; 1183 } 1184 EXPORT_SYMBOL(drm_edid_block_valid); 1185 1186 /** 1187 * drm_edid_is_valid - sanity check EDID data 1188 * @edid: EDID data 1189 * 1190 * Sanity-check an entire EDID record (including extensions) 1191 * 1192 * Return: True if the EDID data is valid, false otherwise. 1193 */ 1194 bool drm_edid_is_valid(struct edid *edid) 1195 { 1196 int i; 1197 u8 *raw = (u8 *)edid; 1198 1199 if (!edid) 1200 return false; 1201 1202 for (i = 0; i <= edid->extensions; i++) 1203 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1204 return false; 1205 1206 return true; 1207 } 1208 EXPORT_SYMBOL(drm_edid_is_valid); 1209 1210 #define DDC_SEGMENT_ADDR 0x30 1211 /** 1212 * drm_do_probe_ddc_edid() - get EDID information via I2C 1213 * @data: I2C device adapter 1214 * @buf: EDID data buffer to be filled 1215 * @block: 128 byte EDID block to start fetching from 1216 * @len: EDID data buffer length to fetch 1217 * 1218 * Try to fetch EDID information by calling I2C driver functions. 1219 * 1220 * Return: 0 on success or -1 on failure. 1221 */ 1222 static int 1223 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1224 { 1225 struct i2c_adapter *adapter = data; 1226 unsigned char start = block * EDID_LENGTH; 1227 unsigned char segment = block >> 1; 1228 unsigned char xfers = segment ? 3 : 2; 1229 int ret, retries = 5; 1230 1231 /* 1232 * The core I2C driver will automatically retry the transfer if the 1233 * adapter reports EAGAIN. However, we find that bit-banging transfers 1234 * are susceptible to errors under a heavily loaded machine and 1235 * generate spurious NAKs and timeouts. Retrying the transfer 1236 * of the individual block a few times seems to overcome this. 1237 */ 1238 do { 1239 struct i2c_msg msgs[] = { 1240 { 1241 .addr = DDC_SEGMENT_ADDR, 1242 .flags = 0, 1243 .len = 1, 1244 .buf = &segment, 1245 }, { 1246 .addr = DDC_ADDR, 1247 .flags = 0, 1248 .len = 1, 1249 .buf = &start, 1250 }, { 1251 .addr = DDC_ADDR, 1252 .flags = I2C_M_RD, 1253 .len = len, 1254 .buf = buf, 1255 } 1256 }; 1257 1258 /* 1259 * Avoid sending the segment addr to not upset non-compliant 1260 * DDC monitors. 1261 */ 1262 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1263 1264 if (ret == -ENXIO) { 1265 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1266 adapter->name); 1267 break; 1268 } 1269 } while (ret != xfers && --retries); 1270 1271 return ret == xfers ? 0 : -1; 1272 } 1273 1274 /** 1275 * drm_do_get_edid - get EDID data using a custom EDID block read function 1276 * @connector: connector we're probing 1277 * @get_edid_block: EDID block read function 1278 * @data: private data passed to the block read function 1279 * 1280 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1281 * exposes a different interface to read EDID blocks this function can be used 1282 * to get EDID data using a custom block read function. 1283 * 1284 * As in the general case the DDC bus is accessible by the kernel at the I2C 1285 * level, drivers must make all reasonable efforts to expose it as an I2C 1286 * adapter and use drm_get_edid() instead of abusing this function. 1287 * 1288 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1289 */ 1290 struct edid *drm_do_get_edid(struct drm_connector *connector, 1291 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1292 size_t len), 1293 void *data) 1294 { 1295 int i, j = 0, valid_extensions = 0; 1296 u8 *block, *new; 1297 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1298 1299 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1300 return NULL; 1301 1302 /* base block fetch */ 1303 for (i = 0; i < 4; i++) { 1304 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1305 goto out; 1306 if (drm_edid_block_valid(block, 0, print_bad_edid, 1307 &connector->edid_corrupt)) 1308 break; 1309 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1310 connector->null_edid_counter++; 1311 goto carp; 1312 } 1313 } 1314 if (i == 4) 1315 goto carp; 1316 1317 /* if there's no extensions, we're done */ 1318 if (block[0x7e] == 0) 1319 return (struct edid *)block; 1320 1321 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1322 if (!new) 1323 goto out; 1324 block = new; 1325 1326 for (j = 1; j <= block[0x7e]; j++) { 1327 for (i = 0; i < 4; i++) { 1328 if (get_edid_block(data, 1329 block + (valid_extensions + 1) * EDID_LENGTH, 1330 j, EDID_LENGTH)) 1331 goto out; 1332 if (drm_edid_block_valid(block + (valid_extensions + 1) 1333 * EDID_LENGTH, j, 1334 print_bad_edid, 1335 NULL)) { 1336 valid_extensions++; 1337 break; 1338 } 1339 } 1340 1341 if (i == 4 && print_bad_edid) { 1342 dev_warn(connector->dev->dev, 1343 "%s: Ignoring invalid EDID block %d.\n", 1344 connector->name, j); 1345 1346 connector->bad_edid_counter++; 1347 } 1348 } 1349 1350 if (valid_extensions != block[0x7e]) { 1351 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1352 block[0x7e] = valid_extensions; 1353 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1354 if (!new) 1355 goto out; 1356 block = new; 1357 } 1358 1359 return (struct edid *)block; 1360 1361 carp: 1362 if (print_bad_edid) { 1363 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1364 connector->name, j); 1365 } 1366 connector->bad_edid_counter++; 1367 1368 out: 1369 kfree(block); 1370 return NULL; 1371 } 1372 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1373 1374 /** 1375 * drm_probe_ddc() - probe DDC presence 1376 * @adapter: I2C adapter to probe 1377 * 1378 * Return: True on success, false on failure. 1379 */ 1380 bool 1381 drm_probe_ddc(struct i2c_adapter *adapter) 1382 { 1383 unsigned char out; 1384 1385 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1386 } 1387 EXPORT_SYMBOL(drm_probe_ddc); 1388 1389 /** 1390 * drm_get_edid - get EDID data, if available 1391 * @connector: connector we're probing 1392 * @adapter: I2C adapter to use for DDC 1393 * 1394 * Poke the given I2C channel to grab EDID data if possible. If found, 1395 * attach it to the connector. 1396 * 1397 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1398 */ 1399 struct edid *drm_get_edid(struct drm_connector *connector, 1400 struct i2c_adapter *adapter) 1401 { 1402 struct edid *edid; 1403 1404 if (!drm_probe_ddc(adapter)) 1405 return NULL; 1406 1407 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1408 if (edid) 1409 drm_get_displayid(connector, edid); 1410 return edid; 1411 } 1412 EXPORT_SYMBOL(drm_get_edid); 1413 1414 /** 1415 * drm_edid_duplicate - duplicate an EDID and the extensions 1416 * @edid: EDID to duplicate 1417 * 1418 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1419 */ 1420 struct edid *drm_edid_duplicate(const struct edid *edid) 1421 { 1422 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1423 } 1424 EXPORT_SYMBOL(drm_edid_duplicate); 1425 1426 /*** EDID parsing ***/ 1427 1428 /** 1429 * edid_vendor - match a string against EDID's obfuscated vendor field 1430 * @edid: EDID to match 1431 * @vendor: vendor string 1432 * 1433 * Returns true if @vendor is in @edid, false otherwise 1434 */ 1435 static bool edid_vendor(struct edid *edid, char *vendor) 1436 { 1437 char edid_vendor[3]; 1438 1439 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1440 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1441 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1442 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1443 1444 return !strncmp(edid_vendor, vendor, 3); 1445 } 1446 1447 /** 1448 * edid_get_quirks - return quirk flags for a given EDID 1449 * @edid: EDID to process 1450 * 1451 * This tells subsequent routines what fixes they need to apply. 1452 */ 1453 static u32 edid_get_quirks(struct edid *edid) 1454 { 1455 struct edid_quirk *quirk; 1456 int i; 1457 1458 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1459 quirk = &edid_quirk_list[i]; 1460 1461 if (edid_vendor(edid, quirk->vendor) && 1462 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1463 return quirk->quirks; 1464 } 1465 1466 return 0; 1467 } 1468 1469 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1470 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1471 1472 /** 1473 * edid_fixup_preferred - set preferred modes based on quirk list 1474 * @connector: has mode list to fix up 1475 * @quirks: quirks list 1476 * 1477 * Walk the mode list for @connector, clearing the preferred status 1478 * on existing modes and setting it anew for the right mode ala @quirks. 1479 */ 1480 static void edid_fixup_preferred(struct drm_connector *connector, 1481 u32 quirks) 1482 { 1483 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1484 int target_refresh = 0; 1485 int cur_vrefresh, preferred_vrefresh; 1486 1487 if (list_empty(&connector->probed_modes)) 1488 return; 1489 1490 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1491 target_refresh = 60; 1492 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1493 target_refresh = 75; 1494 1495 preferred_mode = list_first_entry(&connector->probed_modes, 1496 struct drm_display_mode, head); 1497 1498 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1499 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1500 1501 if (cur_mode == preferred_mode) 1502 continue; 1503 1504 /* Largest mode is preferred */ 1505 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1506 preferred_mode = cur_mode; 1507 1508 cur_vrefresh = cur_mode->vrefresh ? 1509 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1510 preferred_vrefresh = preferred_mode->vrefresh ? 1511 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1512 /* At a given size, try to get closest to target refresh */ 1513 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1514 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1515 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1516 preferred_mode = cur_mode; 1517 } 1518 } 1519 1520 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1521 } 1522 1523 static bool 1524 mode_is_rb(const struct drm_display_mode *mode) 1525 { 1526 return (mode->htotal - mode->hdisplay == 160) && 1527 (mode->hsync_end - mode->hdisplay == 80) && 1528 (mode->hsync_end - mode->hsync_start == 32) && 1529 (mode->vsync_start - mode->vdisplay == 3); 1530 } 1531 1532 /* 1533 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1534 * @dev: Device to duplicate against 1535 * @hsize: Mode width 1536 * @vsize: Mode height 1537 * @fresh: Mode refresh rate 1538 * @rb: Mode reduced-blanking-ness 1539 * 1540 * Walk the DMT mode list looking for a match for the given parameters. 1541 * 1542 * Return: A newly allocated copy of the mode, or NULL if not found. 1543 */ 1544 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1545 int hsize, int vsize, int fresh, 1546 bool rb) 1547 { 1548 int i; 1549 1550 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1551 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1552 if (hsize != ptr->hdisplay) 1553 continue; 1554 if (vsize != ptr->vdisplay) 1555 continue; 1556 if (fresh != drm_mode_vrefresh(ptr)) 1557 continue; 1558 if (rb != mode_is_rb(ptr)) 1559 continue; 1560 1561 return drm_mode_duplicate(dev, ptr); 1562 } 1563 1564 return NULL; 1565 } 1566 EXPORT_SYMBOL(drm_mode_find_dmt); 1567 1568 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1569 1570 static void 1571 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1572 { 1573 int i, n = 0; 1574 u8 d = ext[0x02]; 1575 u8 *det_base = ext + d; 1576 1577 n = (127 - d) / 18; 1578 for (i = 0; i < n; i++) 1579 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1580 } 1581 1582 static void 1583 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1584 { 1585 unsigned int i, n = min((int)ext[0x02], 6); 1586 u8 *det_base = ext + 5; 1587 1588 if (ext[0x01] != 1) 1589 return; /* unknown version */ 1590 1591 for (i = 0; i < n; i++) 1592 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1593 } 1594 1595 static void 1596 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1597 { 1598 int i; 1599 struct edid *edid = (struct edid *)raw_edid; 1600 1601 if (edid == NULL) 1602 return; 1603 1604 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1605 cb(&(edid->detailed_timings[i]), closure); 1606 1607 for (i = 1; i <= raw_edid[0x7e]; i++) { 1608 u8 *ext = raw_edid + (i * EDID_LENGTH); 1609 switch (*ext) { 1610 case CEA_EXT: 1611 cea_for_each_detailed_block(ext, cb, closure); 1612 break; 1613 case VTB_EXT: 1614 vtb_for_each_detailed_block(ext, cb, closure); 1615 break; 1616 default: 1617 break; 1618 } 1619 } 1620 } 1621 1622 static void 1623 is_rb(struct detailed_timing *t, void *data) 1624 { 1625 u8 *r = (u8 *)t; 1626 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1627 if (r[15] & 0x10) 1628 *(bool *)data = true; 1629 } 1630 1631 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1632 static bool 1633 drm_monitor_supports_rb(struct edid *edid) 1634 { 1635 if (edid->revision >= 4) { 1636 bool ret = false; 1637 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1638 return ret; 1639 } 1640 1641 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1642 } 1643 1644 static void 1645 find_gtf2(struct detailed_timing *t, void *data) 1646 { 1647 u8 *r = (u8 *)t; 1648 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1649 *(u8 **)data = r; 1650 } 1651 1652 /* Secondary GTF curve kicks in above some break frequency */ 1653 static int 1654 drm_gtf2_hbreak(struct edid *edid) 1655 { 1656 u8 *r = NULL; 1657 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1658 return r ? (r[12] * 2) : 0; 1659 } 1660 1661 static int 1662 drm_gtf2_2c(struct edid *edid) 1663 { 1664 u8 *r = NULL; 1665 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1666 return r ? r[13] : 0; 1667 } 1668 1669 static int 1670 drm_gtf2_m(struct edid *edid) 1671 { 1672 u8 *r = NULL; 1673 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1674 return r ? (r[15] << 8) + r[14] : 0; 1675 } 1676 1677 static int 1678 drm_gtf2_k(struct edid *edid) 1679 { 1680 u8 *r = NULL; 1681 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1682 return r ? r[16] : 0; 1683 } 1684 1685 static int 1686 drm_gtf2_2j(struct edid *edid) 1687 { 1688 u8 *r = NULL; 1689 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1690 return r ? r[17] : 0; 1691 } 1692 1693 /** 1694 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1695 * @edid: EDID block to scan 1696 */ 1697 static int standard_timing_level(struct edid *edid) 1698 { 1699 if (edid->revision >= 2) { 1700 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1701 return LEVEL_CVT; 1702 if (drm_gtf2_hbreak(edid)) 1703 return LEVEL_GTF2; 1704 return LEVEL_GTF; 1705 } 1706 return LEVEL_DMT; 1707 } 1708 1709 /* 1710 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1711 * monitors fill with ascii space (0x20) instead. 1712 */ 1713 static int 1714 bad_std_timing(u8 a, u8 b) 1715 { 1716 return (a == 0x00 && b == 0x00) || 1717 (a == 0x01 && b == 0x01) || 1718 (a == 0x20 && b == 0x20); 1719 } 1720 1721 /** 1722 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1723 * @connector: connector of for the EDID block 1724 * @edid: EDID block to scan 1725 * @t: standard timing params 1726 * 1727 * Take the standard timing params (in this case width, aspect, and refresh) 1728 * and convert them into a real mode using CVT/GTF/DMT. 1729 */ 1730 static struct drm_display_mode * 1731 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1732 struct std_timing *t) 1733 { 1734 struct drm_device *dev = connector->dev; 1735 struct drm_display_mode *m, *mode = NULL; 1736 int hsize, vsize; 1737 int vrefresh_rate; 1738 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1739 >> EDID_TIMING_ASPECT_SHIFT; 1740 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1741 >> EDID_TIMING_VFREQ_SHIFT; 1742 int timing_level = standard_timing_level(edid); 1743 1744 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1745 return NULL; 1746 1747 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1748 hsize = t->hsize * 8 + 248; 1749 /* vrefresh_rate = vfreq + 60 */ 1750 vrefresh_rate = vfreq + 60; 1751 /* the vdisplay is calculated based on the aspect ratio */ 1752 if (aspect_ratio == 0) { 1753 if (edid->revision < 3) 1754 vsize = hsize; 1755 else 1756 vsize = (hsize * 10) / 16; 1757 } else if (aspect_ratio == 1) 1758 vsize = (hsize * 3) / 4; 1759 else if (aspect_ratio == 2) 1760 vsize = (hsize * 4) / 5; 1761 else 1762 vsize = (hsize * 9) / 16; 1763 1764 /* HDTV hack, part 1 */ 1765 if (vrefresh_rate == 60 && 1766 ((hsize == 1360 && vsize == 765) || 1767 (hsize == 1368 && vsize == 769))) { 1768 hsize = 1366; 1769 vsize = 768; 1770 } 1771 1772 /* 1773 * If this connector already has a mode for this size and refresh 1774 * rate (because it came from detailed or CVT info), use that 1775 * instead. This way we don't have to guess at interlace or 1776 * reduced blanking. 1777 */ 1778 list_for_each_entry(m, &connector->probed_modes, head) 1779 if (m->hdisplay == hsize && m->vdisplay == vsize && 1780 drm_mode_vrefresh(m) == vrefresh_rate) 1781 return NULL; 1782 1783 /* HDTV hack, part 2 */ 1784 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1785 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1786 false); 1787 mode->hdisplay = 1366; 1788 mode->hsync_start = mode->hsync_start - 1; 1789 mode->hsync_end = mode->hsync_end - 1; 1790 return mode; 1791 } 1792 1793 /* check whether it can be found in default mode table */ 1794 if (drm_monitor_supports_rb(edid)) { 1795 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1796 true); 1797 if (mode) 1798 return mode; 1799 } 1800 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1801 if (mode) 1802 return mode; 1803 1804 /* okay, generate it */ 1805 switch (timing_level) { 1806 case LEVEL_DMT: 1807 break; 1808 case LEVEL_GTF: 1809 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1810 break; 1811 case LEVEL_GTF2: 1812 /* 1813 * This is potentially wrong if there's ever a monitor with 1814 * more than one ranges section, each claiming a different 1815 * secondary GTF curve. Please don't do that. 1816 */ 1817 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1818 if (!mode) 1819 return NULL; 1820 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1821 drm_mode_destroy(dev, mode); 1822 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1823 vrefresh_rate, 0, 0, 1824 drm_gtf2_m(edid), 1825 drm_gtf2_2c(edid), 1826 drm_gtf2_k(edid), 1827 drm_gtf2_2j(edid)); 1828 } 1829 break; 1830 case LEVEL_CVT: 1831 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1832 false); 1833 break; 1834 } 1835 return mode; 1836 } 1837 1838 /* 1839 * EDID is delightfully ambiguous about how interlaced modes are to be 1840 * encoded. Our internal representation is of frame height, but some 1841 * HDTV detailed timings are encoded as field height. 1842 * 1843 * The format list here is from CEA, in frame size. Technically we 1844 * should be checking refresh rate too. Whatever. 1845 */ 1846 static void 1847 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1848 struct detailed_pixel_timing *pt) 1849 { 1850 int i; 1851 static const struct { 1852 int w, h; 1853 } cea_interlaced[] = { 1854 { 1920, 1080 }, 1855 { 720, 480 }, 1856 { 1440, 480 }, 1857 { 2880, 480 }, 1858 { 720, 576 }, 1859 { 1440, 576 }, 1860 { 2880, 576 }, 1861 }; 1862 1863 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1864 return; 1865 1866 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1867 if ((mode->hdisplay == cea_interlaced[i].w) && 1868 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1869 mode->vdisplay *= 2; 1870 mode->vsync_start *= 2; 1871 mode->vsync_end *= 2; 1872 mode->vtotal *= 2; 1873 mode->vtotal |= 1; 1874 } 1875 } 1876 1877 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1878 } 1879 1880 /** 1881 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1882 * @dev: DRM device (needed to create new mode) 1883 * @edid: EDID block 1884 * @timing: EDID detailed timing info 1885 * @quirks: quirks to apply 1886 * 1887 * An EDID detailed timing block contains enough info for us to create and 1888 * return a new struct drm_display_mode. 1889 */ 1890 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1891 struct edid *edid, 1892 struct detailed_timing *timing, 1893 u32 quirks) 1894 { 1895 struct drm_display_mode *mode; 1896 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1897 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1898 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1899 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1900 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1901 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1902 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1903 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1904 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1905 1906 /* ignore tiny modes */ 1907 if (hactive < 64 || vactive < 64) 1908 return NULL; 1909 1910 if (pt->misc & DRM_EDID_PT_STEREO) { 1911 DRM_DEBUG_KMS("stereo mode not supported\n"); 1912 return NULL; 1913 } 1914 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1915 DRM_DEBUG_KMS("composite sync not supported\n"); 1916 } 1917 1918 /* it is incorrect if hsync/vsync width is zero */ 1919 if (!hsync_pulse_width || !vsync_pulse_width) { 1920 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1921 "Wrong Hsync/Vsync pulse width\n"); 1922 return NULL; 1923 } 1924 1925 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1926 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1927 if (!mode) 1928 return NULL; 1929 1930 goto set_size; 1931 } 1932 1933 mode = drm_mode_create(dev); 1934 if (!mode) 1935 return NULL; 1936 1937 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1938 timing->pixel_clock = cpu_to_le16(1088); 1939 1940 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1941 1942 mode->hdisplay = hactive; 1943 mode->hsync_start = mode->hdisplay + hsync_offset; 1944 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1945 mode->htotal = mode->hdisplay + hblank; 1946 1947 mode->vdisplay = vactive; 1948 mode->vsync_start = mode->vdisplay + vsync_offset; 1949 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1950 mode->vtotal = mode->vdisplay + vblank; 1951 1952 /* Some EDIDs have bogus h/vtotal values */ 1953 if (mode->hsync_end > mode->htotal) 1954 mode->htotal = mode->hsync_end + 1; 1955 if (mode->vsync_end > mode->vtotal) 1956 mode->vtotal = mode->vsync_end + 1; 1957 1958 drm_mode_do_interlace_quirk(mode, pt); 1959 1960 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1961 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1962 } 1963 1964 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1965 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1966 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1967 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1968 1969 set_size: 1970 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1971 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1972 1973 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1974 mode->width_mm *= 10; 1975 mode->height_mm *= 10; 1976 } 1977 1978 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1979 mode->width_mm = edid->width_cm * 10; 1980 mode->height_mm = edid->height_cm * 10; 1981 } 1982 1983 mode->type = DRM_MODE_TYPE_DRIVER; 1984 mode->vrefresh = drm_mode_vrefresh(mode); 1985 drm_mode_set_name(mode); 1986 1987 return mode; 1988 } 1989 1990 static bool 1991 mode_in_hsync_range(const struct drm_display_mode *mode, 1992 struct edid *edid, u8 *t) 1993 { 1994 int hsync, hmin, hmax; 1995 1996 hmin = t[7]; 1997 if (edid->revision >= 4) 1998 hmin += ((t[4] & 0x04) ? 255 : 0); 1999 hmax = t[8]; 2000 if (edid->revision >= 4) 2001 hmax += ((t[4] & 0x08) ? 255 : 0); 2002 hsync = drm_mode_hsync(mode); 2003 2004 return (hsync <= hmax && hsync >= hmin); 2005 } 2006 2007 static bool 2008 mode_in_vsync_range(const struct drm_display_mode *mode, 2009 struct edid *edid, u8 *t) 2010 { 2011 int vsync, vmin, vmax; 2012 2013 vmin = t[5]; 2014 if (edid->revision >= 4) 2015 vmin += ((t[4] & 0x01) ? 255 : 0); 2016 vmax = t[6]; 2017 if (edid->revision >= 4) 2018 vmax += ((t[4] & 0x02) ? 255 : 0); 2019 vsync = drm_mode_vrefresh(mode); 2020 2021 return (vsync <= vmax && vsync >= vmin); 2022 } 2023 2024 static u32 2025 range_pixel_clock(struct edid *edid, u8 *t) 2026 { 2027 /* unspecified */ 2028 if (t[9] == 0 || t[9] == 255) 2029 return 0; 2030 2031 /* 1.4 with CVT support gives us real precision, yay */ 2032 if (edid->revision >= 4 && t[10] == 0x04) 2033 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2034 2035 /* 1.3 is pathetic, so fuzz up a bit */ 2036 return t[9] * 10000 + 5001; 2037 } 2038 2039 static bool 2040 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2041 struct detailed_timing *timing) 2042 { 2043 u32 max_clock; 2044 u8 *t = (u8 *)timing; 2045 2046 if (!mode_in_hsync_range(mode, edid, t)) 2047 return false; 2048 2049 if (!mode_in_vsync_range(mode, edid, t)) 2050 return false; 2051 2052 if ((max_clock = range_pixel_clock(edid, t))) 2053 if (mode->clock > max_clock) 2054 return false; 2055 2056 /* 1.4 max horizontal check */ 2057 if (edid->revision >= 4 && t[10] == 0x04) 2058 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2059 return false; 2060 2061 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2062 return false; 2063 2064 return true; 2065 } 2066 2067 static bool valid_inferred_mode(const struct drm_connector *connector, 2068 const struct drm_display_mode *mode) 2069 { 2070 const struct drm_display_mode *m; 2071 bool ok = false; 2072 2073 list_for_each_entry(m, &connector->probed_modes, head) { 2074 if (mode->hdisplay == m->hdisplay && 2075 mode->vdisplay == m->vdisplay && 2076 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2077 return false; /* duplicated */ 2078 if (mode->hdisplay <= m->hdisplay && 2079 mode->vdisplay <= m->vdisplay) 2080 ok = true; 2081 } 2082 return ok; 2083 } 2084 2085 static int 2086 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2087 struct detailed_timing *timing) 2088 { 2089 int i, modes = 0; 2090 struct drm_display_mode *newmode; 2091 struct drm_device *dev = connector->dev; 2092 2093 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2094 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2095 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2096 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2097 if (newmode) { 2098 drm_mode_probed_add(connector, newmode); 2099 modes++; 2100 } 2101 } 2102 } 2103 2104 return modes; 2105 } 2106 2107 /* fix up 1366x768 mode from 1368x768; 2108 * GFT/CVT can't express 1366 width which isn't dividable by 8 2109 */ 2110 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2111 { 2112 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2113 mode->hdisplay = 1366; 2114 mode->hsync_start--; 2115 mode->hsync_end--; 2116 drm_mode_set_name(mode); 2117 } 2118 } 2119 2120 static int 2121 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2122 struct detailed_timing *timing) 2123 { 2124 int i, modes = 0; 2125 struct drm_display_mode *newmode; 2126 struct drm_device *dev = connector->dev; 2127 2128 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2129 const struct minimode *m = &extra_modes[i]; 2130 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2131 if (!newmode) 2132 return modes; 2133 2134 fixup_mode_1366x768(newmode); 2135 if (!mode_in_range(newmode, edid, timing) || 2136 !valid_inferred_mode(connector, newmode)) { 2137 drm_mode_destroy(dev, newmode); 2138 continue; 2139 } 2140 2141 drm_mode_probed_add(connector, newmode); 2142 modes++; 2143 } 2144 2145 return modes; 2146 } 2147 2148 static int 2149 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2150 struct detailed_timing *timing) 2151 { 2152 int i, modes = 0; 2153 struct drm_display_mode *newmode; 2154 struct drm_device *dev = connector->dev; 2155 bool rb = drm_monitor_supports_rb(edid); 2156 2157 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2158 const struct minimode *m = &extra_modes[i]; 2159 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2160 if (!newmode) 2161 return modes; 2162 2163 fixup_mode_1366x768(newmode); 2164 if (!mode_in_range(newmode, edid, timing) || 2165 !valid_inferred_mode(connector, newmode)) { 2166 drm_mode_destroy(dev, newmode); 2167 continue; 2168 } 2169 2170 drm_mode_probed_add(connector, newmode); 2171 modes++; 2172 } 2173 2174 return modes; 2175 } 2176 2177 static void 2178 do_inferred_modes(struct detailed_timing *timing, void *c) 2179 { 2180 struct detailed_mode_closure *closure = c; 2181 struct detailed_non_pixel *data = &timing->data.other_data; 2182 struct detailed_data_monitor_range *range = &data->data.range; 2183 2184 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2185 return; 2186 2187 closure->modes += drm_dmt_modes_for_range(closure->connector, 2188 closure->edid, 2189 timing); 2190 2191 if (!version_greater(closure->edid, 1, 1)) 2192 return; /* GTF not defined yet */ 2193 2194 switch (range->flags) { 2195 case 0x02: /* secondary gtf, XXX could do more */ 2196 case 0x00: /* default gtf */ 2197 closure->modes += drm_gtf_modes_for_range(closure->connector, 2198 closure->edid, 2199 timing); 2200 break; 2201 case 0x04: /* cvt, only in 1.4+ */ 2202 if (!version_greater(closure->edid, 1, 3)) 2203 break; 2204 2205 closure->modes += drm_cvt_modes_for_range(closure->connector, 2206 closure->edid, 2207 timing); 2208 break; 2209 case 0x01: /* just the ranges, no formula */ 2210 default: 2211 break; 2212 } 2213 } 2214 2215 static int 2216 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2217 { 2218 struct detailed_mode_closure closure = { 2219 .connector = connector, 2220 .edid = edid, 2221 }; 2222 2223 if (version_greater(edid, 1, 0)) 2224 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2225 &closure); 2226 2227 return closure.modes; 2228 } 2229 2230 static int 2231 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2232 { 2233 int i, j, m, modes = 0; 2234 struct drm_display_mode *mode; 2235 u8 *est = ((u8 *)timing) + 5; 2236 2237 for (i = 0; i < 6; i++) { 2238 for (j = 7; j >= 0; j--) { 2239 m = (i * 8) + (7 - j); 2240 if (m >= ARRAY_SIZE(est3_modes)) 2241 break; 2242 if (est[i] & (1 << j)) { 2243 mode = drm_mode_find_dmt(connector->dev, 2244 est3_modes[m].w, 2245 est3_modes[m].h, 2246 est3_modes[m].r, 2247 est3_modes[m].rb); 2248 if (mode) { 2249 drm_mode_probed_add(connector, mode); 2250 modes++; 2251 } 2252 } 2253 } 2254 } 2255 2256 return modes; 2257 } 2258 2259 static void 2260 do_established_modes(struct detailed_timing *timing, void *c) 2261 { 2262 struct detailed_mode_closure *closure = c; 2263 struct detailed_non_pixel *data = &timing->data.other_data; 2264 2265 if (data->type == EDID_DETAIL_EST_TIMINGS) 2266 closure->modes += drm_est3_modes(closure->connector, timing); 2267 } 2268 2269 /** 2270 * add_established_modes - get est. modes from EDID and add them 2271 * @connector: connector to add mode(s) to 2272 * @edid: EDID block to scan 2273 * 2274 * Each EDID block contains a bitmap of the supported "established modes" list 2275 * (defined above). Tease them out and add them to the global modes list. 2276 */ 2277 static int 2278 add_established_modes(struct drm_connector *connector, struct edid *edid) 2279 { 2280 struct drm_device *dev = connector->dev; 2281 unsigned long est_bits = edid->established_timings.t1 | 2282 (edid->established_timings.t2 << 8) | 2283 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2284 int i, modes = 0; 2285 struct detailed_mode_closure closure = { 2286 .connector = connector, 2287 .edid = edid, 2288 }; 2289 2290 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2291 if (est_bits & (1<<i)) { 2292 struct drm_display_mode *newmode; 2293 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2294 if (newmode) { 2295 drm_mode_probed_add(connector, newmode); 2296 modes++; 2297 } 2298 } 2299 } 2300 2301 if (version_greater(edid, 1, 0)) 2302 drm_for_each_detailed_block((u8 *)edid, 2303 do_established_modes, &closure); 2304 2305 return modes + closure.modes; 2306 } 2307 2308 static void 2309 do_standard_modes(struct detailed_timing *timing, void *c) 2310 { 2311 struct detailed_mode_closure *closure = c; 2312 struct detailed_non_pixel *data = &timing->data.other_data; 2313 struct drm_connector *connector = closure->connector; 2314 struct edid *edid = closure->edid; 2315 2316 if (data->type == EDID_DETAIL_STD_MODES) { 2317 int i; 2318 for (i = 0; i < 6; i++) { 2319 struct std_timing *std; 2320 struct drm_display_mode *newmode; 2321 2322 std = &data->data.timings[i]; 2323 newmode = drm_mode_std(connector, edid, std); 2324 if (newmode) { 2325 drm_mode_probed_add(connector, newmode); 2326 closure->modes++; 2327 } 2328 } 2329 } 2330 } 2331 2332 /** 2333 * add_standard_modes - get std. modes from EDID and add them 2334 * @connector: connector to add mode(s) to 2335 * @edid: EDID block to scan 2336 * 2337 * Standard modes can be calculated using the appropriate standard (DMT, 2338 * GTF or CVT. Grab them from @edid and add them to the list. 2339 */ 2340 static int 2341 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2342 { 2343 int i, modes = 0; 2344 struct detailed_mode_closure closure = { 2345 .connector = connector, 2346 .edid = edid, 2347 }; 2348 2349 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2350 struct drm_display_mode *newmode; 2351 2352 newmode = drm_mode_std(connector, edid, 2353 &edid->standard_timings[i]); 2354 if (newmode) { 2355 drm_mode_probed_add(connector, newmode); 2356 modes++; 2357 } 2358 } 2359 2360 if (version_greater(edid, 1, 0)) 2361 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2362 &closure); 2363 2364 /* XXX should also look for standard codes in VTB blocks */ 2365 2366 return modes + closure.modes; 2367 } 2368 2369 static int drm_cvt_modes(struct drm_connector *connector, 2370 struct detailed_timing *timing) 2371 { 2372 int i, j, modes = 0; 2373 struct drm_display_mode *newmode; 2374 struct drm_device *dev = connector->dev; 2375 struct cvt_timing *cvt; 2376 const int rates[] = { 60, 85, 75, 60, 50 }; 2377 const u8 empty[3] = { 0, 0, 0 }; 2378 2379 for (i = 0; i < 4; i++) { 2380 int uninitialized_var(width), height; 2381 cvt = &(timing->data.other_data.data.cvt[i]); 2382 2383 if (!memcmp(cvt->code, empty, 3)) 2384 continue; 2385 2386 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2387 switch (cvt->code[1] & 0x0c) { 2388 case 0x00: 2389 width = height * 4 / 3; 2390 break; 2391 case 0x04: 2392 width = height * 16 / 9; 2393 break; 2394 case 0x08: 2395 width = height * 16 / 10; 2396 break; 2397 case 0x0c: 2398 width = height * 15 / 9; 2399 break; 2400 } 2401 2402 for (j = 1; j < 5; j++) { 2403 if (cvt->code[2] & (1 << j)) { 2404 newmode = drm_cvt_mode(dev, width, height, 2405 rates[j], j == 0, 2406 false, false); 2407 if (newmode) { 2408 drm_mode_probed_add(connector, newmode); 2409 modes++; 2410 } 2411 } 2412 } 2413 } 2414 2415 return modes; 2416 } 2417 2418 static void 2419 do_cvt_mode(struct detailed_timing *timing, void *c) 2420 { 2421 struct detailed_mode_closure *closure = c; 2422 struct detailed_non_pixel *data = &timing->data.other_data; 2423 2424 if (data->type == EDID_DETAIL_CVT_3BYTE) 2425 closure->modes += drm_cvt_modes(closure->connector, timing); 2426 } 2427 2428 static int 2429 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2430 { 2431 struct detailed_mode_closure closure = { 2432 .connector = connector, 2433 .edid = edid, 2434 }; 2435 2436 if (version_greater(edid, 1, 2)) 2437 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2438 2439 /* XXX should also look for CVT codes in VTB blocks */ 2440 2441 return closure.modes; 2442 } 2443 2444 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2445 2446 static void 2447 do_detailed_mode(struct detailed_timing *timing, void *c) 2448 { 2449 struct detailed_mode_closure *closure = c; 2450 struct drm_display_mode *newmode; 2451 2452 if (timing->pixel_clock) { 2453 newmode = drm_mode_detailed(closure->connector->dev, 2454 closure->edid, timing, 2455 closure->quirks); 2456 if (!newmode) 2457 return; 2458 2459 if (closure->preferred) 2460 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2461 2462 /* 2463 * Detailed modes are limited to 10kHz pixel clock resolution, 2464 * so fix up anything that looks like CEA/HDMI mode, but the clock 2465 * is just slightly off. 2466 */ 2467 fixup_detailed_cea_mode_clock(newmode); 2468 2469 drm_mode_probed_add(closure->connector, newmode); 2470 closure->modes++; 2471 closure->preferred = 0; 2472 } 2473 } 2474 2475 /* 2476 * add_detailed_modes - Add modes from detailed timings 2477 * @connector: attached connector 2478 * @edid: EDID block to scan 2479 * @quirks: quirks to apply 2480 */ 2481 static int 2482 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2483 u32 quirks) 2484 { 2485 struct detailed_mode_closure closure = { 2486 .connector = connector, 2487 .edid = edid, 2488 .preferred = 1, 2489 .quirks = quirks, 2490 }; 2491 2492 if (closure.preferred && !version_greater(edid, 1, 3)) 2493 closure.preferred = 2494 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2495 2496 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2497 2498 return closure.modes; 2499 } 2500 2501 #define AUDIO_BLOCK 0x01 2502 #define VIDEO_BLOCK 0x02 2503 #define VENDOR_BLOCK 0x03 2504 #define SPEAKER_BLOCK 0x04 2505 #define VIDEO_CAPABILITY_BLOCK 0x07 2506 #define EDID_BASIC_AUDIO (1 << 6) 2507 #define EDID_CEA_YCRCB444 (1 << 5) 2508 #define EDID_CEA_YCRCB422 (1 << 4) 2509 #define EDID_CEA_VCDB_QS (1 << 6) 2510 2511 /* 2512 * Search EDID for CEA extension block. 2513 */ 2514 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2515 { 2516 u8 *edid_ext = NULL; 2517 int i; 2518 2519 /* No EDID or EDID extensions */ 2520 if (edid == NULL || edid->extensions == 0) 2521 return NULL; 2522 2523 /* Find CEA extension */ 2524 for (i = 0; i < edid->extensions; i++) { 2525 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2526 if (edid_ext[0] == ext_id) 2527 break; 2528 } 2529 2530 if (i == edid->extensions) 2531 return NULL; 2532 2533 return edid_ext; 2534 } 2535 2536 static u8 *drm_find_cea_extension(struct edid *edid) 2537 { 2538 return drm_find_edid_extension(edid, CEA_EXT); 2539 } 2540 2541 static u8 *drm_find_displayid_extension(struct edid *edid) 2542 { 2543 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2544 } 2545 2546 /* 2547 * Calculate the alternate clock for the CEA mode 2548 * (60Hz vs. 59.94Hz etc.) 2549 */ 2550 static unsigned int 2551 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2552 { 2553 unsigned int clock = cea_mode->clock; 2554 2555 if (cea_mode->vrefresh % 6 != 0) 2556 return clock; 2557 2558 /* 2559 * edid_cea_modes contains the 59.94Hz 2560 * variant for 240 and 480 line modes, 2561 * and the 60Hz variant otherwise. 2562 */ 2563 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2564 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2565 else 2566 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2567 2568 return clock; 2569 } 2570 2571 /** 2572 * drm_match_cea_mode - look for a CEA mode matching given mode 2573 * @to_match: display mode 2574 * 2575 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2576 * mode. 2577 */ 2578 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2579 { 2580 u8 mode; 2581 2582 if (!to_match->clock) 2583 return 0; 2584 2585 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2586 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2587 unsigned int clock1, clock2; 2588 2589 /* Check both 60Hz and 59.94Hz */ 2590 clock1 = cea_mode->clock; 2591 clock2 = cea_mode_alternate_clock(cea_mode); 2592 2593 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2594 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2595 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2596 return mode + 1; 2597 } 2598 return 0; 2599 } 2600 EXPORT_SYMBOL(drm_match_cea_mode); 2601 2602 /** 2603 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2604 * the input VIC from the CEA mode list 2605 * @video_code: ID given to each of the CEA modes 2606 * 2607 * Returns picture aspect ratio 2608 */ 2609 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2610 { 2611 /* return picture aspect ratio for video_code - 1 to access the 2612 * right array element 2613 */ 2614 return edid_cea_modes[video_code-1].picture_aspect_ratio; 2615 } 2616 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2617 2618 /* 2619 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2620 * specific block). 2621 * 2622 * It's almost like cea_mode_alternate_clock(), we just need to add an 2623 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2624 * one. 2625 */ 2626 static unsigned int 2627 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2628 { 2629 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2630 return hdmi_mode->clock; 2631 2632 return cea_mode_alternate_clock(hdmi_mode); 2633 } 2634 2635 /* 2636 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2637 * @to_match: display mode 2638 * 2639 * An HDMI mode is one defined in the HDMI vendor specific block. 2640 * 2641 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2642 */ 2643 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2644 { 2645 u8 mode; 2646 2647 if (!to_match->clock) 2648 return 0; 2649 2650 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { 2651 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; 2652 unsigned int clock1, clock2; 2653 2654 /* Make sure to also match alternate clocks */ 2655 clock1 = hdmi_mode->clock; 2656 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2657 2658 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2659 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2660 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2661 return mode + 1; 2662 } 2663 return 0; 2664 } 2665 2666 static int 2667 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2668 { 2669 struct drm_device *dev = connector->dev; 2670 struct drm_display_mode *mode, *tmp; 2671 LIST_HEAD(list); 2672 int modes = 0; 2673 2674 /* Don't add CEA modes if the CEA extension block is missing */ 2675 if (!drm_find_cea_extension(edid)) 2676 return 0; 2677 2678 /* 2679 * Go through all probed modes and create a new mode 2680 * with the alternate clock for certain CEA modes. 2681 */ 2682 list_for_each_entry(mode, &connector->probed_modes, head) { 2683 const struct drm_display_mode *cea_mode = NULL; 2684 struct drm_display_mode *newmode; 2685 u8 mode_idx = drm_match_cea_mode(mode) - 1; 2686 unsigned int clock1, clock2; 2687 2688 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 2689 cea_mode = &edid_cea_modes[mode_idx]; 2690 clock2 = cea_mode_alternate_clock(cea_mode); 2691 } else { 2692 mode_idx = drm_match_hdmi_mode(mode) - 1; 2693 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 2694 cea_mode = &edid_4k_modes[mode_idx]; 2695 clock2 = hdmi_mode_alternate_clock(cea_mode); 2696 } 2697 } 2698 2699 if (!cea_mode) 2700 continue; 2701 2702 clock1 = cea_mode->clock; 2703 2704 if (clock1 == clock2) 2705 continue; 2706 2707 if (mode->clock != clock1 && mode->clock != clock2) 2708 continue; 2709 2710 newmode = drm_mode_duplicate(dev, cea_mode); 2711 if (!newmode) 2712 continue; 2713 2714 /* Carry over the stereo flags */ 2715 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2716 2717 /* 2718 * The current mode could be either variant. Make 2719 * sure to pick the "other" clock for the new mode. 2720 */ 2721 if (mode->clock != clock1) 2722 newmode->clock = clock1; 2723 else 2724 newmode->clock = clock2; 2725 2726 list_add_tail(&newmode->head, &list); 2727 } 2728 2729 list_for_each_entry_safe(mode, tmp, &list, head) { 2730 list_del(&mode->head); 2731 drm_mode_probed_add(connector, mode); 2732 modes++; 2733 } 2734 2735 return modes; 2736 } 2737 2738 static struct drm_display_mode * 2739 drm_display_mode_from_vic_index(struct drm_connector *connector, 2740 const u8 *video_db, u8 video_len, 2741 u8 video_index) 2742 { 2743 struct drm_device *dev = connector->dev; 2744 struct drm_display_mode *newmode; 2745 u8 cea_mode; 2746 2747 if (video_db == NULL || video_index >= video_len) 2748 return NULL; 2749 2750 /* CEA modes are numbered 1..127 */ 2751 cea_mode = (video_db[video_index] & 127) - 1; 2752 if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) 2753 return NULL; 2754 2755 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2756 if (!newmode) 2757 return NULL; 2758 2759 newmode->vrefresh = 0; 2760 2761 return newmode; 2762 } 2763 2764 static int 2765 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2766 { 2767 int i, modes = 0; 2768 2769 for (i = 0; i < len; i++) { 2770 struct drm_display_mode *mode; 2771 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2772 if (mode) { 2773 drm_mode_probed_add(connector, mode); 2774 modes++; 2775 } 2776 } 2777 2778 return modes; 2779 } 2780 2781 struct stereo_mandatory_mode { 2782 int width, height, vrefresh; 2783 unsigned int flags; 2784 }; 2785 2786 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2787 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2788 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2789 { 1920, 1080, 50, 2790 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2791 { 1920, 1080, 60, 2792 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2793 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2794 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2795 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2796 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2797 }; 2798 2799 static bool 2800 stereo_match_mandatory(const struct drm_display_mode *mode, 2801 const struct stereo_mandatory_mode *stereo_mode) 2802 { 2803 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2804 2805 return mode->hdisplay == stereo_mode->width && 2806 mode->vdisplay == stereo_mode->height && 2807 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2808 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2809 } 2810 2811 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2812 { 2813 struct drm_device *dev = connector->dev; 2814 const struct drm_display_mode *mode; 2815 struct list_head stereo_modes; 2816 int modes = 0, i; 2817 2818 INIT_LIST_HEAD(&stereo_modes); 2819 2820 list_for_each_entry(mode, &connector->probed_modes, head) { 2821 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2822 const struct stereo_mandatory_mode *mandatory; 2823 struct drm_display_mode *new_mode; 2824 2825 if (!stereo_match_mandatory(mode, 2826 &stereo_mandatory_modes[i])) 2827 continue; 2828 2829 mandatory = &stereo_mandatory_modes[i]; 2830 new_mode = drm_mode_duplicate(dev, mode); 2831 if (!new_mode) 2832 continue; 2833 2834 new_mode->flags |= mandatory->flags; 2835 list_add_tail(&new_mode->head, &stereo_modes); 2836 modes++; 2837 } 2838 } 2839 2840 list_splice_tail(&stereo_modes, &connector->probed_modes); 2841 2842 return modes; 2843 } 2844 2845 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2846 { 2847 struct drm_device *dev = connector->dev; 2848 struct drm_display_mode *newmode; 2849 2850 vic--; /* VICs start at 1 */ 2851 if (vic >= ARRAY_SIZE(edid_4k_modes)) { 2852 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2853 return 0; 2854 } 2855 2856 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2857 if (!newmode) 2858 return 0; 2859 2860 drm_mode_probed_add(connector, newmode); 2861 2862 return 1; 2863 } 2864 2865 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2866 const u8 *video_db, u8 video_len, u8 video_index) 2867 { 2868 struct drm_display_mode *newmode; 2869 int modes = 0; 2870 2871 if (structure & (1 << 0)) { 2872 newmode = drm_display_mode_from_vic_index(connector, video_db, 2873 video_len, 2874 video_index); 2875 if (newmode) { 2876 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2877 drm_mode_probed_add(connector, newmode); 2878 modes++; 2879 } 2880 } 2881 if (structure & (1 << 6)) { 2882 newmode = drm_display_mode_from_vic_index(connector, video_db, 2883 video_len, 2884 video_index); 2885 if (newmode) { 2886 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2887 drm_mode_probed_add(connector, newmode); 2888 modes++; 2889 } 2890 } 2891 if (structure & (1 << 8)) { 2892 newmode = drm_display_mode_from_vic_index(connector, video_db, 2893 video_len, 2894 video_index); 2895 if (newmode) { 2896 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2897 drm_mode_probed_add(connector, newmode); 2898 modes++; 2899 } 2900 } 2901 2902 return modes; 2903 } 2904 2905 /* 2906 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2907 * @connector: connector corresponding to the HDMI sink 2908 * @db: start of the CEA vendor specific block 2909 * @len: length of the CEA block payload, ie. one can access up to db[len] 2910 * 2911 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2912 * also adds the stereo 3d modes when applicable. 2913 */ 2914 static int 2915 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2916 const u8 *video_db, u8 video_len) 2917 { 2918 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2919 u8 vic_len, hdmi_3d_len = 0; 2920 u16 mask; 2921 u16 structure_all; 2922 2923 if (len < 8) 2924 goto out; 2925 2926 /* no HDMI_Video_Present */ 2927 if (!(db[8] & (1 << 5))) 2928 goto out; 2929 2930 /* Latency_Fields_Present */ 2931 if (db[8] & (1 << 7)) 2932 offset += 2; 2933 2934 /* I_Latency_Fields_Present */ 2935 if (db[8] & (1 << 6)) 2936 offset += 2; 2937 2938 /* the declared length is not long enough for the 2 first bytes 2939 * of additional video format capabilities */ 2940 if (len < (8 + offset + 2)) 2941 goto out; 2942 2943 /* 3D_Present */ 2944 offset++; 2945 if (db[8 + offset] & (1 << 7)) { 2946 modes += add_hdmi_mandatory_stereo_modes(connector); 2947 2948 /* 3D_Multi_present */ 2949 multi_present = (db[8 + offset] & 0x60) >> 5; 2950 } 2951 2952 offset++; 2953 vic_len = db[8 + offset] >> 5; 2954 hdmi_3d_len = db[8 + offset] & 0x1f; 2955 2956 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2957 u8 vic; 2958 2959 vic = db[9 + offset + i]; 2960 modes += add_hdmi_mode(connector, vic); 2961 } 2962 offset += 1 + vic_len; 2963 2964 if (multi_present == 1) 2965 multi_len = 2; 2966 else if (multi_present == 2) 2967 multi_len = 4; 2968 else 2969 multi_len = 0; 2970 2971 if (len < (8 + offset + hdmi_3d_len - 1)) 2972 goto out; 2973 2974 if (hdmi_3d_len < multi_len) 2975 goto out; 2976 2977 if (multi_present == 1 || multi_present == 2) { 2978 /* 3D_Structure_ALL */ 2979 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2980 2981 /* check if 3D_MASK is present */ 2982 if (multi_present == 2) 2983 mask = (db[10 + offset] << 8) | db[11 + offset]; 2984 else 2985 mask = 0xffff; 2986 2987 for (i = 0; i < 16; i++) { 2988 if (mask & (1 << i)) 2989 modes += add_3d_struct_modes(connector, 2990 structure_all, 2991 video_db, 2992 video_len, i); 2993 } 2994 } 2995 2996 offset += multi_len; 2997 2998 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2999 int vic_index; 3000 struct drm_display_mode *newmode = NULL; 3001 unsigned int newflag = 0; 3002 bool detail_present; 3003 3004 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3005 3006 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3007 break; 3008 3009 /* 2D_VIC_order_X */ 3010 vic_index = db[8 + offset + i] >> 4; 3011 3012 /* 3D_Structure_X */ 3013 switch (db[8 + offset + i] & 0x0f) { 3014 case 0: 3015 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3016 break; 3017 case 6: 3018 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3019 break; 3020 case 8: 3021 /* 3D_Detail_X */ 3022 if ((db[9 + offset + i] >> 4) == 1) 3023 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3024 break; 3025 } 3026 3027 if (newflag != 0) { 3028 newmode = drm_display_mode_from_vic_index(connector, 3029 video_db, 3030 video_len, 3031 vic_index); 3032 3033 if (newmode) { 3034 newmode->flags |= newflag; 3035 drm_mode_probed_add(connector, newmode); 3036 modes++; 3037 } 3038 } 3039 3040 if (detail_present) 3041 i++; 3042 } 3043 3044 out: 3045 return modes; 3046 } 3047 3048 static int 3049 cea_db_payload_len(const u8 *db) 3050 { 3051 return db[0] & 0x1f; 3052 } 3053 3054 static int 3055 cea_db_tag(const u8 *db) 3056 { 3057 return db[0] >> 5; 3058 } 3059 3060 static int 3061 cea_revision(const u8 *cea) 3062 { 3063 return cea[1]; 3064 } 3065 3066 static int 3067 cea_db_offsets(const u8 *cea, int *start, int *end) 3068 { 3069 /* Data block offset in CEA extension block */ 3070 *start = 4; 3071 *end = cea[2]; 3072 if (*end == 0) 3073 *end = 127; 3074 if (*end < 4 || *end > 127) 3075 return -ERANGE; 3076 return 0; 3077 } 3078 3079 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3080 { 3081 int hdmi_id; 3082 3083 if (cea_db_tag(db) != VENDOR_BLOCK) 3084 return false; 3085 3086 if (cea_db_payload_len(db) < 5) 3087 return false; 3088 3089 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3090 3091 return hdmi_id == HDMI_IEEE_OUI; 3092 } 3093 3094 #define for_each_cea_db(cea, i, start, end) \ 3095 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3096 3097 static int 3098 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3099 { 3100 const u8 *cea = drm_find_cea_extension(edid); 3101 const u8 *db, *hdmi = NULL, *video = NULL; 3102 u8 dbl, hdmi_len, video_len = 0; 3103 int modes = 0; 3104 3105 if (cea && cea_revision(cea) >= 3) { 3106 int i, start, end; 3107 3108 if (cea_db_offsets(cea, &start, &end)) 3109 return 0; 3110 3111 for_each_cea_db(cea, i, start, end) { 3112 db = &cea[i]; 3113 dbl = cea_db_payload_len(db); 3114 3115 if (cea_db_tag(db) == VIDEO_BLOCK) { 3116 video = db + 1; 3117 video_len = dbl; 3118 modes += do_cea_modes(connector, video, dbl); 3119 } 3120 else if (cea_db_is_hdmi_vsdb(db)) { 3121 hdmi = db; 3122 hdmi_len = dbl; 3123 } 3124 } 3125 } 3126 3127 /* 3128 * We parse the HDMI VSDB after having added the cea modes as we will 3129 * be patching their flags when the sink supports stereo 3D. 3130 */ 3131 if (hdmi) 3132 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3133 video_len); 3134 3135 return modes; 3136 } 3137 3138 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3139 { 3140 const struct drm_display_mode *cea_mode; 3141 int clock1, clock2, clock; 3142 u8 mode_idx; 3143 const char *type; 3144 3145 mode_idx = drm_match_cea_mode(mode) - 1; 3146 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 3147 type = "CEA"; 3148 cea_mode = &edid_cea_modes[mode_idx]; 3149 clock1 = cea_mode->clock; 3150 clock2 = cea_mode_alternate_clock(cea_mode); 3151 } else { 3152 mode_idx = drm_match_hdmi_mode(mode) - 1; 3153 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 3154 type = "HDMI"; 3155 cea_mode = &edid_4k_modes[mode_idx]; 3156 clock1 = cea_mode->clock; 3157 clock2 = hdmi_mode_alternate_clock(cea_mode); 3158 } else { 3159 return; 3160 } 3161 } 3162 3163 /* pick whichever is closest */ 3164 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3165 clock = clock1; 3166 else 3167 clock = clock2; 3168 3169 if (mode->clock == clock) 3170 return; 3171 3172 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3173 type, mode_idx + 1, mode->clock, clock); 3174 mode->clock = clock; 3175 } 3176 3177 static void 3178 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3179 { 3180 u8 len = cea_db_payload_len(db); 3181 3182 if (len >= 5) { 3183 connector->physical_address = (db[4] << 8) | db[5]; 3184 } 3185 if (len >= 6) { 3186 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3187 connector->dvi_dual = db[6] & 1; 3188 } 3189 if (len >= 7) 3190 connector->max_tmds_clock = db[7] * 5; 3191 if (len >= 8) { 3192 connector->latency_present[0] = db[8] >> 7; 3193 connector->latency_present[1] = (db[8] >> 6) & 1; 3194 } 3195 if (len >= 9) 3196 connector->video_latency[0] = db[9]; 3197 if (len >= 10) 3198 connector->audio_latency[0] = db[10]; 3199 if (len >= 11) 3200 connector->video_latency[1] = db[11]; 3201 if (len >= 12) 3202 connector->audio_latency[1] = db[12]; 3203 3204 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3205 "max TMDS clock %d, " 3206 "latency present %d %d, " 3207 "video latency %d %d, " 3208 "audio latency %d %d\n", 3209 connector->dvi_dual, 3210 connector->max_tmds_clock, 3211 (int) connector->latency_present[0], 3212 (int) connector->latency_present[1], 3213 connector->video_latency[0], 3214 connector->video_latency[1], 3215 connector->audio_latency[0], 3216 connector->audio_latency[1]); 3217 } 3218 3219 static void 3220 monitor_name(struct detailed_timing *t, void *data) 3221 { 3222 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3223 *(u8 **)data = t->data.other_data.data.str.str; 3224 } 3225 3226 /** 3227 * drm_edid_to_eld - build ELD from EDID 3228 * @connector: connector corresponding to the HDMI/DP sink 3229 * @edid: EDID to parse 3230 * 3231 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3232 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 3233 */ 3234 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3235 { 3236 uint8_t *eld = connector->eld; 3237 u8 *cea; 3238 u8 *name; 3239 u8 *db; 3240 int sad_count = 0; 3241 int mnl; 3242 int dbl; 3243 3244 memset(eld, 0, sizeof(connector->eld)); 3245 3246 cea = drm_find_cea_extension(edid); 3247 if (!cea) { 3248 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3249 return; 3250 } 3251 3252 name = NULL; 3253 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 3254 for (mnl = 0; name && mnl < 13; mnl++) { 3255 if (name[mnl] == 0x0a) 3256 break; 3257 eld[20 + mnl] = name[mnl]; 3258 } 3259 eld[4] = (cea[1] << 5) | mnl; 3260 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3261 3262 eld[0] = 2 << 3; /* ELD version: 2 */ 3263 3264 eld[16] = edid->mfg_id[0]; 3265 eld[17] = edid->mfg_id[1]; 3266 eld[18] = edid->prod_code[0]; 3267 eld[19] = edid->prod_code[1]; 3268 3269 if (cea_revision(cea) >= 3) { 3270 int i, start, end; 3271 3272 if (cea_db_offsets(cea, &start, &end)) { 3273 start = 0; 3274 end = 0; 3275 } 3276 3277 for_each_cea_db(cea, i, start, end) { 3278 db = &cea[i]; 3279 dbl = cea_db_payload_len(db); 3280 3281 switch (cea_db_tag(db)) { 3282 case AUDIO_BLOCK: 3283 /* Audio Data Block, contains SADs */ 3284 sad_count = dbl / 3; 3285 if (dbl >= 1) 3286 memcpy(eld + 20 + mnl, &db[1], dbl); 3287 break; 3288 case SPEAKER_BLOCK: 3289 /* Speaker Allocation Data Block */ 3290 if (dbl >= 1) 3291 eld[7] = db[1]; 3292 break; 3293 case VENDOR_BLOCK: 3294 /* HDMI Vendor-Specific Data Block */ 3295 if (cea_db_is_hdmi_vsdb(db)) 3296 parse_hdmi_vsdb(connector, db); 3297 break; 3298 default: 3299 break; 3300 } 3301 } 3302 } 3303 eld[5] |= sad_count << 4; 3304 3305 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3306 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3307 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 3308 else 3309 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 3310 3311 eld[DRM_ELD_BASELINE_ELD_LEN] = 3312 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3313 3314 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3315 drm_eld_size(eld), sad_count); 3316 } 3317 EXPORT_SYMBOL(drm_edid_to_eld); 3318 3319 /** 3320 * drm_edid_to_sad - extracts SADs from EDID 3321 * @edid: EDID to parse 3322 * @sads: pointer that will be set to the extracted SADs 3323 * 3324 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3325 * 3326 * Note: The returned pointer needs to be freed using kfree(). 3327 * 3328 * Return: The number of found SADs or negative number on error. 3329 */ 3330 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3331 { 3332 int count = 0; 3333 int i, start, end, dbl; 3334 u8 *cea; 3335 3336 cea = drm_find_cea_extension(edid); 3337 if (!cea) { 3338 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3339 return -ENOENT; 3340 } 3341 3342 if (cea_revision(cea) < 3) { 3343 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3344 return -ENOTSUPP; 3345 } 3346 3347 if (cea_db_offsets(cea, &start, &end)) { 3348 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3349 return -EPROTO; 3350 } 3351 3352 for_each_cea_db(cea, i, start, end) { 3353 u8 *db = &cea[i]; 3354 3355 if (cea_db_tag(db) == AUDIO_BLOCK) { 3356 int j; 3357 dbl = cea_db_payload_len(db); 3358 3359 count = dbl / 3; /* SAD is 3B */ 3360 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3361 if (!*sads) 3362 return -ENOMEM; 3363 for (j = 0; j < count; j++) { 3364 u8 *sad = &db[1 + j * 3]; 3365 3366 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3367 (*sads)[j].channels = sad[0] & 0x7; 3368 (*sads)[j].freq = sad[1] & 0x7F; 3369 (*sads)[j].byte2 = sad[2]; 3370 } 3371 break; 3372 } 3373 } 3374 3375 return count; 3376 } 3377 EXPORT_SYMBOL(drm_edid_to_sad); 3378 3379 /** 3380 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3381 * @edid: EDID to parse 3382 * @sadb: pointer to the speaker block 3383 * 3384 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3385 * 3386 * Note: The returned pointer needs to be freed using kfree(). 3387 * 3388 * Return: The number of found Speaker Allocation Blocks or negative number on 3389 * error. 3390 */ 3391 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3392 { 3393 int count = 0; 3394 int i, start, end, dbl; 3395 const u8 *cea; 3396 3397 cea = drm_find_cea_extension(edid); 3398 if (!cea) { 3399 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3400 return -ENOENT; 3401 } 3402 3403 if (cea_revision(cea) < 3) { 3404 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3405 return -ENOTSUPP; 3406 } 3407 3408 if (cea_db_offsets(cea, &start, &end)) { 3409 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3410 return -EPROTO; 3411 } 3412 3413 for_each_cea_db(cea, i, start, end) { 3414 const u8 *db = &cea[i]; 3415 3416 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3417 dbl = cea_db_payload_len(db); 3418 3419 /* Speaker Allocation Data Block */ 3420 if (dbl == 3) { 3421 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3422 if (!*sadb) 3423 return -ENOMEM; 3424 count = dbl; 3425 break; 3426 } 3427 } 3428 } 3429 3430 return count; 3431 } 3432 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3433 3434 /** 3435 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3436 * @connector: connector associated with the HDMI/DP sink 3437 * @mode: the display mode 3438 * 3439 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3440 * the sink doesn't support audio or video. 3441 */ 3442 int drm_av_sync_delay(struct drm_connector *connector, 3443 const struct drm_display_mode *mode) 3444 { 3445 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3446 int a, v; 3447 3448 if (!connector->latency_present[0]) 3449 return 0; 3450 if (!connector->latency_present[1]) 3451 i = 0; 3452 3453 a = connector->audio_latency[i]; 3454 v = connector->video_latency[i]; 3455 3456 /* 3457 * HDMI/DP sink doesn't support audio or video? 3458 */ 3459 if (a == 255 || v == 255) 3460 return 0; 3461 3462 /* 3463 * Convert raw EDID values to millisecond. 3464 * Treat unknown latency as 0ms. 3465 */ 3466 if (a) 3467 a = min(2 * (a - 1), 500); 3468 if (v) 3469 v = min(2 * (v - 1), 500); 3470 3471 return max(v - a, 0); 3472 } 3473 EXPORT_SYMBOL(drm_av_sync_delay); 3474 3475 /** 3476 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3477 * @encoder: the encoder just changed display mode 3478 * 3479 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3480 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3481 * 3482 * Return: The connector associated with the first HDMI/DP sink that has ELD 3483 * attached to it. 3484 */ 3485 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3486 { 3487 struct drm_connector *connector; 3488 struct drm_device *dev = encoder->dev; 3489 3490 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3491 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3492 3493 drm_for_each_connector(connector, dev) 3494 if (connector->encoder == encoder && connector->eld[0]) 3495 return connector; 3496 3497 return NULL; 3498 } 3499 EXPORT_SYMBOL(drm_select_eld); 3500 3501 /** 3502 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3503 * @edid: monitor EDID information 3504 * 3505 * Parse the CEA extension according to CEA-861-B. 3506 * 3507 * Return: True if the monitor is HDMI, false if not or unknown. 3508 */ 3509 bool drm_detect_hdmi_monitor(struct edid *edid) 3510 { 3511 u8 *edid_ext; 3512 int i; 3513 int start_offset, end_offset; 3514 3515 edid_ext = drm_find_cea_extension(edid); 3516 if (!edid_ext) 3517 return false; 3518 3519 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3520 return false; 3521 3522 /* 3523 * Because HDMI identifier is in Vendor Specific Block, 3524 * search it from all data blocks of CEA extension. 3525 */ 3526 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3527 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3528 return true; 3529 } 3530 3531 return false; 3532 } 3533 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3534 3535 /** 3536 * drm_detect_monitor_audio - check monitor audio capability 3537 * @edid: EDID block to scan 3538 * 3539 * Monitor should have CEA extension block. 3540 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3541 * audio' only. If there is any audio extension block and supported 3542 * audio format, assume at least 'basic audio' support, even if 'basic 3543 * audio' is not defined in EDID. 3544 * 3545 * Return: True if the monitor supports audio, false otherwise. 3546 */ 3547 bool drm_detect_monitor_audio(struct edid *edid) 3548 { 3549 u8 *edid_ext; 3550 int i, j; 3551 bool has_audio = false; 3552 int start_offset, end_offset; 3553 3554 edid_ext = drm_find_cea_extension(edid); 3555 if (!edid_ext) 3556 goto end; 3557 3558 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3559 3560 if (has_audio) { 3561 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3562 goto end; 3563 } 3564 3565 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3566 goto end; 3567 3568 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3569 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3570 has_audio = true; 3571 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3572 DRM_DEBUG_KMS("CEA audio format %d\n", 3573 (edid_ext[i + j] >> 3) & 0xf); 3574 goto end; 3575 } 3576 } 3577 end: 3578 return has_audio; 3579 } 3580 EXPORT_SYMBOL(drm_detect_monitor_audio); 3581 3582 /** 3583 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3584 * @edid: EDID block to scan 3585 * 3586 * Check whether the monitor reports the RGB quantization range selection 3587 * as supported. The AVI infoframe can then be used to inform the monitor 3588 * which quantization range (full or limited) is used. 3589 * 3590 * Return: True if the RGB quantization range is selectable, false otherwise. 3591 */ 3592 bool drm_rgb_quant_range_selectable(struct edid *edid) 3593 { 3594 u8 *edid_ext; 3595 int i, start, end; 3596 3597 edid_ext = drm_find_cea_extension(edid); 3598 if (!edid_ext) 3599 return false; 3600 3601 if (cea_db_offsets(edid_ext, &start, &end)) 3602 return false; 3603 3604 for_each_cea_db(edid_ext, i, start, end) { 3605 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3606 cea_db_payload_len(&edid_ext[i]) == 2) { 3607 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3608 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3609 } 3610 } 3611 3612 return false; 3613 } 3614 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3615 3616 /** 3617 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3618 * hdmi deep color modes and update drm_display_info if so. 3619 * @edid: monitor EDID information 3620 * @info: Updated with maximum supported deep color bpc and color format 3621 * if deep color supported. 3622 * @connector: DRM connector, used only for debug output 3623 * 3624 * Parse the CEA extension according to CEA-861-B. 3625 * Return true if HDMI deep color supported, false if not or unknown. 3626 */ 3627 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3628 struct drm_display_info *info, 3629 struct drm_connector *connector) 3630 { 3631 u8 *edid_ext, *hdmi; 3632 int i; 3633 int start_offset, end_offset; 3634 unsigned int dc_bpc = 0; 3635 3636 edid_ext = drm_find_cea_extension(edid); 3637 if (!edid_ext) 3638 return false; 3639 3640 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3641 return false; 3642 3643 /* 3644 * Because HDMI identifier is in Vendor Specific Block, 3645 * search it from all data blocks of CEA extension. 3646 */ 3647 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3648 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3649 /* HDMI supports at least 8 bpc */ 3650 info->bpc = 8; 3651 3652 hdmi = &edid_ext[i]; 3653 if (cea_db_payload_len(hdmi) < 6) 3654 return false; 3655 3656 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3657 dc_bpc = 10; 3658 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3659 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3660 connector->name); 3661 } 3662 3663 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3664 dc_bpc = 12; 3665 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3666 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3667 connector->name); 3668 } 3669 3670 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3671 dc_bpc = 16; 3672 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3673 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3674 connector->name); 3675 } 3676 3677 if (dc_bpc > 0) { 3678 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3679 connector->name, dc_bpc); 3680 info->bpc = dc_bpc; 3681 3682 /* 3683 * Deep color support mandates RGB444 support for all video 3684 * modes and forbids YCRCB422 support for all video modes per 3685 * HDMI 1.3 spec. 3686 */ 3687 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3688 3689 /* YCRCB444 is optional according to spec. */ 3690 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3691 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3692 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3693 connector->name); 3694 } 3695 3696 /* 3697 * Spec says that if any deep color mode is supported at all, 3698 * then deep color 36 bit must be supported. 3699 */ 3700 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3701 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3702 connector->name); 3703 } 3704 3705 return true; 3706 } 3707 else { 3708 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3709 connector->name); 3710 } 3711 } 3712 } 3713 3714 return false; 3715 } 3716 3717 /** 3718 * drm_add_display_info - pull display info out if present 3719 * @edid: EDID data 3720 * @info: display info (attached to connector) 3721 * @connector: connector whose edid is used to build display info 3722 * 3723 * Grab any available display info and stuff it into the drm_display_info 3724 * structure that's part of the connector. Useful for tracking bpp and 3725 * color spaces. 3726 */ 3727 static void drm_add_display_info(struct edid *edid, 3728 struct drm_display_info *info, 3729 struct drm_connector *connector) 3730 { 3731 u8 *edid_ext; 3732 3733 info->width_mm = edid->width_cm * 10; 3734 info->height_mm = edid->height_cm * 10; 3735 3736 /* driver figures it out in this case */ 3737 info->bpc = 0; 3738 info->color_formats = 0; 3739 3740 if (edid->revision < 3) 3741 return; 3742 3743 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3744 return; 3745 3746 /* Get data from CEA blocks if present */ 3747 edid_ext = drm_find_cea_extension(edid); 3748 if (edid_ext) { 3749 info->cea_rev = edid_ext[1]; 3750 3751 /* The existence of a CEA block should imply RGB support */ 3752 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3753 if (edid_ext[3] & EDID_CEA_YCRCB444) 3754 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3755 if (edid_ext[3] & EDID_CEA_YCRCB422) 3756 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3757 } 3758 3759 /* HDMI deep color modes supported? Assign to info, if so */ 3760 drm_assign_hdmi_deep_color_info(edid, info, connector); 3761 3762 /* Only defined for 1.4 with digital displays */ 3763 if (edid->revision < 4) 3764 return; 3765 3766 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3767 case DRM_EDID_DIGITAL_DEPTH_6: 3768 info->bpc = 6; 3769 break; 3770 case DRM_EDID_DIGITAL_DEPTH_8: 3771 info->bpc = 8; 3772 break; 3773 case DRM_EDID_DIGITAL_DEPTH_10: 3774 info->bpc = 10; 3775 break; 3776 case DRM_EDID_DIGITAL_DEPTH_12: 3777 info->bpc = 12; 3778 break; 3779 case DRM_EDID_DIGITAL_DEPTH_14: 3780 info->bpc = 14; 3781 break; 3782 case DRM_EDID_DIGITAL_DEPTH_16: 3783 info->bpc = 16; 3784 break; 3785 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3786 default: 3787 info->bpc = 0; 3788 break; 3789 } 3790 3791 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3792 connector->name, info->bpc); 3793 3794 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3795 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3796 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3797 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3798 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3799 } 3800 3801 /** 3802 * drm_add_edid_modes - add modes from EDID data, if available 3803 * @connector: connector we're probing 3804 * @edid: EDID data 3805 * 3806 * Add the specified modes to the connector's mode list. 3807 * 3808 * Return: The number of modes added or 0 if we couldn't find any. 3809 */ 3810 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3811 { 3812 int num_modes = 0; 3813 u32 quirks; 3814 3815 if (edid == NULL) { 3816 return 0; 3817 } 3818 if (!drm_edid_is_valid(edid)) { 3819 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3820 connector->name); 3821 return 0; 3822 } 3823 3824 quirks = edid_get_quirks(edid); 3825 3826 /* 3827 * EDID spec says modes should be preferred in this order: 3828 * - preferred detailed mode 3829 * - other detailed modes from base block 3830 * - detailed modes from extension blocks 3831 * - CVT 3-byte code modes 3832 * - standard timing codes 3833 * - established timing codes 3834 * - modes inferred from GTF or CVT range information 3835 * 3836 * We get this pretty much right. 3837 * 3838 * XXX order for additional mode types in extension blocks? 3839 */ 3840 num_modes += add_detailed_modes(connector, edid, quirks); 3841 num_modes += add_cvt_modes(connector, edid); 3842 num_modes += add_standard_modes(connector, edid); 3843 num_modes += add_established_modes(connector, edid); 3844 num_modes += add_cea_modes(connector, edid); 3845 num_modes += add_alternate_cea_modes(connector, edid); 3846 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3847 num_modes += add_inferred_modes(connector, edid); 3848 3849 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3850 edid_fixup_preferred(connector, quirks); 3851 3852 drm_add_display_info(edid, &connector->display_info, connector); 3853 3854 if (quirks & EDID_QUIRK_FORCE_6BPC) 3855 connector->display_info.bpc = 6; 3856 3857 if (quirks & EDID_QUIRK_FORCE_8BPC) 3858 connector->display_info.bpc = 8; 3859 3860 if (quirks & EDID_QUIRK_FORCE_10BPC) 3861 connector->display_info.bpc = 10; 3862 3863 if (quirks & EDID_QUIRK_FORCE_12BPC) 3864 connector->display_info.bpc = 12; 3865 3866 return num_modes; 3867 } 3868 EXPORT_SYMBOL(drm_add_edid_modes); 3869 3870 /** 3871 * drm_add_modes_noedid - add modes for the connectors without EDID 3872 * @connector: connector we're probing 3873 * @hdisplay: the horizontal display limit 3874 * @vdisplay: the vertical display limit 3875 * 3876 * Add the specified modes to the connector's mode list. Only when the 3877 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3878 * 3879 * Return: The number of modes added or 0 if we couldn't find any. 3880 */ 3881 int drm_add_modes_noedid(struct drm_connector *connector, 3882 int hdisplay, int vdisplay) 3883 { 3884 int i, count, num_modes = 0; 3885 struct drm_display_mode *mode; 3886 struct drm_device *dev = connector->dev; 3887 3888 count = ARRAY_SIZE(drm_dmt_modes); 3889 if (hdisplay < 0) 3890 hdisplay = 0; 3891 if (vdisplay < 0) 3892 vdisplay = 0; 3893 3894 for (i = 0; i < count; i++) { 3895 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3896 if (hdisplay && vdisplay) { 3897 /* 3898 * Only when two are valid, they will be used to check 3899 * whether the mode should be added to the mode list of 3900 * the connector. 3901 */ 3902 if (ptr->hdisplay > hdisplay || 3903 ptr->vdisplay > vdisplay) 3904 continue; 3905 } 3906 if (drm_mode_vrefresh(ptr) > 61) 3907 continue; 3908 mode = drm_mode_duplicate(dev, ptr); 3909 if (mode) { 3910 drm_mode_probed_add(connector, mode); 3911 num_modes++; 3912 } 3913 } 3914 return num_modes; 3915 } 3916 EXPORT_SYMBOL(drm_add_modes_noedid); 3917 3918 /** 3919 * drm_set_preferred_mode - Sets the preferred mode of a connector 3920 * @connector: connector whose mode list should be processed 3921 * @hpref: horizontal resolution of preferred mode 3922 * @vpref: vertical resolution of preferred mode 3923 * 3924 * Marks a mode as preferred if it matches the resolution specified by @hpref 3925 * and @vpref. 3926 */ 3927 void drm_set_preferred_mode(struct drm_connector *connector, 3928 int hpref, int vpref) 3929 { 3930 struct drm_display_mode *mode; 3931 3932 list_for_each_entry(mode, &connector->probed_modes, head) { 3933 if (mode->hdisplay == hpref && 3934 mode->vdisplay == vpref) 3935 mode->type |= DRM_MODE_TYPE_PREFERRED; 3936 } 3937 } 3938 EXPORT_SYMBOL(drm_set_preferred_mode); 3939 3940 /** 3941 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3942 * data from a DRM display mode 3943 * @frame: HDMI AVI infoframe 3944 * @mode: DRM display mode 3945 * 3946 * Return: 0 on success or a negative error code on failure. 3947 */ 3948 int 3949 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3950 const struct drm_display_mode *mode) 3951 { 3952 int err; 3953 3954 if (!frame || !mode) 3955 return -EINVAL; 3956 3957 err = hdmi_avi_infoframe_init(frame); 3958 if (err < 0) 3959 return err; 3960 3961 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3962 frame->pixel_repeat = 1; 3963 3964 frame->video_code = drm_match_cea_mode(mode); 3965 3966 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3967 3968 /* 3969 * Populate picture aspect ratio from either 3970 * user input (if specified) or from the CEA mode list. 3971 */ 3972 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 3973 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 3974 frame->picture_aspect = mode->picture_aspect_ratio; 3975 else if (frame->video_code > 0) 3976 frame->picture_aspect = drm_get_cea_aspect_ratio( 3977 frame->video_code); 3978 3979 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 3980 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 3981 3982 return 0; 3983 } 3984 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 3985 3986 static enum hdmi_3d_structure 3987 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 3988 { 3989 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 3990 3991 switch (layout) { 3992 case DRM_MODE_FLAG_3D_FRAME_PACKING: 3993 return HDMI_3D_STRUCTURE_FRAME_PACKING; 3994 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 3995 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 3996 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 3997 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 3998 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 3999 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4000 case DRM_MODE_FLAG_3D_L_DEPTH: 4001 return HDMI_3D_STRUCTURE_L_DEPTH; 4002 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4003 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4004 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4005 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4006 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4007 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4008 default: 4009 return HDMI_3D_STRUCTURE_INVALID; 4010 } 4011 } 4012 4013 /** 4014 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4015 * data from a DRM display mode 4016 * @frame: HDMI vendor infoframe 4017 * @mode: DRM display mode 4018 * 4019 * Note that there's is a need to send HDMI vendor infoframes only when using a 4020 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4021 * function will return -EINVAL, error that can be safely ignored. 4022 * 4023 * Return: 0 on success or a negative error code on failure. 4024 */ 4025 int 4026 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4027 const struct drm_display_mode *mode) 4028 { 4029 int err; 4030 u32 s3d_flags; 4031 u8 vic; 4032 4033 if (!frame || !mode) 4034 return -EINVAL; 4035 4036 vic = drm_match_hdmi_mode(mode); 4037 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4038 4039 if (!vic && !s3d_flags) 4040 return -EINVAL; 4041 4042 if (vic && s3d_flags) 4043 return -EINVAL; 4044 4045 err = hdmi_vendor_infoframe_init(frame); 4046 if (err < 0) 4047 return err; 4048 4049 if (vic) 4050 frame->vic = vic; 4051 else 4052 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4053 4054 return 0; 4055 } 4056 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4057 4058 static int drm_parse_display_id(struct drm_connector *connector, 4059 u8 *displayid, int length, 4060 bool is_edid_extension) 4061 { 4062 /* if this is an EDID extension the first byte will be 0x70 */ 4063 int idx = 0; 4064 struct displayid_hdr *base; 4065 struct displayid_block *block; 4066 u8 csum = 0; 4067 int i; 4068 4069 if (is_edid_extension) 4070 idx = 1; 4071 4072 base = (struct displayid_hdr *)&displayid[idx]; 4073 4074 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4075 base->rev, base->bytes, base->prod_id, base->ext_count); 4076 4077 if (base->bytes + 5 > length - idx) 4078 return -EINVAL; 4079 4080 for (i = idx; i <= base->bytes + 5; i++) { 4081 csum += displayid[i]; 4082 } 4083 if (csum) { 4084 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); 4085 return -EINVAL; 4086 } 4087 4088 block = (struct displayid_block *)&displayid[idx + 4]; 4089 DRM_DEBUG_KMS("block id %d, rev %d, len %d\n", 4090 block->tag, block->rev, block->num_bytes); 4091 4092 switch (block->tag) { 4093 case DATA_BLOCK_TILED_DISPLAY: { 4094 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4095 4096 u16 w, h; 4097 u8 tile_v_loc, tile_h_loc; 4098 u8 num_v_tile, num_h_tile; 4099 struct drm_tile_group *tg; 4100 4101 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4102 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4103 4104 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4105 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4106 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4107 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4108 4109 connector->has_tile = true; 4110 if (tile->tile_cap & 0x80) 4111 connector->tile_is_single_monitor = true; 4112 4113 connector->num_h_tile = num_h_tile + 1; 4114 connector->num_v_tile = num_v_tile + 1; 4115 connector->tile_h_loc = tile_h_loc; 4116 connector->tile_v_loc = tile_v_loc; 4117 connector->tile_h_size = w + 1; 4118 connector->tile_v_size = h + 1; 4119 4120 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4121 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4122 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4123 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4124 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4125 4126 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4127 if (!tg) { 4128 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4129 } 4130 if (!tg) 4131 return -ENOMEM; 4132 4133 if (connector->tile_group != tg) { 4134 /* if we haven't got a pointer, 4135 take the reference, drop ref to old tile group */ 4136 if (connector->tile_group) { 4137 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4138 } 4139 connector->tile_group = tg; 4140 } else 4141 /* if same tile group, then release the ref we just took. */ 4142 drm_mode_put_tile_group(connector->dev, tg); 4143 } 4144 break; 4145 default: 4146 printk("unknown displayid tag %d\n", block->tag); 4147 break; 4148 } 4149 return 0; 4150 } 4151 4152 static void drm_get_displayid(struct drm_connector *connector, 4153 struct edid *edid) 4154 { 4155 void *displayid = NULL; 4156 int ret; 4157 connector->has_tile = false; 4158 displayid = drm_find_displayid_extension(edid); 4159 if (!displayid) { 4160 /* drop reference to any tile group we had */ 4161 goto out_drop_ref; 4162 } 4163 4164 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 4165 if (ret < 0) 4166 goto out_drop_ref; 4167 if (!connector->has_tile) 4168 goto out_drop_ref; 4169 return; 4170 out_drop_ref: 4171 if (connector->tile_group) { 4172 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4173 connector->tile_group = NULL; 4174 } 4175 return; 4176 } 4177