1 /* $NetBSD: drm_edid.c,v 1.7 2020/02/14 04:38:48 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Luc Verhaegen (quirks list) 5 * Copyright (c) 2007-2008 Intel Corporation 6 * Jesse Barnes <jesse.barnes@intel.com> 7 * Copyright 2010 Red Hat, Inc. 8 * 9 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 10 * FB layer. 11 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a 14 * copy of this software and associated documentation files (the "Software"), 15 * to deal in the Software without restriction, including without limitation 16 * the rights to use, copy, modify, merge, publish, distribute, sub license, 17 * and/or sell copies of the Software, and to permit persons to whom the 18 * Software is furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 26 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 27 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 28 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 29 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 30 * DEALINGS IN THE SOFTWARE. 31 */ 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: drm_edid.c,v 1.7 2020/02/14 04:38:48 riastradh Exp $"); 34 35 #include <linux/kernel.h> 36 #include <linux/slab.h> 37 #include <linux/hdmi.h> 38 #include <linux/i2c.h> 39 #include <linux/module.h> 40 #include <linux/moduleparam.h> 41 #include <linux/export.h> 42 #include <linux/printk.h> 43 #include <linux/device.h> 44 #include <linux/string.h> 45 #include <linux/errno.h> 46 #include <asm/byteorder.h> 47 #include <drm/drmP.h> 48 #include <drm/drm_edid.h> 49 #include <drm/drm_displayid.h> 50 51 #include <linux/nbsd-namespace.h> 52 53 #define version_greater(edid, maj, min) \ 54 (((edid)->version > (maj)) || \ 55 ((edid)->version == (maj) && (edid)->revision > (min))) 56 57 #define EDID_EST_TIMINGS 16 58 #define EDID_STD_TIMINGS 8 59 #define EDID_DETAILED_TIMINGS 4 60 61 /* 62 * EDID blocks out in the wild have a variety of bugs, try to collect 63 * them here (note that userspace may work around broken monitors first, 64 * but fixes should make their way here so that the kernel "just works" 65 * on as many displays as possible). 66 */ 67 68 /* First detailed mode wrong, use largest 60Hz mode */ 69 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 70 /* Reported 135MHz pixel clock is too high, needs adjustment */ 71 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 72 /* Prefer the largest mode at 75 Hz */ 73 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 74 /* Detail timing is in cm not mm */ 75 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 76 /* Detailed timing descriptors have bogus size values, so just take the 77 * maximum size and use that. 78 */ 79 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 80 /* Monitor forgot to set the first detailed is preferred bit. */ 81 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 82 /* use +hsync +vsync for detailed mode */ 83 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 84 /* Force reduced-blanking timings for detailed modes */ 85 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 86 /* Force 8bpc */ 87 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 88 /* Force 12bpc */ 89 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 90 /* Force 6bpc */ 91 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 92 /* Force 10bpc */ 93 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 94 95 struct detailed_mode_closure { 96 struct drm_connector *connector; 97 struct edid *edid; 98 bool preferred; 99 u32 quirks; 100 int modes; 101 }; 102 103 #define LEVEL_DMT 0 104 #define LEVEL_GTF 1 105 #define LEVEL_GTF2 2 106 #define LEVEL_CVT 3 107 108 static struct edid_quirk { 109 char vendor[4]; 110 int product_id; 111 u32 quirks; 112 } edid_quirk_list[] = { 113 /* Acer AL1706 */ 114 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 115 /* Acer F51 */ 116 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 117 /* Unknown Acer */ 118 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 119 120 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 121 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 122 123 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 124 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 125 126 /* Belinea 10 15 55 */ 127 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 128 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 129 130 /* Envision Peripherals, Inc. EN-7100e */ 131 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 132 /* Envision EN2028 */ 133 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 134 135 /* Funai Electronics PM36B */ 136 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 137 EDID_QUIRK_DETAILED_IN_CM }, 138 139 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 140 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 141 142 /* LG Philips LCD LP154W01-A5 */ 143 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 144 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 146 /* Philips 107p5 CRT */ 147 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 148 149 /* Proview AY765C */ 150 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 151 152 /* Samsung SyncMaster 205BW. Note: irony */ 153 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 154 /* Samsung SyncMaster 22[5-6]BW */ 155 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 156 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 157 158 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 159 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 160 161 /* ViewSonic VA2026w */ 162 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 163 164 /* Medion MD 30217 PG */ 165 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 166 167 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 168 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 169 170 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 171 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 172 }; 173 174 /* 175 * Autogenerated from the DMT spec. 176 * This table is copied from xfree86/modes/xf86EdidModes.c. 177 */ 178 static const struct drm_display_mode drm_dmt_modes[] = { 179 /* 0x01 - 640x350@85Hz */ 180 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 181 736, 832, 0, 350, 382, 385, 445, 0, 182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 183 /* 0x02 - 640x400@85Hz */ 184 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 185 736, 832, 0, 400, 401, 404, 445, 0, 186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 187 /* 0x03 - 720x400@85Hz */ 188 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 189 828, 936, 0, 400, 401, 404, 446, 0, 190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 191 /* 0x04 - 640x480@60Hz */ 192 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 193 752, 800, 0, 480, 490, 492, 525, 0, 194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 195 /* 0x05 - 640x480@72Hz */ 196 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 197 704, 832, 0, 480, 489, 492, 520, 0, 198 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 199 /* 0x06 - 640x480@75Hz */ 200 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 201 720, 840, 0, 480, 481, 484, 500, 0, 202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 203 /* 0x07 - 640x480@85Hz */ 204 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 205 752, 832, 0, 480, 481, 484, 509, 0, 206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 207 /* 0x08 - 800x600@56Hz */ 208 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 209 896, 1024, 0, 600, 601, 603, 625, 0, 210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 211 /* 0x09 - 800x600@60Hz */ 212 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 213 968, 1056, 0, 600, 601, 605, 628, 0, 214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 215 /* 0x0a - 800x600@72Hz */ 216 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 217 976, 1040, 0, 600, 637, 643, 666, 0, 218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 219 /* 0x0b - 800x600@75Hz */ 220 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 221 896, 1056, 0, 600, 601, 604, 625, 0, 222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 223 /* 0x0c - 800x600@85Hz */ 224 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 225 896, 1048, 0, 600, 601, 604, 631, 0, 226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 227 /* 0x0d - 800x600@120Hz RB */ 228 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 229 880, 960, 0, 600, 603, 607, 636, 0, 230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 231 /* 0x0e - 848x480@60Hz */ 232 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 233 976, 1088, 0, 480, 486, 494, 517, 0, 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 235 /* 0x0f - 1024x768@43Hz, interlace */ 236 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 237 1208, 1264, 0, 768, 768, 772, 817, 0, 238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 239 DRM_MODE_FLAG_INTERLACE) }, 240 /* 0x10 - 1024x768@60Hz */ 241 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 242 1184, 1344, 0, 768, 771, 777, 806, 0, 243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 244 /* 0x11 - 1024x768@70Hz */ 245 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 246 1184, 1328, 0, 768, 771, 777, 806, 0, 247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x12 - 1024x768@75Hz */ 249 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 250 1136, 1312, 0, 768, 769, 772, 800, 0, 251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 252 /* 0x13 - 1024x768@85Hz */ 253 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 254 1168, 1376, 0, 768, 769, 772, 808, 0, 255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x14 - 1024x768@120Hz RB */ 257 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 258 1104, 1184, 0, 768, 771, 775, 813, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 260 /* 0x15 - 1152x864@75Hz */ 261 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 262 1344, 1600, 0, 864, 865, 868, 900, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x55 - 1280x720@60Hz */ 265 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 266 1430, 1650, 0, 720, 725, 730, 750, 0, 267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 0x16 - 1280x768@60Hz RB */ 269 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 270 1360, 1440, 0, 768, 771, 778, 790, 0, 271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 272 /* 0x17 - 1280x768@60Hz */ 273 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 274 1472, 1664, 0, 768, 771, 778, 798, 0, 275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x18 - 1280x768@75Hz */ 277 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 278 1488, 1696, 0, 768, 771, 778, 805, 0, 279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x19 - 1280x768@85Hz */ 281 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 282 1496, 1712, 0, 768, 771, 778, 809, 0, 283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 284 /* 0x1a - 1280x768@120Hz RB */ 285 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 286 1360, 1440, 0, 768, 771, 778, 813, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 288 /* 0x1b - 1280x800@60Hz RB */ 289 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 290 1360, 1440, 0, 800, 803, 809, 823, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 292 /* 0x1c - 1280x800@60Hz */ 293 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 294 1480, 1680, 0, 800, 803, 809, 831, 0, 295 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 296 /* 0x1d - 1280x800@75Hz */ 297 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 298 1488, 1696, 0, 800, 803, 809, 838, 0, 299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x1e - 1280x800@85Hz */ 301 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 302 1496, 1712, 0, 800, 803, 809, 843, 0, 303 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 304 /* 0x1f - 1280x800@120Hz RB */ 305 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 306 1360, 1440, 0, 800, 803, 809, 847, 0, 307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 308 /* 0x20 - 1280x960@60Hz */ 309 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 310 1488, 1800, 0, 960, 961, 964, 1000, 0, 311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 312 /* 0x21 - 1280x960@85Hz */ 313 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 314 1504, 1728, 0, 960, 961, 964, 1011, 0, 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 316 /* 0x22 - 1280x960@120Hz RB */ 317 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 318 1360, 1440, 0, 960, 963, 967, 1017, 0, 319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 320 /* 0x23 - 1280x1024@60Hz */ 321 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 322 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 324 /* 0x24 - 1280x1024@75Hz */ 325 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 326 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 328 /* 0x25 - 1280x1024@85Hz */ 329 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 330 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 332 /* 0x26 - 1280x1024@120Hz RB */ 333 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 334 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 336 /* 0x27 - 1360x768@60Hz */ 337 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 338 1536, 1792, 0, 768, 771, 777, 795, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 340 /* 0x28 - 1360x768@120Hz RB */ 341 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 342 1440, 1520, 0, 768, 771, 776, 813, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 344 /* 0x51 - 1366x768@60Hz */ 345 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 346 1579, 1792, 0, 768, 771, 774, 798, 0, 347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 348 /* 0x56 - 1366x768@60Hz */ 349 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 350 1436, 1500, 0, 768, 769, 772, 800, 0, 351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 352 /* 0x29 - 1400x1050@60Hz RB */ 353 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 354 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 356 /* 0x2a - 1400x1050@60Hz */ 357 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 358 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 359 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 360 /* 0x2b - 1400x1050@75Hz */ 361 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 362 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 364 /* 0x2c - 1400x1050@85Hz */ 365 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 366 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 368 /* 0x2d - 1400x1050@120Hz RB */ 369 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 370 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 372 /* 0x2e - 1440x900@60Hz RB */ 373 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 374 1520, 1600, 0, 900, 903, 909, 926, 0, 375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 376 /* 0x2f - 1440x900@60Hz */ 377 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 378 1672, 1904, 0, 900, 903, 909, 934, 0, 379 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 380 /* 0x30 - 1440x900@75Hz */ 381 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 382 1688, 1936, 0, 900, 903, 909, 942, 0, 383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x31 - 1440x900@85Hz */ 385 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 386 1696, 1952, 0, 900, 903, 909, 948, 0, 387 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 388 /* 0x32 - 1440x900@120Hz RB */ 389 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 390 1520, 1600, 0, 900, 903, 909, 953, 0, 391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 392 /* 0x53 - 1600x900@60Hz */ 393 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 394 1704, 1800, 0, 900, 901, 904, 1000, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 396 /* 0x33 - 1600x1200@60Hz */ 397 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 398 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 400 /* 0x34 - 1600x1200@65Hz */ 401 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 402 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 404 /* 0x35 - 1600x1200@70Hz */ 405 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 406 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 408 /* 0x36 - 1600x1200@75Hz */ 409 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 410 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 412 /* 0x37 - 1600x1200@85Hz */ 413 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 414 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 416 /* 0x38 - 1600x1200@120Hz RB */ 417 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 418 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 420 /* 0x39 - 1680x1050@60Hz RB */ 421 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 422 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 424 /* 0x3a - 1680x1050@60Hz */ 425 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 426 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 428 /* 0x3b - 1680x1050@75Hz */ 429 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 430 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 0x3c - 1680x1050@85Hz */ 433 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 434 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 436 /* 0x3d - 1680x1050@120Hz RB */ 437 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 438 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 440 /* 0x3e - 1792x1344@60Hz */ 441 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 442 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 444 /* 0x3f - 1792x1344@75Hz */ 445 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 446 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 448 /* 0x40 - 1792x1344@120Hz RB */ 449 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 450 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 452 /* 0x41 - 1856x1392@60Hz */ 453 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 454 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 456 /* 0x42 - 1856x1392@75Hz */ 457 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 458 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 459 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 460 /* 0x43 - 1856x1392@120Hz RB */ 461 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 462 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 464 /* 0x52 - 1920x1080@60Hz */ 465 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 466 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 468 /* 0x44 - 1920x1200@60Hz RB */ 469 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 470 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 472 /* 0x45 - 1920x1200@60Hz */ 473 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 474 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 475 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 476 /* 0x46 - 1920x1200@75Hz */ 477 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 478 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 480 /* 0x47 - 1920x1200@85Hz */ 481 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 482 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 483 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 484 /* 0x48 - 1920x1200@120Hz RB */ 485 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 486 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 488 /* 0x49 - 1920x1440@60Hz */ 489 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 490 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 492 /* 0x4a - 1920x1440@75Hz */ 493 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 494 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 496 /* 0x4b - 1920x1440@120Hz RB */ 497 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 498 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 500 /* 0x54 - 2048x1152@60Hz */ 501 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 502 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 504 /* 0x4c - 2560x1600@60Hz RB */ 505 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 506 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 508 /* 0x4d - 2560x1600@60Hz */ 509 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 510 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 512 /* 0x4e - 2560x1600@75Hz */ 513 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 514 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 516 /* 0x4f - 2560x1600@85Hz */ 517 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 518 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 519 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 520 /* 0x50 - 2560x1600@120Hz RB */ 521 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 522 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 524 /* 0x57 - 4096x2160@60Hz RB */ 525 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 526 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 528 /* 0x58 - 4096x2160@59.94Hz RB */ 529 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 530 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 532 }; 533 534 /* 535 * These more or less come from the DMT spec. The 720x400 modes are 536 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 537 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 538 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 539 * mode. 540 * 541 * The DMT modes have been fact-checked; the rest are mild guesses. 542 */ 543 static const struct drm_display_mode edid_est_modes[] = { 544 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 545 968, 1056, 0, 600, 601, 605, 628, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 547 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 548 896, 1024, 0, 600, 601, 603, 625, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 550 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 551 720, 840, 0, 480, 481, 484, 500, 0, 552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 553 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 554 704, 832, 0, 480, 489, 491, 520, 0, 555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 556 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 557 768, 864, 0, 480, 483, 486, 525, 0, 558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 559 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 560 752, 800, 0, 480, 490, 492, 525, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 562 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 563 846, 900, 0, 400, 421, 423, 449, 0, 564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 565 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 566 846, 900, 0, 400, 412, 414, 449, 0, 567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 568 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 569 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 571 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 572 1136, 1312, 0, 768, 769, 772, 800, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 574 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 575 1184, 1328, 0, 768, 771, 777, 806, 0, 576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 577 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 578 1184, 1344, 0, 768, 771, 777, 806, 0, 579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 580 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 581 1208, 1264, 0, 768, 768, 776, 817, 0, 582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 583 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 584 928, 1152, 0, 624, 625, 628, 667, 0, 585 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 586 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 587 896, 1056, 0, 600, 601, 604, 625, 0, 588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 590 976, 1040, 0, 600, 637, 643, 666, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 592 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 593 1344, 1600, 0, 864, 865, 868, 900, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 595 }; 596 597 struct minimode { 598 short w; 599 short h; 600 short r; 601 short rb; 602 }; 603 604 static const struct minimode est3_modes[] = { 605 /* byte 6 */ 606 { 640, 350, 85, 0 }, 607 { 640, 400, 85, 0 }, 608 { 720, 400, 85, 0 }, 609 { 640, 480, 85, 0 }, 610 { 848, 480, 60, 0 }, 611 { 800, 600, 85, 0 }, 612 { 1024, 768, 85, 0 }, 613 { 1152, 864, 75, 0 }, 614 /* byte 7 */ 615 { 1280, 768, 60, 1 }, 616 { 1280, 768, 60, 0 }, 617 { 1280, 768, 75, 0 }, 618 { 1280, 768, 85, 0 }, 619 { 1280, 960, 60, 0 }, 620 { 1280, 960, 85, 0 }, 621 { 1280, 1024, 60, 0 }, 622 { 1280, 1024, 85, 0 }, 623 /* byte 8 */ 624 { 1360, 768, 60, 0 }, 625 { 1440, 900, 60, 1 }, 626 { 1440, 900, 60, 0 }, 627 { 1440, 900, 75, 0 }, 628 { 1440, 900, 85, 0 }, 629 { 1400, 1050, 60, 1 }, 630 { 1400, 1050, 60, 0 }, 631 { 1400, 1050, 75, 0 }, 632 /* byte 9 */ 633 { 1400, 1050, 85, 0 }, 634 { 1680, 1050, 60, 1 }, 635 { 1680, 1050, 60, 0 }, 636 { 1680, 1050, 75, 0 }, 637 { 1680, 1050, 85, 0 }, 638 { 1600, 1200, 60, 0 }, 639 { 1600, 1200, 65, 0 }, 640 { 1600, 1200, 70, 0 }, 641 /* byte 10 */ 642 { 1600, 1200, 75, 0 }, 643 { 1600, 1200, 85, 0 }, 644 { 1792, 1344, 60, 0 }, 645 { 1792, 1344, 75, 0 }, 646 { 1856, 1392, 60, 0 }, 647 { 1856, 1392, 75, 0 }, 648 { 1920, 1200, 60, 1 }, 649 { 1920, 1200, 60, 0 }, 650 /* byte 11 */ 651 { 1920, 1200, 75, 0 }, 652 { 1920, 1200, 85, 0 }, 653 { 1920, 1440, 60, 0 }, 654 { 1920, 1440, 75, 0 }, 655 }; 656 657 static const struct minimode extra_modes[] = { 658 { 1024, 576, 60, 0 }, 659 { 1366, 768, 60, 0 }, 660 { 1600, 900, 60, 0 }, 661 { 1680, 945, 60, 0 }, 662 { 1920, 1080, 60, 0 }, 663 { 2048, 1152, 60, 0 }, 664 { 2048, 1536, 60, 0 }, 665 }; 666 667 /* 668 * Probably taken from CEA-861 spec. 669 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 670 */ 671 static const struct drm_display_mode edid_cea_modes[] = { 672 /* 1 - 640x480@60Hz */ 673 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 674 752, 800, 0, 480, 490, 492, 525, 0, 675 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 676 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 677 /* 2 - 720x480@60Hz */ 678 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 679 798, 858, 0, 480, 489, 495, 525, 0, 680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 681 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 682 /* 3 - 720x480@60Hz */ 683 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 684 798, 858, 0, 480, 489, 495, 525, 0, 685 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 687 /* 4 - 1280x720@60Hz */ 688 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 689 1430, 1650, 0, 720, 725, 730, 750, 0, 690 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 692 /* 5 - 1920x1080i@60Hz */ 693 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 694 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 696 DRM_MODE_FLAG_INTERLACE), 697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 698 /* 6 - 720(1440)x480i@60Hz */ 699 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 700 801, 858, 0, 480, 488, 494, 525, 0, 701 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 702 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 703 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 704 /* 7 - 720(1440)x480i@60Hz */ 705 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 706 801, 858, 0, 480, 488, 494, 525, 0, 707 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 708 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 710 /* 8 - 720(1440)x240@60Hz */ 711 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 712 801, 858, 0, 240, 244, 247, 262, 0, 713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 714 DRM_MODE_FLAG_DBLCLK), 715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 716 /* 9 - 720(1440)x240@60Hz */ 717 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 718 801, 858, 0, 240, 244, 247, 262, 0, 719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 720 DRM_MODE_FLAG_DBLCLK), 721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 722 /* 10 - 2880x480i@60Hz */ 723 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 724 3204, 3432, 0, 480, 488, 494, 525, 0, 725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 726 DRM_MODE_FLAG_INTERLACE), 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 728 /* 11 - 2880x480i@60Hz */ 729 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 730 3204, 3432, 0, 480, 488, 494, 525, 0, 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 732 DRM_MODE_FLAG_INTERLACE), 733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 12 - 2880x240@60Hz */ 735 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 736 3204, 3432, 0, 240, 244, 247, 262, 0, 737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 738 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 739 /* 13 - 2880x240@60Hz */ 740 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 741 3204, 3432, 0, 240, 244, 247, 262, 0, 742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 744 /* 14 - 1440x480@60Hz */ 745 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 746 1596, 1716, 0, 480, 489, 495, 525, 0, 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 748 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 749 /* 15 - 1440x480@60Hz */ 750 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 751 1596, 1716, 0, 480, 489, 495, 525, 0, 752 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 753 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 754 /* 16 - 1920x1080@60Hz */ 755 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 756 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 759 /* 17 - 720x576@50Hz */ 760 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 761 796, 864, 0, 576, 581, 586, 625, 0, 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 763 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 764 /* 18 - 720x576@50Hz */ 765 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 766 796, 864, 0, 576, 581, 586, 625, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 19 - 1280x720@50Hz */ 770 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 771 1760, 1980, 0, 720, 725, 730, 750, 0, 772 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 774 /* 20 - 1920x1080i@50Hz */ 775 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 776 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 777 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 778 DRM_MODE_FLAG_INTERLACE), 779 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 780 /* 21 - 720(1440)x576i@50Hz */ 781 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 782 795, 864, 0, 576, 580, 586, 625, 0, 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 784 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 785 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 786 /* 22 - 720(1440)x576i@50Hz */ 787 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 788 795, 864, 0, 576, 580, 586, 625, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 790 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 792 /* 23 - 720(1440)x288@50Hz */ 793 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 794 795, 864, 0, 288, 290, 293, 312, 0, 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 796 DRM_MODE_FLAG_DBLCLK), 797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 798 /* 24 - 720(1440)x288@50Hz */ 799 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 800 795, 864, 0, 288, 290, 293, 312, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 802 DRM_MODE_FLAG_DBLCLK), 803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 804 /* 25 - 2880x576i@50Hz */ 805 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 806 3180, 3456, 0, 576, 580, 586, 625, 0, 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 808 DRM_MODE_FLAG_INTERLACE), 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 810 /* 26 - 2880x576i@50Hz */ 811 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 812 3180, 3456, 0, 576, 580, 586, 625, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 814 DRM_MODE_FLAG_INTERLACE), 815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 27 - 2880x288@50Hz */ 817 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 818 3180, 3456, 0, 288, 290, 293, 312, 0, 819 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 821 /* 28 - 2880x288@50Hz */ 822 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 823 3180, 3456, 0, 288, 290, 293, 312, 0, 824 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 826 /* 29 - 1440x576@50Hz */ 827 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 828 1592, 1728, 0, 576, 581, 586, 625, 0, 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 830 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 831 /* 30 - 1440x576@50Hz */ 832 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 833 1592, 1728, 0, 576, 581, 586, 625, 0, 834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 835 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 836 /* 31 - 1920x1080@50Hz */ 837 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 838 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 841 /* 32 - 1920x1080@24Hz */ 842 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 843 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 845 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 846 /* 33 - 1920x1080@25Hz */ 847 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 848 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 850 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 34 - 1920x1080@30Hz */ 852 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 853 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 855 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 856 /* 35 - 2880x480@60Hz */ 857 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 858 3192, 3432, 0, 480, 489, 495, 525, 0, 859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 860 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 861 /* 36 - 2880x480@60Hz */ 862 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 863 3192, 3432, 0, 480, 489, 495, 525, 0, 864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 865 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 866 /* 37 - 2880x576@50Hz */ 867 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 868 3184, 3456, 0, 576, 581, 586, 625, 0, 869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 870 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 871 /* 38 - 2880x576@50Hz */ 872 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 873 3184, 3456, 0, 576, 581, 586, 625, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 875 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 876 /* 39 - 1920x1080i@50Hz */ 877 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 878 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 880 DRM_MODE_FLAG_INTERLACE), 881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 40 - 1920x1080i@100Hz */ 883 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 884 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 886 DRM_MODE_FLAG_INTERLACE), 887 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 41 - 1280x720@100Hz */ 889 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 890 1760, 1980, 0, 720, 725, 730, 750, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 892 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 893 /* 42 - 720x576@100Hz */ 894 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 895 796, 864, 0, 576, 581, 586, 625, 0, 896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 897 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 898 /* 43 - 720x576@100Hz */ 899 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 900 796, 864, 0, 576, 581, 586, 625, 0, 901 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 902 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 44 - 720(1440)x576i@100Hz */ 904 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 905 795, 864, 0, 576, 580, 586, 625, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 907 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 908 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 909 /* 45 - 720(1440)x576i@100Hz */ 910 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 911 795, 864, 0, 576, 580, 586, 625, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 913 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 914 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 915 /* 46 - 1920x1080i@120Hz */ 916 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 917 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 919 DRM_MODE_FLAG_INTERLACE), 920 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 921 /* 47 - 1280x720@120Hz */ 922 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 923 1430, 1650, 0, 720, 725, 730, 750, 0, 924 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 925 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 926 /* 48 - 720x480@120Hz */ 927 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 928 798, 858, 0, 480, 489, 495, 525, 0, 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 930 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 931 /* 49 - 720x480@120Hz */ 932 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 933 798, 858, 0, 480, 489, 495, 525, 0, 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 935 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 936 /* 50 - 720(1440)x480i@120Hz */ 937 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 938 801, 858, 0, 480, 488, 494, 525, 0, 939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 940 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 941 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 942 /* 51 - 720(1440)x480i@120Hz */ 943 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 944 801, 858, 0, 480, 488, 494, 525, 0, 945 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 946 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 947 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 52 - 720x576@200Hz */ 949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 950 796, 864, 0, 576, 581, 586, 625, 0, 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 952 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 953 /* 53 - 720x576@200Hz */ 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 955 796, 864, 0, 576, 581, 586, 625, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 957 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 958 /* 54 - 720(1440)x576i@200Hz */ 959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 960 795, 864, 0, 576, 580, 586, 625, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 963 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 964 /* 55 - 720(1440)x576i@200Hz */ 965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 966 795, 864, 0, 576, 580, 586, 625, 0, 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 969 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 970 /* 56 - 720x480@240Hz */ 971 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 972 798, 858, 0, 480, 489, 495, 525, 0, 973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 974 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 975 /* 57 - 720x480@240Hz */ 976 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 977 798, 858, 0, 480, 489, 495, 525, 0, 978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 979 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 980 /* 58 - 720(1440)x480i@240 */ 981 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 982 801, 858, 0, 480, 488, 494, 525, 0, 983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 984 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 985 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 986 /* 59 - 720(1440)x480i@240 */ 987 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 988 801, 858, 0, 480, 488, 494, 525, 0, 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 990 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 991 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 992 /* 60 - 1280x720@24Hz */ 993 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 994 3080, 3300, 0, 720, 725, 730, 750, 0, 995 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 996 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 997 /* 61 - 1280x720@25Hz */ 998 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 999 3740, 3960, 0, 720, 725, 730, 750, 0, 1000 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1001 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1002 /* 62 - 1280x720@30Hz */ 1003 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1004 3080, 3300, 0, 720, 725, 730, 750, 0, 1005 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1006 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1007 /* 63 - 1920x1080@120Hz */ 1008 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1009 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1010 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1011 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1012 /* 64 - 1920x1080@100Hz */ 1013 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1014 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 1015 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1016 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 }; 1018 1019 /* 1020 * HDMI 1.4 4k modes. 1021 */ 1022 static const struct drm_display_mode edid_4k_modes[] = { 1023 /* 1 - 3840x2160@30Hz */ 1024 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1025 3840, 4016, 4104, 4400, 0, 1026 2160, 2168, 2178, 2250, 0, 1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1028 .vrefresh = 30, }, 1029 /* 2 - 3840x2160@25Hz */ 1030 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1031 3840, 4896, 4984, 5280, 0, 1032 2160, 2168, 2178, 2250, 0, 1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1034 .vrefresh = 25, }, 1035 /* 3 - 3840x2160@24Hz */ 1036 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1037 3840, 5116, 5204, 5500, 0, 1038 2160, 2168, 2178, 2250, 0, 1039 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1040 .vrefresh = 24, }, 1041 /* 4 - 4096x2160@24Hz (SMPTE) */ 1042 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1043 4096, 5116, 5204, 5500, 0, 1044 2160, 2168, 2178, 2250, 0, 1045 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1046 .vrefresh = 24, }, 1047 }; 1048 1049 /*** DDC fetch and block validation ***/ 1050 1051 static const u8 edid_header[] = { 1052 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1053 }; 1054 1055 /** 1056 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1057 * @raw_edid: pointer to raw base EDID block 1058 * 1059 * Sanity check the header of the base EDID block. 1060 * 1061 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1062 */ 1063 int drm_edid_header_is_valid(const u8 *raw_edid) 1064 { 1065 int i, score = 0; 1066 1067 for (i = 0; i < sizeof(edid_header); i++) 1068 if (raw_edid[i] == edid_header[i]) 1069 score++; 1070 1071 return score; 1072 } 1073 EXPORT_SYMBOL(drm_edid_header_is_valid); 1074 1075 static int edid_fixup __read_mostly = 6; 1076 module_param_named(edid_fixup, edid_fixup, int, 0400); 1077 MODULE_PARM_DESC(edid_fixup, 1078 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1079 1080 static void drm_get_displayid(struct drm_connector *connector, 1081 struct edid *edid); 1082 1083 static int drm_edid_block_checksum(const u8 *raw_edid) 1084 { 1085 int i; 1086 u8 csum = 0; 1087 for (i = 0; i < EDID_LENGTH; i++) 1088 csum += raw_edid[i]; 1089 1090 return csum; 1091 } 1092 1093 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1094 { 1095 if (memchr_inv(in_edid, 0, length)) 1096 return false; 1097 1098 return true; 1099 } 1100 1101 /** 1102 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1103 * @raw_edid: pointer to raw EDID block 1104 * @block: type of block to validate (0 for base, extension otherwise) 1105 * @print_bad_edid: if true, dump bad EDID blocks to the console 1106 * @edid_corrupt: if true, the header or checksum is invalid 1107 * 1108 * Validate a base or extension EDID block and optionally dump bad blocks to 1109 * the console. 1110 * 1111 * Return: True if the block is valid, false otherwise. 1112 */ 1113 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1114 bool *edid_corrupt) 1115 { 1116 u8 csum; 1117 struct edid *edid = (struct edid *)raw_edid; 1118 1119 if (WARN_ON(!raw_edid)) 1120 return false; 1121 1122 if (edid_fixup > 8 || edid_fixup < 0) 1123 edid_fixup = 6; 1124 1125 if (block == 0) { 1126 int score = drm_edid_header_is_valid(raw_edid); 1127 if (score == 8) { 1128 if (edid_corrupt) 1129 *edid_corrupt = false; 1130 } else if (score >= edid_fixup) { 1131 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1132 * The corrupt flag needs to be set here otherwise, the 1133 * fix-up code here will correct the problem, the 1134 * checksum is correct and the test fails 1135 */ 1136 if (edid_corrupt) 1137 *edid_corrupt = true; 1138 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1139 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1140 } else { 1141 if (edid_corrupt) 1142 *edid_corrupt = true; 1143 goto bad; 1144 } 1145 } 1146 1147 csum = drm_edid_block_checksum(raw_edid); 1148 if (csum) { 1149 if (print_bad_edid) { 1150 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1151 } 1152 1153 if (edid_corrupt) 1154 *edid_corrupt = true; 1155 1156 /* allow CEA to slide through, switches mangle this */ 1157 if (raw_edid[0] != 0x02) 1158 goto bad; 1159 } 1160 1161 /* per-block-type checks */ 1162 switch (raw_edid[0]) { 1163 case 0: /* base */ 1164 if (edid->version != 1) { 1165 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1166 goto bad; 1167 } 1168 1169 if (edid->revision > 4) 1170 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1171 break; 1172 1173 default: 1174 break; 1175 } 1176 1177 return true; 1178 1179 bad: 1180 if (print_bad_edid) { 1181 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1182 printk(KERN_ERR "EDID block is all zeroes\n"); 1183 } else { 1184 printk(KERN_ERR "Raw EDID:\n"); 1185 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1186 raw_edid, EDID_LENGTH, false); 1187 } 1188 } 1189 return false; 1190 } 1191 EXPORT_SYMBOL(drm_edid_block_valid); 1192 1193 /** 1194 * drm_edid_is_valid - sanity check EDID data 1195 * @edid: EDID data 1196 * 1197 * Sanity-check an entire EDID record (including extensions) 1198 * 1199 * Return: True if the EDID data is valid, false otherwise. 1200 */ 1201 bool drm_edid_is_valid(struct edid *edid) 1202 { 1203 int i; 1204 u8 *raw = (u8 *)edid; 1205 1206 if (!edid) 1207 return false; 1208 1209 for (i = 0; i <= edid->extensions; i++) 1210 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1211 return false; 1212 1213 return true; 1214 } 1215 EXPORT_SYMBOL(drm_edid_is_valid); 1216 1217 #define DDC_SEGMENT_ADDR 0x30 1218 /** 1219 * drm_do_probe_ddc_edid() - get EDID information via I2C 1220 * @data: I2C device adapter 1221 * @buf: EDID data buffer to be filled 1222 * @block: 128 byte EDID block to start fetching from 1223 * @len: EDID data buffer length to fetch 1224 * 1225 * Try to fetch EDID information by calling I2C driver functions. 1226 * 1227 * Return: 0 on success or -1 on failure. 1228 */ 1229 static int 1230 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1231 { 1232 struct i2c_adapter *adapter = data; 1233 unsigned char start = block * EDID_LENGTH; 1234 unsigned char segment = block >> 1; 1235 unsigned char xfers = segment ? 3 : 2; 1236 int ret, retries = 5; 1237 1238 /* 1239 * The core I2C driver will automatically retry the transfer if the 1240 * adapter reports EAGAIN. However, we find that bit-banging transfers 1241 * are susceptible to errors under a heavily loaded machine and 1242 * generate spurious NAKs and timeouts. Retrying the transfer 1243 * of the individual block a few times seems to overcome this. 1244 */ 1245 do { 1246 struct i2c_msg msgs[] = { 1247 { 1248 .addr = DDC_SEGMENT_ADDR, 1249 .flags = 0, 1250 .len = 1, 1251 .buf = &segment, 1252 }, { 1253 .addr = DDC_ADDR, 1254 .flags = 0, 1255 .len = 1, 1256 .buf = &start, 1257 }, { 1258 .addr = DDC_ADDR, 1259 .flags = I2C_M_RD, 1260 .len = len, 1261 .buf = buf, 1262 } 1263 }; 1264 1265 /* 1266 * Avoid sending the segment addr to not upset non-compliant 1267 * DDC monitors. 1268 */ 1269 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1270 1271 if (ret == -ENXIO) { 1272 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1273 adapter->name); 1274 break; 1275 } 1276 } while (ret != xfers && --retries); 1277 1278 return ret == xfers ? 0 : -1; 1279 } 1280 1281 /** 1282 * drm_do_get_edid - get EDID data using a custom EDID block read function 1283 * @connector: connector we're probing 1284 * @get_edid_block: EDID block read function 1285 * @data: private data passed to the block read function 1286 * 1287 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1288 * exposes a different interface to read EDID blocks this function can be used 1289 * to get EDID data using a custom block read function. 1290 * 1291 * As in the general case the DDC bus is accessible by the kernel at the I2C 1292 * level, drivers must make all reasonable efforts to expose it as an I2C 1293 * adapter and use drm_get_edid() instead of abusing this function. 1294 * 1295 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1296 */ 1297 struct edid *drm_do_get_edid(struct drm_connector *connector, 1298 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1299 size_t len), 1300 void *data) 1301 { 1302 int i, j = 0, valid_extensions = 0; 1303 u8 *block, *new; 1304 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1305 1306 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1307 return NULL; 1308 1309 /* base block fetch */ 1310 for (i = 0; i < 4; i++) { 1311 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1312 goto out; 1313 if (drm_edid_block_valid(block, 0, print_bad_edid, 1314 &connector->edid_corrupt)) 1315 break; 1316 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1317 connector->null_edid_counter++; 1318 goto carp; 1319 } 1320 } 1321 if (i == 4) 1322 goto carp; 1323 1324 /* if there's no extensions, we're done */ 1325 if (block[0x7e] == 0) 1326 return (struct edid *)block; 1327 1328 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1329 if (!new) 1330 goto out; 1331 block = new; 1332 1333 for (j = 1; j <= block[0x7e]; j++) { 1334 for (i = 0; i < 4; i++) { 1335 if (get_edid_block(data, 1336 block + (valid_extensions + 1) * EDID_LENGTH, 1337 j, EDID_LENGTH)) 1338 goto out; 1339 if (drm_edid_block_valid(block + (valid_extensions + 1) 1340 * EDID_LENGTH, j, 1341 print_bad_edid, 1342 NULL)) { 1343 valid_extensions++; 1344 break; 1345 } 1346 } 1347 1348 if (i == 4 && print_bad_edid) { 1349 dev_warn(connector->dev->dev, 1350 "%s: Ignoring invalid EDID block %d.\n", 1351 connector->name, j); 1352 1353 connector->bad_edid_counter++; 1354 } 1355 } 1356 1357 if (valid_extensions != block[0x7e]) { 1358 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1359 block[0x7e] = valid_extensions; 1360 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1361 if (!new) 1362 goto out; 1363 block = new; 1364 } 1365 1366 return (struct edid *)block; 1367 1368 carp: 1369 if (print_bad_edid) { 1370 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1371 connector->name, j); 1372 } 1373 connector->bad_edid_counter++; 1374 1375 out: 1376 kfree(block); 1377 return NULL; 1378 } 1379 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1380 1381 /** 1382 * drm_probe_ddc() - probe DDC presence 1383 * @adapter: I2C adapter to probe 1384 * 1385 * Return: True on success, false on failure. 1386 */ 1387 bool 1388 drm_probe_ddc(struct i2c_adapter *adapter) 1389 { 1390 unsigned char out; 1391 1392 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1393 } 1394 EXPORT_SYMBOL(drm_probe_ddc); 1395 1396 /** 1397 * drm_get_edid - get EDID data, if available 1398 * @connector: connector we're probing 1399 * @adapter: I2C adapter to use for DDC 1400 * 1401 * Poke the given I2C channel to grab EDID data if possible. If found, 1402 * attach it to the connector. 1403 * 1404 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1405 */ 1406 struct edid *drm_get_edid(struct drm_connector *connector, 1407 struct i2c_adapter *adapter) 1408 { 1409 struct edid *edid; 1410 1411 if (!drm_probe_ddc(adapter)) 1412 return NULL; 1413 1414 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1415 if (edid) 1416 drm_get_displayid(connector, edid); 1417 return edid; 1418 } 1419 EXPORT_SYMBOL(drm_get_edid); 1420 1421 /** 1422 * drm_edid_duplicate - duplicate an EDID and the extensions 1423 * @edid: EDID to duplicate 1424 * 1425 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1426 */ 1427 struct edid *drm_edid_duplicate(const struct edid *edid) 1428 { 1429 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1430 } 1431 EXPORT_SYMBOL(drm_edid_duplicate); 1432 1433 /*** EDID parsing ***/ 1434 1435 /** 1436 * edid_vendor - match a string against EDID's obfuscated vendor field 1437 * @edid: EDID to match 1438 * @vendor: vendor string 1439 * 1440 * Returns true if @vendor is in @edid, false otherwise 1441 */ 1442 static bool edid_vendor(struct edid *edid, char *vendor) 1443 { 1444 char edid_vendor[3]; 1445 1446 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1447 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1448 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1449 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1450 1451 return !strncmp(edid_vendor, vendor, 3); 1452 } 1453 1454 /** 1455 * edid_get_quirks - return quirk flags for a given EDID 1456 * @edid: EDID to process 1457 * 1458 * This tells subsequent routines what fixes they need to apply. 1459 */ 1460 static u32 edid_get_quirks(struct edid *edid) 1461 { 1462 struct edid_quirk *quirk; 1463 int i; 1464 1465 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1466 quirk = &edid_quirk_list[i]; 1467 1468 if (edid_vendor(edid, quirk->vendor) && 1469 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1470 return quirk->quirks; 1471 } 1472 1473 return 0; 1474 } 1475 1476 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1477 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1478 1479 /** 1480 * edid_fixup_preferred - set preferred modes based on quirk list 1481 * @connector: has mode list to fix up 1482 * @quirks: quirks list 1483 * 1484 * Walk the mode list for @connector, clearing the preferred status 1485 * on existing modes and setting it anew for the right mode ala @quirks. 1486 */ 1487 static void edid_fixup_preferred(struct drm_connector *connector, 1488 u32 quirks) 1489 { 1490 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1491 int target_refresh = 0; 1492 int cur_vrefresh, preferred_vrefresh; 1493 1494 if (list_empty(&connector->probed_modes)) 1495 return; 1496 1497 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1498 target_refresh = 60; 1499 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1500 target_refresh = 75; 1501 1502 preferred_mode = list_first_entry(&connector->probed_modes, 1503 struct drm_display_mode, head); 1504 1505 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1506 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1507 1508 if (cur_mode == preferred_mode) 1509 continue; 1510 1511 /* Largest mode is preferred */ 1512 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1513 preferred_mode = cur_mode; 1514 1515 cur_vrefresh = cur_mode->vrefresh ? 1516 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1517 preferred_vrefresh = preferred_mode->vrefresh ? 1518 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1519 /* At a given size, try to get closest to target refresh */ 1520 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1521 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1522 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1523 preferred_mode = cur_mode; 1524 } 1525 } 1526 1527 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1528 } 1529 1530 static bool 1531 mode_is_rb(const struct drm_display_mode *mode) 1532 { 1533 return (mode->htotal - mode->hdisplay == 160) && 1534 (mode->hsync_end - mode->hdisplay == 80) && 1535 (mode->hsync_end - mode->hsync_start == 32) && 1536 (mode->vsync_start - mode->vdisplay == 3); 1537 } 1538 1539 /* 1540 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1541 * @dev: Device to duplicate against 1542 * @hsize: Mode width 1543 * @vsize: Mode height 1544 * @fresh: Mode refresh rate 1545 * @rb: Mode reduced-blanking-ness 1546 * 1547 * Walk the DMT mode list looking for a match for the given parameters. 1548 * 1549 * Return: A newly allocated copy of the mode, or NULL if not found. 1550 */ 1551 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1552 int hsize, int vsize, int fresh, 1553 bool rb) 1554 { 1555 int i; 1556 1557 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1558 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1559 if (hsize != ptr->hdisplay) 1560 continue; 1561 if (vsize != ptr->vdisplay) 1562 continue; 1563 if (fresh != drm_mode_vrefresh(ptr)) 1564 continue; 1565 if (rb != mode_is_rb(ptr)) 1566 continue; 1567 1568 return drm_mode_duplicate(dev, ptr); 1569 } 1570 1571 return NULL; 1572 } 1573 EXPORT_SYMBOL(drm_mode_find_dmt); 1574 1575 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1576 1577 static void 1578 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1579 { 1580 int i, n = 0; 1581 u8 d = ext[0x02]; 1582 u8 *det_base = ext + d; 1583 1584 n = (127 - d) / 18; 1585 for (i = 0; i < n; i++) 1586 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1587 } 1588 1589 static void 1590 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1591 { 1592 unsigned int i, n = min((int)ext[0x02], 6); 1593 u8 *det_base = ext + 5; 1594 1595 if (ext[0x01] != 1) 1596 return; /* unknown version */ 1597 1598 for (i = 0; i < n; i++) 1599 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1600 } 1601 1602 static void 1603 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1604 { 1605 int i; 1606 struct edid *edid = (struct edid *)raw_edid; 1607 1608 if (edid == NULL) 1609 return; 1610 1611 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1612 cb(&(edid->detailed_timings[i]), closure); 1613 1614 for (i = 1; i <= raw_edid[0x7e]; i++) { 1615 u8 *ext = raw_edid + (i * EDID_LENGTH); 1616 switch (*ext) { 1617 case CEA_EXT: 1618 cea_for_each_detailed_block(ext, cb, closure); 1619 break; 1620 case VTB_EXT: 1621 vtb_for_each_detailed_block(ext, cb, closure); 1622 break; 1623 default: 1624 break; 1625 } 1626 } 1627 } 1628 1629 static void 1630 is_rb(struct detailed_timing *t, void *data) 1631 { 1632 u8 *r = (u8 *)t; 1633 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1634 if (r[15] & 0x10) 1635 *(bool *)data = true; 1636 } 1637 1638 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1639 static bool 1640 drm_monitor_supports_rb(struct edid *edid) 1641 { 1642 if (edid->revision >= 4) { 1643 bool ret = false; 1644 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1645 return ret; 1646 } 1647 1648 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1649 } 1650 1651 static void 1652 find_gtf2(struct detailed_timing *t, void *data) 1653 { 1654 u8 *r = (u8 *)t; 1655 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1656 *(u8 **)data = r; 1657 } 1658 1659 /* Secondary GTF curve kicks in above some break frequency */ 1660 static int 1661 drm_gtf2_hbreak(struct edid *edid) 1662 { 1663 u8 *r = NULL; 1664 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1665 return r ? (r[12] * 2) : 0; 1666 } 1667 1668 static int 1669 drm_gtf2_2c(struct edid *edid) 1670 { 1671 u8 *r = NULL; 1672 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1673 return r ? r[13] : 0; 1674 } 1675 1676 static int 1677 drm_gtf2_m(struct edid *edid) 1678 { 1679 u8 *r = NULL; 1680 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1681 return r ? (r[15] << 8) + r[14] : 0; 1682 } 1683 1684 static int 1685 drm_gtf2_k(struct edid *edid) 1686 { 1687 u8 *r = NULL; 1688 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1689 return r ? r[16] : 0; 1690 } 1691 1692 static int 1693 drm_gtf2_2j(struct edid *edid) 1694 { 1695 u8 *r = NULL; 1696 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1697 return r ? r[17] : 0; 1698 } 1699 1700 /** 1701 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1702 * @edid: EDID block to scan 1703 */ 1704 static int standard_timing_level(struct edid *edid) 1705 { 1706 if (edid->revision >= 2) { 1707 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1708 return LEVEL_CVT; 1709 if (drm_gtf2_hbreak(edid)) 1710 return LEVEL_GTF2; 1711 return LEVEL_GTF; 1712 } 1713 return LEVEL_DMT; 1714 } 1715 1716 /* 1717 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1718 * monitors fill with ascii space (0x20) instead. 1719 */ 1720 static int 1721 bad_std_timing(u8 a, u8 b) 1722 { 1723 return (a == 0x00 && b == 0x00) || 1724 (a == 0x01 && b == 0x01) || 1725 (a == 0x20 && b == 0x20); 1726 } 1727 1728 /** 1729 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1730 * @connector: connector of for the EDID block 1731 * @edid: EDID block to scan 1732 * @t: standard timing params 1733 * 1734 * Take the standard timing params (in this case width, aspect, and refresh) 1735 * and convert them into a real mode using CVT/GTF/DMT. 1736 */ 1737 static struct drm_display_mode * 1738 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1739 struct std_timing *t) 1740 { 1741 struct drm_device *dev = connector->dev; 1742 struct drm_display_mode *m, *mode = NULL; 1743 int hsize, vsize; 1744 int vrefresh_rate; 1745 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1746 >> EDID_TIMING_ASPECT_SHIFT; 1747 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1748 >> EDID_TIMING_VFREQ_SHIFT; 1749 int timing_level = standard_timing_level(edid); 1750 1751 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1752 return NULL; 1753 1754 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1755 hsize = t->hsize * 8 + 248; 1756 /* vrefresh_rate = vfreq + 60 */ 1757 vrefresh_rate = vfreq + 60; 1758 /* the vdisplay is calculated based on the aspect ratio */ 1759 if (aspect_ratio == 0) { 1760 if (edid->revision < 3) 1761 vsize = hsize; 1762 else 1763 vsize = (hsize * 10) / 16; 1764 } else if (aspect_ratio == 1) 1765 vsize = (hsize * 3) / 4; 1766 else if (aspect_ratio == 2) 1767 vsize = (hsize * 4) / 5; 1768 else 1769 vsize = (hsize * 9) / 16; 1770 1771 /* HDTV hack, part 1 */ 1772 if (vrefresh_rate == 60 && 1773 ((hsize == 1360 && vsize == 765) || 1774 (hsize == 1368 && vsize == 769))) { 1775 hsize = 1366; 1776 vsize = 768; 1777 } 1778 1779 /* 1780 * If this connector already has a mode for this size and refresh 1781 * rate (because it came from detailed or CVT info), use that 1782 * instead. This way we don't have to guess at interlace or 1783 * reduced blanking. 1784 */ 1785 list_for_each_entry(m, &connector->probed_modes, head) 1786 if (m->hdisplay == hsize && m->vdisplay == vsize && 1787 drm_mode_vrefresh(m) == vrefresh_rate) 1788 return NULL; 1789 1790 /* HDTV hack, part 2 */ 1791 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1792 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1793 false); 1794 mode->hdisplay = 1366; 1795 mode->hsync_start = mode->hsync_start - 1; 1796 mode->hsync_end = mode->hsync_end - 1; 1797 return mode; 1798 } 1799 1800 /* check whether it can be found in default mode table */ 1801 if (drm_monitor_supports_rb(edid)) { 1802 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1803 true); 1804 if (mode) 1805 return mode; 1806 } 1807 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1808 if (mode) 1809 return mode; 1810 1811 /* okay, generate it */ 1812 switch (timing_level) { 1813 case LEVEL_DMT: 1814 break; 1815 case LEVEL_GTF: 1816 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1817 break; 1818 case LEVEL_GTF2: 1819 /* 1820 * This is potentially wrong if there's ever a monitor with 1821 * more than one ranges section, each claiming a different 1822 * secondary GTF curve. Please don't do that. 1823 */ 1824 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1825 if (!mode) 1826 return NULL; 1827 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1828 drm_mode_destroy(dev, mode); 1829 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1830 vrefresh_rate, 0, 0, 1831 drm_gtf2_m(edid), 1832 drm_gtf2_2c(edid), 1833 drm_gtf2_k(edid), 1834 drm_gtf2_2j(edid)); 1835 } 1836 break; 1837 case LEVEL_CVT: 1838 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1839 false); 1840 break; 1841 } 1842 return mode; 1843 } 1844 1845 /* 1846 * EDID is delightfully ambiguous about how interlaced modes are to be 1847 * encoded. Our internal representation is of frame height, but some 1848 * HDTV detailed timings are encoded as field height. 1849 * 1850 * The format list here is from CEA, in frame size. Technically we 1851 * should be checking refresh rate too. Whatever. 1852 */ 1853 static void 1854 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1855 struct detailed_pixel_timing *pt) 1856 { 1857 int i; 1858 static const struct { 1859 int w, h; 1860 } cea_interlaced[] = { 1861 { 1920, 1080 }, 1862 { 720, 480 }, 1863 { 1440, 480 }, 1864 { 2880, 480 }, 1865 { 720, 576 }, 1866 { 1440, 576 }, 1867 { 2880, 576 }, 1868 }; 1869 1870 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1871 return; 1872 1873 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1874 if ((mode->hdisplay == cea_interlaced[i].w) && 1875 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1876 mode->vdisplay *= 2; 1877 mode->vsync_start *= 2; 1878 mode->vsync_end *= 2; 1879 mode->vtotal *= 2; 1880 mode->vtotal |= 1; 1881 } 1882 } 1883 1884 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1885 } 1886 1887 /** 1888 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1889 * @dev: DRM device (needed to create new mode) 1890 * @edid: EDID block 1891 * @timing: EDID detailed timing info 1892 * @quirks: quirks to apply 1893 * 1894 * An EDID detailed timing block contains enough info for us to create and 1895 * return a new struct drm_display_mode. 1896 */ 1897 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1898 struct edid *edid, 1899 struct detailed_timing *timing, 1900 u32 quirks) 1901 { 1902 struct drm_display_mode *mode; 1903 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1904 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1905 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1906 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1907 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1908 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1909 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1910 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1911 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1912 1913 /* ignore tiny modes */ 1914 if (hactive < 64 || vactive < 64) 1915 return NULL; 1916 1917 if (pt->misc & DRM_EDID_PT_STEREO) { 1918 DRM_DEBUG_KMS("stereo mode not supported\n"); 1919 return NULL; 1920 } 1921 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1922 DRM_DEBUG_KMS("composite sync not supported\n"); 1923 } 1924 1925 /* it is incorrect if hsync/vsync width is zero */ 1926 if (!hsync_pulse_width || !vsync_pulse_width) { 1927 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1928 "Wrong Hsync/Vsync pulse width\n"); 1929 return NULL; 1930 } 1931 1932 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1933 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1934 if (!mode) 1935 return NULL; 1936 1937 goto set_size; 1938 } 1939 1940 mode = drm_mode_create(dev); 1941 if (!mode) 1942 return NULL; 1943 1944 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1945 timing->pixel_clock = cpu_to_le16(1088); 1946 1947 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1948 1949 mode->hdisplay = hactive; 1950 mode->hsync_start = mode->hdisplay + hsync_offset; 1951 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1952 mode->htotal = mode->hdisplay + hblank; 1953 1954 mode->vdisplay = vactive; 1955 mode->vsync_start = mode->vdisplay + vsync_offset; 1956 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1957 mode->vtotal = mode->vdisplay + vblank; 1958 1959 /* Some EDIDs have bogus h/vtotal values */ 1960 if (mode->hsync_end > mode->htotal) 1961 mode->htotal = mode->hsync_end + 1; 1962 if (mode->vsync_end > mode->vtotal) 1963 mode->vtotal = mode->vsync_end + 1; 1964 1965 drm_mode_do_interlace_quirk(mode, pt); 1966 1967 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1968 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1969 } 1970 1971 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1972 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1973 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1974 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1975 1976 set_size: 1977 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1978 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1979 1980 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1981 mode->width_mm *= 10; 1982 mode->height_mm *= 10; 1983 } 1984 1985 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1986 mode->width_mm = edid->width_cm * 10; 1987 mode->height_mm = edid->height_cm * 10; 1988 } 1989 1990 mode->type = DRM_MODE_TYPE_DRIVER; 1991 mode->vrefresh = drm_mode_vrefresh(mode); 1992 drm_mode_set_name(mode); 1993 1994 return mode; 1995 } 1996 1997 static bool 1998 mode_in_hsync_range(const struct drm_display_mode *mode, 1999 struct edid *edid, u8 *t) 2000 { 2001 int hsync, hmin, hmax; 2002 2003 hmin = t[7]; 2004 if (edid->revision >= 4) 2005 hmin += ((t[4] & 0x04) ? 255 : 0); 2006 hmax = t[8]; 2007 if (edid->revision >= 4) 2008 hmax += ((t[4] & 0x08) ? 255 : 0); 2009 hsync = drm_mode_hsync(mode); 2010 2011 return (hsync <= hmax && hsync >= hmin); 2012 } 2013 2014 static bool 2015 mode_in_vsync_range(const struct drm_display_mode *mode, 2016 struct edid *edid, u8 *t) 2017 { 2018 int vsync, vmin, vmax; 2019 2020 vmin = t[5]; 2021 if (edid->revision >= 4) 2022 vmin += ((t[4] & 0x01) ? 255 : 0); 2023 vmax = t[6]; 2024 if (edid->revision >= 4) 2025 vmax += ((t[4] & 0x02) ? 255 : 0); 2026 vsync = drm_mode_vrefresh(mode); 2027 2028 return (vsync <= vmax && vsync >= vmin); 2029 } 2030 2031 static u32 2032 range_pixel_clock(struct edid *edid, u8 *t) 2033 { 2034 /* unspecified */ 2035 if (t[9] == 0 || t[9] == 255) 2036 return 0; 2037 2038 /* 1.4 with CVT support gives us real precision, yay */ 2039 if (edid->revision >= 4 && t[10] == 0x04) 2040 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2041 2042 /* 1.3 is pathetic, so fuzz up a bit */ 2043 return t[9] * 10000 + 5001; 2044 } 2045 2046 static bool 2047 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2048 struct detailed_timing *timing) 2049 { 2050 u32 max_clock; 2051 u8 *t = (u8 *)timing; 2052 2053 if (!mode_in_hsync_range(mode, edid, t)) 2054 return false; 2055 2056 if (!mode_in_vsync_range(mode, edid, t)) 2057 return false; 2058 2059 if ((max_clock = range_pixel_clock(edid, t))) 2060 if (mode->clock > max_clock) 2061 return false; 2062 2063 /* 1.4 max horizontal check */ 2064 if (edid->revision >= 4 && t[10] == 0x04) 2065 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2066 return false; 2067 2068 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2069 return false; 2070 2071 return true; 2072 } 2073 2074 static bool valid_inferred_mode(const struct drm_connector *connector, 2075 const struct drm_display_mode *mode) 2076 { 2077 const struct drm_display_mode *m; 2078 bool ok = false; 2079 2080 list_for_each_entry(m, &connector->probed_modes, head) { 2081 if (mode->hdisplay == m->hdisplay && 2082 mode->vdisplay == m->vdisplay && 2083 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2084 return false; /* duplicated */ 2085 if (mode->hdisplay <= m->hdisplay && 2086 mode->vdisplay <= m->vdisplay) 2087 ok = true; 2088 } 2089 return ok; 2090 } 2091 2092 static int 2093 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2094 struct detailed_timing *timing) 2095 { 2096 int i, modes = 0; 2097 struct drm_display_mode *newmode; 2098 struct drm_device *dev = connector->dev; 2099 2100 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2101 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2102 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2103 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2104 if (newmode) { 2105 drm_mode_probed_add(connector, newmode); 2106 modes++; 2107 } 2108 } 2109 } 2110 2111 return modes; 2112 } 2113 2114 /* fix up 1366x768 mode from 1368x768; 2115 * GFT/CVT can't express 1366 width which isn't dividable by 8 2116 */ 2117 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2118 { 2119 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2120 mode->hdisplay = 1366; 2121 mode->hsync_start--; 2122 mode->hsync_end--; 2123 drm_mode_set_name(mode); 2124 } 2125 } 2126 2127 static int 2128 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2129 struct detailed_timing *timing) 2130 { 2131 int i, modes = 0; 2132 struct drm_display_mode *newmode; 2133 struct drm_device *dev = connector->dev; 2134 2135 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2136 const struct minimode *m = &extra_modes[i]; 2137 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2138 if (!newmode) 2139 return modes; 2140 2141 fixup_mode_1366x768(newmode); 2142 if (!mode_in_range(newmode, edid, timing) || 2143 !valid_inferred_mode(connector, newmode)) { 2144 drm_mode_destroy(dev, newmode); 2145 continue; 2146 } 2147 2148 drm_mode_probed_add(connector, newmode); 2149 modes++; 2150 } 2151 2152 return modes; 2153 } 2154 2155 static int 2156 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2157 struct detailed_timing *timing) 2158 { 2159 int i, modes = 0; 2160 struct drm_display_mode *newmode; 2161 struct drm_device *dev = connector->dev; 2162 bool rb = drm_monitor_supports_rb(edid); 2163 2164 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2165 const struct minimode *m = &extra_modes[i]; 2166 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2167 if (!newmode) 2168 return modes; 2169 2170 fixup_mode_1366x768(newmode); 2171 if (!mode_in_range(newmode, edid, timing) || 2172 !valid_inferred_mode(connector, newmode)) { 2173 drm_mode_destroy(dev, newmode); 2174 continue; 2175 } 2176 2177 drm_mode_probed_add(connector, newmode); 2178 modes++; 2179 } 2180 2181 return modes; 2182 } 2183 2184 static void 2185 do_inferred_modes(struct detailed_timing *timing, void *c) 2186 { 2187 struct detailed_mode_closure *closure = c; 2188 struct detailed_non_pixel *data = &timing->data.other_data; 2189 struct detailed_data_monitor_range *range = &data->data.range; 2190 2191 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2192 return; 2193 2194 closure->modes += drm_dmt_modes_for_range(closure->connector, 2195 closure->edid, 2196 timing); 2197 2198 if (!version_greater(closure->edid, 1, 1)) 2199 return; /* GTF not defined yet */ 2200 2201 switch (range->flags) { 2202 case 0x02: /* secondary gtf, XXX could do more */ 2203 case 0x00: /* default gtf */ 2204 closure->modes += drm_gtf_modes_for_range(closure->connector, 2205 closure->edid, 2206 timing); 2207 break; 2208 case 0x04: /* cvt, only in 1.4+ */ 2209 if (!version_greater(closure->edid, 1, 3)) 2210 break; 2211 2212 closure->modes += drm_cvt_modes_for_range(closure->connector, 2213 closure->edid, 2214 timing); 2215 break; 2216 case 0x01: /* just the ranges, no formula */ 2217 default: 2218 break; 2219 } 2220 } 2221 2222 static int 2223 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2224 { 2225 struct detailed_mode_closure closure = { 2226 .connector = connector, 2227 .edid = edid, 2228 }; 2229 2230 if (version_greater(edid, 1, 0)) 2231 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2232 &closure); 2233 2234 return closure.modes; 2235 } 2236 2237 static int 2238 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2239 { 2240 int i, j, m, modes = 0; 2241 struct drm_display_mode *mode; 2242 u8 *est = ((u8 *)timing) + 5; 2243 2244 for (i = 0; i < 6; i++) { 2245 for (j = 7; j >= 0; j--) { 2246 m = (i * 8) + (7 - j); 2247 if (m >= ARRAY_SIZE(est3_modes)) 2248 break; 2249 if (est[i] & (1 << j)) { 2250 mode = drm_mode_find_dmt(connector->dev, 2251 est3_modes[m].w, 2252 est3_modes[m].h, 2253 est3_modes[m].r, 2254 est3_modes[m].rb); 2255 if (mode) { 2256 drm_mode_probed_add(connector, mode); 2257 modes++; 2258 } 2259 } 2260 } 2261 } 2262 2263 return modes; 2264 } 2265 2266 static void 2267 do_established_modes(struct detailed_timing *timing, void *c) 2268 { 2269 struct detailed_mode_closure *closure = c; 2270 struct detailed_non_pixel *data = &timing->data.other_data; 2271 2272 if (data->type == EDID_DETAIL_EST_TIMINGS) 2273 closure->modes += drm_est3_modes(closure->connector, timing); 2274 } 2275 2276 /** 2277 * add_established_modes - get est. modes from EDID and add them 2278 * @connector: connector to add mode(s) to 2279 * @edid: EDID block to scan 2280 * 2281 * Each EDID block contains a bitmap of the supported "established modes" list 2282 * (defined above). Tease them out and add them to the global modes list. 2283 */ 2284 static int 2285 add_established_modes(struct drm_connector *connector, struct edid *edid) 2286 { 2287 struct drm_device *dev = connector->dev; 2288 unsigned long est_bits = edid->established_timings.t1 | 2289 (edid->established_timings.t2 << 8) | 2290 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2291 int i, modes = 0; 2292 struct detailed_mode_closure closure = { 2293 .connector = connector, 2294 .edid = edid, 2295 }; 2296 2297 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2298 if (est_bits & (1<<i)) { 2299 struct drm_display_mode *newmode; 2300 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2301 if (newmode) { 2302 drm_mode_probed_add(connector, newmode); 2303 modes++; 2304 } 2305 } 2306 } 2307 2308 if (version_greater(edid, 1, 0)) 2309 drm_for_each_detailed_block((u8 *)edid, 2310 do_established_modes, &closure); 2311 2312 return modes + closure.modes; 2313 } 2314 2315 static void 2316 do_standard_modes(struct detailed_timing *timing, void *c) 2317 { 2318 struct detailed_mode_closure *closure = c; 2319 struct detailed_non_pixel *data = &timing->data.other_data; 2320 struct drm_connector *connector = closure->connector; 2321 struct edid *edid = closure->edid; 2322 2323 if (data->type == EDID_DETAIL_STD_MODES) { 2324 int i; 2325 for (i = 0; i < 6; i++) { 2326 struct std_timing *std; 2327 struct drm_display_mode *newmode; 2328 2329 std = &data->data.timings[i]; 2330 newmode = drm_mode_std(connector, edid, std); 2331 if (newmode) { 2332 drm_mode_probed_add(connector, newmode); 2333 closure->modes++; 2334 } 2335 } 2336 } 2337 } 2338 2339 /** 2340 * add_standard_modes - get std. modes from EDID and add them 2341 * @connector: connector to add mode(s) to 2342 * @edid: EDID block to scan 2343 * 2344 * Standard modes can be calculated using the appropriate standard (DMT, 2345 * GTF or CVT. Grab them from @edid and add them to the list. 2346 */ 2347 static int 2348 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2349 { 2350 int i, modes = 0; 2351 struct detailed_mode_closure closure = { 2352 .connector = connector, 2353 .edid = edid, 2354 }; 2355 2356 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2357 struct drm_display_mode *newmode; 2358 2359 newmode = drm_mode_std(connector, edid, 2360 &edid->standard_timings[i]); 2361 if (newmode) { 2362 drm_mode_probed_add(connector, newmode); 2363 modes++; 2364 } 2365 } 2366 2367 if (version_greater(edid, 1, 0)) 2368 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2369 &closure); 2370 2371 /* XXX should also look for standard codes in VTB blocks */ 2372 2373 return modes + closure.modes; 2374 } 2375 2376 static int drm_cvt_modes(struct drm_connector *connector, 2377 struct detailed_timing *timing) 2378 { 2379 int i, j, modes = 0; 2380 struct drm_display_mode *newmode; 2381 struct drm_device *dev = connector->dev; 2382 struct cvt_timing *cvt; 2383 const int rates[] = { 60, 85, 75, 60, 50 }; 2384 const u8 empty[3] = { 0, 0, 0 }; 2385 2386 for (i = 0; i < 4; i++) { 2387 int uninitialized_var(width), height; 2388 cvt = &(timing->data.other_data.data.cvt[i]); 2389 2390 if (!memcmp(cvt->code, empty, 3)) 2391 continue; 2392 2393 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2394 switch (cvt->code[1] & 0x0c) { 2395 case 0x00: 2396 width = height * 4 / 3; 2397 break; 2398 case 0x04: 2399 width = height * 16 / 9; 2400 break; 2401 case 0x08: 2402 width = height * 16 / 10; 2403 break; 2404 case 0x0c: 2405 width = height * 15 / 9; 2406 break; 2407 } 2408 2409 for (j = 1; j < 5; j++) { 2410 if (cvt->code[2] & (1 << j)) { 2411 newmode = drm_cvt_mode(dev, width, height, 2412 rates[j], j == 0, 2413 false, false); 2414 if (newmode) { 2415 drm_mode_probed_add(connector, newmode); 2416 modes++; 2417 } 2418 } 2419 } 2420 } 2421 2422 return modes; 2423 } 2424 2425 static void 2426 do_cvt_mode(struct detailed_timing *timing, void *c) 2427 { 2428 struct detailed_mode_closure *closure = c; 2429 struct detailed_non_pixel *data = &timing->data.other_data; 2430 2431 if (data->type == EDID_DETAIL_CVT_3BYTE) 2432 closure->modes += drm_cvt_modes(closure->connector, timing); 2433 } 2434 2435 static int 2436 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2437 { 2438 struct detailed_mode_closure closure = { 2439 .connector = connector, 2440 .edid = edid, 2441 }; 2442 2443 if (version_greater(edid, 1, 2)) 2444 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2445 2446 /* XXX should also look for CVT codes in VTB blocks */ 2447 2448 return closure.modes; 2449 } 2450 2451 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2452 2453 static void 2454 do_detailed_mode(struct detailed_timing *timing, void *c) 2455 { 2456 struct detailed_mode_closure *closure = c; 2457 struct drm_display_mode *newmode; 2458 2459 if (timing->pixel_clock) { 2460 newmode = drm_mode_detailed(closure->connector->dev, 2461 closure->edid, timing, 2462 closure->quirks); 2463 if (!newmode) 2464 return; 2465 2466 if (closure->preferred) 2467 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2468 2469 /* 2470 * Detailed modes are limited to 10kHz pixel clock resolution, 2471 * so fix up anything that looks like CEA/HDMI mode, but the clock 2472 * is just slightly off. 2473 */ 2474 fixup_detailed_cea_mode_clock(newmode); 2475 2476 drm_mode_probed_add(closure->connector, newmode); 2477 closure->modes++; 2478 closure->preferred = 0; 2479 } 2480 } 2481 2482 /* 2483 * add_detailed_modes - Add modes from detailed timings 2484 * @connector: attached connector 2485 * @edid: EDID block to scan 2486 * @quirks: quirks to apply 2487 */ 2488 static int 2489 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2490 u32 quirks) 2491 { 2492 struct detailed_mode_closure closure = { 2493 .connector = connector, 2494 .edid = edid, 2495 .preferred = 1, 2496 .quirks = quirks, 2497 }; 2498 2499 if (closure.preferred && !version_greater(edid, 1, 3)) 2500 closure.preferred = 2501 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2502 2503 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2504 2505 return closure.modes; 2506 } 2507 2508 #define AUDIO_BLOCK 0x01 2509 #define VIDEO_BLOCK 0x02 2510 #define VENDOR_BLOCK 0x03 2511 #define SPEAKER_BLOCK 0x04 2512 #define VIDEO_CAPABILITY_BLOCK 0x07 2513 #define EDID_BASIC_AUDIO (1 << 6) 2514 #define EDID_CEA_YCRCB444 (1 << 5) 2515 #define EDID_CEA_YCRCB422 (1 << 4) 2516 #define EDID_CEA_VCDB_QS (1 << 6) 2517 2518 /* 2519 * Search EDID for CEA extension block. 2520 */ 2521 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2522 { 2523 u8 *edid_ext = NULL; 2524 int i; 2525 2526 /* No EDID or EDID extensions */ 2527 if (edid == NULL || edid->extensions == 0) 2528 return NULL; 2529 2530 /* Find CEA extension */ 2531 for (i = 0; i < edid->extensions; i++) { 2532 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2533 if (edid_ext[0] == ext_id) 2534 break; 2535 } 2536 2537 if (i == edid->extensions) 2538 return NULL; 2539 2540 return edid_ext; 2541 } 2542 2543 static u8 *drm_find_cea_extension(struct edid *edid) 2544 { 2545 return drm_find_edid_extension(edid, CEA_EXT); 2546 } 2547 2548 static u8 *drm_find_displayid_extension(struct edid *edid) 2549 { 2550 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2551 } 2552 2553 /* 2554 * Calculate the alternate clock for the CEA mode 2555 * (60Hz vs. 59.94Hz etc.) 2556 */ 2557 static unsigned int 2558 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2559 { 2560 unsigned int clock = cea_mode->clock; 2561 2562 if (cea_mode->vrefresh % 6 != 0) 2563 return clock; 2564 2565 /* 2566 * edid_cea_modes contains the 59.94Hz 2567 * variant for 240 and 480 line modes, 2568 * and the 60Hz variant otherwise. 2569 */ 2570 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2571 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2572 else 2573 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2574 2575 return clock; 2576 } 2577 2578 /** 2579 * drm_match_cea_mode - look for a CEA mode matching given mode 2580 * @to_match: display mode 2581 * 2582 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2583 * mode. 2584 */ 2585 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2586 { 2587 u8 mode; 2588 2589 if (!to_match->clock) 2590 return 0; 2591 2592 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2593 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2594 unsigned int clock1, clock2; 2595 2596 /* Check both 60Hz and 59.94Hz */ 2597 clock1 = cea_mode->clock; 2598 clock2 = cea_mode_alternate_clock(cea_mode); 2599 2600 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2601 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2602 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2603 return mode + 1; 2604 } 2605 return 0; 2606 } 2607 EXPORT_SYMBOL(drm_match_cea_mode); 2608 2609 /** 2610 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2611 * the input VIC from the CEA mode list 2612 * @video_code: ID given to each of the CEA modes 2613 * 2614 * Returns picture aspect ratio 2615 */ 2616 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2617 { 2618 /* return picture aspect ratio for video_code - 1 to access the 2619 * right array element 2620 */ 2621 return edid_cea_modes[video_code-1].picture_aspect_ratio; 2622 } 2623 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2624 2625 /* 2626 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2627 * specific block). 2628 * 2629 * It's almost like cea_mode_alternate_clock(), we just need to add an 2630 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2631 * one. 2632 */ 2633 static unsigned int 2634 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2635 { 2636 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2637 return hdmi_mode->clock; 2638 2639 return cea_mode_alternate_clock(hdmi_mode); 2640 } 2641 2642 /* 2643 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2644 * @to_match: display mode 2645 * 2646 * An HDMI mode is one defined in the HDMI vendor specific block. 2647 * 2648 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2649 */ 2650 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2651 { 2652 u8 mode; 2653 2654 if (!to_match->clock) 2655 return 0; 2656 2657 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { 2658 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; 2659 unsigned int clock1, clock2; 2660 2661 /* Make sure to also match alternate clocks */ 2662 clock1 = hdmi_mode->clock; 2663 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2664 2665 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2666 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2667 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2668 return mode + 1; 2669 } 2670 return 0; 2671 } 2672 2673 static int 2674 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2675 { 2676 struct drm_device *dev = connector->dev; 2677 struct drm_display_mode *mode, *tmp; 2678 LIST_HEAD(list); 2679 int modes = 0; 2680 2681 /* Don't add CEA modes if the CEA extension block is missing */ 2682 if (!drm_find_cea_extension(edid)) 2683 return 0; 2684 2685 /* 2686 * Go through all probed modes and create a new mode 2687 * with the alternate clock for certain CEA modes. 2688 */ 2689 list_for_each_entry(mode, &connector->probed_modes, head) { 2690 const struct drm_display_mode *cea_mode = NULL; 2691 struct drm_display_mode *newmode; 2692 u8 mode_idx = drm_match_cea_mode(mode) - 1; 2693 unsigned int clock1, clock2; 2694 2695 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 2696 cea_mode = &edid_cea_modes[mode_idx]; 2697 clock2 = cea_mode_alternate_clock(cea_mode); 2698 } else { 2699 mode_idx = drm_match_hdmi_mode(mode) - 1; 2700 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 2701 cea_mode = &edid_4k_modes[mode_idx]; 2702 clock2 = hdmi_mode_alternate_clock(cea_mode); 2703 } 2704 } 2705 2706 if (!cea_mode) 2707 continue; 2708 2709 clock1 = cea_mode->clock; 2710 2711 if (clock1 == clock2) 2712 continue; 2713 2714 if (mode->clock != clock1 && mode->clock != clock2) 2715 continue; 2716 2717 newmode = drm_mode_duplicate(dev, cea_mode); 2718 if (!newmode) 2719 continue; 2720 2721 /* Carry over the stereo flags */ 2722 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2723 2724 /* 2725 * The current mode could be either variant. Make 2726 * sure to pick the "other" clock for the new mode. 2727 */ 2728 if (mode->clock != clock1) 2729 newmode->clock = clock1; 2730 else 2731 newmode->clock = clock2; 2732 2733 list_add_tail(&newmode->head, &list); 2734 } 2735 2736 list_for_each_entry_safe(mode, tmp, &list, head) { 2737 list_del(&mode->head); 2738 drm_mode_probed_add(connector, mode); 2739 modes++; 2740 } 2741 2742 return modes; 2743 } 2744 2745 static struct drm_display_mode * 2746 drm_display_mode_from_vic_index(struct drm_connector *connector, 2747 const u8 *video_db, u8 video_len, 2748 u8 video_index) 2749 { 2750 struct drm_device *dev = connector->dev; 2751 struct drm_display_mode *newmode; 2752 u8 cea_mode; 2753 2754 if (video_db == NULL || video_index >= video_len) 2755 return NULL; 2756 2757 /* CEA modes are numbered 1..127 */ 2758 cea_mode = (video_db[video_index] & 127) - 1; 2759 if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) 2760 return NULL; 2761 2762 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2763 if (!newmode) 2764 return NULL; 2765 2766 newmode->vrefresh = 0; 2767 2768 return newmode; 2769 } 2770 2771 static int 2772 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2773 { 2774 int i, modes = 0; 2775 2776 for (i = 0; i < len; i++) { 2777 struct drm_display_mode *mode; 2778 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2779 if (mode) { 2780 drm_mode_probed_add(connector, mode); 2781 modes++; 2782 } 2783 } 2784 2785 return modes; 2786 } 2787 2788 struct stereo_mandatory_mode { 2789 int width, height, vrefresh; 2790 unsigned int flags; 2791 }; 2792 2793 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2794 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2795 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2796 { 1920, 1080, 50, 2797 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2798 { 1920, 1080, 60, 2799 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2800 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2801 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2802 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2803 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2804 }; 2805 2806 static bool 2807 stereo_match_mandatory(const struct drm_display_mode *mode, 2808 const struct stereo_mandatory_mode *stereo_mode) 2809 { 2810 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2811 2812 return mode->hdisplay == stereo_mode->width && 2813 mode->vdisplay == stereo_mode->height && 2814 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2815 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2816 } 2817 2818 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2819 { 2820 struct drm_device *dev = connector->dev; 2821 const struct drm_display_mode *mode; 2822 struct list_head stereo_modes; 2823 int modes = 0, i; 2824 2825 INIT_LIST_HEAD(&stereo_modes); 2826 2827 list_for_each_entry(mode, &connector->probed_modes, head) { 2828 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2829 const struct stereo_mandatory_mode *mandatory; 2830 struct drm_display_mode *new_mode; 2831 2832 if (!stereo_match_mandatory(mode, 2833 &stereo_mandatory_modes[i])) 2834 continue; 2835 2836 mandatory = &stereo_mandatory_modes[i]; 2837 new_mode = drm_mode_duplicate(dev, mode); 2838 if (!new_mode) 2839 continue; 2840 2841 new_mode->flags |= mandatory->flags; 2842 list_add_tail(&new_mode->head, &stereo_modes); 2843 modes++; 2844 } 2845 } 2846 2847 list_splice_tail(&stereo_modes, &connector->probed_modes); 2848 2849 return modes; 2850 } 2851 2852 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2853 { 2854 struct drm_device *dev = connector->dev; 2855 struct drm_display_mode *newmode; 2856 2857 vic--; /* VICs start at 1 */ 2858 if (vic >= ARRAY_SIZE(edid_4k_modes)) { 2859 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2860 return 0; 2861 } 2862 2863 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2864 if (!newmode) 2865 return 0; 2866 2867 drm_mode_probed_add(connector, newmode); 2868 2869 return 1; 2870 } 2871 2872 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2873 const u8 *video_db, u8 video_len, u8 video_index) 2874 { 2875 struct drm_display_mode *newmode; 2876 int modes = 0; 2877 2878 if (structure & (1 << 0)) { 2879 newmode = drm_display_mode_from_vic_index(connector, video_db, 2880 video_len, 2881 video_index); 2882 if (newmode) { 2883 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2884 drm_mode_probed_add(connector, newmode); 2885 modes++; 2886 } 2887 } 2888 if (structure & (1 << 6)) { 2889 newmode = drm_display_mode_from_vic_index(connector, video_db, 2890 video_len, 2891 video_index); 2892 if (newmode) { 2893 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2894 drm_mode_probed_add(connector, newmode); 2895 modes++; 2896 } 2897 } 2898 if (structure & (1 << 8)) { 2899 newmode = drm_display_mode_from_vic_index(connector, video_db, 2900 video_len, 2901 video_index); 2902 if (newmode) { 2903 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2904 drm_mode_probed_add(connector, newmode); 2905 modes++; 2906 } 2907 } 2908 2909 return modes; 2910 } 2911 2912 /* 2913 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2914 * @connector: connector corresponding to the HDMI sink 2915 * @db: start of the CEA vendor specific block 2916 * @len: length of the CEA block payload, ie. one can access up to db[len] 2917 * 2918 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2919 * also adds the stereo 3d modes when applicable. 2920 */ 2921 static int 2922 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2923 const u8 *video_db, u8 video_len) 2924 { 2925 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2926 u8 vic_len, hdmi_3d_len = 0; 2927 u16 mask; 2928 u16 structure_all; 2929 2930 if (len < 8) 2931 goto out; 2932 2933 /* no HDMI_Video_Present */ 2934 if (!(db[8] & (1 << 5))) 2935 goto out; 2936 2937 /* Latency_Fields_Present */ 2938 if (db[8] & (1 << 7)) 2939 offset += 2; 2940 2941 /* I_Latency_Fields_Present */ 2942 if (db[8] & (1 << 6)) 2943 offset += 2; 2944 2945 /* the declared length is not long enough for the 2 first bytes 2946 * of additional video format capabilities */ 2947 if (len < (8 + offset + 2)) 2948 goto out; 2949 2950 /* 3D_Present */ 2951 offset++; 2952 if (db[8 + offset] & (1 << 7)) { 2953 modes += add_hdmi_mandatory_stereo_modes(connector); 2954 2955 /* 3D_Multi_present */ 2956 multi_present = (db[8 + offset] & 0x60) >> 5; 2957 } 2958 2959 offset++; 2960 vic_len = db[8 + offset] >> 5; 2961 hdmi_3d_len = db[8 + offset] & 0x1f; 2962 2963 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2964 u8 vic; 2965 2966 vic = db[9 + offset + i]; 2967 modes += add_hdmi_mode(connector, vic); 2968 } 2969 offset += 1 + vic_len; 2970 2971 if (multi_present == 1) 2972 multi_len = 2; 2973 else if (multi_present == 2) 2974 multi_len = 4; 2975 else 2976 multi_len = 0; 2977 2978 if (len < (8 + offset + hdmi_3d_len - 1)) 2979 goto out; 2980 2981 if (hdmi_3d_len < multi_len) 2982 goto out; 2983 2984 if (multi_present == 1 || multi_present == 2) { 2985 /* 3D_Structure_ALL */ 2986 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2987 2988 /* check if 3D_MASK is present */ 2989 if (multi_present == 2) 2990 mask = (db[10 + offset] << 8) | db[11 + offset]; 2991 else 2992 mask = 0xffff; 2993 2994 for (i = 0; i < 16; i++) { 2995 if (mask & (1 << i)) 2996 modes += add_3d_struct_modes(connector, 2997 structure_all, 2998 video_db, 2999 video_len, i); 3000 } 3001 } 3002 3003 offset += multi_len; 3004 3005 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3006 int vic_index; 3007 struct drm_display_mode *newmode = NULL; 3008 unsigned int newflag = 0; 3009 bool detail_present; 3010 3011 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3012 3013 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3014 break; 3015 3016 /* 2D_VIC_order_X */ 3017 vic_index = db[8 + offset + i] >> 4; 3018 3019 /* 3D_Structure_X */ 3020 switch (db[8 + offset + i] & 0x0f) { 3021 case 0: 3022 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3023 break; 3024 case 6: 3025 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3026 break; 3027 case 8: 3028 /* 3D_Detail_X */ 3029 if ((db[9 + offset + i] >> 4) == 1) 3030 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3031 break; 3032 } 3033 3034 if (newflag != 0) { 3035 newmode = drm_display_mode_from_vic_index(connector, 3036 video_db, 3037 video_len, 3038 vic_index); 3039 3040 if (newmode) { 3041 newmode->flags |= newflag; 3042 drm_mode_probed_add(connector, newmode); 3043 modes++; 3044 } 3045 } 3046 3047 if (detail_present) 3048 i++; 3049 } 3050 3051 out: 3052 return modes; 3053 } 3054 3055 static int 3056 cea_db_payload_len(const u8 *db) 3057 { 3058 return db[0] & 0x1f; 3059 } 3060 3061 static int 3062 cea_db_tag(const u8 *db) 3063 { 3064 return db[0] >> 5; 3065 } 3066 3067 static int 3068 cea_revision(const u8 *cea) 3069 { 3070 return cea[1]; 3071 } 3072 3073 static int 3074 cea_db_offsets(const u8 *cea, int *start, int *end) 3075 { 3076 /* Data block offset in CEA extension block */ 3077 *start = 4; 3078 *end = cea[2]; 3079 if (*end == 0) 3080 *end = 127; 3081 if (*end < 4 || *end > 127) 3082 return -ERANGE; 3083 return 0; 3084 } 3085 3086 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3087 { 3088 int hdmi_id; 3089 3090 if (cea_db_tag(db) != VENDOR_BLOCK) 3091 return false; 3092 3093 if (cea_db_payload_len(db) < 5) 3094 return false; 3095 3096 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3097 3098 return hdmi_id == HDMI_IEEE_OUI; 3099 } 3100 3101 #define for_each_cea_db(cea, i, start, end) \ 3102 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3103 3104 static int 3105 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3106 { 3107 const u8 *cea = drm_find_cea_extension(edid); 3108 const u8 *db, *hdmi = NULL, *video = NULL; 3109 u8 dbl, hdmi_len, video_len = 0; 3110 int modes = 0; 3111 3112 if (cea && cea_revision(cea) >= 3) { 3113 int i, start, end; 3114 3115 if (cea_db_offsets(cea, &start, &end)) 3116 return 0; 3117 3118 for_each_cea_db(cea, i, start, end) { 3119 db = &cea[i]; 3120 dbl = cea_db_payload_len(db); 3121 3122 if (cea_db_tag(db) == VIDEO_BLOCK) { 3123 video = db + 1; 3124 video_len = dbl; 3125 modes += do_cea_modes(connector, video, dbl); 3126 } 3127 else if (cea_db_is_hdmi_vsdb(db)) { 3128 hdmi = db; 3129 hdmi_len = dbl; 3130 } 3131 } 3132 } 3133 3134 /* 3135 * We parse the HDMI VSDB after having added the cea modes as we will 3136 * be patching their flags when the sink supports stereo 3D. 3137 */ 3138 if (hdmi) 3139 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3140 video_len); 3141 3142 return modes; 3143 } 3144 3145 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3146 { 3147 const struct drm_display_mode *cea_mode; 3148 int clock1, clock2, clock; 3149 u8 mode_idx; 3150 const char *type; 3151 3152 mode_idx = drm_match_cea_mode(mode) - 1; 3153 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 3154 type = "CEA"; 3155 cea_mode = &edid_cea_modes[mode_idx]; 3156 clock1 = cea_mode->clock; 3157 clock2 = cea_mode_alternate_clock(cea_mode); 3158 } else { 3159 mode_idx = drm_match_hdmi_mode(mode) - 1; 3160 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 3161 type = "HDMI"; 3162 cea_mode = &edid_4k_modes[mode_idx]; 3163 clock1 = cea_mode->clock; 3164 clock2 = hdmi_mode_alternate_clock(cea_mode); 3165 } else { 3166 return; 3167 } 3168 } 3169 3170 /* pick whichever is closest */ 3171 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3172 clock = clock1; 3173 else 3174 clock = clock2; 3175 3176 if (mode->clock == clock) 3177 return; 3178 3179 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3180 type, mode_idx + 1, mode->clock, clock); 3181 mode->clock = clock; 3182 } 3183 3184 static void 3185 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3186 { 3187 u8 len = cea_db_payload_len(db); 3188 3189 if (len >= 5) { 3190 connector->physical_address = (db[4] << 8) | db[5]; 3191 } 3192 if (len >= 6) { 3193 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3194 connector->dvi_dual = db[6] & 1; 3195 } 3196 if (len >= 7) 3197 connector->max_tmds_clock = db[7] * 5; 3198 if (len >= 8) { 3199 connector->latency_present[0] = db[8] >> 7; 3200 connector->latency_present[1] = (db[8] >> 6) & 1; 3201 } 3202 if (len >= 9) 3203 connector->video_latency[0] = db[9]; 3204 if (len >= 10) 3205 connector->audio_latency[0] = db[10]; 3206 if (len >= 11) 3207 connector->video_latency[1] = db[11]; 3208 if (len >= 12) 3209 connector->audio_latency[1] = db[12]; 3210 3211 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3212 "max TMDS clock %d, " 3213 "latency present %d %d, " 3214 "video latency %d %d, " 3215 "audio latency %d %d\n", 3216 connector->dvi_dual, 3217 connector->max_tmds_clock, 3218 (int) connector->latency_present[0], 3219 (int) connector->latency_present[1], 3220 connector->video_latency[0], 3221 connector->video_latency[1], 3222 connector->audio_latency[0], 3223 connector->audio_latency[1]); 3224 } 3225 3226 static void 3227 monitor_name(struct detailed_timing *t, void *data) 3228 { 3229 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3230 *(u8 **)data = t->data.other_data.data.str.str; 3231 } 3232 3233 /** 3234 * drm_edid_to_eld - build ELD from EDID 3235 * @connector: connector corresponding to the HDMI/DP sink 3236 * @edid: EDID to parse 3237 * 3238 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3239 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 3240 */ 3241 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3242 { 3243 uint8_t *eld = connector->eld; 3244 u8 *cea; 3245 u8 *name; 3246 u8 *db; 3247 int sad_count = 0; 3248 int mnl; 3249 int dbl; 3250 3251 memset(eld, 0, sizeof(connector->eld)); 3252 3253 cea = drm_find_cea_extension(edid); 3254 if (!cea) { 3255 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3256 return; 3257 } 3258 3259 name = NULL; 3260 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 3261 for (mnl = 0; name && mnl < 13; mnl++) { 3262 if (name[mnl] == 0x0a) 3263 break; 3264 eld[20 + mnl] = name[mnl]; 3265 } 3266 eld[4] = (cea[1] << 5) | mnl; 3267 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3268 3269 eld[0] = 2 << 3; /* ELD version: 2 */ 3270 3271 eld[16] = edid->mfg_id[0]; 3272 eld[17] = edid->mfg_id[1]; 3273 eld[18] = edid->prod_code[0]; 3274 eld[19] = edid->prod_code[1]; 3275 3276 if (cea_revision(cea) >= 3) { 3277 int i, start, end; 3278 3279 if (cea_db_offsets(cea, &start, &end)) { 3280 start = 0; 3281 end = 0; 3282 } 3283 3284 for_each_cea_db(cea, i, start, end) { 3285 db = &cea[i]; 3286 dbl = cea_db_payload_len(db); 3287 3288 switch (cea_db_tag(db)) { 3289 case AUDIO_BLOCK: 3290 /* Audio Data Block, contains SADs */ 3291 sad_count = dbl / 3; 3292 if (dbl >= 1) 3293 memcpy(eld + 20 + mnl, &db[1], dbl); 3294 break; 3295 case SPEAKER_BLOCK: 3296 /* Speaker Allocation Data Block */ 3297 if (dbl >= 1) 3298 eld[7] = db[1]; 3299 break; 3300 case VENDOR_BLOCK: 3301 /* HDMI Vendor-Specific Data Block */ 3302 if (cea_db_is_hdmi_vsdb(db)) 3303 parse_hdmi_vsdb(connector, db); 3304 break; 3305 default: 3306 break; 3307 } 3308 } 3309 } 3310 eld[5] |= sad_count << 4; 3311 3312 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3313 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3314 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 3315 else 3316 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 3317 3318 eld[DRM_ELD_BASELINE_ELD_LEN] = 3319 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3320 3321 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3322 drm_eld_size(eld), sad_count); 3323 } 3324 EXPORT_SYMBOL(drm_edid_to_eld); 3325 3326 /** 3327 * drm_edid_to_sad - extracts SADs from EDID 3328 * @edid: EDID to parse 3329 * @sads: pointer that will be set to the extracted SADs 3330 * 3331 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3332 * 3333 * Note: The returned pointer needs to be freed using kfree(). 3334 * 3335 * Return: The number of found SADs or negative number on error. 3336 */ 3337 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3338 { 3339 int count = 0; 3340 int i, start, end, dbl; 3341 u8 *cea; 3342 3343 cea = drm_find_cea_extension(edid); 3344 if (!cea) { 3345 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3346 return -ENOENT; 3347 } 3348 3349 if (cea_revision(cea) < 3) { 3350 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3351 return -ENOTSUPP; 3352 } 3353 3354 if (cea_db_offsets(cea, &start, &end)) { 3355 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3356 return -EPROTO; 3357 } 3358 3359 for_each_cea_db(cea, i, start, end) { 3360 u8 *db = &cea[i]; 3361 3362 if (cea_db_tag(db) == AUDIO_BLOCK) { 3363 int j; 3364 dbl = cea_db_payload_len(db); 3365 3366 count = dbl / 3; /* SAD is 3B */ 3367 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3368 if (!*sads) 3369 return -ENOMEM; 3370 for (j = 0; j < count; j++) { 3371 u8 *sad = &db[1 + j * 3]; 3372 3373 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3374 (*sads)[j].channels = sad[0] & 0x7; 3375 (*sads)[j].freq = sad[1] & 0x7F; 3376 (*sads)[j].byte2 = sad[2]; 3377 } 3378 break; 3379 } 3380 } 3381 3382 return count; 3383 } 3384 EXPORT_SYMBOL(drm_edid_to_sad); 3385 3386 /** 3387 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3388 * @edid: EDID to parse 3389 * @sadb: pointer to the speaker block 3390 * 3391 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3392 * 3393 * Note: The returned pointer needs to be freed using kfree(). 3394 * 3395 * Return: The number of found Speaker Allocation Blocks or negative number on 3396 * error. 3397 */ 3398 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3399 { 3400 int count = 0; 3401 int i, start, end, dbl; 3402 const u8 *cea; 3403 3404 cea = drm_find_cea_extension(edid); 3405 if (!cea) { 3406 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3407 return -ENOENT; 3408 } 3409 3410 if (cea_revision(cea) < 3) { 3411 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3412 return -ENOTSUPP; 3413 } 3414 3415 if (cea_db_offsets(cea, &start, &end)) { 3416 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3417 return -EPROTO; 3418 } 3419 3420 for_each_cea_db(cea, i, start, end) { 3421 const u8 *db = &cea[i]; 3422 3423 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3424 dbl = cea_db_payload_len(db); 3425 3426 /* Speaker Allocation Data Block */ 3427 if (dbl == 3) { 3428 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3429 if (!*sadb) 3430 return -ENOMEM; 3431 count = dbl; 3432 break; 3433 } 3434 } 3435 } 3436 3437 return count; 3438 } 3439 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3440 3441 /** 3442 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3443 * @connector: connector associated with the HDMI/DP sink 3444 * @mode: the display mode 3445 * 3446 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3447 * the sink doesn't support audio or video. 3448 */ 3449 int drm_av_sync_delay(struct drm_connector *connector, 3450 const struct drm_display_mode *mode) 3451 { 3452 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3453 int a, v; 3454 3455 if (!connector->latency_present[0]) 3456 return 0; 3457 if (!connector->latency_present[1]) 3458 i = 0; 3459 3460 a = connector->audio_latency[i]; 3461 v = connector->video_latency[i]; 3462 3463 /* 3464 * HDMI/DP sink doesn't support audio or video? 3465 */ 3466 if (a == 255 || v == 255) 3467 return 0; 3468 3469 /* 3470 * Convert raw EDID values to millisecond. 3471 * Treat unknown latency as 0ms. 3472 */ 3473 if (a) 3474 a = min(2 * (a - 1), 500); 3475 if (v) 3476 v = min(2 * (v - 1), 500); 3477 3478 return max(v - a, 0); 3479 } 3480 EXPORT_SYMBOL(drm_av_sync_delay); 3481 3482 /** 3483 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3484 * @encoder: the encoder just changed display mode 3485 * 3486 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3487 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3488 * 3489 * Return: The connector associated with the first HDMI/DP sink that has ELD 3490 * attached to it. 3491 */ 3492 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3493 { 3494 struct drm_connector *connector; 3495 struct drm_device *dev = encoder->dev; 3496 3497 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3498 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3499 3500 drm_for_each_connector(connector, dev) 3501 if (connector->encoder == encoder && connector->eld[0]) 3502 return connector; 3503 3504 return NULL; 3505 } 3506 EXPORT_SYMBOL(drm_select_eld); 3507 3508 /** 3509 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3510 * @edid: monitor EDID information 3511 * 3512 * Parse the CEA extension according to CEA-861-B. 3513 * 3514 * Return: True if the monitor is HDMI, false if not or unknown. 3515 */ 3516 bool drm_detect_hdmi_monitor(struct edid *edid) 3517 { 3518 u8 *edid_ext; 3519 int i; 3520 int start_offset, end_offset; 3521 3522 edid_ext = drm_find_cea_extension(edid); 3523 if (!edid_ext) 3524 return false; 3525 3526 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3527 return false; 3528 3529 /* 3530 * Because HDMI identifier is in Vendor Specific Block, 3531 * search it from all data blocks of CEA extension. 3532 */ 3533 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3534 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3535 return true; 3536 } 3537 3538 return false; 3539 } 3540 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3541 3542 /** 3543 * drm_detect_monitor_audio - check monitor audio capability 3544 * @edid: EDID block to scan 3545 * 3546 * Monitor should have CEA extension block. 3547 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3548 * audio' only. If there is any audio extension block and supported 3549 * audio format, assume at least 'basic audio' support, even if 'basic 3550 * audio' is not defined in EDID. 3551 * 3552 * Return: True if the monitor supports audio, false otherwise. 3553 */ 3554 bool drm_detect_monitor_audio(struct edid *edid) 3555 { 3556 u8 *edid_ext; 3557 int i, j; 3558 bool has_audio = false; 3559 int start_offset, end_offset; 3560 3561 edid_ext = drm_find_cea_extension(edid); 3562 if (!edid_ext) 3563 goto end; 3564 3565 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3566 3567 if (has_audio) { 3568 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3569 goto end; 3570 } 3571 3572 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3573 goto end; 3574 3575 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3576 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3577 has_audio = true; 3578 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3579 DRM_DEBUG_KMS("CEA audio format %d\n", 3580 (edid_ext[i + j] >> 3) & 0xf); 3581 goto end; 3582 } 3583 } 3584 end: 3585 return has_audio; 3586 } 3587 EXPORT_SYMBOL(drm_detect_monitor_audio); 3588 3589 /** 3590 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3591 * @edid: EDID block to scan 3592 * 3593 * Check whether the monitor reports the RGB quantization range selection 3594 * as supported. The AVI infoframe can then be used to inform the monitor 3595 * which quantization range (full or limited) is used. 3596 * 3597 * Return: True if the RGB quantization range is selectable, false otherwise. 3598 */ 3599 bool drm_rgb_quant_range_selectable(struct edid *edid) 3600 { 3601 u8 *edid_ext; 3602 int i, start, end; 3603 3604 edid_ext = drm_find_cea_extension(edid); 3605 if (!edid_ext) 3606 return false; 3607 3608 if (cea_db_offsets(edid_ext, &start, &end)) 3609 return false; 3610 3611 for_each_cea_db(edid_ext, i, start, end) { 3612 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3613 cea_db_payload_len(&edid_ext[i]) == 2) { 3614 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3615 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3616 } 3617 } 3618 3619 return false; 3620 } 3621 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3622 3623 /** 3624 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3625 * hdmi deep color modes and update drm_display_info if so. 3626 * @edid: monitor EDID information 3627 * @info: Updated with maximum supported deep color bpc and color format 3628 * if deep color supported. 3629 * @connector: DRM connector, used only for debug output 3630 * 3631 * Parse the CEA extension according to CEA-861-B. 3632 * Return true if HDMI deep color supported, false if not or unknown. 3633 */ 3634 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3635 struct drm_display_info *info, 3636 struct drm_connector *connector) 3637 { 3638 u8 *edid_ext, *hdmi; 3639 int i; 3640 int start_offset, end_offset; 3641 unsigned int dc_bpc = 0; 3642 3643 edid_ext = drm_find_cea_extension(edid); 3644 if (!edid_ext) 3645 return false; 3646 3647 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3648 return false; 3649 3650 /* 3651 * Because HDMI identifier is in Vendor Specific Block, 3652 * search it from all data blocks of CEA extension. 3653 */ 3654 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3655 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3656 /* HDMI supports at least 8 bpc */ 3657 info->bpc = 8; 3658 3659 hdmi = &edid_ext[i]; 3660 if (cea_db_payload_len(hdmi) < 6) 3661 return false; 3662 3663 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3664 dc_bpc = 10; 3665 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3666 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3667 connector->name); 3668 } 3669 3670 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3671 dc_bpc = 12; 3672 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3673 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3674 connector->name); 3675 } 3676 3677 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3678 dc_bpc = 16; 3679 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3680 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3681 connector->name); 3682 } 3683 3684 if (dc_bpc > 0) { 3685 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3686 connector->name, dc_bpc); 3687 info->bpc = dc_bpc; 3688 3689 /* 3690 * Deep color support mandates RGB444 support for all video 3691 * modes and forbids YCRCB422 support for all video modes per 3692 * HDMI 1.3 spec. 3693 */ 3694 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3695 3696 /* YCRCB444 is optional according to spec. */ 3697 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3698 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3699 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3700 connector->name); 3701 } 3702 3703 /* 3704 * Spec says that if any deep color mode is supported at all, 3705 * then deep color 36 bit must be supported. 3706 */ 3707 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3708 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3709 connector->name); 3710 } 3711 3712 return true; 3713 } 3714 else { 3715 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3716 connector->name); 3717 } 3718 } 3719 } 3720 3721 return false; 3722 } 3723 3724 /** 3725 * drm_add_display_info - pull display info out if present 3726 * @edid: EDID data 3727 * @info: display info (attached to connector) 3728 * @connector: connector whose edid is used to build display info 3729 * 3730 * Grab any available display info and stuff it into the drm_display_info 3731 * structure that's part of the connector. Useful for tracking bpp and 3732 * color spaces. 3733 */ 3734 static void drm_add_display_info(struct edid *edid, 3735 struct drm_display_info *info, 3736 struct drm_connector *connector) 3737 { 3738 u8 *edid_ext; 3739 3740 info->width_mm = edid->width_cm * 10; 3741 info->height_mm = edid->height_cm * 10; 3742 3743 /* driver figures it out in this case */ 3744 info->bpc = 0; 3745 info->color_formats = 0; 3746 3747 if (edid->revision < 3) 3748 return; 3749 3750 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3751 return; 3752 3753 /* Get data from CEA blocks if present */ 3754 edid_ext = drm_find_cea_extension(edid); 3755 if (edid_ext) { 3756 info->cea_rev = edid_ext[1]; 3757 3758 /* The existence of a CEA block should imply RGB support */ 3759 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3760 if (edid_ext[3] & EDID_CEA_YCRCB444) 3761 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3762 if (edid_ext[3] & EDID_CEA_YCRCB422) 3763 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3764 } 3765 3766 /* HDMI deep color modes supported? Assign to info, if so */ 3767 drm_assign_hdmi_deep_color_info(edid, info, connector); 3768 3769 /* Only defined for 1.4 with digital displays */ 3770 if (edid->revision < 4) 3771 return; 3772 3773 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3774 case DRM_EDID_DIGITAL_DEPTH_6: 3775 info->bpc = 6; 3776 break; 3777 case DRM_EDID_DIGITAL_DEPTH_8: 3778 info->bpc = 8; 3779 break; 3780 case DRM_EDID_DIGITAL_DEPTH_10: 3781 info->bpc = 10; 3782 break; 3783 case DRM_EDID_DIGITAL_DEPTH_12: 3784 info->bpc = 12; 3785 break; 3786 case DRM_EDID_DIGITAL_DEPTH_14: 3787 info->bpc = 14; 3788 break; 3789 case DRM_EDID_DIGITAL_DEPTH_16: 3790 info->bpc = 16; 3791 break; 3792 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3793 default: 3794 info->bpc = 0; 3795 break; 3796 } 3797 3798 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3799 connector->name, info->bpc); 3800 3801 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3802 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3803 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3804 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3805 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3806 } 3807 3808 /** 3809 * drm_add_edid_modes - add modes from EDID data, if available 3810 * @connector: connector we're probing 3811 * @edid: EDID data 3812 * 3813 * Add the specified modes to the connector's mode list. 3814 * 3815 * Return: The number of modes added or 0 if we couldn't find any. 3816 */ 3817 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3818 { 3819 int num_modes = 0; 3820 u32 quirks; 3821 3822 if (edid == NULL) { 3823 return 0; 3824 } 3825 if (!drm_edid_is_valid(edid)) { 3826 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3827 connector->name); 3828 return 0; 3829 } 3830 3831 quirks = edid_get_quirks(edid); 3832 3833 /* 3834 * EDID spec says modes should be preferred in this order: 3835 * - preferred detailed mode 3836 * - other detailed modes from base block 3837 * - detailed modes from extension blocks 3838 * - CVT 3-byte code modes 3839 * - standard timing codes 3840 * - established timing codes 3841 * - modes inferred from GTF or CVT range information 3842 * 3843 * We get this pretty much right. 3844 * 3845 * XXX order for additional mode types in extension blocks? 3846 */ 3847 num_modes += add_detailed_modes(connector, edid, quirks); 3848 num_modes += add_cvt_modes(connector, edid); 3849 num_modes += add_standard_modes(connector, edid); 3850 num_modes += add_established_modes(connector, edid); 3851 num_modes += add_cea_modes(connector, edid); 3852 num_modes += add_alternate_cea_modes(connector, edid); 3853 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3854 num_modes += add_inferred_modes(connector, edid); 3855 3856 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3857 edid_fixup_preferred(connector, quirks); 3858 3859 drm_add_display_info(edid, &connector->display_info, connector); 3860 3861 if (quirks & EDID_QUIRK_FORCE_6BPC) 3862 connector->display_info.bpc = 6; 3863 3864 if (quirks & EDID_QUIRK_FORCE_8BPC) 3865 connector->display_info.bpc = 8; 3866 3867 if (quirks & EDID_QUIRK_FORCE_10BPC) 3868 connector->display_info.bpc = 10; 3869 3870 if (quirks & EDID_QUIRK_FORCE_12BPC) 3871 connector->display_info.bpc = 12; 3872 3873 return num_modes; 3874 } 3875 EXPORT_SYMBOL(drm_add_edid_modes); 3876 3877 /** 3878 * drm_add_modes_noedid - add modes for the connectors without EDID 3879 * @connector: connector we're probing 3880 * @hdisplay: the horizontal display limit 3881 * @vdisplay: the vertical display limit 3882 * 3883 * Add the specified modes to the connector's mode list. Only when the 3884 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3885 * 3886 * Return: The number of modes added or 0 if we couldn't find any. 3887 */ 3888 int drm_add_modes_noedid(struct drm_connector *connector, 3889 int hdisplay, int vdisplay) 3890 { 3891 int i, count, num_modes = 0; 3892 struct drm_display_mode *mode; 3893 struct drm_device *dev = connector->dev; 3894 3895 count = ARRAY_SIZE(drm_dmt_modes); 3896 if (hdisplay < 0) 3897 hdisplay = 0; 3898 if (vdisplay < 0) 3899 vdisplay = 0; 3900 3901 for (i = 0; i < count; i++) { 3902 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3903 if (hdisplay && vdisplay) { 3904 /* 3905 * Only when two are valid, they will be used to check 3906 * whether the mode should be added to the mode list of 3907 * the connector. 3908 */ 3909 if (ptr->hdisplay > hdisplay || 3910 ptr->vdisplay > vdisplay) 3911 continue; 3912 } 3913 if (drm_mode_vrefresh(ptr) > 61) 3914 continue; 3915 mode = drm_mode_duplicate(dev, ptr); 3916 if (mode) { 3917 drm_mode_probed_add(connector, mode); 3918 num_modes++; 3919 } 3920 } 3921 return num_modes; 3922 } 3923 EXPORT_SYMBOL(drm_add_modes_noedid); 3924 3925 /** 3926 * drm_set_preferred_mode - Sets the preferred mode of a connector 3927 * @connector: connector whose mode list should be processed 3928 * @hpref: horizontal resolution of preferred mode 3929 * @vpref: vertical resolution of preferred mode 3930 * 3931 * Marks a mode as preferred if it matches the resolution specified by @hpref 3932 * and @vpref. 3933 */ 3934 void drm_set_preferred_mode(struct drm_connector *connector, 3935 int hpref, int vpref) 3936 { 3937 struct drm_display_mode *mode; 3938 3939 list_for_each_entry(mode, &connector->probed_modes, head) { 3940 if (mode->hdisplay == hpref && 3941 mode->vdisplay == vpref) 3942 mode->type |= DRM_MODE_TYPE_PREFERRED; 3943 } 3944 } 3945 EXPORT_SYMBOL(drm_set_preferred_mode); 3946 3947 /** 3948 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3949 * data from a DRM display mode 3950 * @frame: HDMI AVI infoframe 3951 * @mode: DRM display mode 3952 * 3953 * Return: 0 on success or a negative error code on failure. 3954 */ 3955 int 3956 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3957 const struct drm_display_mode *mode) 3958 { 3959 int err; 3960 3961 if (!frame || !mode) 3962 return -EINVAL; 3963 3964 err = hdmi_avi_infoframe_init(frame); 3965 if (err < 0) 3966 return err; 3967 3968 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3969 frame->pixel_repeat = 1; 3970 3971 frame->video_code = drm_match_cea_mode(mode); 3972 3973 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3974 3975 /* 3976 * Populate picture aspect ratio from either 3977 * user input (if specified) or from the CEA mode list. 3978 */ 3979 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 3980 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 3981 frame->picture_aspect = mode->picture_aspect_ratio; 3982 else if (frame->video_code > 0) 3983 frame->picture_aspect = drm_get_cea_aspect_ratio( 3984 frame->video_code); 3985 3986 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 3987 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 3988 3989 return 0; 3990 } 3991 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 3992 3993 static enum hdmi_3d_structure 3994 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 3995 { 3996 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 3997 3998 switch (layout) { 3999 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4000 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4001 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4002 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4003 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4004 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4005 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4006 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4007 case DRM_MODE_FLAG_3D_L_DEPTH: 4008 return HDMI_3D_STRUCTURE_L_DEPTH; 4009 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4010 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4011 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4012 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4013 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4014 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4015 default: 4016 return HDMI_3D_STRUCTURE_INVALID; 4017 } 4018 } 4019 4020 /** 4021 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4022 * data from a DRM display mode 4023 * @frame: HDMI vendor infoframe 4024 * @mode: DRM display mode 4025 * 4026 * Note that there's is a need to send HDMI vendor infoframes only when using a 4027 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4028 * function will return -EINVAL, error that can be safely ignored. 4029 * 4030 * Return: 0 on success or a negative error code on failure. 4031 */ 4032 int 4033 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4034 const struct drm_display_mode *mode) 4035 { 4036 int err; 4037 u32 s3d_flags; 4038 u8 vic; 4039 4040 if (!frame || !mode) 4041 return -EINVAL; 4042 4043 vic = drm_match_hdmi_mode(mode); 4044 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4045 4046 if (!vic && !s3d_flags) 4047 return -EINVAL; 4048 4049 if (vic && s3d_flags) 4050 return -EINVAL; 4051 4052 err = hdmi_vendor_infoframe_init(frame); 4053 if (err < 0) 4054 return err; 4055 4056 if (vic) 4057 frame->vic = vic; 4058 else 4059 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4060 4061 return 0; 4062 } 4063 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4064 4065 static int drm_parse_display_id(struct drm_connector *connector, 4066 u8 *displayid, int length, 4067 bool is_edid_extension) 4068 { 4069 /* if this is an EDID extension the first byte will be 0x70 */ 4070 int idx = 0; 4071 struct displayid_hdr *base; 4072 struct displayid_block *block; 4073 u8 csum = 0; 4074 int i; 4075 4076 if (is_edid_extension) 4077 idx = 1; 4078 4079 base = (struct displayid_hdr *)&displayid[idx]; 4080 4081 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4082 base->rev, base->bytes, base->prod_id, base->ext_count); 4083 4084 if (base->bytes + 5 > length - idx) 4085 return -EINVAL; 4086 4087 for (i = idx; i <= base->bytes + 5; i++) { 4088 csum += displayid[i]; 4089 } 4090 if (csum) { 4091 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); 4092 return -EINVAL; 4093 } 4094 4095 block = (struct displayid_block *)&displayid[idx + 4]; 4096 DRM_DEBUG_KMS("block id %d, rev %d, len %d\n", 4097 block->tag, block->rev, block->num_bytes); 4098 4099 switch (block->tag) { 4100 case DATA_BLOCK_TILED_DISPLAY: { 4101 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4102 4103 u16 w, h; 4104 u8 tile_v_loc, tile_h_loc; 4105 u8 num_v_tile, num_h_tile; 4106 struct drm_tile_group *tg; 4107 4108 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4109 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4110 4111 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4112 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4113 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4114 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4115 4116 connector->has_tile = true; 4117 if (tile->tile_cap & 0x80) 4118 connector->tile_is_single_monitor = true; 4119 4120 connector->num_h_tile = num_h_tile + 1; 4121 connector->num_v_tile = num_v_tile + 1; 4122 connector->tile_h_loc = tile_h_loc; 4123 connector->tile_v_loc = tile_v_loc; 4124 connector->tile_h_size = w + 1; 4125 connector->tile_v_size = h + 1; 4126 4127 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4128 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4129 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4130 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4131 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4132 4133 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4134 if (!tg) { 4135 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4136 } 4137 if (!tg) 4138 return -ENOMEM; 4139 4140 if (connector->tile_group != tg) { 4141 /* if we haven't got a pointer, 4142 take the reference, drop ref to old tile group */ 4143 if (connector->tile_group) { 4144 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4145 } 4146 connector->tile_group = tg; 4147 } else 4148 /* if same tile group, then release the ref we just took. */ 4149 drm_mode_put_tile_group(connector->dev, tg); 4150 } 4151 break; 4152 default: 4153 printk("unknown displayid tag %d\n", block->tag); 4154 break; 4155 } 4156 return 0; 4157 } 4158 4159 static void drm_get_displayid(struct drm_connector *connector, 4160 struct edid *edid) 4161 { 4162 void *displayid = NULL; 4163 int ret; 4164 connector->has_tile = false; 4165 displayid = drm_find_displayid_extension(edid); 4166 if (!displayid) { 4167 /* drop reference to any tile group we had */ 4168 goto out_drop_ref; 4169 } 4170 4171 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 4172 if (ret < 0) 4173 goto out_drop_ref; 4174 if (!connector->has_tile) 4175 goto out_drop_ref; 4176 return; 4177 out_drop_ref: 4178 if (connector->tile_group) { 4179 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4180 connector->tile_group = NULL; 4181 } 4182 return; 4183 } 4184