1*1571a7a1Sriastradhconfig DRM_I915_USERFAULT_AUTOSUSPEND 2*1571a7a1Sriastradh int "Runtime autosuspend delay for userspace GGTT mmaps (ms)" 3*1571a7a1Sriastradh default 250 # milliseconds 4*1571a7a1Sriastradh help 5*1571a7a1Sriastradh On runtime suspend, as we suspend the device, we have to revoke 6*1571a7a1Sriastradh userspace GGTT mmaps and force userspace to take a pagefault on 7*1571a7a1Sriastradh their next access. The revocation and subsequent recreation of 8*1571a7a1Sriastradh the GGTT mmap can be very slow and so we impose a small hysteris 9*1571a7a1Sriastradh that complements the runtime-pm autosuspend and provides a lower 10*1571a7a1Sriastradh floor on the autosuspend delay. 11*1571a7a1Sriastradh 12*1571a7a1Sriastradh May be 0 to disable the extra delay and solely use the device level 13*1571a7a1Sriastradh runtime pm autosuspend delay tunable. 14*1571a7a1Sriastradh 15*1571a7a1Sriastradhconfig DRM_I915_HEARTBEAT_INTERVAL 16*1571a7a1Sriastradh int "Interval between heartbeat pulses (ms)" 17*1571a7a1Sriastradh default 2500 # milliseconds 18*1571a7a1Sriastradh help 19*1571a7a1Sriastradh The driver sends a periodic heartbeat down all active engines to 20*1571a7a1Sriastradh check the health of the GPU and undertake regular house-keeping of 21*1571a7a1Sriastradh internal driver state. 22*1571a7a1Sriastradh 23*1571a7a1Sriastradh May be 0 to disable heartbeats and therefore disable automatic GPU 24*1571a7a1Sriastradh hang detection. 25*1571a7a1Sriastradh 26*1571a7a1Sriastradhconfig DRM_I915_PREEMPT_TIMEOUT 27*1571a7a1Sriastradh int "Preempt timeout (ms, jiffy granularity)" 28*1571a7a1Sriastradh default 640 # milliseconds 29*1571a7a1Sriastradh help 30*1571a7a1Sriastradh How long to wait (in milliseconds) for a preemption event to occur 31*1571a7a1Sriastradh when submitting a new context via execlists. If the current context 32*1571a7a1Sriastradh does not hit an arbitration point and yield to HW before the timer 33*1571a7a1Sriastradh expires, the HW will be reset to allow the more important context 34*1571a7a1Sriastradh to execute. 35*1571a7a1Sriastradh 36*1571a7a1Sriastradh May be 0 to disable the timeout. 37*1571a7a1Sriastradh 38*1571a7a1Sriastradhconfig DRM_I915_SPIN_REQUEST 39*1571a7a1Sriastradh int "Busywait for request completion (us)" 40*1571a7a1Sriastradh default 5 # microseconds 41*1571a7a1Sriastradh help 42*1571a7a1Sriastradh Before sleeping waiting for a request (GPU operation) to complete, 43*1571a7a1Sriastradh we may spend some time polling for its completion. As the IRQ may 44*1571a7a1Sriastradh take a non-negligible time to setup, we do a short spin first to 45*1571a7a1Sriastradh check if the request will complete in the time it would have taken 46*1571a7a1Sriastradh us to enable the interrupt. 47*1571a7a1Sriastradh 48*1571a7a1Sriastradh May be 0 to disable the initial spin. In practice, we estimate 49*1571a7a1Sriastradh the cost of enabling the interrupt (if currently disabled) to be 50*1571a7a1Sriastradh a few microseconds. 51*1571a7a1Sriastradh 52*1571a7a1Sriastradhconfig DRM_I915_STOP_TIMEOUT 53*1571a7a1Sriastradh int "How long to wait for an engine to quiesce gracefully before reset (ms)" 54*1571a7a1Sriastradh default 100 # milliseconds 55*1571a7a1Sriastradh help 56*1571a7a1Sriastradh By stopping submission and sleeping for a short time before resetting 57*1571a7a1Sriastradh the GPU, we allow the innocent contexts also on the system to quiesce. 58*1571a7a1Sriastradh It is then less likely for a hanging context to cause collateral 59*1571a7a1Sriastradh damage as the system is reset in order to recover. The corollary is 60*1571a7a1Sriastradh that the reset itself may take longer and so be more disruptive to 61*1571a7a1Sriastradh interactive or low latency workloads. 62*1571a7a1Sriastradh 63*1571a7a1Sriastradhconfig DRM_I915_TIMESLICE_DURATION 64*1571a7a1Sriastradh int "Scheduling quantum for userspace batches (ms, jiffy granularity)" 65*1571a7a1Sriastradh default 1 # milliseconds 66*1571a7a1Sriastradh help 67*1571a7a1Sriastradh When two user batches of equal priority are executing, we will 68*1571a7a1Sriastradh alternate execution of each batch to ensure forward progress of 69*1571a7a1Sriastradh all users. This is necessary in some cases where there may be 70*1571a7a1Sriastradh an implicit dependency between those batches that requires 71*1571a7a1Sriastradh concurrent execution in order for them to proceed, e.g. they 72*1571a7a1Sriastradh interact with each other via userspace semaphores. Each context 73*1571a7a1Sriastradh is scheduled for execution for the timeslice duration, before 74*1571a7a1Sriastradh switching to the next context. 75*1571a7a1Sriastradh 76*1571a7a1Sriastradh May be 0 to disable timeslicing. 77