1*677dec6eSriastradh /* $NetBSD: i915_pmu.h,v 1.2 2021/12/18 23:45:28 riastradh Exp $ */ 21571a7a1Sriastradh 31571a7a1Sriastradh /* 41571a7a1Sriastradh * SPDX-License-Identifier: MIT 51571a7a1Sriastradh * 61571a7a1Sriastradh * Copyright © 2017-2018 Intel Corporation 71571a7a1Sriastradh */ 81571a7a1Sriastradh 91571a7a1Sriastradh #ifndef __I915_PMU_H__ 101571a7a1Sriastradh #define __I915_PMU_H__ 111571a7a1Sriastradh 121571a7a1Sriastradh #include <linux/hrtimer.h> 131571a7a1Sriastradh #include <linux/perf_event.h> 141571a7a1Sriastradh #include <linux/spinlock_types.h> 151571a7a1Sriastradh #include <drm/i915_drm.h> 161571a7a1Sriastradh 171571a7a1Sriastradh struct drm_i915_private; 181571a7a1Sriastradh 191571a7a1Sriastradh enum { 201571a7a1Sriastradh __I915_SAMPLE_FREQ_ACT = 0, 211571a7a1Sriastradh __I915_SAMPLE_FREQ_REQ, 221571a7a1Sriastradh __I915_SAMPLE_RC6, 231571a7a1Sriastradh __I915_SAMPLE_RC6_LAST_REPORTED, 241571a7a1Sriastradh __I915_NUM_PMU_SAMPLERS 251571a7a1Sriastradh }; 261571a7a1Sriastradh 271571a7a1Sriastradh /** 281571a7a1Sriastradh * How many different events we track in the global PMU mask. 291571a7a1Sriastradh * 301571a7a1Sriastradh * It is also used to know to needed number of event reference counters. 311571a7a1Sriastradh */ 321571a7a1Sriastradh #define I915_PMU_MASK_BITS \ 331571a7a1Sriastradh ((1 << I915_PMU_SAMPLE_BITS) + \ 341571a7a1Sriastradh (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0))) 351571a7a1Sriastradh 361571a7a1Sriastradh #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1) 371571a7a1Sriastradh 381571a7a1Sriastradh struct i915_pmu_sample { 391571a7a1Sriastradh u64 cur; 401571a7a1Sriastradh }; 411571a7a1Sriastradh 421571a7a1Sriastradh struct i915_pmu { 431571a7a1Sriastradh /** 441571a7a1Sriastradh * @node: List node for CPU hotplug handling. 451571a7a1Sriastradh */ 461571a7a1Sriastradh struct hlist_node node; 471571a7a1Sriastradh /** 481571a7a1Sriastradh * @base: PMU base. 491571a7a1Sriastradh */ 501571a7a1Sriastradh struct pmu base; 511571a7a1Sriastradh /** 521571a7a1Sriastradh * @name: Name as registered with perf core. 531571a7a1Sriastradh */ 541571a7a1Sriastradh const char *name; 551571a7a1Sriastradh /** 561571a7a1Sriastradh * @lock: Lock protecting enable mask and ref count handling. 571571a7a1Sriastradh */ 581571a7a1Sriastradh spinlock_t lock; 591571a7a1Sriastradh /** 601571a7a1Sriastradh * @timer: Timer for internal i915 PMU sampling. 611571a7a1Sriastradh */ 621571a7a1Sriastradh struct hrtimer timer; 631571a7a1Sriastradh /** 641571a7a1Sriastradh * @enable: Bitmask of all currently enabled events. 651571a7a1Sriastradh * 661571a7a1Sriastradh * Bits are derived from uAPI event numbers in a way that low 16 bits 671571a7a1Sriastradh * correspond to engine event _sample_ _type_ (I915_SAMPLE_QUEUED is 681571a7a1Sriastradh * bit 0), and higher bits correspond to other events (for instance 691571a7a1Sriastradh * I915_PMU_ACTUAL_FREQUENCY is bit 16 etc). 701571a7a1Sriastradh * 711571a7a1Sriastradh * In other words, low 16 bits are not per engine but per engine 721571a7a1Sriastradh * sampler type, while the upper bits are directly mapped to other 731571a7a1Sriastradh * event types. 741571a7a1Sriastradh */ 751571a7a1Sriastradh u64 enable; 761571a7a1Sriastradh 771571a7a1Sriastradh /** 781571a7a1Sriastradh * @timer_last: 791571a7a1Sriastradh * 801571a7a1Sriastradh * Timestmap of the previous timer invocation. 811571a7a1Sriastradh */ 821571a7a1Sriastradh ktime_t timer_last; 831571a7a1Sriastradh 841571a7a1Sriastradh /** 851571a7a1Sriastradh * @enable_count: Reference counts for the enabled events. 861571a7a1Sriastradh * 871571a7a1Sriastradh * Array indices are mapped in the same way as bits in the @enable field 881571a7a1Sriastradh * and they are used to control sampling on/off when multiple clients 891571a7a1Sriastradh * are using the PMU API. 901571a7a1Sriastradh */ 911571a7a1Sriastradh unsigned int enable_count[I915_PMU_MASK_BITS]; 921571a7a1Sriastradh /** 931571a7a1Sriastradh * @timer_enabled: Should the internal sampling timer be running. 941571a7a1Sriastradh */ 951571a7a1Sriastradh bool timer_enabled; 961571a7a1Sriastradh /** 971571a7a1Sriastradh * @sample: Current and previous (raw) counters for sampling events. 981571a7a1Sriastradh * 991571a7a1Sriastradh * These counters are updated from the i915 PMU sampling timer. 1001571a7a1Sriastradh * 1011571a7a1Sriastradh * Only global counters are held here, while the per-engine ones are in 1021571a7a1Sriastradh * struct intel_engine_cs. 1031571a7a1Sriastradh */ 1041571a7a1Sriastradh struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS]; 1051571a7a1Sriastradh /** 1061571a7a1Sriastradh * @sleep_last: Last time GT parked for RC6 estimation. 1071571a7a1Sriastradh */ 1081571a7a1Sriastradh ktime_t sleep_last; 1091571a7a1Sriastradh /** 1101571a7a1Sriastradh * @i915_attr: Memory block holding device attributes. 1111571a7a1Sriastradh */ 1121571a7a1Sriastradh void *i915_attr; 1131571a7a1Sriastradh /** 1141571a7a1Sriastradh * @pmu_attr: Memory block holding device attributes. 1151571a7a1Sriastradh */ 1161571a7a1Sriastradh void *pmu_attr; 1171571a7a1Sriastradh }; 1181571a7a1Sriastradh 1191571a7a1Sriastradh #ifdef CONFIG_PERF_EVENTS 1201571a7a1Sriastradh void i915_pmu_register(struct drm_i915_private *i915); 1211571a7a1Sriastradh void i915_pmu_unregister(struct drm_i915_private *i915); 1221571a7a1Sriastradh void i915_pmu_gt_parked(struct drm_i915_private *i915); 1231571a7a1Sriastradh void i915_pmu_gt_unparked(struct drm_i915_private *i915); 1241571a7a1Sriastradh #else i915_pmu_register(struct drm_i915_private * i915)1251571a7a1Sriastradhstatic inline void i915_pmu_register(struct drm_i915_private *i915) {} i915_pmu_unregister(struct drm_i915_private * i915)1261571a7a1Sriastradhstatic inline void i915_pmu_unregister(struct drm_i915_private *i915) {} i915_pmu_gt_parked(struct drm_i915_private * i915)1271571a7a1Sriastradhstatic inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {} i915_pmu_gt_unparked(struct drm_i915_private * i915)1281571a7a1Sriastradhstatic inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {} 1291571a7a1Sriastradh #endif 1301571a7a1Sriastradh 1311571a7a1Sriastradh #endif 132