1*677dec6eSriastradh /* $NetBSD: device.h,v 1.9 2021/12/18 23:45:33 riastradh Exp $ */
2d350ecf5Sriastradh
3*677dec6eSriastradh /* SPDX-License-Identifier: MIT */
4d350ecf5Sriastradh #ifndef __NVKM_DEVICE_H__
5d350ecf5Sriastradh #define __NVKM_DEVICE_H__
6*677dec6eSriastradh #include <core/oclass.h>
7d350ecf5Sriastradh #include <core/event.h>
8d350ecf5Sriastradh
9d350ecf5Sriastradh enum nvkm_devidx {
10d350ecf5Sriastradh NVKM_SUBDEV_PCI,
11d350ecf5Sriastradh NVKM_SUBDEV_VBIOS,
12d350ecf5Sriastradh NVKM_SUBDEV_DEVINIT,
13*677dec6eSriastradh NVKM_SUBDEV_TOP,
14d350ecf5Sriastradh NVKM_SUBDEV_IBUS,
15d350ecf5Sriastradh NVKM_SUBDEV_GPIO,
16d350ecf5Sriastradh NVKM_SUBDEV_I2C,
17d350ecf5Sriastradh NVKM_SUBDEV_FUSE,
18d350ecf5Sriastradh NVKM_SUBDEV_MXM,
19d350ecf5Sriastradh NVKM_SUBDEV_MC,
20d350ecf5Sriastradh NVKM_SUBDEV_BUS,
21d350ecf5Sriastradh NVKM_SUBDEV_TIMER,
22*677dec6eSriastradh NVKM_SUBDEV_INSTMEM,
23d350ecf5Sriastradh NVKM_SUBDEV_FB,
24d350ecf5Sriastradh NVKM_SUBDEV_LTC,
25d350ecf5Sriastradh NVKM_SUBDEV_MMU,
26d350ecf5Sriastradh NVKM_SUBDEV_BAR,
27*677dec6eSriastradh NVKM_SUBDEV_FAULT,
28*677dec6eSriastradh NVKM_SUBDEV_ACR,
29d350ecf5Sriastradh NVKM_SUBDEV_PMU,
30d350ecf5Sriastradh NVKM_SUBDEV_VOLT,
31*677dec6eSriastradh NVKM_SUBDEV_ICCSENSE,
32d350ecf5Sriastradh NVKM_SUBDEV_THERM,
33d350ecf5Sriastradh NVKM_SUBDEV_CLK,
34*677dec6eSriastradh NVKM_SUBDEV_GSP,
35d350ecf5Sriastradh
36d350ecf5Sriastradh NVKM_ENGINE_BSP,
37*677dec6eSriastradh
38d350ecf5Sriastradh NVKM_ENGINE_CE0,
39d350ecf5Sriastradh NVKM_ENGINE_CE1,
40d350ecf5Sriastradh NVKM_ENGINE_CE2,
41*677dec6eSriastradh NVKM_ENGINE_CE3,
42*677dec6eSriastradh NVKM_ENGINE_CE4,
43*677dec6eSriastradh NVKM_ENGINE_CE5,
44*677dec6eSriastradh NVKM_ENGINE_CE6,
45*677dec6eSriastradh NVKM_ENGINE_CE7,
46*677dec6eSriastradh NVKM_ENGINE_CE8,
47*677dec6eSriastradh NVKM_ENGINE_CE_LAST = NVKM_ENGINE_CE8,
48*677dec6eSriastradh
49*677dec6eSriastradh NVKM_ENGINE_CIPHER,
50d350ecf5Sriastradh NVKM_ENGINE_DISP,
51*677dec6eSriastradh NVKM_ENGINE_DMAOBJ,
52*677dec6eSriastradh NVKM_ENGINE_FIFO,
53*677dec6eSriastradh NVKM_ENGINE_GR,
54*677dec6eSriastradh NVKM_ENGINE_IFB,
55*677dec6eSriastradh NVKM_ENGINE_ME,
56*677dec6eSriastradh NVKM_ENGINE_MPEG,
57*677dec6eSriastradh NVKM_ENGINE_MSENC,
58d350ecf5Sriastradh NVKM_ENGINE_MSPDEC,
59*677dec6eSriastradh NVKM_ENGINE_MSPPP,
60*677dec6eSriastradh NVKM_ENGINE_MSVLD,
61*677dec6eSriastradh
62*677dec6eSriastradh NVKM_ENGINE_NVENC0,
63*677dec6eSriastradh NVKM_ENGINE_NVENC1,
64*677dec6eSriastradh NVKM_ENGINE_NVENC2,
65*677dec6eSriastradh NVKM_ENGINE_NVENC_LAST = NVKM_ENGINE_NVENC2,
66*677dec6eSriastradh
67*677dec6eSriastradh NVKM_ENGINE_NVDEC0,
68*677dec6eSriastradh NVKM_ENGINE_NVDEC1,
69*677dec6eSriastradh NVKM_ENGINE_NVDEC2,
70*677dec6eSriastradh NVKM_ENGINE_NVDEC_LAST = NVKM_ENGINE_NVDEC2,
71*677dec6eSriastradh
72*677dec6eSriastradh NVKM_ENGINE_PM,
73*677dec6eSriastradh NVKM_ENGINE_SEC,
74*677dec6eSriastradh NVKM_ENGINE_SEC2,
75*677dec6eSriastradh NVKM_ENGINE_SW,
76*677dec6eSriastradh NVKM_ENGINE_VIC,
77*677dec6eSriastradh NVKM_ENGINE_VP,
78d350ecf5Sriastradh
79d350ecf5Sriastradh NVKM_SUBDEV_NR
80d350ecf5Sriastradh };
81d350ecf5Sriastradh
82d350ecf5Sriastradh enum nvkm_device_type {
83d350ecf5Sriastradh NVKM_DEVICE_PCI,
84d350ecf5Sriastradh NVKM_DEVICE_AGP,
85d350ecf5Sriastradh NVKM_DEVICE_PCIE,
86d350ecf5Sriastradh NVKM_DEVICE_TEGRA,
87d350ecf5Sriastradh };
88d350ecf5Sriastradh
89d350ecf5Sriastradh struct nvkm_device {
90d350ecf5Sriastradh const struct nvkm_device_func *func;
91d350ecf5Sriastradh const struct nvkm_device_quirk *quirk;
92d350ecf5Sriastradh struct device *dev;
93d350ecf5Sriastradh enum nvkm_device_type type;
94d350ecf5Sriastradh u64 handle;
95d350ecf5Sriastradh const char *name;
96d350ecf5Sriastradh const char *cfgopt;
97d350ecf5Sriastradh const char *dbgopt;
98d350ecf5Sriastradh
99d350ecf5Sriastradh struct list_head head;
100d350ecf5Sriastradh struct mutex mutex;
101d350ecf5Sriastradh int refcount;
102d350ecf5Sriastradh
1034e59feabSriastradh #ifdef __NetBSD__
1044e59feabSriastradh bus_space_tag_t mmiot;
1054e59feabSriastradh bus_space_handle_t mmioh;
106a9a34f45Sriastradh bus_addr_t mmioaddr;
1074e59feabSriastradh bus_size_t mmiosz;
1084e59feabSriastradh #else
109d350ecf5Sriastradh void __iomem *pri;
1104e59feabSriastradh #endif
111d350ecf5Sriastradh
112d350ecf5Sriastradh struct nvkm_event event;
113d350ecf5Sriastradh
114d350ecf5Sriastradh u64 disable_mask;
115d350ecf5Sriastradh u32 debug;
116d350ecf5Sriastradh
117d350ecf5Sriastradh const struct nvkm_device_chip *chip;
118d350ecf5Sriastradh enum {
119d350ecf5Sriastradh NV_04 = 0x04,
120d350ecf5Sriastradh NV_10 = 0x10,
121d350ecf5Sriastradh NV_11 = 0x11,
122d350ecf5Sriastradh NV_20 = 0x20,
123d350ecf5Sriastradh NV_30 = 0x30,
124d350ecf5Sriastradh NV_40 = 0x40,
125d350ecf5Sriastradh NV_50 = 0x50,
126d350ecf5Sriastradh NV_C0 = 0xc0,
127d350ecf5Sriastradh NV_E0 = 0xe0,
128d350ecf5Sriastradh GM100 = 0x110,
129*677dec6eSriastradh GP100 = 0x130,
130*677dec6eSriastradh GV100 = 0x140,
131*677dec6eSriastradh TU100 = 0x160,
132d350ecf5Sriastradh } card_type;
133d350ecf5Sriastradh u32 chipset;
134d350ecf5Sriastradh u8 chiprev;
135d350ecf5Sriastradh u32 crystal;
136d350ecf5Sriastradh
137d350ecf5Sriastradh struct {
138d350ecf5Sriastradh struct notifier_block nb;
139d350ecf5Sriastradh } acpi;
140d350ecf5Sriastradh
141*677dec6eSriastradh struct nvkm_acr *acr;
142d350ecf5Sriastradh struct nvkm_bar *bar;
143d350ecf5Sriastradh struct nvkm_bios *bios;
144d350ecf5Sriastradh struct nvkm_bus *bus;
145d350ecf5Sriastradh struct nvkm_clk *clk;
146d350ecf5Sriastradh struct nvkm_devinit *devinit;
147*677dec6eSriastradh struct nvkm_fault *fault;
148d350ecf5Sriastradh struct nvkm_fb *fb;
149d350ecf5Sriastradh struct nvkm_fuse *fuse;
150d350ecf5Sriastradh struct nvkm_gpio *gpio;
151*677dec6eSriastradh struct nvkm_gsp *gsp;
152d350ecf5Sriastradh struct nvkm_i2c *i2c;
153d350ecf5Sriastradh struct nvkm_subdev *ibus;
154*677dec6eSriastradh struct nvkm_iccsense *iccsense;
155d350ecf5Sriastradh struct nvkm_instmem *imem;
156d350ecf5Sriastradh struct nvkm_ltc *ltc;
157d350ecf5Sriastradh struct nvkm_mc *mc;
158d350ecf5Sriastradh struct nvkm_mmu *mmu;
159d350ecf5Sriastradh struct nvkm_subdev *mxm;
160d350ecf5Sriastradh struct nvkm_pci *pci;
161d350ecf5Sriastradh struct nvkm_pmu *pmu;
162d350ecf5Sriastradh struct nvkm_therm *therm;
163d350ecf5Sriastradh struct nvkm_timer *timer;
164*677dec6eSriastradh struct nvkm_top *top;
165d350ecf5Sriastradh struct nvkm_volt *volt;
166d350ecf5Sriastradh
167d350ecf5Sriastradh struct nvkm_engine *bsp;
168*677dec6eSriastradh struct nvkm_engine *ce[9];
169d350ecf5Sriastradh struct nvkm_engine *cipher;
170d350ecf5Sriastradh struct nvkm_disp *disp;
171d350ecf5Sriastradh struct nvkm_dma *dma;
172d350ecf5Sriastradh struct nvkm_fifo *fifo;
173d350ecf5Sriastradh struct nvkm_gr *gr;
174d350ecf5Sriastradh struct nvkm_engine *ifb;
175d350ecf5Sriastradh struct nvkm_engine *me;
176d350ecf5Sriastradh struct nvkm_engine *mpeg;
177d350ecf5Sriastradh struct nvkm_engine *msenc;
178d350ecf5Sriastradh struct nvkm_engine *mspdec;
179d350ecf5Sriastradh struct nvkm_engine *msppp;
180d350ecf5Sriastradh struct nvkm_engine *msvld;
181*677dec6eSriastradh struct nvkm_nvenc *nvenc[3];
182*677dec6eSriastradh struct nvkm_nvdec *nvdec[3];
183d350ecf5Sriastradh struct nvkm_pm *pm;
184d350ecf5Sriastradh struct nvkm_engine *sec;
185*677dec6eSriastradh struct nvkm_sec2 *sec2;
186d350ecf5Sriastradh struct nvkm_sw *sw;
187d350ecf5Sriastradh struct nvkm_engine *vic;
188d350ecf5Sriastradh struct nvkm_engine *vp;
189d350ecf5Sriastradh };
190d350ecf5Sriastradh
191d350ecf5Sriastradh struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index);
192d350ecf5Sriastradh struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int index);
193d350ecf5Sriastradh
194d350ecf5Sriastradh struct nvkm_device_func {
195d350ecf5Sriastradh struct nvkm_device_pci *(*pci)(struct nvkm_device *);
196d350ecf5Sriastradh struct nvkm_device_tegra *(*tegra)(struct nvkm_device *);
197d350ecf5Sriastradh void *(*dtor)(struct nvkm_device *);
198d350ecf5Sriastradh int (*preinit)(struct nvkm_device *);
199d350ecf5Sriastradh int (*init)(struct nvkm_device *);
200d350ecf5Sriastradh void (*fini)(struct nvkm_device *, bool suspend);
2014e59feabSriastradh #ifdef __NetBSD__
2024e59feabSriastradh bus_dma_tag_t (*dma_tag)(struct nvkm_device *);
2034e59feabSriastradh bus_space_tag_t (*resource_tag)(struct nvkm_device *, unsigned bar);
2044e59feabSriastradh #endif
205d350ecf5Sriastradh resource_size_t (*resource_addr)(struct nvkm_device *, unsigned bar);
206d350ecf5Sriastradh resource_size_t (*resource_size)(struct nvkm_device *, unsigned bar);
207d350ecf5Sriastradh bool cpu_coherent;
208d350ecf5Sriastradh };
209d350ecf5Sriastradh
210d350ecf5Sriastradh struct nvkm_device_quirk {
211d350ecf5Sriastradh u8 tv_pin_mask;
212d350ecf5Sriastradh u8 tv_gpio;
213d350ecf5Sriastradh };
214d350ecf5Sriastradh
215d350ecf5Sriastradh struct nvkm_device_chip {
216d350ecf5Sriastradh const char *name;
217d350ecf5Sriastradh
218*677dec6eSriastradh int (*acr )(struct nvkm_device *, int idx, struct nvkm_acr **);
219d350ecf5Sriastradh int (*bar )(struct nvkm_device *, int idx, struct nvkm_bar **);
220d350ecf5Sriastradh int (*bios )(struct nvkm_device *, int idx, struct nvkm_bios **);
221d350ecf5Sriastradh int (*bus )(struct nvkm_device *, int idx, struct nvkm_bus **);
222d350ecf5Sriastradh int (*clk )(struct nvkm_device *, int idx, struct nvkm_clk **);
223d350ecf5Sriastradh int (*devinit )(struct nvkm_device *, int idx, struct nvkm_devinit **);
224*677dec6eSriastradh int (*fault )(struct nvkm_device *, int idx, struct nvkm_fault **);
225d350ecf5Sriastradh int (*fb )(struct nvkm_device *, int idx, struct nvkm_fb **);
226d350ecf5Sriastradh int (*fuse )(struct nvkm_device *, int idx, struct nvkm_fuse **);
227d350ecf5Sriastradh int (*gpio )(struct nvkm_device *, int idx, struct nvkm_gpio **);
228*677dec6eSriastradh int (*gsp )(struct nvkm_device *, int idx, struct nvkm_gsp **);
229d350ecf5Sriastradh int (*i2c )(struct nvkm_device *, int idx, struct nvkm_i2c **);
230d350ecf5Sriastradh int (*ibus )(struct nvkm_device *, int idx, struct nvkm_subdev **);
231*677dec6eSriastradh int (*iccsense)(struct nvkm_device *, int idx, struct nvkm_iccsense **);
232d350ecf5Sriastradh int (*imem )(struct nvkm_device *, int idx, struct nvkm_instmem **);
233d350ecf5Sriastradh int (*ltc )(struct nvkm_device *, int idx, struct nvkm_ltc **);
234d350ecf5Sriastradh int (*mc )(struct nvkm_device *, int idx, struct nvkm_mc **);
235d350ecf5Sriastradh int (*mmu )(struct nvkm_device *, int idx, struct nvkm_mmu **);
236d350ecf5Sriastradh int (*mxm )(struct nvkm_device *, int idx, struct nvkm_subdev **);
237d350ecf5Sriastradh int (*pci )(struct nvkm_device *, int idx, struct nvkm_pci **);
238d350ecf5Sriastradh int (*pmu )(struct nvkm_device *, int idx, struct nvkm_pmu **);
239d350ecf5Sriastradh int (*therm )(struct nvkm_device *, int idx, struct nvkm_therm **);
240d350ecf5Sriastradh int (*timer )(struct nvkm_device *, int idx, struct nvkm_timer **);
241*677dec6eSriastradh int (*top )(struct nvkm_device *, int idx, struct nvkm_top **);
242d350ecf5Sriastradh int (*volt )(struct nvkm_device *, int idx, struct nvkm_volt **);
243d350ecf5Sriastradh
244d350ecf5Sriastradh int (*bsp )(struct nvkm_device *, int idx, struct nvkm_engine **);
245*677dec6eSriastradh int (*ce[9] )(struct nvkm_device *, int idx, struct nvkm_engine **);
246d350ecf5Sriastradh int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **);
247d350ecf5Sriastradh int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **);
248d350ecf5Sriastradh int (*dma )(struct nvkm_device *, int idx, struct nvkm_dma **);
249d350ecf5Sriastradh int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **);
250d350ecf5Sriastradh int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **);
251d350ecf5Sriastradh int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **);
252d350ecf5Sriastradh int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **);
253d350ecf5Sriastradh int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **);
254d350ecf5Sriastradh int (*msenc )(struct nvkm_device *, int idx, struct nvkm_engine **);
255d350ecf5Sriastradh int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **);
256d350ecf5Sriastradh int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **);
257d350ecf5Sriastradh int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **);
258*677dec6eSriastradh int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_nvenc **);
259*677dec6eSriastradh int (*nvdec[3])(struct nvkm_device *, int idx, struct nvkm_nvdec **);
260d350ecf5Sriastradh int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **);
261d350ecf5Sriastradh int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **);
262*677dec6eSriastradh int (*sec2 )(struct nvkm_device *, int idx, struct nvkm_sec2 **);
263d350ecf5Sriastradh int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **);
264d350ecf5Sriastradh int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **);
265d350ecf5Sriastradh int (*vp )(struct nvkm_device *, int idx, struct nvkm_engine **);
266d350ecf5Sriastradh };
267d350ecf5Sriastradh
268d350ecf5Sriastradh struct nvkm_device *nvkm_device_find(u64 name);
269d350ecf5Sriastradh int nvkm_device_list(u64 *name, int size);
270d350ecf5Sriastradh
2714e59feabSriastradh #ifdef __NetBSD__
272639498f7Sriastradh void nvkm_devices_init(void);
273639498f7Sriastradh void nvkm_devices_fini(void);
2744e59feabSriastradh #endif
2754e59feabSriastradh
276d350ecf5Sriastradh /* privileged register interface accessor macros */
2774e59feabSriastradh #ifdef __NetBSD__
2784e59feabSriastradh static inline uint8_t
nvkm_rd08(struct nvkm_device * d,bus_size_t a)2794e59feabSriastradh nvkm_rd08(struct nvkm_device *d, bus_size_t a)
2804e59feabSriastradh {
2814e59feabSriastradh return bus_space_read_1(d->mmiot, d->mmioh, a);
2824e59feabSriastradh }
2834e59feabSriastradh static inline uint16_t
nvkm_rd16(struct nvkm_device * d,bus_size_t a)2844e59feabSriastradh nvkm_rd16(struct nvkm_device *d, bus_size_t a)
2854e59feabSriastradh {
2864e59feabSriastradh return bus_space_read_stream_2(d->mmiot, d->mmioh, a);
2874e59feabSriastradh }
2884e59feabSriastradh static inline uint32_t
nvkm_rd32(struct nvkm_device * d,bus_size_t a)2894e59feabSriastradh nvkm_rd32(struct nvkm_device *d, bus_size_t a)
2904e59feabSriastradh {
2914e59feabSriastradh return bus_space_read_stream_4(d->mmiot, d->mmioh, a);
2924e59feabSriastradh }
2934e59feabSriastradh static inline void
nvkm_wr08(struct nvkm_device * d,bus_size_t a,uint8_t v)2944e59feabSriastradh nvkm_wr08(struct nvkm_device *d, bus_size_t a, uint8_t v)
2954e59feabSriastradh {
29685f1dbcdSmrg bus_space_write_1(d->mmiot, d->mmioh, a, v);
2974e59feabSriastradh }
2984e59feabSriastradh static inline void
nvkm_wr16(struct nvkm_device * d,bus_size_t a,uint16_t v)2994e59feabSriastradh nvkm_wr16(struct nvkm_device *d, bus_size_t a, uint16_t v)
3004e59feabSriastradh {
30185f1dbcdSmrg bus_space_write_stream_2(d->mmiot, d->mmioh, a, v);
3024e59feabSriastradh }
3034e59feabSriastradh static inline void
nvkm_wr32(struct nvkm_device * d,bus_size_t a,uint32_t v)304461f3f63Sriastradh nvkm_wr32(struct nvkm_device *d, bus_size_t a, uint32_t v)
3054e59feabSriastradh {
30685f1dbcdSmrg bus_space_write_stream_4(d->mmiot, d->mmioh, a, v);
3074e59feabSriastradh }
3084e59feabSriastradh #else
309d350ecf5Sriastradh #define nvkm_rd08(d,a) ioread8((d)->pri + (a))
310d350ecf5Sriastradh #define nvkm_rd16(d,a) ioread16_native((d)->pri + (a))
311d350ecf5Sriastradh #define nvkm_rd32(d,a) ioread32_native((d)->pri + (a))
312d350ecf5Sriastradh #define nvkm_wr08(d,a,v) iowrite8((v), (d)->pri + (a))
313d350ecf5Sriastradh #define nvkm_wr16(d,a,v) iowrite16_native((v), (d)->pri + (a))
314d350ecf5Sriastradh #define nvkm_wr32(d,a,v) iowrite32_native((v), (d)->pri + (a))
3154e59feabSriastradh #endif
316d350ecf5Sriastradh #define nvkm_mask(d,a,m,v) ({ \
317d350ecf5Sriastradh struct nvkm_device *_device = (d); \
318d350ecf5Sriastradh u32 _addr = (a), _temp = nvkm_rd32(_device, _addr); \
319d350ecf5Sriastradh nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v)); \
320d350ecf5Sriastradh _temp; \
321d350ecf5Sriastradh })
322d350ecf5Sriastradh
323d350ecf5Sriastradh void nvkm_device_del(struct nvkm_device **);
324d350ecf5Sriastradh
325d350ecf5Sriastradh struct nvkm_device_oclass {
326d350ecf5Sriastradh int (*ctor)(struct nvkm_device *, const struct nvkm_oclass *,
327d350ecf5Sriastradh void *data, u32 size, struct nvkm_object **);
328d350ecf5Sriastradh struct nvkm_sclass base;
329d350ecf5Sriastradh };
330d350ecf5Sriastradh
331d350ecf5Sriastradh extern const struct nvkm_sclass nvkm_udevice_sclass;
332d350ecf5Sriastradh
333d350ecf5Sriastradh /* device logging */
334d350ecf5Sriastradh #define nvdev_printk_(d,l,p,f,a...) do { \
335*677dec6eSriastradh const struct nvkm_device *_device = (d); \
336d350ecf5Sriastradh if (_device->debug >= (l)) \
337d350ecf5Sriastradh dev_##p(_device->dev, f, ##a); \
338d350ecf5Sriastradh } while(0)
339d350ecf5Sriastradh #define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a)
340d350ecf5Sriastradh #define nvdev_fatal(d,f,a...) nvdev_printk((d), FATAL, crit, f, ##a)
341d350ecf5Sriastradh #define nvdev_error(d,f,a...) nvdev_printk((d), ERROR, err, f, ##a)
342d350ecf5Sriastradh #define nvdev_warn(d,f,a...) nvdev_printk((d), WARN, notice, f, ##a)
343d350ecf5Sriastradh #define nvdev_info(d,f,a...) nvdev_printk((d), INFO, info, f, ##a)
344d350ecf5Sriastradh #define nvdev_debug(d,f,a...) nvdev_printk((d), DEBUG, info, f, ##a)
345d350ecf5Sriastradh #define nvdev_trace(d,f,a...) nvdev_printk((d), TRACE, info, f, ##a)
346d350ecf5Sriastradh #define nvdev_spam(d,f,a...) nvdev_printk((d), SPAM, dbg, f, ##a)
347d350ecf5Sriastradh #endif
348