1*677dec6eSriastradh /* $NetBSD: radeon_btc_dpm.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */ 2d8817e4aSriastradh 3d8817e4aSriastradh /* 4d8817e4aSriastradh * Copyright 2011 Advanced Micro Devices, Inc. 5d8817e4aSriastradh * 6d8817e4aSriastradh * Permission is hereby granted, free of charge, to any person obtaining a 7d8817e4aSriastradh * copy of this software and associated documentation files (the "Software"), 8d8817e4aSriastradh * to deal in the Software without restriction, including without limitation 9d8817e4aSriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10d8817e4aSriastradh * and/or sell copies of the Software, and to permit persons to whom the 11d8817e4aSriastradh * Software is furnished to do so, subject to the following conditions: 12d8817e4aSriastradh * 13d8817e4aSriastradh * The above copyright notice and this permission notice shall be included in 14d8817e4aSriastradh * all copies or substantial portions of the Software. 15d8817e4aSriastradh * 16d8817e4aSriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d8817e4aSriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d8817e4aSriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d8817e4aSriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20d8817e4aSriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21d8817e4aSriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22d8817e4aSriastradh * OTHER DEALINGS IN THE SOFTWARE. 23d8817e4aSriastradh * 24d8817e4aSriastradh * Authors: Alex Deucher 25d8817e4aSriastradh */ 26d8817e4aSriastradh 27d8817e4aSriastradh #include <sys/cdefs.h> 28*677dec6eSriastradh __KERNEL_RCSID(0, "$NetBSD: radeon_btc_dpm.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $"); 29d8817e4aSriastradh 301571a7a1Sriastradh #include <linux/pci.h> 311571a7a1Sriastradh #include <linux/seq_file.h> 321571a7a1Sriastradh 331571a7a1Sriastradh #include "atom.h" 341571a7a1Sriastradh #include "btc_dpm.h" 351571a7a1Sriastradh #include "btcd.h" 361571a7a1Sriastradh #include "cypress_dpm.h" 371571a7a1Sriastradh #include "r600_dpm.h" 38d8817e4aSriastradh #include "radeon.h" 39d8817e4aSriastradh #include "radeon_asic.h" 40d8817e4aSriastradh 41d8817e4aSriastradh #define MC_CG_ARB_FREQ_F0 0x0a 42d8817e4aSriastradh #define MC_CG_ARB_FREQ_F1 0x0b 43d8817e4aSriastradh #define MC_CG_ARB_FREQ_F2 0x0c 44d8817e4aSriastradh #define MC_CG_ARB_FREQ_F3 0x0d 45d8817e4aSriastradh 46d8817e4aSriastradh #define MC_CG_SEQ_DRAMCONF_S0 0x05 47d8817e4aSriastradh #define MC_CG_SEQ_DRAMCONF_S1 0x06 48d8817e4aSriastradh #define MC_CG_SEQ_YCLK_SUSPEND 0x04 49d8817e4aSriastradh #define MC_CG_SEQ_YCLK_RESUME 0x0a 50d8817e4aSriastradh 51d8817e4aSriastradh #define SMC_RAM_END 0x8000 52d8817e4aSriastradh 53d8817e4aSriastradh #ifndef BTC_MGCG_SEQUENCE 54d8817e4aSriastradh #define BTC_MGCG_SEQUENCE 300 55d8817e4aSriastradh 56d8817e4aSriastradh struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps); 57d8817e4aSriastradh struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 58d8817e4aSriastradh struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 59d8817e4aSriastradh 60d8817e4aSriastradh extern int ni_mc_load_microcode(struct radeon_device *rdev); 61d8817e4aSriastradh 62d8817e4aSriastradh //********* BARTS **************// 63d8817e4aSriastradh static const u32 barts_cgcg_cgls_default[] = 64d8817e4aSriastradh { 65d8817e4aSriastradh /* Register, Value, Mask bits */ 66d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 67d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 68d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 69d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 70d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 71d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 72d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 73d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 74d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 75d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 76d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 77d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 78d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 79d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 80d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 81d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 82d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 83d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 84d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 85d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 86d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 87d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 88d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 89d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 90d8817e4aSriastradh 0x000008f8, 0x00000020, 0xffffffff, 91d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 92d8817e4aSriastradh 0x000008f8, 0x00000021, 0xffffffff, 93d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 94d8817e4aSriastradh 0x000008f8, 0x00000022, 0xffffffff, 95d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 96d8817e4aSriastradh 0x000008f8, 0x00000023, 0xffffffff, 97d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 98d8817e4aSriastradh 0x000008f8, 0x00000024, 0xffffffff, 99d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 100d8817e4aSriastradh 0x000008f8, 0x00000025, 0xffffffff, 101d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 102d8817e4aSriastradh 0x000008f8, 0x00000026, 0xffffffff, 103d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 104d8817e4aSriastradh 0x000008f8, 0x00000027, 0xffffffff, 105d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 106d8817e4aSriastradh 0x000008f8, 0x00000028, 0xffffffff, 107d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 108d8817e4aSriastradh 0x000008f8, 0x00000029, 0xffffffff, 109d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 110d8817e4aSriastradh 0x000008f8, 0x0000002a, 0xffffffff, 111d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 112d8817e4aSriastradh 0x000008f8, 0x0000002b, 0xffffffff, 113d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff 114d8817e4aSriastradh }; 115d8817e4aSriastradh #define BARTS_CGCG_CGLS_DEFAULT_LENGTH sizeof(barts_cgcg_cgls_default) / (3 * sizeof(u32)) 116d8817e4aSriastradh 117d8817e4aSriastradh static const u32 barts_cgcg_cgls_disable[] = 118d8817e4aSriastradh { 119d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 120d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 121d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 122d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 123d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 124d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 125d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 126d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 127d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 128d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 129d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 130d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 131d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 132d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 133d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 134d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 135d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 136d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 137d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 138d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 139d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 140d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 141d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 142d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 143d8817e4aSriastradh 0x000008f8, 0x00000020, 0xffffffff, 144d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 145d8817e4aSriastradh 0x000008f8, 0x00000021, 0xffffffff, 146d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 147d8817e4aSriastradh 0x000008f8, 0x00000022, 0xffffffff, 148d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 149d8817e4aSriastradh 0x000008f8, 0x00000023, 0xffffffff, 150d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 151d8817e4aSriastradh 0x000008f8, 0x00000024, 0xffffffff, 152d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 153d8817e4aSriastradh 0x000008f8, 0x00000025, 0xffffffff, 154d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 155d8817e4aSriastradh 0x000008f8, 0x00000026, 0xffffffff, 156d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 157d8817e4aSriastradh 0x000008f8, 0x00000027, 0xffffffff, 158d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 159d8817e4aSriastradh 0x000008f8, 0x00000028, 0xffffffff, 160d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 161d8817e4aSriastradh 0x000008f8, 0x00000029, 0xffffffff, 162d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 163d8817e4aSriastradh 0x000008f8, 0x0000002a, 0xffffffff, 164d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 165d8817e4aSriastradh 0x000008f8, 0x0000002b, 0xffffffff, 166d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 167d8817e4aSriastradh 0x00000644, 0x000f7912, 0x001f4180, 168d8817e4aSriastradh 0x00000644, 0x000f3812, 0x001f4180 169d8817e4aSriastradh }; 170d8817e4aSriastradh #define BARTS_CGCG_CGLS_DISABLE_LENGTH sizeof(barts_cgcg_cgls_disable) / (3 * sizeof(u32)) 171d8817e4aSriastradh 172d8817e4aSriastradh static const u32 barts_cgcg_cgls_enable[] = 173d8817e4aSriastradh { 174d8817e4aSriastradh /* 0x0000c124, 0x84180000, 0x00180000, */ 175d8817e4aSriastradh 0x00000644, 0x000f7892, 0x001f4080, 176d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 177d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 178d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 179d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 180d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 181d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 182d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 183d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 184d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 185d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 186d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 187d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 188d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 189d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 190d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 191d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 192d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 193d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 194d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 195d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 196d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 197d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 198d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 199d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 200d8817e4aSriastradh 0x000008f8, 0x00000020, 0xffffffff, 201d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 202d8817e4aSriastradh 0x000008f8, 0x00000021, 0xffffffff, 203d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 204d8817e4aSriastradh 0x000008f8, 0x00000022, 0xffffffff, 205d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 206d8817e4aSriastradh 0x000008f8, 0x00000023, 0xffffffff, 207d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 208d8817e4aSriastradh 0x000008f8, 0x00000024, 0xffffffff, 209d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 210d8817e4aSriastradh 0x000008f8, 0x00000025, 0xffffffff, 211d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 212d8817e4aSriastradh 0x000008f8, 0x00000026, 0xffffffff, 213d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 214d8817e4aSriastradh 0x000008f8, 0x00000027, 0xffffffff, 215d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 216d8817e4aSriastradh 0x000008f8, 0x00000028, 0xffffffff, 217d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 218d8817e4aSriastradh 0x000008f8, 0x00000029, 0xffffffff, 219d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 220d8817e4aSriastradh 0x000008f8, 0x0000002a, 0xffffffff, 221d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 222d8817e4aSriastradh 0x000008f8, 0x0000002b, 0xffffffff, 223d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff 224d8817e4aSriastradh }; 225d8817e4aSriastradh #define BARTS_CGCG_CGLS_ENABLE_LENGTH sizeof(barts_cgcg_cgls_enable) / (3 * sizeof(u32)) 226d8817e4aSriastradh 227d8817e4aSriastradh static const u32 barts_mgcg_default[] = 228d8817e4aSriastradh { 229d8817e4aSriastradh 0x0000802c, 0xc0000000, 0xffffffff, 230d8817e4aSriastradh 0x00005448, 0x00000100, 0xffffffff, 231d8817e4aSriastradh 0x000055e4, 0x00600100, 0xffffffff, 232d8817e4aSriastradh 0x0000160c, 0x00000100, 0xffffffff, 233d8817e4aSriastradh 0x0000c164, 0x00000100, 0xffffffff, 234d8817e4aSriastradh 0x00008a18, 0x00000100, 0xffffffff, 235d8817e4aSriastradh 0x0000897c, 0x06000100, 0xffffffff, 236d8817e4aSriastradh 0x00008b28, 0x00000100, 0xffffffff, 237d8817e4aSriastradh 0x00009144, 0x00000100, 0xffffffff, 238d8817e4aSriastradh 0x00009a60, 0x00000100, 0xffffffff, 239d8817e4aSriastradh 0x00009868, 0x00000100, 0xffffffff, 240d8817e4aSriastradh 0x00008d58, 0x00000100, 0xffffffff, 241d8817e4aSriastradh 0x00009510, 0x00000100, 0xffffffff, 242d8817e4aSriastradh 0x0000949c, 0x00000100, 0xffffffff, 243d8817e4aSriastradh 0x00009654, 0x00000100, 0xffffffff, 244d8817e4aSriastradh 0x00009030, 0x00000100, 0xffffffff, 245d8817e4aSriastradh 0x00009034, 0x00000100, 0xffffffff, 246d8817e4aSriastradh 0x00009038, 0x00000100, 0xffffffff, 247d8817e4aSriastradh 0x0000903c, 0x00000100, 0xffffffff, 248d8817e4aSriastradh 0x00009040, 0x00000100, 0xffffffff, 249d8817e4aSriastradh 0x0000a200, 0x00000100, 0xffffffff, 250d8817e4aSriastradh 0x0000a204, 0x00000100, 0xffffffff, 251d8817e4aSriastradh 0x0000a208, 0x00000100, 0xffffffff, 252d8817e4aSriastradh 0x0000a20c, 0x00000100, 0xffffffff, 253d8817e4aSriastradh 0x0000977c, 0x00000100, 0xffffffff, 254d8817e4aSriastradh 0x00003f80, 0x00000100, 0xffffffff, 255d8817e4aSriastradh 0x0000a210, 0x00000100, 0xffffffff, 256d8817e4aSriastradh 0x0000a214, 0x00000100, 0xffffffff, 257d8817e4aSriastradh 0x000004d8, 0x00000100, 0xffffffff, 258d8817e4aSriastradh 0x00009784, 0x00000100, 0xffffffff, 259d8817e4aSriastradh 0x00009698, 0x00000100, 0xffffffff, 260d8817e4aSriastradh 0x000004d4, 0x00000200, 0xffffffff, 261d8817e4aSriastradh 0x000004d0, 0x00000000, 0xffffffff, 262d8817e4aSriastradh 0x000030cc, 0x00000100, 0xffffffff, 263d8817e4aSriastradh 0x0000d0c0, 0xff000100, 0xffffffff, 264d8817e4aSriastradh 0x0000802c, 0x40000000, 0xffffffff, 265d8817e4aSriastradh 0x0000915c, 0x00010000, 0xffffffff, 266d8817e4aSriastradh 0x00009160, 0x00030002, 0xffffffff, 267d8817e4aSriastradh 0x00009164, 0x00050004, 0xffffffff, 268d8817e4aSriastradh 0x00009168, 0x00070006, 0xffffffff, 269d8817e4aSriastradh 0x00009178, 0x00070000, 0xffffffff, 270d8817e4aSriastradh 0x0000917c, 0x00030002, 0xffffffff, 271d8817e4aSriastradh 0x00009180, 0x00050004, 0xffffffff, 272d8817e4aSriastradh 0x0000918c, 0x00010006, 0xffffffff, 273d8817e4aSriastradh 0x00009190, 0x00090008, 0xffffffff, 274d8817e4aSriastradh 0x00009194, 0x00070000, 0xffffffff, 275d8817e4aSriastradh 0x00009198, 0x00030002, 0xffffffff, 276d8817e4aSriastradh 0x0000919c, 0x00050004, 0xffffffff, 277d8817e4aSriastradh 0x000091a8, 0x00010006, 0xffffffff, 278d8817e4aSriastradh 0x000091ac, 0x00090008, 0xffffffff, 279d8817e4aSriastradh 0x000091b0, 0x00070000, 0xffffffff, 280d8817e4aSriastradh 0x000091b4, 0x00030002, 0xffffffff, 281d8817e4aSriastradh 0x000091b8, 0x00050004, 0xffffffff, 282d8817e4aSriastradh 0x000091c4, 0x00010006, 0xffffffff, 283d8817e4aSriastradh 0x000091c8, 0x00090008, 0xffffffff, 284d8817e4aSriastradh 0x000091cc, 0x00070000, 0xffffffff, 285d8817e4aSriastradh 0x000091d0, 0x00030002, 0xffffffff, 286d8817e4aSriastradh 0x000091d4, 0x00050004, 0xffffffff, 287d8817e4aSriastradh 0x000091e0, 0x00010006, 0xffffffff, 288d8817e4aSriastradh 0x000091e4, 0x00090008, 0xffffffff, 289d8817e4aSriastradh 0x000091e8, 0x00000000, 0xffffffff, 290d8817e4aSriastradh 0x000091ec, 0x00070000, 0xffffffff, 291d8817e4aSriastradh 0x000091f0, 0x00030002, 0xffffffff, 292d8817e4aSriastradh 0x000091f4, 0x00050004, 0xffffffff, 293d8817e4aSriastradh 0x00009200, 0x00010006, 0xffffffff, 294d8817e4aSriastradh 0x00009204, 0x00090008, 0xffffffff, 295d8817e4aSriastradh 0x00009208, 0x00070000, 0xffffffff, 296d8817e4aSriastradh 0x0000920c, 0x00030002, 0xffffffff, 297d8817e4aSriastradh 0x00009210, 0x00050004, 0xffffffff, 298d8817e4aSriastradh 0x0000921c, 0x00010006, 0xffffffff, 299d8817e4aSriastradh 0x00009220, 0x00090008, 0xffffffff, 300d8817e4aSriastradh 0x00009224, 0x00070000, 0xffffffff, 301d8817e4aSriastradh 0x00009228, 0x00030002, 0xffffffff, 302d8817e4aSriastradh 0x0000922c, 0x00050004, 0xffffffff, 303d8817e4aSriastradh 0x00009238, 0x00010006, 0xffffffff, 304d8817e4aSriastradh 0x0000923c, 0x00090008, 0xffffffff, 305d8817e4aSriastradh 0x00009294, 0x00000000, 0xffffffff, 306d8817e4aSriastradh 0x0000802c, 0x40010000, 0xffffffff, 307d8817e4aSriastradh 0x0000915c, 0x00010000, 0xffffffff, 308d8817e4aSriastradh 0x00009160, 0x00030002, 0xffffffff, 309d8817e4aSriastradh 0x00009164, 0x00050004, 0xffffffff, 310d8817e4aSriastradh 0x00009168, 0x00070006, 0xffffffff, 311d8817e4aSriastradh 0x00009178, 0x00070000, 0xffffffff, 312d8817e4aSriastradh 0x0000917c, 0x00030002, 0xffffffff, 313d8817e4aSriastradh 0x00009180, 0x00050004, 0xffffffff, 314d8817e4aSriastradh 0x0000918c, 0x00010006, 0xffffffff, 315d8817e4aSriastradh 0x00009190, 0x00090008, 0xffffffff, 316d8817e4aSriastradh 0x00009194, 0x00070000, 0xffffffff, 317d8817e4aSriastradh 0x00009198, 0x00030002, 0xffffffff, 318d8817e4aSriastradh 0x0000919c, 0x00050004, 0xffffffff, 319d8817e4aSriastradh 0x000091a8, 0x00010006, 0xffffffff, 320d8817e4aSriastradh 0x000091ac, 0x00090008, 0xffffffff, 321d8817e4aSriastradh 0x000091b0, 0x00070000, 0xffffffff, 322d8817e4aSriastradh 0x000091b4, 0x00030002, 0xffffffff, 323d8817e4aSriastradh 0x000091b8, 0x00050004, 0xffffffff, 324d8817e4aSriastradh 0x000091c4, 0x00010006, 0xffffffff, 325d8817e4aSriastradh 0x000091c8, 0x00090008, 0xffffffff, 326d8817e4aSriastradh 0x000091cc, 0x00070000, 0xffffffff, 327d8817e4aSriastradh 0x000091d0, 0x00030002, 0xffffffff, 328d8817e4aSriastradh 0x000091d4, 0x00050004, 0xffffffff, 329d8817e4aSriastradh 0x000091e0, 0x00010006, 0xffffffff, 330d8817e4aSriastradh 0x000091e4, 0x00090008, 0xffffffff, 331d8817e4aSriastradh 0x000091e8, 0x00000000, 0xffffffff, 332d8817e4aSriastradh 0x000091ec, 0x00070000, 0xffffffff, 333d8817e4aSriastradh 0x000091f0, 0x00030002, 0xffffffff, 334d8817e4aSriastradh 0x000091f4, 0x00050004, 0xffffffff, 335d8817e4aSriastradh 0x00009200, 0x00010006, 0xffffffff, 336d8817e4aSriastradh 0x00009204, 0x00090008, 0xffffffff, 337d8817e4aSriastradh 0x00009208, 0x00070000, 0xffffffff, 338d8817e4aSriastradh 0x0000920c, 0x00030002, 0xffffffff, 339d8817e4aSriastradh 0x00009210, 0x00050004, 0xffffffff, 340d8817e4aSriastradh 0x0000921c, 0x00010006, 0xffffffff, 341d8817e4aSriastradh 0x00009220, 0x00090008, 0xffffffff, 342d8817e4aSriastradh 0x00009224, 0x00070000, 0xffffffff, 343d8817e4aSriastradh 0x00009228, 0x00030002, 0xffffffff, 344d8817e4aSriastradh 0x0000922c, 0x00050004, 0xffffffff, 345d8817e4aSriastradh 0x00009238, 0x00010006, 0xffffffff, 346d8817e4aSriastradh 0x0000923c, 0x00090008, 0xffffffff, 347d8817e4aSriastradh 0x00009294, 0x00000000, 0xffffffff, 348d8817e4aSriastradh 0x0000802c, 0xc0000000, 0xffffffff, 349d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 350d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 351d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 352d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 353d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 354d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 355d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 356d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 357d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 358d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 359d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 360d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 361d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 362d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 363d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 364d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 365d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 366d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 367d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 368d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 369d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 370d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 371d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 372d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff 373d8817e4aSriastradh }; 374d8817e4aSriastradh #define BARTS_MGCG_DEFAULT_LENGTH sizeof(barts_mgcg_default) / (3 * sizeof(u32)) 375d8817e4aSriastradh 376d8817e4aSriastradh static const u32 barts_mgcg_disable[] = 377d8817e4aSriastradh { 378d8817e4aSriastradh 0x0000802c, 0xc0000000, 0xffffffff, 379d8817e4aSriastradh 0x000008f8, 0x00000000, 0xffffffff, 380d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 381d8817e4aSriastradh 0x000008f8, 0x00000001, 0xffffffff, 382d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 383d8817e4aSriastradh 0x000008f8, 0x00000002, 0xffffffff, 384d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 385d8817e4aSriastradh 0x000008f8, 0x00000003, 0xffffffff, 386d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 387d8817e4aSriastradh 0x00009150, 0x00600000, 0xffffffff 388d8817e4aSriastradh }; 389d8817e4aSriastradh #define BARTS_MGCG_DISABLE_LENGTH sizeof(barts_mgcg_disable) / (3 * sizeof(u32)) 390d8817e4aSriastradh 391d8817e4aSriastradh static const u32 barts_mgcg_enable[] = 392d8817e4aSriastradh { 393d8817e4aSriastradh 0x0000802c, 0xc0000000, 0xffffffff, 394d8817e4aSriastradh 0x000008f8, 0x00000000, 0xffffffff, 395d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 396d8817e4aSriastradh 0x000008f8, 0x00000001, 0xffffffff, 397d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 398d8817e4aSriastradh 0x000008f8, 0x00000002, 0xffffffff, 399d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 400d8817e4aSriastradh 0x000008f8, 0x00000003, 0xffffffff, 401d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 402d8817e4aSriastradh 0x00009150, 0x81944000, 0xffffffff 403d8817e4aSriastradh }; 404d8817e4aSriastradh #define BARTS_MGCG_ENABLE_LENGTH sizeof(barts_mgcg_enable) / (3 * sizeof(u32)) 405d8817e4aSriastradh 406d8817e4aSriastradh //********* CAICOS **************// 407d8817e4aSriastradh static const u32 caicos_cgcg_cgls_default[] = 408d8817e4aSriastradh { 409d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 410d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 411d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 412d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 413d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 414d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 415d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 416d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 417d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 418d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 419d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 420d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 421d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 422d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 423d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 424d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 425d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 426d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 427d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 428d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 429d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 430d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 431d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 432d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 433d8817e4aSriastradh 0x000008f8, 0x00000020, 0xffffffff, 434d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 435d8817e4aSriastradh 0x000008f8, 0x00000021, 0xffffffff, 436d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 437d8817e4aSriastradh 0x000008f8, 0x00000022, 0xffffffff, 438d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 439d8817e4aSriastradh 0x000008f8, 0x00000023, 0xffffffff, 440d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 441d8817e4aSriastradh 0x000008f8, 0x00000024, 0xffffffff, 442d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 443d8817e4aSriastradh 0x000008f8, 0x00000025, 0xffffffff, 444d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 445d8817e4aSriastradh 0x000008f8, 0x00000026, 0xffffffff, 446d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 447d8817e4aSriastradh 0x000008f8, 0x00000027, 0xffffffff, 448d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 449d8817e4aSriastradh 0x000008f8, 0x00000028, 0xffffffff, 450d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 451d8817e4aSriastradh 0x000008f8, 0x00000029, 0xffffffff, 452d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 453d8817e4aSriastradh 0x000008f8, 0x0000002a, 0xffffffff, 454d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 455d8817e4aSriastradh 0x000008f8, 0x0000002b, 0xffffffff, 456d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff 457d8817e4aSriastradh }; 458d8817e4aSriastradh #define CAICOS_CGCG_CGLS_DEFAULT_LENGTH sizeof(caicos_cgcg_cgls_default) / (3 * sizeof(u32)) 459d8817e4aSriastradh 460d8817e4aSriastradh static const u32 caicos_cgcg_cgls_disable[] = 461d8817e4aSriastradh { 462d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 463d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 464d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 465d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 466d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 467d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 468d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 469d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 470d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 471d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 472d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 473d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 474d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 475d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 476d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 477d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 478d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 479d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 480d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 481d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 482d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 483d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 484d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 485d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 486d8817e4aSriastradh 0x000008f8, 0x00000020, 0xffffffff, 487d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 488d8817e4aSriastradh 0x000008f8, 0x00000021, 0xffffffff, 489d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 490d8817e4aSriastradh 0x000008f8, 0x00000022, 0xffffffff, 491d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 492d8817e4aSriastradh 0x000008f8, 0x00000023, 0xffffffff, 493d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 494d8817e4aSriastradh 0x000008f8, 0x00000024, 0xffffffff, 495d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 496d8817e4aSriastradh 0x000008f8, 0x00000025, 0xffffffff, 497d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 498d8817e4aSriastradh 0x000008f8, 0x00000026, 0xffffffff, 499d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 500d8817e4aSriastradh 0x000008f8, 0x00000027, 0xffffffff, 501d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 502d8817e4aSriastradh 0x000008f8, 0x00000028, 0xffffffff, 503d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 504d8817e4aSriastradh 0x000008f8, 0x00000029, 0xffffffff, 505d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 506d8817e4aSriastradh 0x000008f8, 0x0000002a, 0xffffffff, 507d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 508d8817e4aSriastradh 0x000008f8, 0x0000002b, 0xffffffff, 509d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 510d8817e4aSriastradh 0x00000644, 0x000f7912, 0x001f4180, 511d8817e4aSriastradh 0x00000644, 0x000f3812, 0x001f4180 512d8817e4aSriastradh }; 513d8817e4aSriastradh #define CAICOS_CGCG_CGLS_DISABLE_LENGTH sizeof(caicos_cgcg_cgls_disable) / (3 * sizeof(u32)) 514d8817e4aSriastradh 515d8817e4aSriastradh static const u32 caicos_cgcg_cgls_enable[] = 516d8817e4aSriastradh { 517d8817e4aSriastradh /* 0x0000c124, 0x84180000, 0x00180000, */ 518d8817e4aSriastradh 0x00000644, 0x000f7892, 0x001f4080, 519d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 520d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 521d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 522d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 523d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 524d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 525d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 526d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 527d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 528d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 529d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 530d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 531d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 532d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 533d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 534d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 535d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 536d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 537d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 538d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 539d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 540d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 541d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 542d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 543d8817e4aSriastradh 0x000008f8, 0x00000020, 0xffffffff, 544d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 545d8817e4aSriastradh 0x000008f8, 0x00000021, 0xffffffff, 546d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 547d8817e4aSriastradh 0x000008f8, 0x00000022, 0xffffffff, 548d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 549d8817e4aSriastradh 0x000008f8, 0x00000023, 0xffffffff, 550d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 551d8817e4aSriastradh 0x000008f8, 0x00000024, 0xffffffff, 552d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 553d8817e4aSriastradh 0x000008f8, 0x00000025, 0xffffffff, 554d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 555d8817e4aSriastradh 0x000008f8, 0x00000026, 0xffffffff, 556d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 557d8817e4aSriastradh 0x000008f8, 0x00000027, 0xffffffff, 558d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 559d8817e4aSriastradh 0x000008f8, 0x00000028, 0xffffffff, 560d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 561d8817e4aSriastradh 0x000008f8, 0x00000029, 0xffffffff, 562d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 563d8817e4aSriastradh 0x000008f8, 0x0000002a, 0xffffffff, 564d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 565d8817e4aSriastradh 0x000008f8, 0x0000002b, 0xffffffff, 566d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff 567d8817e4aSriastradh }; 568d8817e4aSriastradh #define CAICOS_CGCG_CGLS_ENABLE_LENGTH sizeof(caicos_cgcg_cgls_enable) / (3 * sizeof(u32)) 569d8817e4aSriastradh 570d8817e4aSriastradh static const u32 caicos_mgcg_default[] = 571d8817e4aSriastradh { 572d8817e4aSriastradh 0x0000802c, 0xc0000000, 0xffffffff, 573d8817e4aSriastradh 0x00005448, 0x00000100, 0xffffffff, 574d8817e4aSriastradh 0x000055e4, 0x00600100, 0xffffffff, 575d8817e4aSriastradh 0x0000160c, 0x00000100, 0xffffffff, 576d8817e4aSriastradh 0x0000c164, 0x00000100, 0xffffffff, 577d8817e4aSriastradh 0x00008a18, 0x00000100, 0xffffffff, 578d8817e4aSriastradh 0x0000897c, 0x06000100, 0xffffffff, 579d8817e4aSriastradh 0x00008b28, 0x00000100, 0xffffffff, 580d8817e4aSriastradh 0x00009144, 0x00000100, 0xffffffff, 581d8817e4aSriastradh 0x00009a60, 0x00000100, 0xffffffff, 582d8817e4aSriastradh 0x00009868, 0x00000100, 0xffffffff, 583d8817e4aSriastradh 0x00008d58, 0x00000100, 0xffffffff, 584d8817e4aSriastradh 0x00009510, 0x00000100, 0xffffffff, 585d8817e4aSriastradh 0x0000949c, 0x00000100, 0xffffffff, 586d8817e4aSriastradh 0x00009654, 0x00000100, 0xffffffff, 587d8817e4aSriastradh 0x00009030, 0x00000100, 0xffffffff, 588d8817e4aSriastradh 0x00009034, 0x00000100, 0xffffffff, 589d8817e4aSriastradh 0x00009038, 0x00000100, 0xffffffff, 590d8817e4aSriastradh 0x0000903c, 0x00000100, 0xffffffff, 591d8817e4aSriastradh 0x00009040, 0x00000100, 0xffffffff, 592d8817e4aSriastradh 0x0000a200, 0x00000100, 0xffffffff, 593d8817e4aSriastradh 0x0000a204, 0x00000100, 0xffffffff, 594d8817e4aSriastradh 0x0000a208, 0x00000100, 0xffffffff, 595d8817e4aSriastradh 0x0000a20c, 0x00000100, 0xffffffff, 596d8817e4aSriastradh 0x0000977c, 0x00000100, 0xffffffff, 597d8817e4aSriastradh 0x00003f80, 0x00000100, 0xffffffff, 598d8817e4aSriastradh 0x0000a210, 0x00000100, 0xffffffff, 599d8817e4aSriastradh 0x0000a214, 0x00000100, 0xffffffff, 600d8817e4aSriastradh 0x000004d8, 0x00000100, 0xffffffff, 601d8817e4aSriastradh 0x00009784, 0x00000100, 0xffffffff, 602d8817e4aSriastradh 0x00009698, 0x00000100, 0xffffffff, 603d8817e4aSriastradh 0x000004d4, 0x00000200, 0xffffffff, 604d8817e4aSriastradh 0x000004d0, 0x00000000, 0xffffffff, 605d8817e4aSriastradh 0x000030cc, 0x00000100, 0xffffffff, 606d8817e4aSriastradh 0x0000d0c0, 0xff000100, 0xffffffff, 607d8817e4aSriastradh 0x0000915c, 0x00010000, 0xffffffff, 608d8817e4aSriastradh 0x00009160, 0x00030002, 0xffffffff, 609d8817e4aSriastradh 0x00009164, 0x00050004, 0xffffffff, 610d8817e4aSriastradh 0x00009168, 0x00070006, 0xffffffff, 611d8817e4aSriastradh 0x00009178, 0x00070000, 0xffffffff, 612d8817e4aSriastradh 0x0000917c, 0x00030002, 0xffffffff, 613d8817e4aSriastradh 0x00009180, 0x00050004, 0xffffffff, 614d8817e4aSriastradh 0x0000918c, 0x00010006, 0xffffffff, 615d8817e4aSriastradh 0x00009190, 0x00090008, 0xffffffff, 616d8817e4aSriastradh 0x00009194, 0x00070000, 0xffffffff, 617d8817e4aSriastradh 0x00009198, 0x00030002, 0xffffffff, 618d8817e4aSriastradh 0x0000919c, 0x00050004, 0xffffffff, 619d8817e4aSriastradh 0x000091a8, 0x00010006, 0xffffffff, 620d8817e4aSriastradh 0x000091ac, 0x00090008, 0xffffffff, 621d8817e4aSriastradh 0x000091e8, 0x00000000, 0xffffffff, 622d8817e4aSriastradh 0x00009294, 0x00000000, 0xffffffff, 623d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 624d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 625d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 626d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 627d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 628d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 629d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 630d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 631d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 632d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 633d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 634d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 635d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 636d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 637d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 638d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 639d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 640d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 641d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 642d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 643d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 644d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 645d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 646d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff 647d8817e4aSriastradh }; 648d8817e4aSriastradh #define CAICOS_MGCG_DEFAULT_LENGTH sizeof(caicos_mgcg_default) / (3 * sizeof(u32)) 649d8817e4aSriastradh 650d8817e4aSriastradh static const u32 caicos_mgcg_disable[] = 651d8817e4aSriastradh { 652d8817e4aSriastradh 0x0000802c, 0xc0000000, 0xffffffff, 653d8817e4aSriastradh 0x000008f8, 0x00000000, 0xffffffff, 654d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 655d8817e4aSriastradh 0x000008f8, 0x00000001, 0xffffffff, 656d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 657d8817e4aSriastradh 0x000008f8, 0x00000002, 0xffffffff, 658d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 659d8817e4aSriastradh 0x000008f8, 0x00000003, 0xffffffff, 660d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 661d8817e4aSriastradh 0x00009150, 0x00600000, 0xffffffff 662d8817e4aSriastradh }; 663d8817e4aSriastradh #define CAICOS_MGCG_DISABLE_LENGTH sizeof(caicos_mgcg_disable) / (3 * sizeof(u32)) 664d8817e4aSriastradh 665d8817e4aSriastradh static const u32 caicos_mgcg_enable[] = 666d8817e4aSriastradh { 667d8817e4aSriastradh 0x0000802c, 0xc0000000, 0xffffffff, 668d8817e4aSriastradh 0x000008f8, 0x00000000, 0xffffffff, 669d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 670d8817e4aSriastradh 0x000008f8, 0x00000001, 0xffffffff, 671d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 672d8817e4aSriastradh 0x000008f8, 0x00000002, 0xffffffff, 673d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 674d8817e4aSriastradh 0x000008f8, 0x00000003, 0xffffffff, 675d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 676d8817e4aSriastradh 0x00009150, 0x46944040, 0xffffffff 677d8817e4aSriastradh }; 678d8817e4aSriastradh #define CAICOS_MGCG_ENABLE_LENGTH sizeof(caicos_mgcg_enable) / (3 * sizeof(u32)) 679d8817e4aSriastradh 680d8817e4aSriastradh //********* TURKS **************// 681d8817e4aSriastradh static const u32 turks_cgcg_cgls_default[] = 682d8817e4aSriastradh { 683d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 684d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 685d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 686d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 687d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 688d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 689d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 690d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 691d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 692d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 693d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 694d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 695d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 696d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 697d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 698d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 699d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 700d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 701d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 702d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 703d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 704d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 705d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 706d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 707d8817e4aSriastradh 0x000008f8, 0x00000020, 0xffffffff, 708d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 709d8817e4aSriastradh 0x000008f8, 0x00000021, 0xffffffff, 710d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 711d8817e4aSriastradh 0x000008f8, 0x00000022, 0xffffffff, 712d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 713d8817e4aSriastradh 0x000008f8, 0x00000023, 0xffffffff, 714d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 715d8817e4aSriastradh 0x000008f8, 0x00000024, 0xffffffff, 716d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 717d8817e4aSriastradh 0x000008f8, 0x00000025, 0xffffffff, 718d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 719d8817e4aSriastradh 0x000008f8, 0x00000026, 0xffffffff, 720d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 721d8817e4aSriastradh 0x000008f8, 0x00000027, 0xffffffff, 722d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 723d8817e4aSriastradh 0x000008f8, 0x00000028, 0xffffffff, 724d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 725d8817e4aSriastradh 0x000008f8, 0x00000029, 0xffffffff, 726d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 727d8817e4aSriastradh 0x000008f8, 0x0000002a, 0xffffffff, 728d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 729d8817e4aSriastradh 0x000008f8, 0x0000002b, 0xffffffff, 730d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff 731d8817e4aSriastradh }; 732d8817e4aSriastradh #define TURKS_CGCG_CGLS_DEFAULT_LENGTH sizeof(turks_cgcg_cgls_default) / (3 * sizeof(u32)) 733d8817e4aSriastradh 734d8817e4aSriastradh static const u32 turks_cgcg_cgls_disable[] = 735d8817e4aSriastradh { 736d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 737d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 738d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 739d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 740d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 741d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 742d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 743d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 744d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 745d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 746d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 747d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 748d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 749d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 750d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 751d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 752d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 753d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 754d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 755d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 756d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 757d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 758d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 759d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 760d8817e4aSriastradh 0x000008f8, 0x00000020, 0xffffffff, 761d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 762d8817e4aSriastradh 0x000008f8, 0x00000021, 0xffffffff, 763d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 764d8817e4aSriastradh 0x000008f8, 0x00000022, 0xffffffff, 765d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 766d8817e4aSriastradh 0x000008f8, 0x00000023, 0xffffffff, 767d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 768d8817e4aSriastradh 0x000008f8, 0x00000024, 0xffffffff, 769d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 770d8817e4aSriastradh 0x000008f8, 0x00000025, 0xffffffff, 771d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 772d8817e4aSriastradh 0x000008f8, 0x00000026, 0xffffffff, 773d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 774d8817e4aSriastradh 0x000008f8, 0x00000027, 0xffffffff, 775d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 776d8817e4aSriastradh 0x000008f8, 0x00000028, 0xffffffff, 777d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 778d8817e4aSriastradh 0x000008f8, 0x00000029, 0xffffffff, 779d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 780d8817e4aSriastradh 0x000008f8, 0x0000002a, 0xffffffff, 781d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 782d8817e4aSriastradh 0x000008f8, 0x0000002b, 0xffffffff, 783d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 784d8817e4aSriastradh 0x00000644, 0x000f7912, 0x001f4180, 785d8817e4aSriastradh 0x00000644, 0x000f3812, 0x001f4180 786d8817e4aSriastradh }; 787d8817e4aSriastradh #define TURKS_CGCG_CGLS_DISABLE_LENGTH sizeof(turks_cgcg_cgls_disable) / (3 * sizeof(u32)) 788d8817e4aSriastradh 789d8817e4aSriastradh static const u32 turks_cgcg_cgls_enable[] = 790d8817e4aSriastradh { 791d8817e4aSriastradh /* 0x0000c124, 0x84180000, 0x00180000, */ 792d8817e4aSriastradh 0x00000644, 0x000f7892, 0x001f4080, 793d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 794d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 795d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 796d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 797d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 798d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 799d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 800d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 801d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 802d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 803d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 804d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 805d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 806d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 807d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 808d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 809d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 810d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 811d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 812d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 813d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 814d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 815d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 816d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 817d8817e4aSriastradh 0x000008f8, 0x00000020, 0xffffffff, 818d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 819d8817e4aSriastradh 0x000008f8, 0x00000021, 0xffffffff, 820d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 821d8817e4aSriastradh 0x000008f8, 0x00000022, 0xffffffff, 822d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 823d8817e4aSriastradh 0x000008f8, 0x00000023, 0xffffffff, 824d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 825d8817e4aSriastradh 0x000008f8, 0x00000024, 0xffffffff, 826d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 827d8817e4aSriastradh 0x000008f8, 0x00000025, 0xffffffff, 828d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 829d8817e4aSriastradh 0x000008f8, 0x00000026, 0xffffffff, 830d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 831d8817e4aSriastradh 0x000008f8, 0x00000027, 0xffffffff, 832d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 833d8817e4aSriastradh 0x000008f8, 0x00000028, 0xffffffff, 834d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 835d8817e4aSriastradh 0x000008f8, 0x00000029, 0xffffffff, 836d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 837d8817e4aSriastradh 0x000008f8, 0x0000002a, 0xffffffff, 838d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 839d8817e4aSriastradh 0x000008f8, 0x0000002b, 0xffffffff, 840d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff 841d8817e4aSriastradh }; 842d8817e4aSriastradh #define TURKS_CGCG_CGLS_ENABLE_LENGTH sizeof(turks_cgcg_cgls_enable) / (3 * sizeof(u32)) 843d8817e4aSriastradh 844d8817e4aSriastradh // These are the sequences for turks_mgcg_shls 845d8817e4aSriastradh static const u32 turks_mgcg_default[] = 846d8817e4aSriastradh { 847d8817e4aSriastradh 0x0000802c, 0xc0000000, 0xffffffff, 848d8817e4aSriastradh 0x00005448, 0x00000100, 0xffffffff, 849d8817e4aSriastradh 0x000055e4, 0x00600100, 0xffffffff, 850d8817e4aSriastradh 0x0000160c, 0x00000100, 0xffffffff, 851d8817e4aSriastradh 0x0000c164, 0x00000100, 0xffffffff, 852d8817e4aSriastradh 0x00008a18, 0x00000100, 0xffffffff, 853d8817e4aSriastradh 0x0000897c, 0x06000100, 0xffffffff, 854d8817e4aSriastradh 0x00008b28, 0x00000100, 0xffffffff, 855d8817e4aSriastradh 0x00009144, 0x00000100, 0xffffffff, 856d8817e4aSriastradh 0x00009a60, 0x00000100, 0xffffffff, 857d8817e4aSriastradh 0x00009868, 0x00000100, 0xffffffff, 858d8817e4aSriastradh 0x00008d58, 0x00000100, 0xffffffff, 859d8817e4aSriastradh 0x00009510, 0x00000100, 0xffffffff, 860d8817e4aSriastradh 0x0000949c, 0x00000100, 0xffffffff, 861d8817e4aSriastradh 0x00009654, 0x00000100, 0xffffffff, 862d8817e4aSriastradh 0x00009030, 0x00000100, 0xffffffff, 863d8817e4aSriastradh 0x00009034, 0x00000100, 0xffffffff, 864d8817e4aSriastradh 0x00009038, 0x00000100, 0xffffffff, 865d8817e4aSriastradh 0x0000903c, 0x00000100, 0xffffffff, 866d8817e4aSriastradh 0x00009040, 0x00000100, 0xffffffff, 867d8817e4aSriastradh 0x0000a200, 0x00000100, 0xffffffff, 868d8817e4aSriastradh 0x0000a204, 0x00000100, 0xffffffff, 869d8817e4aSriastradh 0x0000a208, 0x00000100, 0xffffffff, 870d8817e4aSriastradh 0x0000a20c, 0x00000100, 0xffffffff, 871d8817e4aSriastradh 0x0000977c, 0x00000100, 0xffffffff, 872d8817e4aSriastradh 0x00003f80, 0x00000100, 0xffffffff, 873d8817e4aSriastradh 0x0000a210, 0x00000100, 0xffffffff, 874d8817e4aSriastradh 0x0000a214, 0x00000100, 0xffffffff, 875d8817e4aSriastradh 0x000004d8, 0x00000100, 0xffffffff, 876d8817e4aSriastradh 0x00009784, 0x00000100, 0xffffffff, 877d8817e4aSriastradh 0x00009698, 0x00000100, 0xffffffff, 878d8817e4aSriastradh 0x000004d4, 0x00000200, 0xffffffff, 879d8817e4aSriastradh 0x000004d0, 0x00000000, 0xffffffff, 880d8817e4aSriastradh 0x000030cc, 0x00000100, 0xffffffff, 881d8817e4aSriastradh 0x0000d0c0, 0x00000100, 0xffffffff, 882d8817e4aSriastradh 0x0000915c, 0x00010000, 0xffffffff, 883d8817e4aSriastradh 0x00009160, 0x00030002, 0xffffffff, 884d8817e4aSriastradh 0x00009164, 0x00050004, 0xffffffff, 885d8817e4aSriastradh 0x00009168, 0x00070006, 0xffffffff, 886d8817e4aSriastradh 0x00009178, 0x00070000, 0xffffffff, 887d8817e4aSriastradh 0x0000917c, 0x00030002, 0xffffffff, 888d8817e4aSriastradh 0x00009180, 0x00050004, 0xffffffff, 889d8817e4aSriastradh 0x0000918c, 0x00010006, 0xffffffff, 890d8817e4aSriastradh 0x00009190, 0x00090008, 0xffffffff, 891d8817e4aSriastradh 0x00009194, 0x00070000, 0xffffffff, 892d8817e4aSriastradh 0x00009198, 0x00030002, 0xffffffff, 893d8817e4aSriastradh 0x0000919c, 0x00050004, 0xffffffff, 894d8817e4aSriastradh 0x000091a8, 0x00010006, 0xffffffff, 895d8817e4aSriastradh 0x000091ac, 0x00090008, 0xffffffff, 896d8817e4aSriastradh 0x000091b0, 0x00070000, 0xffffffff, 897d8817e4aSriastradh 0x000091b4, 0x00030002, 0xffffffff, 898d8817e4aSriastradh 0x000091b8, 0x00050004, 0xffffffff, 899d8817e4aSriastradh 0x000091c4, 0x00010006, 0xffffffff, 900d8817e4aSriastradh 0x000091c8, 0x00090008, 0xffffffff, 901d8817e4aSriastradh 0x000091cc, 0x00070000, 0xffffffff, 902d8817e4aSriastradh 0x000091d0, 0x00030002, 0xffffffff, 903d8817e4aSriastradh 0x000091d4, 0x00050004, 0xffffffff, 904d8817e4aSriastradh 0x000091e0, 0x00010006, 0xffffffff, 905d8817e4aSriastradh 0x000091e4, 0x00090008, 0xffffffff, 906d8817e4aSriastradh 0x000091e8, 0x00000000, 0xffffffff, 907d8817e4aSriastradh 0x000091ec, 0x00070000, 0xffffffff, 908d8817e4aSriastradh 0x000091f0, 0x00030002, 0xffffffff, 909d8817e4aSriastradh 0x000091f4, 0x00050004, 0xffffffff, 910d8817e4aSriastradh 0x00009200, 0x00010006, 0xffffffff, 911d8817e4aSriastradh 0x00009204, 0x00090008, 0xffffffff, 912d8817e4aSriastradh 0x00009208, 0x00070000, 0xffffffff, 913d8817e4aSriastradh 0x0000920c, 0x00030002, 0xffffffff, 914d8817e4aSriastradh 0x00009210, 0x00050004, 0xffffffff, 915d8817e4aSriastradh 0x0000921c, 0x00010006, 0xffffffff, 916d8817e4aSriastradh 0x00009220, 0x00090008, 0xffffffff, 917d8817e4aSriastradh 0x00009294, 0x00000000, 0xffffffff, 918d8817e4aSriastradh 0x000008f8, 0x00000010, 0xffffffff, 919d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 920d8817e4aSriastradh 0x000008f8, 0x00000011, 0xffffffff, 921d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 922d8817e4aSriastradh 0x000008f8, 0x00000012, 0xffffffff, 923d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 924d8817e4aSriastradh 0x000008f8, 0x00000013, 0xffffffff, 925d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 926d8817e4aSriastradh 0x000008f8, 0x00000014, 0xffffffff, 927d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 928d8817e4aSriastradh 0x000008f8, 0x00000015, 0xffffffff, 929d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 930d8817e4aSriastradh 0x000008f8, 0x00000016, 0xffffffff, 931d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 932d8817e4aSriastradh 0x000008f8, 0x00000017, 0xffffffff, 933d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 934d8817e4aSriastradh 0x000008f8, 0x00000018, 0xffffffff, 935d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 936d8817e4aSriastradh 0x000008f8, 0x00000019, 0xffffffff, 937d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 938d8817e4aSriastradh 0x000008f8, 0x0000001a, 0xffffffff, 939d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 940d8817e4aSriastradh 0x000008f8, 0x0000001b, 0xffffffff, 941d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff 942d8817e4aSriastradh }; 943d8817e4aSriastradh #define TURKS_MGCG_DEFAULT_LENGTH sizeof(turks_mgcg_default) / (3 * sizeof(u32)) 944d8817e4aSriastradh 945d8817e4aSriastradh static const u32 turks_mgcg_disable[] = 946d8817e4aSriastradh { 947d8817e4aSriastradh 0x0000802c, 0xc0000000, 0xffffffff, 948d8817e4aSriastradh 0x000008f8, 0x00000000, 0xffffffff, 949d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 950d8817e4aSriastradh 0x000008f8, 0x00000001, 0xffffffff, 951d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 952d8817e4aSriastradh 0x000008f8, 0x00000002, 0xffffffff, 953d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 954d8817e4aSriastradh 0x000008f8, 0x00000003, 0xffffffff, 955d8817e4aSriastradh 0x000008fc, 0xffffffff, 0xffffffff, 956d8817e4aSriastradh 0x00009150, 0x00600000, 0xffffffff 957d8817e4aSriastradh }; 958d8817e4aSriastradh #define TURKS_MGCG_DISABLE_LENGTH sizeof(turks_mgcg_disable) / (3 * sizeof(u32)) 959d8817e4aSriastradh 960d8817e4aSriastradh static const u32 turks_mgcg_enable[] = 961d8817e4aSriastradh { 962d8817e4aSriastradh 0x0000802c, 0xc0000000, 0xffffffff, 963d8817e4aSriastradh 0x000008f8, 0x00000000, 0xffffffff, 964d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 965d8817e4aSriastradh 0x000008f8, 0x00000001, 0xffffffff, 966d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 967d8817e4aSriastradh 0x000008f8, 0x00000002, 0xffffffff, 968d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 969d8817e4aSriastradh 0x000008f8, 0x00000003, 0xffffffff, 970d8817e4aSriastradh 0x000008fc, 0x00000000, 0xffffffff, 971d8817e4aSriastradh 0x00009150, 0x6e944000, 0xffffffff 972d8817e4aSriastradh }; 973d8817e4aSriastradh #define TURKS_MGCG_ENABLE_LENGTH sizeof(turks_mgcg_enable) / (3 * sizeof(u32)) 974d8817e4aSriastradh 975d8817e4aSriastradh #endif 976d8817e4aSriastradh 977d8817e4aSriastradh #ifndef BTC_SYSLS_SEQUENCE 978d8817e4aSriastradh #define BTC_SYSLS_SEQUENCE 100 979d8817e4aSriastradh 980d8817e4aSriastradh 981d8817e4aSriastradh //********* BARTS **************// 982d8817e4aSriastradh static const u32 barts_sysls_default[] = 983d8817e4aSriastradh { 984d8817e4aSriastradh /* Register, Value, Mask bits */ 985d8817e4aSriastradh 0x000055e8, 0x00000000, 0xffffffff, 986d8817e4aSriastradh 0x0000d0bc, 0x00000000, 0xffffffff, 987d8817e4aSriastradh 0x000015c0, 0x000c1401, 0xffffffff, 988d8817e4aSriastradh 0x0000264c, 0x000c0400, 0xffffffff, 989d8817e4aSriastradh 0x00002648, 0x000c0400, 0xffffffff, 990d8817e4aSriastradh 0x00002650, 0x000c0400, 0xffffffff, 991d8817e4aSriastradh 0x000020b8, 0x000c0400, 0xffffffff, 992d8817e4aSriastradh 0x000020bc, 0x000c0400, 0xffffffff, 993d8817e4aSriastradh 0x000020c0, 0x000c0c80, 0xffffffff, 994d8817e4aSriastradh 0x0000f4a0, 0x000000c0, 0xffffffff, 995d8817e4aSriastradh 0x0000f4a4, 0x00680fff, 0xffffffff, 996d8817e4aSriastradh 0x000004c8, 0x00000001, 0xffffffff, 997d8817e4aSriastradh 0x000064ec, 0x00000000, 0xffffffff, 998d8817e4aSriastradh 0x00000c7c, 0x00000000, 0xffffffff, 999d8817e4aSriastradh 0x00006dfc, 0x00000000, 0xffffffff 1000d8817e4aSriastradh }; 1001d8817e4aSriastradh #define BARTS_SYSLS_DEFAULT_LENGTH sizeof(barts_sysls_default) / (3 * sizeof(u32)) 1002d8817e4aSriastradh 1003d8817e4aSriastradh static const u32 barts_sysls_disable[] = 1004d8817e4aSriastradh { 1005d8817e4aSriastradh 0x000055e8, 0x00000000, 0xffffffff, 1006d8817e4aSriastradh 0x0000d0bc, 0x00000000, 0xffffffff, 1007d8817e4aSriastradh 0x000015c0, 0x00041401, 0xffffffff, 1008d8817e4aSriastradh 0x0000264c, 0x00040400, 0xffffffff, 1009d8817e4aSriastradh 0x00002648, 0x00040400, 0xffffffff, 1010d8817e4aSriastradh 0x00002650, 0x00040400, 0xffffffff, 1011d8817e4aSriastradh 0x000020b8, 0x00040400, 0xffffffff, 1012d8817e4aSriastradh 0x000020bc, 0x00040400, 0xffffffff, 1013d8817e4aSriastradh 0x000020c0, 0x00040c80, 0xffffffff, 1014d8817e4aSriastradh 0x0000f4a0, 0x000000c0, 0xffffffff, 1015d8817e4aSriastradh 0x0000f4a4, 0x00680000, 0xffffffff, 1016d8817e4aSriastradh 0x000004c8, 0x00000001, 0xffffffff, 1017d8817e4aSriastradh 0x000064ec, 0x00007ffd, 0xffffffff, 1018d8817e4aSriastradh 0x00000c7c, 0x0000ff00, 0xffffffff, 1019d8817e4aSriastradh 0x00006dfc, 0x0000007f, 0xffffffff 1020d8817e4aSriastradh }; 1021d8817e4aSriastradh #define BARTS_SYSLS_DISABLE_LENGTH sizeof(barts_sysls_disable) / (3 * sizeof(u32)) 1022d8817e4aSriastradh 1023d8817e4aSriastradh static const u32 barts_sysls_enable[] = 1024d8817e4aSriastradh { 1025d8817e4aSriastradh 0x000055e8, 0x00000001, 0xffffffff, 1026d8817e4aSriastradh 0x0000d0bc, 0x00000100, 0xffffffff, 1027d8817e4aSriastradh 0x000015c0, 0x000c1401, 0xffffffff, 1028d8817e4aSriastradh 0x0000264c, 0x000c0400, 0xffffffff, 1029d8817e4aSriastradh 0x00002648, 0x000c0400, 0xffffffff, 1030d8817e4aSriastradh 0x00002650, 0x000c0400, 0xffffffff, 1031d8817e4aSriastradh 0x000020b8, 0x000c0400, 0xffffffff, 1032d8817e4aSriastradh 0x000020bc, 0x000c0400, 0xffffffff, 1033d8817e4aSriastradh 0x000020c0, 0x000c0c80, 0xffffffff, 1034d8817e4aSriastradh 0x0000f4a0, 0x000000c0, 0xffffffff, 1035d8817e4aSriastradh 0x0000f4a4, 0x00680fff, 0xffffffff, 1036d8817e4aSriastradh 0x000004c8, 0x00000000, 0xffffffff, 1037d8817e4aSriastradh 0x000064ec, 0x00000000, 0xffffffff, 1038d8817e4aSriastradh 0x00000c7c, 0x00000000, 0xffffffff, 1039d8817e4aSriastradh 0x00006dfc, 0x00000000, 0xffffffff 1040d8817e4aSriastradh }; 1041d8817e4aSriastradh #define BARTS_SYSLS_ENABLE_LENGTH sizeof(barts_sysls_enable) / (3 * sizeof(u32)) 1042d8817e4aSriastradh 1043d8817e4aSriastradh //********* CAICOS **************// 1044d8817e4aSriastradh static const u32 caicos_sysls_default[] = 1045d8817e4aSriastradh { 1046d8817e4aSriastradh 0x000055e8, 0x00000000, 0xffffffff, 1047d8817e4aSriastradh 0x0000d0bc, 0x00000000, 0xffffffff, 1048d8817e4aSriastradh 0x000015c0, 0x000c1401, 0xffffffff, 1049d8817e4aSriastradh 0x0000264c, 0x000c0400, 0xffffffff, 1050d8817e4aSriastradh 0x00002648, 0x000c0400, 0xffffffff, 1051d8817e4aSriastradh 0x00002650, 0x000c0400, 0xffffffff, 1052d8817e4aSriastradh 0x000020b8, 0x000c0400, 0xffffffff, 1053d8817e4aSriastradh 0x000020bc, 0x000c0400, 0xffffffff, 1054d8817e4aSriastradh 0x0000f4a0, 0x000000c0, 0xffffffff, 1055d8817e4aSriastradh 0x0000f4a4, 0x00680fff, 0xffffffff, 1056d8817e4aSriastradh 0x000004c8, 0x00000001, 0xffffffff, 1057d8817e4aSriastradh 0x000064ec, 0x00000000, 0xffffffff, 1058d8817e4aSriastradh 0x00000c7c, 0x00000000, 0xffffffff, 1059d8817e4aSriastradh 0x00006dfc, 0x00000000, 0xffffffff 1060d8817e4aSriastradh }; 1061d8817e4aSriastradh #define CAICOS_SYSLS_DEFAULT_LENGTH sizeof(caicos_sysls_default) / (3 * sizeof(u32)) 1062d8817e4aSriastradh 1063d8817e4aSriastradh static const u32 caicos_sysls_disable[] = 1064d8817e4aSriastradh { 1065d8817e4aSriastradh 0x000055e8, 0x00000000, 0xffffffff, 1066d8817e4aSriastradh 0x0000d0bc, 0x00000000, 0xffffffff, 1067d8817e4aSriastradh 0x000015c0, 0x00041401, 0xffffffff, 1068d8817e4aSriastradh 0x0000264c, 0x00040400, 0xffffffff, 1069d8817e4aSriastradh 0x00002648, 0x00040400, 0xffffffff, 1070d8817e4aSriastradh 0x00002650, 0x00040400, 0xffffffff, 1071d8817e4aSriastradh 0x000020b8, 0x00040400, 0xffffffff, 1072d8817e4aSriastradh 0x000020bc, 0x00040400, 0xffffffff, 1073d8817e4aSriastradh 0x0000f4a0, 0x000000c0, 0xffffffff, 1074d8817e4aSriastradh 0x0000f4a4, 0x00680000, 0xffffffff, 1075d8817e4aSriastradh 0x000004c8, 0x00000001, 0xffffffff, 1076d8817e4aSriastradh 0x000064ec, 0x00007ffd, 0xffffffff, 1077d8817e4aSriastradh 0x00000c7c, 0x0000ff00, 0xffffffff, 1078d8817e4aSriastradh 0x00006dfc, 0x0000007f, 0xffffffff 1079d8817e4aSriastradh }; 1080d8817e4aSriastradh #define CAICOS_SYSLS_DISABLE_LENGTH sizeof(caicos_sysls_disable) / (3 * sizeof(u32)) 1081d8817e4aSriastradh 1082d8817e4aSriastradh static const u32 caicos_sysls_enable[] = 1083d8817e4aSriastradh { 1084d8817e4aSriastradh 0x000055e8, 0x00000001, 0xffffffff, 1085d8817e4aSriastradh 0x0000d0bc, 0x00000100, 0xffffffff, 1086d8817e4aSriastradh 0x000015c0, 0x000c1401, 0xffffffff, 1087d8817e4aSriastradh 0x0000264c, 0x000c0400, 0xffffffff, 1088d8817e4aSriastradh 0x00002648, 0x000c0400, 0xffffffff, 1089d8817e4aSriastradh 0x00002650, 0x000c0400, 0xffffffff, 1090d8817e4aSriastradh 0x000020b8, 0x000c0400, 0xffffffff, 1091d8817e4aSriastradh 0x000020bc, 0x000c0400, 0xffffffff, 1092d8817e4aSriastradh 0x0000f4a0, 0x000000c0, 0xffffffff, 1093d8817e4aSriastradh 0x0000f4a4, 0x00680fff, 0xffffffff, 1094d8817e4aSriastradh 0x000064ec, 0x00000000, 0xffffffff, 1095d8817e4aSriastradh 0x00000c7c, 0x00000000, 0xffffffff, 1096d8817e4aSriastradh 0x00006dfc, 0x00000000, 0xffffffff, 1097d8817e4aSriastradh 0x000004c8, 0x00000000, 0xffffffff 1098d8817e4aSriastradh }; 1099d8817e4aSriastradh #define CAICOS_SYSLS_ENABLE_LENGTH sizeof(caicos_sysls_enable) / (3 * sizeof(u32)) 1100d8817e4aSriastradh 1101d8817e4aSriastradh //********* TURKS **************// 1102d8817e4aSriastradh static const u32 turks_sysls_default[] = 1103d8817e4aSriastradh { 1104d8817e4aSriastradh 0x000055e8, 0x00000000, 0xffffffff, 1105d8817e4aSriastradh 0x0000d0bc, 0x00000000, 0xffffffff, 1106d8817e4aSriastradh 0x000015c0, 0x000c1401, 0xffffffff, 1107d8817e4aSriastradh 0x0000264c, 0x000c0400, 0xffffffff, 1108d8817e4aSriastradh 0x00002648, 0x000c0400, 0xffffffff, 1109d8817e4aSriastradh 0x00002650, 0x000c0400, 0xffffffff, 1110d8817e4aSriastradh 0x000020b8, 0x000c0400, 0xffffffff, 1111d8817e4aSriastradh 0x000020bc, 0x000c0400, 0xffffffff, 1112d8817e4aSriastradh 0x000020c0, 0x000c0c80, 0xffffffff, 1113d8817e4aSriastradh 0x0000f4a0, 0x000000c0, 0xffffffff, 1114d8817e4aSriastradh 0x0000f4a4, 0x00680fff, 0xffffffff, 1115d8817e4aSriastradh 0x000004c8, 0x00000001, 0xffffffff, 1116d8817e4aSriastradh 0x000064ec, 0x00000000, 0xffffffff, 1117d8817e4aSriastradh 0x00000c7c, 0x00000000, 0xffffffff, 1118d8817e4aSriastradh 0x00006dfc, 0x00000000, 0xffffffff 1119d8817e4aSriastradh }; 1120d8817e4aSriastradh #define TURKS_SYSLS_DEFAULT_LENGTH sizeof(turks_sysls_default) / (3 * sizeof(u32)) 1121d8817e4aSriastradh 1122d8817e4aSriastradh static const u32 turks_sysls_disable[] = 1123d8817e4aSriastradh { 1124d8817e4aSriastradh 0x000055e8, 0x00000000, 0xffffffff, 1125d8817e4aSriastradh 0x0000d0bc, 0x00000000, 0xffffffff, 1126d8817e4aSriastradh 0x000015c0, 0x00041401, 0xffffffff, 1127d8817e4aSriastradh 0x0000264c, 0x00040400, 0xffffffff, 1128d8817e4aSriastradh 0x00002648, 0x00040400, 0xffffffff, 1129d8817e4aSriastradh 0x00002650, 0x00040400, 0xffffffff, 1130d8817e4aSriastradh 0x000020b8, 0x00040400, 0xffffffff, 1131d8817e4aSriastradh 0x000020bc, 0x00040400, 0xffffffff, 1132d8817e4aSriastradh 0x000020c0, 0x00040c80, 0xffffffff, 1133d8817e4aSriastradh 0x0000f4a0, 0x000000c0, 0xffffffff, 1134d8817e4aSriastradh 0x0000f4a4, 0x00680000, 0xffffffff, 1135d8817e4aSriastradh 0x000004c8, 0x00000001, 0xffffffff, 1136d8817e4aSriastradh 0x000064ec, 0x00007ffd, 0xffffffff, 1137d8817e4aSriastradh 0x00000c7c, 0x0000ff00, 0xffffffff, 1138d8817e4aSriastradh 0x00006dfc, 0x0000007f, 0xffffffff 1139d8817e4aSriastradh }; 1140d8817e4aSriastradh #define TURKS_SYSLS_DISABLE_LENGTH sizeof(turks_sysls_disable) / (3 * sizeof(u32)) 1141d8817e4aSriastradh 1142d8817e4aSriastradh static const u32 turks_sysls_enable[] = 1143d8817e4aSriastradh { 1144d8817e4aSriastradh 0x000055e8, 0x00000001, 0xffffffff, 1145d8817e4aSriastradh 0x0000d0bc, 0x00000100, 0xffffffff, 1146d8817e4aSriastradh 0x000015c0, 0x000c1401, 0xffffffff, 1147d8817e4aSriastradh 0x0000264c, 0x000c0400, 0xffffffff, 1148d8817e4aSriastradh 0x00002648, 0x000c0400, 0xffffffff, 1149d8817e4aSriastradh 0x00002650, 0x000c0400, 0xffffffff, 1150d8817e4aSriastradh 0x000020b8, 0x000c0400, 0xffffffff, 1151d8817e4aSriastradh 0x000020bc, 0x000c0400, 0xffffffff, 1152d8817e4aSriastradh 0x000020c0, 0x000c0c80, 0xffffffff, 1153d8817e4aSriastradh 0x0000f4a0, 0x000000c0, 0xffffffff, 1154d8817e4aSriastradh 0x0000f4a4, 0x00680fff, 0xffffffff, 1155d8817e4aSriastradh 0x000004c8, 0x00000000, 0xffffffff, 1156d8817e4aSriastradh 0x000064ec, 0x00000000, 0xffffffff, 1157d8817e4aSriastradh 0x00000c7c, 0x00000000, 0xffffffff, 1158d8817e4aSriastradh 0x00006dfc, 0x00000000, 0xffffffff 1159d8817e4aSriastradh }; 1160d8817e4aSriastradh #define TURKS_SYSLS_ENABLE_LENGTH sizeof(turks_sysls_enable) / (3 * sizeof(u32)) 1161d8817e4aSriastradh 1162d8817e4aSriastradh #endif 1163d8817e4aSriastradh 1164d8817e4aSriastradh u32 btc_valid_sclk[40] = 1165d8817e4aSriastradh { 1166d8817e4aSriastradh 5000, 10000, 15000, 20000, 25000, 30000, 35000, 40000, 45000, 50000, 1167d8817e4aSriastradh 55000, 60000, 65000, 70000, 75000, 80000, 85000, 90000, 95000, 100000, 1168d8817e4aSriastradh 105000, 110000, 11500, 120000, 125000, 130000, 135000, 140000, 145000, 150000, 1169d8817e4aSriastradh 155000, 160000, 165000, 170000, 175000, 180000, 185000, 190000, 195000, 200000 1170d8817e4aSriastradh }; 1171d8817e4aSriastradh 11721571a7a1Sriastradh static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = { 1173d8817e4aSriastradh { 10000, 30000, RADEON_SCLK_UP }, 1174d8817e4aSriastradh { 15000, 30000, RADEON_SCLK_UP }, 1175d8817e4aSriastradh { 20000, 30000, RADEON_SCLK_UP }, 1176d8817e4aSriastradh { 25000, 30000, RADEON_SCLK_UP } 1177d8817e4aSriastradh }; 1178d8817e4aSriastradh 1179d8817e4aSriastradh void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table, 1180d8817e4aSriastradh u32 *max_clock) 1181d8817e4aSriastradh { 1182d8817e4aSriastradh u32 i, clock = 0; 1183d8817e4aSriastradh 1184d8817e4aSriastradh if ((table == NULL) || (table->count == 0)) { 1185d8817e4aSriastradh *max_clock = clock; 1186d8817e4aSriastradh return; 1187d8817e4aSriastradh } 1188d8817e4aSriastradh 1189d8817e4aSriastradh for (i = 0; i < table->count; i++) { 1190d8817e4aSriastradh if (clock < table->entries[i].clk) 1191d8817e4aSriastradh clock = table->entries[i].clk; 1192d8817e4aSriastradh } 1193d8817e4aSriastradh *max_clock = clock; 1194d8817e4aSriastradh } 1195d8817e4aSriastradh 1196d8817e4aSriastradh void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table, 1197d8817e4aSriastradh u32 clock, u16 max_voltage, u16 *voltage) 1198d8817e4aSriastradh { 1199d8817e4aSriastradh u32 i; 1200d8817e4aSriastradh 1201d8817e4aSriastradh if ((table == NULL) || (table->count == 0)) 1202d8817e4aSriastradh return; 1203d8817e4aSriastradh 1204d8817e4aSriastradh for (i= 0; i < table->count; i++) { 1205d8817e4aSriastradh if (clock <= table->entries[i].clk) { 1206d8817e4aSriastradh if (*voltage < table->entries[i].v) 1207d8817e4aSriastradh *voltage = (u16)((table->entries[i].v < max_voltage) ? 1208d8817e4aSriastradh table->entries[i].v : max_voltage); 1209d8817e4aSriastradh return; 1210d8817e4aSriastradh } 1211d8817e4aSriastradh } 1212d8817e4aSriastradh 1213d8817e4aSriastradh *voltage = (*voltage > max_voltage) ? *voltage : max_voltage; 1214d8817e4aSriastradh } 1215d8817e4aSriastradh 1216d8817e4aSriastradh static u32 btc_find_valid_clock(struct radeon_clock_array *clocks, 1217d8817e4aSriastradh u32 max_clock, u32 requested_clock) 1218d8817e4aSriastradh { 1219d8817e4aSriastradh unsigned int i; 1220d8817e4aSriastradh 1221d8817e4aSriastradh if ((clocks == NULL) || (clocks->count == 0)) 1222d8817e4aSriastradh return (requested_clock < max_clock) ? requested_clock : max_clock; 1223d8817e4aSriastradh 1224d8817e4aSriastradh for (i = 0; i < clocks->count; i++) { 1225d8817e4aSriastradh if (clocks->values[i] >= requested_clock) 1226d8817e4aSriastradh return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; 1227d8817e4aSriastradh } 1228d8817e4aSriastradh 1229d8817e4aSriastradh return (clocks->values[clocks->count - 1] < max_clock) ? 1230d8817e4aSriastradh clocks->values[clocks->count - 1] : max_clock; 1231d8817e4aSriastradh } 1232d8817e4aSriastradh 1233d8817e4aSriastradh static u32 btc_get_valid_mclk(struct radeon_device *rdev, 1234d8817e4aSriastradh u32 max_mclk, u32 requested_mclk) 1235d8817e4aSriastradh { 1236d8817e4aSriastradh return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values, 1237d8817e4aSriastradh max_mclk, requested_mclk); 1238d8817e4aSriastradh } 1239d8817e4aSriastradh 1240d8817e4aSriastradh static u32 btc_get_valid_sclk(struct radeon_device *rdev, 1241d8817e4aSriastradh u32 max_sclk, u32 requested_sclk) 1242d8817e4aSriastradh { 1243d8817e4aSriastradh return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values, 1244d8817e4aSriastradh max_sclk, requested_sclk); 1245d8817e4aSriastradh } 1246d8817e4aSriastradh 1247d8817e4aSriastradh void btc_skip_blacklist_clocks(struct radeon_device *rdev, 1248d8817e4aSriastradh const u32 max_sclk, const u32 max_mclk, 1249d8817e4aSriastradh u32 *sclk, u32 *mclk) 1250d8817e4aSriastradh { 1251d8817e4aSriastradh int i, num_blacklist_clocks; 1252d8817e4aSriastradh 1253d8817e4aSriastradh if ((sclk == NULL) || (mclk == NULL)) 1254d8817e4aSriastradh return; 1255d8817e4aSriastradh 1256d8817e4aSriastradh num_blacklist_clocks = ARRAY_SIZE(btc_blacklist_clocks); 1257d8817e4aSriastradh 1258d8817e4aSriastradh for (i = 0; i < num_blacklist_clocks; i++) { 1259d8817e4aSriastradh if ((btc_blacklist_clocks[i].sclk == *sclk) && 1260d8817e4aSriastradh (btc_blacklist_clocks[i].mclk == *mclk)) 1261d8817e4aSriastradh break; 1262d8817e4aSriastradh } 1263d8817e4aSriastradh 1264d8817e4aSriastradh if (i < num_blacklist_clocks) { 1265d8817e4aSriastradh if (btc_blacklist_clocks[i].action == RADEON_SCLK_UP) { 1266d8817e4aSriastradh *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1); 1267d8817e4aSriastradh 1268d8817e4aSriastradh if (*sclk < max_sclk) 1269d8817e4aSriastradh btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); 1270d8817e4aSriastradh } 1271d8817e4aSriastradh } 1272d8817e4aSriastradh } 1273d8817e4aSriastradh 1274d8817e4aSriastradh void btc_adjust_clock_combinations(struct radeon_device *rdev, 1275d8817e4aSriastradh const struct radeon_clock_and_voltage_limits *max_limits, 1276d8817e4aSriastradh struct rv7xx_pl *pl) 1277d8817e4aSriastradh { 1278d8817e4aSriastradh 1279d8817e4aSriastradh if ((pl->mclk == 0) || (pl->sclk == 0)) 1280d8817e4aSriastradh return; 1281d8817e4aSriastradh 1282d8817e4aSriastradh if (pl->mclk == pl->sclk) 1283d8817e4aSriastradh return; 1284d8817e4aSriastradh 1285d8817e4aSriastradh if (pl->mclk > pl->sclk) { 1286d8817e4aSriastradh if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) 1287d8817e4aSriastradh pl->sclk = btc_get_valid_sclk(rdev, 1288d8817e4aSriastradh max_limits->sclk, 1289d8817e4aSriastradh (pl->mclk + 1290d8817e4aSriastradh (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / 1291d8817e4aSriastradh rdev->pm.dpm.dyn_state.mclk_sclk_ratio); 1292d8817e4aSriastradh } else { 1293d8817e4aSriastradh if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) 1294d8817e4aSriastradh pl->mclk = btc_get_valid_mclk(rdev, 1295d8817e4aSriastradh max_limits->mclk, 1296d8817e4aSriastradh pl->sclk - 1297d8817e4aSriastradh rdev->pm.dpm.dyn_state.sclk_mclk_delta); 1298d8817e4aSriastradh } 1299d8817e4aSriastradh } 1300d8817e4aSriastradh 1301d8817e4aSriastradh static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage) 1302d8817e4aSriastradh { 1303d8817e4aSriastradh unsigned int i; 1304d8817e4aSriastradh 1305d8817e4aSriastradh for (i = 0; i < table->count; i++) { 1306d8817e4aSriastradh if (voltage <= table->entries[i].value) 1307d8817e4aSriastradh return table->entries[i].value; 1308d8817e4aSriastradh } 1309d8817e4aSriastradh 1310d8817e4aSriastradh return table->entries[table->count - 1].value; 1311d8817e4aSriastradh } 1312d8817e4aSriastradh 1313d8817e4aSriastradh void btc_apply_voltage_delta_rules(struct radeon_device *rdev, 1314d8817e4aSriastradh u16 max_vddc, u16 max_vddci, 1315d8817e4aSriastradh u16 *vddc, u16 *vddci) 1316d8817e4aSriastradh { 1317d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1318d8817e4aSriastradh u16 new_voltage; 1319d8817e4aSriastradh 1320d8817e4aSriastradh if ((0 == *vddc) || (0 == *vddci)) 1321d8817e4aSriastradh return; 1322d8817e4aSriastradh 1323d8817e4aSriastradh if (*vddc > *vddci) { 1324d8817e4aSriastradh if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { 1325d8817e4aSriastradh new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, 1326d8817e4aSriastradh (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); 1327d8817e4aSriastradh *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci; 1328d8817e4aSriastradh } 1329d8817e4aSriastradh } else { 1330d8817e4aSriastradh if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { 1331d8817e4aSriastradh new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, 1332d8817e4aSriastradh (*vddci - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); 1333d8817e4aSriastradh *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc; 1334d8817e4aSriastradh } 1335d8817e4aSriastradh } 1336d8817e4aSriastradh } 1337d8817e4aSriastradh 1338d8817e4aSriastradh static void btc_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev, 1339d8817e4aSriastradh bool enable) 1340d8817e4aSriastradh { 1341d8817e4aSriastradh struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1342d8817e4aSriastradh u32 tmp, bif; 1343d8817e4aSriastradh 1344d8817e4aSriastradh tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1345d8817e4aSriastradh if (enable) { 1346d8817e4aSriastradh if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) && 1347d8817e4aSriastradh (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 1348d8817e4aSriastradh if (!pi->boot_in_gen2) { 1349d8817e4aSriastradh bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; 1350d8817e4aSriastradh bif |= CG_CLIENT_REQ(0xd); 1351d8817e4aSriastradh WREG32(CG_BIF_REQ_AND_RSP, bif); 1352d8817e4aSriastradh 1353d8817e4aSriastradh tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK; 1354d8817e4aSriastradh tmp |= LC_HW_VOLTAGE_IF_CONTROL(1); 1355d8817e4aSriastradh tmp |= LC_GEN2_EN_STRAP; 1356d8817e4aSriastradh 1357d8817e4aSriastradh tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT; 1358d8817e4aSriastradh WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); 1359d8817e4aSriastradh udelay(10); 1360d8817e4aSriastradh tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 1361d8817e4aSriastradh WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); 1362d8817e4aSriastradh } 1363d8817e4aSriastradh } 1364d8817e4aSriastradh } else { 1365d8817e4aSriastradh if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) || 1366d8817e4aSriastradh (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 1367d8817e4aSriastradh if (!pi->boot_in_gen2) { 1368d8817e4aSriastradh bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; 1369d8817e4aSriastradh bif |= CG_CLIENT_REQ(0xd); 1370d8817e4aSriastradh WREG32(CG_BIF_REQ_AND_RSP, bif); 1371d8817e4aSriastradh 1372d8817e4aSriastradh tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK; 1373d8817e4aSriastradh tmp &= ~LC_GEN2_EN_STRAP; 1374d8817e4aSriastradh } 1375d8817e4aSriastradh WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); 1376d8817e4aSriastradh } 1377d8817e4aSriastradh } 1378d8817e4aSriastradh } 1379d8817e4aSriastradh 1380d8817e4aSriastradh static void btc_enable_dynamic_pcie_gen2(struct radeon_device *rdev, 1381d8817e4aSriastradh bool enable) 1382d8817e4aSriastradh { 1383d8817e4aSriastradh btc_enable_bif_dynamic_pcie_gen2(rdev, enable); 1384d8817e4aSriastradh 1385d8817e4aSriastradh if (enable) 1386d8817e4aSriastradh WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); 1387d8817e4aSriastradh else 1388d8817e4aSriastradh WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); 1389d8817e4aSriastradh } 1390d8817e4aSriastradh 1391d8817e4aSriastradh static int btc_disable_ulv(struct radeon_device *rdev) 1392d8817e4aSriastradh { 1393d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1394d8817e4aSriastradh 1395d8817e4aSriastradh if (eg_pi->ulv.supported) { 1396d8817e4aSriastradh if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) != PPSMC_Result_OK) 1397d8817e4aSriastradh return -EINVAL; 1398d8817e4aSriastradh } 1399d8817e4aSriastradh return 0; 1400d8817e4aSriastradh } 1401d8817e4aSriastradh 1402d8817e4aSriastradh static int btc_populate_ulv_state(struct radeon_device *rdev, 1403d8817e4aSriastradh RV770_SMC_STATETABLE *table) 1404d8817e4aSriastradh { 1405d8817e4aSriastradh int ret = -EINVAL; 1406d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1407d8817e4aSriastradh struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; 1408d8817e4aSriastradh 1409d8817e4aSriastradh if (ulv_pl->vddc) { 1410d8817e4aSriastradh ret = cypress_convert_power_level_to_smc(rdev, 1411d8817e4aSriastradh ulv_pl, 1412d8817e4aSriastradh &table->ULVState.levels[0], 1413d8817e4aSriastradh PPSMC_DISPLAY_WATERMARK_LOW); 1414d8817e4aSriastradh if (ret == 0) { 1415d8817e4aSriastradh table->ULVState.levels[0].arbValue = MC_CG_ARB_FREQ_F0; 1416d8817e4aSriastradh table->ULVState.levels[0].ACIndex = 1; 1417d8817e4aSriastradh 1418d8817e4aSriastradh table->ULVState.levels[1] = table->ULVState.levels[0]; 1419d8817e4aSriastradh table->ULVState.levels[2] = table->ULVState.levels[0]; 1420d8817e4aSriastradh 1421d8817e4aSriastradh table->ULVState.flags |= PPSMC_SWSTATE_FLAG_DC; 1422d8817e4aSriastradh 1423d8817e4aSriastradh WREG32(CG_ULV_CONTROL, BTC_CGULVCONTROL_DFLT); 1424d8817e4aSriastradh WREG32(CG_ULV_PARAMETER, BTC_CGULVPARAMETER_DFLT); 1425d8817e4aSriastradh } 1426d8817e4aSriastradh } 1427d8817e4aSriastradh 1428d8817e4aSriastradh return ret; 1429d8817e4aSriastradh } 1430d8817e4aSriastradh 1431d8817e4aSriastradh static int btc_populate_smc_acpi_state(struct radeon_device *rdev, 1432d8817e4aSriastradh RV770_SMC_STATETABLE *table) 1433d8817e4aSriastradh { 1434d8817e4aSriastradh int ret = cypress_populate_smc_acpi_state(rdev, table); 1435d8817e4aSriastradh 1436d8817e4aSriastradh if (ret == 0) { 1437d8817e4aSriastradh table->ACPIState.levels[0].ACIndex = 0; 1438d8817e4aSriastradh table->ACPIState.levels[1].ACIndex = 0; 1439d8817e4aSriastradh table->ACPIState.levels[2].ACIndex = 0; 1440d8817e4aSriastradh } 1441d8817e4aSriastradh 1442d8817e4aSriastradh return ret; 1443d8817e4aSriastradh } 1444d8817e4aSriastradh 1445d8817e4aSriastradh void btc_program_mgcg_hw_sequence(struct radeon_device *rdev, 1446d8817e4aSriastradh const u32 *sequence, u32 count) 1447d8817e4aSriastradh { 1448d8817e4aSriastradh u32 i, length = count * 3; 1449d8817e4aSriastradh u32 tmp; 1450d8817e4aSriastradh 1451d8817e4aSriastradh for (i = 0; i < length; i+=3) { 1452d8817e4aSriastradh tmp = RREG32(sequence[i]); 1453d8817e4aSriastradh tmp &= ~sequence[i+2]; 1454d8817e4aSriastradh tmp |= sequence[i+1] & sequence[i+2]; 1455d8817e4aSriastradh WREG32(sequence[i], tmp); 1456d8817e4aSriastradh } 1457d8817e4aSriastradh } 1458d8817e4aSriastradh 1459d8817e4aSriastradh static void btc_cg_clock_gating_default(struct radeon_device *rdev) 1460d8817e4aSriastradh { 1461d8817e4aSriastradh u32 count; 1462d8817e4aSriastradh const u32 *p = NULL; 1463d8817e4aSriastradh 1464d8817e4aSriastradh if (rdev->family == CHIP_BARTS) { 1465d8817e4aSriastradh p = (const u32 *)&barts_cgcg_cgls_default; 1466d8817e4aSriastradh count = BARTS_CGCG_CGLS_DEFAULT_LENGTH; 1467d8817e4aSriastradh } else if (rdev->family == CHIP_TURKS) { 1468d8817e4aSriastradh p = (const u32 *)&turks_cgcg_cgls_default; 1469d8817e4aSriastradh count = TURKS_CGCG_CGLS_DEFAULT_LENGTH; 1470d8817e4aSriastradh } else if (rdev->family == CHIP_CAICOS) { 1471d8817e4aSriastradh p = (const u32 *)&caicos_cgcg_cgls_default; 1472d8817e4aSriastradh count = CAICOS_CGCG_CGLS_DEFAULT_LENGTH; 1473d8817e4aSriastradh } else 1474d8817e4aSriastradh return; 1475d8817e4aSriastradh 1476d8817e4aSriastradh btc_program_mgcg_hw_sequence(rdev, p, count); 1477d8817e4aSriastradh } 1478d8817e4aSriastradh 1479d8817e4aSriastradh static void btc_cg_clock_gating_enable(struct radeon_device *rdev, 1480d8817e4aSriastradh bool enable) 1481d8817e4aSriastradh { 1482d8817e4aSriastradh u32 count; 1483d8817e4aSriastradh const u32 *p = NULL; 1484d8817e4aSriastradh 1485d8817e4aSriastradh if (enable) { 1486d8817e4aSriastradh if (rdev->family == CHIP_BARTS) { 1487d8817e4aSriastradh p = (const u32 *)&barts_cgcg_cgls_enable; 1488d8817e4aSriastradh count = BARTS_CGCG_CGLS_ENABLE_LENGTH; 1489d8817e4aSriastradh } else if (rdev->family == CHIP_TURKS) { 1490d8817e4aSriastradh p = (const u32 *)&turks_cgcg_cgls_enable; 1491d8817e4aSriastradh count = TURKS_CGCG_CGLS_ENABLE_LENGTH; 1492d8817e4aSriastradh } else if (rdev->family == CHIP_CAICOS) { 1493d8817e4aSriastradh p = (const u32 *)&caicos_cgcg_cgls_enable; 1494d8817e4aSriastradh count = CAICOS_CGCG_CGLS_ENABLE_LENGTH; 1495d8817e4aSriastradh } else 1496d8817e4aSriastradh return; 1497d8817e4aSriastradh } else { 1498d8817e4aSriastradh if (rdev->family == CHIP_BARTS) { 1499d8817e4aSriastradh p = (const u32 *)&barts_cgcg_cgls_disable; 1500d8817e4aSriastradh count = BARTS_CGCG_CGLS_DISABLE_LENGTH; 1501d8817e4aSriastradh } else if (rdev->family == CHIP_TURKS) { 1502d8817e4aSriastradh p = (const u32 *)&turks_cgcg_cgls_disable; 1503d8817e4aSriastradh count = TURKS_CGCG_CGLS_DISABLE_LENGTH; 1504d8817e4aSriastradh } else if (rdev->family == CHIP_CAICOS) { 1505d8817e4aSriastradh p = (const u32 *)&caicos_cgcg_cgls_disable; 1506d8817e4aSriastradh count = CAICOS_CGCG_CGLS_DISABLE_LENGTH; 1507d8817e4aSriastradh } else 1508d8817e4aSriastradh return; 1509d8817e4aSriastradh } 1510d8817e4aSriastradh 1511d8817e4aSriastradh btc_program_mgcg_hw_sequence(rdev, p, count); 1512d8817e4aSriastradh } 1513d8817e4aSriastradh 1514d8817e4aSriastradh static void btc_mg_clock_gating_default(struct radeon_device *rdev) 1515d8817e4aSriastradh { 1516d8817e4aSriastradh u32 count; 1517d8817e4aSriastradh const u32 *p = NULL; 1518d8817e4aSriastradh 1519d8817e4aSriastradh if (rdev->family == CHIP_BARTS) { 1520d8817e4aSriastradh p = (const u32 *)&barts_mgcg_default; 1521d8817e4aSriastradh count = BARTS_MGCG_DEFAULT_LENGTH; 1522d8817e4aSriastradh } else if (rdev->family == CHIP_TURKS) { 1523d8817e4aSriastradh p = (const u32 *)&turks_mgcg_default; 1524d8817e4aSriastradh count = TURKS_MGCG_DEFAULT_LENGTH; 1525d8817e4aSriastradh } else if (rdev->family == CHIP_CAICOS) { 1526d8817e4aSriastradh p = (const u32 *)&caicos_mgcg_default; 1527d8817e4aSriastradh count = CAICOS_MGCG_DEFAULT_LENGTH; 1528d8817e4aSriastradh } else 1529d8817e4aSriastradh return; 1530d8817e4aSriastradh 1531d8817e4aSriastradh btc_program_mgcg_hw_sequence(rdev, p, count); 1532d8817e4aSriastradh } 1533d8817e4aSriastradh 1534d8817e4aSriastradh static void btc_mg_clock_gating_enable(struct radeon_device *rdev, 1535d8817e4aSriastradh bool enable) 1536d8817e4aSriastradh { 1537d8817e4aSriastradh u32 count; 1538d8817e4aSriastradh const u32 *p = NULL; 1539d8817e4aSriastradh 1540d8817e4aSriastradh if (enable) { 1541d8817e4aSriastradh if (rdev->family == CHIP_BARTS) { 1542d8817e4aSriastradh p = (const u32 *)&barts_mgcg_enable; 1543d8817e4aSriastradh count = BARTS_MGCG_ENABLE_LENGTH; 1544d8817e4aSriastradh } else if (rdev->family == CHIP_TURKS) { 1545d8817e4aSriastradh p = (const u32 *)&turks_mgcg_enable; 1546d8817e4aSriastradh count = TURKS_MGCG_ENABLE_LENGTH; 1547d8817e4aSriastradh } else if (rdev->family == CHIP_CAICOS) { 1548d8817e4aSriastradh p = (const u32 *)&caicos_mgcg_enable; 1549d8817e4aSriastradh count = CAICOS_MGCG_ENABLE_LENGTH; 1550d8817e4aSriastradh } else 1551d8817e4aSriastradh return; 1552d8817e4aSriastradh } else { 1553d8817e4aSriastradh if (rdev->family == CHIP_BARTS) { 1554d8817e4aSriastradh p = (const u32 *)&barts_mgcg_disable[0]; 1555d8817e4aSriastradh count = BARTS_MGCG_DISABLE_LENGTH; 1556d8817e4aSriastradh } else if (rdev->family == CHIP_TURKS) { 1557d8817e4aSriastradh p = (const u32 *)&turks_mgcg_disable[0]; 1558d8817e4aSriastradh count = TURKS_MGCG_DISABLE_LENGTH; 1559d8817e4aSriastradh } else if (rdev->family == CHIP_CAICOS) { 1560d8817e4aSriastradh p = (const u32 *)&caicos_mgcg_disable[0]; 1561d8817e4aSriastradh count = CAICOS_MGCG_DISABLE_LENGTH; 1562d8817e4aSriastradh } else 1563d8817e4aSriastradh return; 1564d8817e4aSriastradh } 1565d8817e4aSriastradh 1566d8817e4aSriastradh btc_program_mgcg_hw_sequence(rdev, p, count); 1567d8817e4aSriastradh } 1568d8817e4aSriastradh 1569d8817e4aSriastradh static void btc_ls_clock_gating_default(struct radeon_device *rdev) 1570d8817e4aSriastradh { 1571d8817e4aSriastradh u32 count; 1572d8817e4aSriastradh const u32 *p = NULL; 1573d8817e4aSriastradh 1574d8817e4aSriastradh if (rdev->family == CHIP_BARTS) { 1575d8817e4aSriastradh p = (const u32 *)&barts_sysls_default; 1576d8817e4aSriastradh count = BARTS_SYSLS_DEFAULT_LENGTH; 1577d8817e4aSriastradh } else if (rdev->family == CHIP_TURKS) { 1578d8817e4aSriastradh p = (const u32 *)&turks_sysls_default; 1579d8817e4aSriastradh count = TURKS_SYSLS_DEFAULT_LENGTH; 1580d8817e4aSriastradh } else if (rdev->family == CHIP_CAICOS) { 1581d8817e4aSriastradh p = (const u32 *)&caicos_sysls_default; 1582d8817e4aSriastradh count = CAICOS_SYSLS_DEFAULT_LENGTH; 1583d8817e4aSriastradh } else 1584d8817e4aSriastradh return; 1585d8817e4aSriastradh 1586d8817e4aSriastradh btc_program_mgcg_hw_sequence(rdev, p, count); 1587d8817e4aSriastradh } 1588d8817e4aSriastradh 1589d8817e4aSriastradh static void btc_ls_clock_gating_enable(struct radeon_device *rdev, 1590d8817e4aSriastradh bool enable) 1591d8817e4aSriastradh { 1592d8817e4aSriastradh u32 count; 1593d8817e4aSriastradh const u32 *p = NULL; 1594d8817e4aSriastradh 1595d8817e4aSriastradh if (enable) { 1596d8817e4aSriastradh if (rdev->family == CHIP_BARTS) { 1597d8817e4aSriastradh p = (const u32 *)&barts_sysls_enable; 1598d8817e4aSriastradh count = BARTS_SYSLS_ENABLE_LENGTH; 1599d8817e4aSriastradh } else if (rdev->family == CHIP_TURKS) { 1600d8817e4aSriastradh p = (const u32 *)&turks_sysls_enable; 1601d8817e4aSriastradh count = TURKS_SYSLS_ENABLE_LENGTH; 1602d8817e4aSriastradh } else if (rdev->family == CHIP_CAICOS) { 1603d8817e4aSriastradh p = (const u32 *)&caicos_sysls_enable; 1604d8817e4aSriastradh count = CAICOS_SYSLS_ENABLE_LENGTH; 1605d8817e4aSriastradh } else 1606d8817e4aSriastradh return; 1607d8817e4aSriastradh } else { 1608d8817e4aSriastradh if (rdev->family == CHIP_BARTS) { 1609d8817e4aSriastradh p = (const u32 *)&barts_sysls_disable; 1610d8817e4aSriastradh count = BARTS_SYSLS_DISABLE_LENGTH; 1611d8817e4aSriastradh } else if (rdev->family == CHIP_TURKS) { 1612d8817e4aSriastradh p = (const u32 *)&turks_sysls_disable; 1613d8817e4aSriastradh count = TURKS_SYSLS_DISABLE_LENGTH; 1614d8817e4aSriastradh } else if (rdev->family == CHIP_CAICOS) { 1615d8817e4aSriastradh p = (const u32 *)&caicos_sysls_disable; 1616d8817e4aSriastradh count = CAICOS_SYSLS_DISABLE_LENGTH; 1617d8817e4aSriastradh } else 1618d8817e4aSriastradh return; 1619d8817e4aSriastradh } 1620d8817e4aSriastradh 1621d8817e4aSriastradh btc_program_mgcg_hw_sequence(rdev, p, count); 1622d8817e4aSriastradh } 1623d8817e4aSriastradh 1624d8817e4aSriastradh bool btc_dpm_enabled(struct radeon_device *rdev) 1625d8817e4aSriastradh { 1626d8817e4aSriastradh if (rv770_is_smc_running(rdev)) 1627d8817e4aSriastradh return true; 1628d8817e4aSriastradh else 1629d8817e4aSriastradh return false; 1630d8817e4aSriastradh } 1631d8817e4aSriastradh 1632d8817e4aSriastradh static int btc_init_smc_table(struct radeon_device *rdev, 1633d8817e4aSriastradh struct radeon_ps *radeon_boot_state) 1634d8817e4aSriastradh { 1635d8817e4aSriastradh struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1636d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1637d8817e4aSriastradh RV770_SMC_STATETABLE *table = &pi->smc_statetable; 1638d8817e4aSriastradh int ret; 1639d8817e4aSriastradh 1640d8817e4aSriastradh memset(table, 0, sizeof(RV770_SMC_STATETABLE)); 1641d8817e4aSriastradh 1642d8817e4aSriastradh cypress_populate_smc_voltage_tables(rdev, table); 1643d8817e4aSriastradh 1644d8817e4aSriastradh switch (rdev->pm.int_thermal_type) { 1645d8817e4aSriastradh case THERMAL_TYPE_EVERGREEN: 1646d8817e4aSriastradh case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 1647d8817e4aSriastradh table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 1648d8817e4aSriastradh break; 1649d8817e4aSriastradh case THERMAL_TYPE_NONE: 1650d8817e4aSriastradh table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 1651d8817e4aSriastradh break; 1652d8817e4aSriastradh default: 1653d8817e4aSriastradh table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 1654d8817e4aSriastradh break; 1655d8817e4aSriastradh } 1656d8817e4aSriastradh 1657d8817e4aSriastradh if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 1658d8817e4aSriastradh table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 1659d8817e4aSriastradh 1660d8817e4aSriastradh if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) 1661d8817e4aSriastradh table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 1662d8817e4aSriastradh 1663d8817e4aSriastradh if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 1664d8817e4aSriastradh table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 1665d8817e4aSriastradh 1666d8817e4aSriastradh if (pi->mem_gddr5) 1667d8817e4aSriastradh table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 1668d8817e4aSriastradh 1669d8817e4aSriastradh ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table); 1670d8817e4aSriastradh if (ret) 1671d8817e4aSriastradh return ret; 1672d8817e4aSriastradh 1673d8817e4aSriastradh if (eg_pi->sclk_deep_sleep) 1674d8817e4aSriastradh WREG32_P(SCLK_PSKIP_CNTL, PSKIP_ON_ALLOW_STOP_HI(32), 1675d8817e4aSriastradh ~PSKIP_ON_ALLOW_STOP_HI_MASK); 1676d8817e4aSriastradh 1677d8817e4aSriastradh ret = btc_populate_smc_acpi_state(rdev, table); 1678d8817e4aSriastradh if (ret) 1679d8817e4aSriastradh return ret; 1680d8817e4aSriastradh 1681d8817e4aSriastradh if (eg_pi->ulv.supported) { 1682d8817e4aSriastradh ret = btc_populate_ulv_state(rdev, table); 1683d8817e4aSriastradh if (ret) 1684d8817e4aSriastradh eg_pi->ulv.supported = false; 1685d8817e4aSriastradh } 1686d8817e4aSriastradh 1687d8817e4aSriastradh table->driverState = table->initialState; 1688d8817e4aSriastradh 1689d8817e4aSriastradh return rv770_copy_bytes_to_smc(rdev, 1690d8817e4aSriastradh pi->state_table_start, 1691d8817e4aSriastradh (u8 *)table, 1692d8817e4aSriastradh sizeof(RV770_SMC_STATETABLE), 1693d8817e4aSriastradh pi->sram_end); 1694d8817e4aSriastradh } 1695d8817e4aSriastradh 1696d8817e4aSriastradh static void btc_set_at_for_uvd(struct radeon_device *rdev, 1697d8817e4aSriastradh struct radeon_ps *radeon_new_state) 1698d8817e4aSriastradh { 1699d8817e4aSriastradh struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1700d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1701d8817e4aSriastradh int idx = 0; 1702d8817e4aSriastradh 1703d8817e4aSriastradh if (r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) 1704d8817e4aSriastradh idx = 1; 1705d8817e4aSriastradh 1706d8817e4aSriastradh if ((idx == 1) && !eg_pi->smu_uvd_hs) { 1707d8817e4aSriastradh pi->rlp = 10; 1708d8817e4aSriastradh pi->rmp = 100; 1709d8817e4aSriastradh pi->lhp = 100; 1710d8817e4aSriastradh pi->lmp = 10; 1711d8817e4aSriastradh } else { 1712d8817e4aSriastradh pi->rlp = eg_pi->ats[idx].rlp; 1713d8817e4aSriastradh pi->rmp = eg_pi->ats[idx].rmp; 1714d8817e4aSriastradh pi->lhp = eg_pi->ats[idx].lhp; 1715d8817e4aSriastradh pi->lmp = eg_pi->ats[idx].lmp; 1716d8817e4aSriastradh } 1717d8817e4aSriastradh 1718d8817e4aSriastradh } 1719d8817e4aSriastradh 1720d8817e4aSriastradh void btc_notify_uvd_to_smc(struct radeon_device *rdev, 1721d8817e4aSriastradh struct radeon_ps *radeon_new_state) 1722d8817e4aSriastradh { 1723d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1724d8817e4aSriastradh 1725d8817e4aSriastradh if (r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) { 1726d8817e4aSriastradh rv770_write_smc_soft_register(rdev, 1727d8817e4aSriastradh RV770_SMC_SOFT_REGISTER_uvd_enabled, 1); 1728d8817e4aSriastradh eg_pi->uvd_enabled = true; 1729d8817e4aSriastradh } else { 1730d8817e4aSriastradh rv770_write_smc_soft_register(rdev, 1731d8817e4aSriastradh RV770_SMC_SOFT_REGISTER_uvd_enabled, 0); 1732d8817e4aSriastradh eg_pi->uvd_enabled = false; 1733d8817e4aSriastradh } 1734d8817e4aSriastradh } 1735d8817e4aSriastradh 1736d8817e4aSriastradh int btc_reset_to_default(struct radeon_device *rdev) 1737d8817e4aSriastradh { 1738d8817e4aSriastradh if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) != PPSMC_Result_OK) 1739d8817e4aSriastradh return -EINVAL; 1740d8817e4aSriastradh 1741d8817e4aSriastradh return 0; 1742d8817e4aSriastradh } 1743d8817e4aSriastradh 1744d8817e4aSriastradh static void btc_stop_smc(struct radeon_device *rdev) 1745d8817e4aSriastradh { 1746d8817e4aSriastradh int i; 1747d8817e4aSriastradh 1748d8817e4aSriastradh for (i = 0; i < rdev->usec_timeout; i++) { 1749d8817e4aSriastradh if (((RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK) >> LB_SYNC_RESET_SEL_SHIFT) != 1) 1750d8817e4aSriastradh break; 1751d8817e4aSriastradh udelay(1); 1752d8817e4aSriastradh } 1753d8817e4aSriastradh udelay(100); 1754d8817e4aSriastradh 1755d8817e4aSriastradh r7xx_stop_smc(rdev); 1756d8817e4aSriastradh } 1757d8817e4aSriastradh 1758d8817e4aSriastradh void btc_read_arb_registers(struct radeon_device *rdev) 1759d8817e4aSriastradh { 1760d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1761d8817e4aSriastradh struct evergreen_arb_registers *arb_registers = 1762d8817e4aSriastradh &eg_pi->bootup_arb_registers; 1763d8817e4aSriastradh 1764d8817e4aSriastradh arb_registers->mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); 1765d8817e4aSriastradh arb_registers->mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 1766d8817e4aSriastradh arb_registers->mc_arb_rfsh_rate = RREG32(MC_ARB_RFSH_RATE); 1767d8817e4aSriastradh arb_registers->mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME); 1768d8817e4aSriastradh } 1769d8817e4aSriastradh 1770d8817e4aSriastradh 1771d8817e4aSriastradh static void btc_set_arb0_registers(struct radeon_device *rdev, 1772d8817e4aSriastradh struct evergreen_arb_registers *arb_registers) 1773d8817e4aSriastradh { 1774d8817e4aSriastradh u32 val; 1775d8817e4aSriastradh 1776d8817e4aSriastradh WREG32(MC_ARB_DRAM_TIMING, arb_registers->mc_arb_dram_timing); 1777d8817e4aSriastradh WREG32(MC_ARB_DRAM_TIMING2, arb_registers->mc_arb_dram_timing2); 1778d8817e4aSriastradh 1779d8817e4aSriastradh val = (arb_registers->mc_arb_rfsh_rate & POWERMODE0_MASK) >> 1780d8817e4aSriastradh POWERMODE0_SHIFT; 1781d8817e4aSriastradh WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK); 1782d8817e4aSriastradh 1783d8817e4aSriastradh val = (arb_registers->mc_arb_burst_time & STATE0_MASK) >> 1784d8817e4aSriastradh STATE0_SHIFT; 1785d8817e4aSriastradh WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK); 1786d8817e4aSriastradh } 1787d8817e4aSriastradh 1788d8817e4aSriastradh static void btc_set_boot_state_timing(struct radeon_device *rdev) 1789d8817e4aSriastradh { 1790d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1791d8817e4aSriastradh 1792d8817e4aSriastradh if (eg_pi->ulv.supported) 1793d8817e4aSriastradh btc_set_arb0_registers(rdev, &eg_pi->bootup_arb_registers); 1794d8817e4aSriastradh } 1795d8817e4aSriastradh 1796d8817e4aSriastradh static bool btc_is_state_ulv_compatible(struct radeon_device *rdev, 1797d8817e4aSriastradh struct radeon_ps *radeon_state) 1798d8817e4aSriastradh { 1799d8817e4aSriastradh struct rv7xx_ps *state = rv770_get_ps(radeon_state); 1800d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1801d8817e4aSriastradh struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; 1802d8817e4aSriastradh 1803d8817e4aSriastradh if (state->low.mclk != ulv_pl->mclk) 1804d8817e4aSriastradh return false; 1805d8817e4aSriastradh 1806d8817e4aSriastradh if (state->low.vddci != ulv_pl->vddci) 1807d8817e4aSriastradh return false; 1808d8817e4aSriastradh 1809d8817e4aSriastradh /* XXX check minclocks, etc. */ 1810d8817e4aSriastradh 1811d8817e4aSriastradh return true; 1812d8817e4aSriastradh } 1813d8817e4aSriastradh 1814d8817e4aSriastradh 1815d8817e4aSriastradh static int btc_set_ulv_dram_timing(struct radeon_device *rdev) 1816d8817e4aSriastradh { 1817d8817e4aSriastradh u32 val; 1818d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1819d8817e4aSriastradh struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; 1820d8817e4aSriastradh 1821d8817e4aSriastradh radeon_atom_set_engine_dram_timings(rdev, 1822d8817e4aSriastradh ulv_pl->sclk, 1823d8817e4aSriastradh ulv_pl->mclk); 1824d8817e4aSriastradh 1825d8817e4aSriastradh val = rv770_calculate_memory_refresh_rate(rdev, ulv_pl->sclk); 1826d8817e4aSriastradh WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK); 1827d8817e4aSriastradh 1828d8817e4aSriastradh val = cypress_calculate_burst_time(rdev, ulv_pl->sclk, ulv_pl->mclk); 1829d8817e4aSriastradh WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK); 1830d8817e4aSriastradh 1831d8817e4aSriastradh return 0; 1832d8817e4aSriastradh } 1833d8817e4aSriastradh 1834d8817e4aSriastradh static int btc_enable_ulv(struct radeon_device *rdev) 1835d8817e4aSriastradh { 1836d8817e4aSriastradh if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) != PPSMC_Result_OK) 1837d8817e4aSriastradh return -EINVAL; 1838d8817e4aSriastradh 1839d8817e4aSriastradh return 0; 1840d8817e4aSriastradh } 1841d8817e4aSriastradh 1842d8817e4aSriastradh static int btc_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 1843d8817e4aSriastradh struct radeon_ps *radeon_new_state) 1844d8817e4aSriastradh { 1845d8817e4aSriastradh int ret = 0; 1846d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1847d8817e4aSriastradh 1848d8817e4aSriastradh if (eg_pi->ulv.supported) { 1849d8817e4aSriastradh if (btc_is_state_ulv_compatible(rdev, radeon_new_state)) { 1850d8817e4aSriastradh // Set ARB[0] to reflect the DRAM timing needed for ULV. 1851d8817e4aSriastradh ret = btc_set_ulv_dram_timing(rdev); 1852d8817e4aSriastradh if (ret == 0) 1853d8817e4aSriastradh ret = btc_enable_ulv(rdev); 1854d8817e4aSriastradh } 1855d8817e4aSriastradh } 1856d8817e4aSriastradh 1857d8817e4aSriastradh return ret; 1858d8817e4aSriastradh } 1859d8817e4aSriastradh 1860d8817e4aSriastradh static bool btc_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 1861d8817e4aSriastradh { 1862d8817e4aSriastradh bool result = true; 1863d8817e4aSriastradh 1864d8817e4aSriastradh switch (in_reg) { 1865d8817e4aSriastradh case MC_SEQ_RAS_TIMING >> 2: 1866d8817e4aSriastradh *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 1867d8817e4aSriastradh break; 1868d8817e4aSriastradh case MC_SEQ_CAS_TIMING >> 2: 1869d8817e4aSriastradh *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 1870d8817e4aSriastradh break; 1871d8817e4aSriastradh case MC_SEQ_MISC_TIMING >> 2: 1872d8817e4aSriastradh *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 1873d8817e4aSriastradh break; 1874d8817e4aSriastradh case MC_SEQ_MISC_TIMING2 >> 2: 1875d8817e4aSriastradh *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 1876d8817e4aSriastradh break; 1877d8817e4aSriastradh case MC_SEQ_RD_CTL_D0 >> 2: 1878d8817e4aSriastradh *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 1879d8817e4aSriastradh break; 1880d8817e4aSriastradh case MC_SEQ_RD_CTL_D1 >> 2: 1881d8817e4aSriastradh *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 1882d8817e4aSriastradh break; 1883d8817e4aSriastradh case MC_SEQ_WR_CTL_D0 >> 2: 1884d8817e4aSriastradh *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 1885d8817e4aSriastradh break; 1886d8817e4aSriastradh case MC_SEQ_WR_CTL_D1 >> 2: 1887d8817e4aSriastradh *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 1888d8817e4aSriastradh break; 1889d8817e4aSriastradh case MC_PMG_CMD_EMRS >> 2: 1890d8817e4aSriastradh *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 1891d8817e4aSriastradh break; 1892d8817e4aSriastradh case MC_PMG_CMD_MRS >> 2: 1893d8817e4aSriastradh *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 1894d8817e4aSriastradh break; 1895d8817e4aSriastradh case MC_PMG_CMD_MRS1 >> 2: 1896d8817e4aSriastradh *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 1897d8817e4aSriastradh break; 1898d8817e4aSriastradh default: 1899d8817e4aSriastradh result = false; 1900d8817e4aSriastradh break; 1901d8817e4aSriastradh } 1902d8817e4aSriastradh 1903d8817e4aSriastradh return result; 1904d8817e4aSriastradh } 1905d8817e4aSriastradh 1906d8817e4aSriastradh static void btc_set_valid_flag(struct evergreen_mc_reg_table *table) 1907d8817e4aSriastradh { 1908d8817e4aSriastradh u8 i, j; 1909d8817e4aSriastradh 1910d8817e4aSriastradh for (i = 0; i < table->last; i++) { 1911d8817e4aSriastradh for (j = 1; j < table->num_entries; j++) { 1912d8817e4aSriastradh if (table->mc_reg_table_entry[j-1].mc_data[i] != 1913d8817e4aSriastradh table->mc_reg_table_entry[j].mc_data[i]) { 1914d8817e4aSriastradh table->valid_flag |= (1 << i); 1915d8817e4aSriastradh break; 1916d8817e4aSriastradh } 1917d8817e4aSriastradh } 1918d8817e4aSriastradh } 1919d8817e4aSriastradh } 1920d8817e4aSriastradh 1921d8817e4aSriastradh static int btc_set_mc_special_registers(struct radeon_device *rdev, 1922d8817e4aSriastradh struct evergreen_mc_reg_table *table) 1923d8817e4aSriastradh { 1924d8817e4aSriastradh struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1925d8817e4aSriastradh u8 i, j, k; 1926d8817e4aSriastradh u32 tmp; 1927d8817e4aSriastradh 1928d8817e4aSriastradh for (i = 0, j = table->last; i < table->last; i++) { 1929d8817e4aSriastradh switch (table->mc_reg_address[i].s1) { 1930d8817e4aSriastradh case MC_SEQ_MISC1 >> 2: 1931d8817e4aSriastradh tmp = RREG32(MC_PMG_CMD_EMRS); 1932d8817e4aSriastradh table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 1933d8817e4aSriastradh table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 1934d8817e4aSriastradh for (k = 0; k < table->num_entries; k++) { 1935d8817e4aSriastradh table->mc_reg_table_entry[k].mc_data[j] = 1936d8817e4aSriastradh ((tmp & 0xffff0000)) | 1937d8817e4aSriastradh ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 1938d8817e4aSriastradh } 1939d8817e4aSriastradh j++; 1940d8817e4aSriastradh 1941d8817e4aSriastradh if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1942d8817e4aSriastradh return -EINVAL; 1943d8817e4aSriastradh 1944d8817e4aSriastradh tmp = RREG32(MC_PMG_CMD_MRS); 1945d8817e4aSriastradh table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 1946d8817e4aSriastradh table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 1947d8817e4aSriastradh for (k = 0; k < table->num_entries; k++) { 1948d8817e4aSriastradh table->mc_reg_table_entry[k].mc_data[j] = 1949d8817e4aSriastradh (tmp & 0xffff0000) | 1950d8817e4aSriastradh (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 1951d8817e4aSriastradh if (!pi->mem_gddr5) 1952d8817e4aSriastradh table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 1953d8817e4aSriastradh } 1954d8817e4aSriastradh j++; 1955d8817e4aSriastradh 1956d8817e4aSriastradh if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1957d8817e4aSriastradh return -EINVAL; 1958d8817e4aSriastradh break; 1959d8817e4aSriastradh case MC_SEQ_RESERVE_M >> 2: 1960d8817e4aSriastradh tmp = RREG32(MC_PMG_CMD_MRS1); 1961d8817e4aSriastradh table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 1962d8817e4aSriastradh table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 1963d8817e4aSriastradh for (k = 0; k < table->num_entries; k++) { 1964d8817e4aSriastradh table->mc_reg_table_entry[k].mc_data[j] = 1965d8817e4aSriastradh (tmp & 0xffff0000) | 1966d8817e4aSriastradh (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 1967d8817e4aSriastradh } 1968d8817e4aSriastradh j++; 1969d8817e4aSriastradh 1970d8817e4aSriastradh if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1971d8817e4aSriastradh return -EINVAL; 1972d8817e4aSriastradh break; 1973d8817e4aSriastradh default: 1974d8817e4aSriastradh break; 1975d8817e4aSriastradh } 1976d8817e4aSriastradh } 1977d8817e4aSriastradh 1978d8817e4aSriastradh table->last = j; 1979d8817e4aSriastradh 1980d8817e4aSriastradh return 0; 1981d8817e4aSriastradh } 1982d8817e4aSriastradh 1983d8817e4aSriastradh static void btc_set_s0_mc_reg_index(struct evergreen_mc_reg_table *table) 1984d8817e4aSriastradh { 1985d8817e4aSriastradh u32 i; 1986d8817e4aSriastradh u16 address; 1987d8817e4aSriastradh 1988d8817e4aSriastradh for (i = 0; i < table->last; i++) { 1989d8817e4aSriastradh table->mc_reg_address[i].s0 = 1990d8817e4aSriastradh btc_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 1991d8817e4aSriastradh address : table->mc_reg_address[i].s1; 1992d8817e4aSriastradh } 1993d8817e4aSriastradh } 1994d8817e4aSriastradh 1995d8817e4aSriastradh static int btc_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 1996d8817e4aSriastradh struct evergreen_mc_reg_table *eg_table) 1997d8817e4aSriastradh { 1998d8817e4aSriastradh u8 i, j; 1999d8817e4aSriastradh 2000d8817e4aSriastradh if (table->last > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 2001d8817e4aSriastradh return -EINVAL; 2002d8817e4aSriastradh 2003d8817e4aSriastradh if (table->num_entries > MAX_AC_TIMING_ENTRIES) 2004d8817e4aSriastradh return -EINVAL; 2005d8817e4aSriastradh 2006d8817e4aSriastradh for (i = 0; i < table->last; i++) 2007d8817e4aSriastradh eg_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 2008d8817e4aSriastradh eg_table->last = table->last; 2009d8817e4aSriastradh 2010d8817e4aSriastradh for (i = 0; i < table->num_entries; i++) { 2011d8817e4aSriastradh eg_table->mc_reg_table_entry[i].mclk_max = 2012d8817e4aSriastradh table->mc_reg_table_entry[i].mclk_max; 2013d8817e4aSriastradh for(j = 0; j < table->last; j++) 2014d8817e4aSriastradh eg_table->mc_reg_table_entry[i].mc_data[j] = 2015d8817e4aSriastradh table->mc_reg_table_entry[i].mc_data[j]; 2016d8817e4aSriastradh } 2017d8817e4aSriastradh eg_table->num_entries = table->num_entries; 2018d8817e4aSriastradh 2019d8817e4aSriastradh return 0; 2020d8817e4aSriastradh } 2021d8817e4aSriastradh 2022d8817e4aSriastradh static int btc_initialize_mc_reg_table(struct radeon_device *rdev) 2023d8817e4aSriastradh { 2024d8817e4aSriastradh int ret; 2025d8817e4aSriastradh struct atom_mc_reg_table *table; 2026d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2027d8817e4aSriastradh struct evergreen_mc_reg_table *eg_table = &eg_pi->mc_reg_table; 2028d8817e4aSriastradh u8 module_index = rv770_get_memory_module_index(rdev); 2029d8817e4aSriastradh 2030d8817e4aSriastradh table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 2031d8817e4aSriastradh if (!table) 2032d8817e4aSriastradh return -ENOMEM; 2033d8817e4aSriastradh 2034d8817e4aSriastradh /* Program additional LP registers that are no longer programmed by VBIOS */ 2035d8817e4aSriastradh WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 2036d8817e4aSriastradh WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 2037d8817e4aSriastradh WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 2038d8817e4aSriastradh WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 2039d8817e4aSriastradh WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 2040d8817e4aSriastradh WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 2041d8817e4aSriastradh WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 2042d8817e4aSriastradh WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 2043d8817e4aSriastradh WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 2044d8817e4aSriastradh WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 2045d8817e4aSriastradh WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 2046d8817e4aSriastradh 2047d8817e4aSriastradh ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 2048d8817e4aSriastradh 2049d8817e4aSriastradh if (ret) 2050d8817e4aSriastradh goto init_mc_done; 2051d8817e4aSriastradh 2052d8817e4aSriastradh ret = btc_copy_vbios_mc_reg_table(table, eg_table); 2053d8817e4aSriastradh 2054d8817e4aSriastradh if (ret) 2055d8817e4aSriastradh goto init_mc_done; 2056d8817e4aSriastradh 2057d8817e4aSriastradh btc_set_s0_mc_reg_index(eg_table); 2058d8817e4aSriastradh ret = btc_set_mc_special_registers(rdev, eg_table); 2059d8817e4aSriastradh 2060d8817e4aSriastradh if (ret) 2061d8817e4aSriastradh goto init_mc_done; 2062d8817e4aSriastradh 2063d8817e4aSriastradh btc_set_valid_flag(eg_table); 2064d8817e4aSriastradh 2065d8817e4aSriastradh init_mc_done: 2066d8817e4aSriastradh kfree(table); 2067d8817e4aSriastradh 2068d8817e4aSriastradh return ret; 2069d8817e4aSriastradh } 2070d8817e4aSriastradh 2071d8817e4aSriastradh static void btc_init_stutter_mode(struct radeon_device *rdev) 2072d8817e4aSriastradh { 2073d8817e4aSriastradh struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2074d8817e4aSriastradh u32 tmp; 2075d8817e4aSriastradh 2076d8817e4aSriastradh if (pi->mclk_stutter_mode_threshold) { 2077d8817e4aSriastradh if (pi->mem_gddr5) { 2078d8817e4aSriastradh tmp = RREG32(MC_PMG_AUTO_CFG); 2079d8817e4aSriastradh if ((0x200 & tmp) == 0) { 2080d8817e4aSriastradh tmp = (tmp & 0xfffffc0b) | 0x204; 2081d8817e4aSriastradh WREG32(MC_PMG_AUTO_CFG, tmp); 2082d8817e4aSriastradh } 2083d8817e4aSriastradh } 2084d8817e4aSriastradh } 2085d8817e4aSriastradh } 2086d8817e4aSriastradh 2087d8817e4aSriastradh bool btc_dpm_vblank_too_short(struct radeon_device *rdev) 2088d8817e4aSriastradh { 2089d8817e4aSriastradh struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2090d8817e4aSriastradh u32 vblank_time = r600_dpm_get_vblank_time(rdev); 2091d8817e4aSriastradh u32 switch_limit = pi->mem_gddr5 ? 450 : 100; 2092d8817e4aSriastradh 2093d8817e4aSriastradh if (vblank_time < switch_limit) 2094d8817e4aSriastradh return true; 2095d8817e4aSriastradh else 2096d8817e4aSriastradh return false; 2097d8817e4aSriastradh 2098d8817e4aSriastradh } 2099d8817e4aSriastradh 2100d8817e4aSriastradh static void btc_apply_state_adjust_rules(struct radeon_device *rdev, 2101d8817e4aSriastradh struct radeon_ps *rps) 2102d8817e4aSriastradh { 2103d8817e4aSriastradh struct rv7xx_ps *ps = rv770_get_ps(rps); 2104d8817e4aSriastradh struct radeon_clock_and_voltage_limits *max_limits; 2105d8817e4aSriastradh bool disable_mclk_switching; 2106d8817e4aSriastradh u32 mclk, sclk; 2107d8817e4aSriastradh u16 vddc, vddci; 2108d8817e4aSriastradh 2109d8817e4aSriastradh if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2110d8817e4aSriastradh btc_dpm_vblank_too_short(rdev)) 2111d8817e4aSriastradh disable_mclk_switching = true; 2112d8817e4aSriastradh else 2113d8817e4aSriastradh disable_mclk_switching = false; 2114d8817e4aSriastradh 2115d8817e4aSriastradh if (rdev->pm.dpm.ac_power) 2116d8817e4aSriastradh max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2117d8817e4aSriastradh else 2118d8817e4aSriastradh max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2119d8817e4aSriastradh 2120d8817e4aSriastradh if (rdev->pm.dpm.ac_power == false) { 2121d8817e4aSriastradh if (ps->high.mclk > max_limits->mclk) 2122d8817e4aSriastradh ps->high.mclk = max_limits->mclk; 2123d8817e4aSriastradh if (ps->high.sclk > max_limits->sclk) 2124d8817e4aSriastradh ps->high.sclk = max_limits->sclk; 2125d8817e4aSriastradh if (ps->high.vddc > max_limits->vddc) 2126d8817e4aSriastradh ps->high.vddc = max_limits->vddc; 2127d8817e4aSriastradh if (ps->high.vddci > max_limits->vddci) 2128d8817e4aSriastradh ps->high.vddci = max_limits->vddci; 2129d8817e4aSriastradh 2130d8817e4aSriastradh if (ps->medium.mclk > max_limits->mclk) 2131d8817e4aSriastradh ps->medium.mclk = max_limits->mclk; 2132d8817e4aSriastradh if (ps->medium.sclk > max_limits->sclk) 2133d8817e4aSriastradh ps->medium.sclk = max_limits->sclk; 2134d8817e4aSriastradh if (ps->medium.vddc > max_limits->vddc) 2135d8817e4aSriastradh ps->medium.vddc = max_limits->vddc; 2136d8817e4aSriastradh if (ps->medium.vddci > max_limits->vddci) 2137d8817e4aSriastradh ps->medium.vddci = max_limits->vddci; 2138d8817e4aSriastradh 2139d8817e4aSriastradh if (ps->low.mclk > max_limits->mclk) 2140d8817e4aSriastradh ps->low.mclk = max_limits->mclk; 2141d8817e4aSriastradh if (ps->low.sclk > max_limits->sclk) 2142d8817e4aSriastradh ps->low.sclk = max_limits->sclk; 2143d8817e4aSriastradh if (ps->low.vddc > max_limits->vddc) 2144d8817e4aSriastradh ps->low.vddc = max_limits->vddc; 2145d8817e4aSriastradh if (ps->low.vddci > max_limits->vddci) 2146d8817e4aSriastradh ps->low.vddci = max_limits->vddci; 2147d8817e4aSriastradh } 2148d8817e4aSriastradh 2149d8817e4aSriastradh /* XXX validate the min clocks required for display */ 2150d8817e4aSriastradh 2151d8817e4aSriastradh if (disable_mclk_switching) { 2152d8817e4aSriastradh sclk = ps->low.sclk; 2153d8817e4aSriastradh mclk = ps->high.mclk; 2154d8817e4aSriastradh vddc = ps->low.vddc; 2155d8817e4aSriastradh vddci = ps->high.vddci; 2156d8817e4aSriastradh } else { 2157d8817e4aSriastradh sclk = ps->low.sclk; 2158d8817e4aSriastradh mclk = ps->low.mclk; 2159d8817e4aSriastradh vddc = ps->low.vddc; 2160d8817e4aSriastradh vddci = ps->low.vddci; 2161d8817e4aSriastradh } 2162d8817e4aSriastradh 2163d8817e4aSriastradh /* adjusted low state */ 2164d8817e4aSriastradh ps->low.sclk = sclk; 2165d8817e4aSriastradh ps->low.mclk = mclk; 2166d8817e4aSriastradh ps->low.vddc = vddc; 2167d8817e4aSriastradh ps->low.vddci = vddci; 2168d8817e4aSriastradh 2169d8817e4aSriastradh btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, 2170d8817e4aSriastradh &ps->low.sclk, &ps->low.mclk); 2171d8817e4aSriastradh 2172d8817e4aSriastradh /* adjusted medium, high states */ 2173d8817e4aSriastradh if (ps->medium.sclk < ps->low.sclk) 2174d8817e4aSriastradh ps->medium.sclk = ps->low.sclk; 2175d8817e4aSriastradh if (ps->medium.vddc < ps->low.vddc) 2176d8817e4aSriastradh ps->medium.vddc = ps->low.vddc; 2177d8817e4aSriastradh if (ps->high.sclk < ps->medium.sclk) 2178d8817e4aSriastradh ps->high.sclk = ps->medium.sclk; 2179d8817e4aSriastradh if (ps->high.vddc < ps->medium.vddc) 2180d8817e4aSriastradh ps->high.vddc = ps->medium.vddc; 2181d8817e4aSriastradh 2182d8817e4aSriastradh if (disable_mclk_switching) { 2183d8817e4aSriastradh mclk = ps->low.mclk; 2184d8817e4aSriastradh if (mclk < ps->medium.mclk) 2185d8817e4aSriastradh mclk = ps->medium.mclk; 2186d8817e4aSriastradh if (mclk < ps->high.mclk) 2187d8817e4aSriastradh mclk = ps->high.mclk; 2188d8817e4aSriastradh ps->low.mclk = mclk; 2189d8817e4aSriastradh ps->low.vddci = vddci; 2190d8817e4aSriastradh ps->medium.mclk = mclk; 2191d8817e4aSriastradh ps->medium.vddci = vddci; 2192d8817e4aSriastradh ps->high.mclk = mclk; 2193d8817e4aSriastradh ps->high.vddci = vddci; 2194d8817e4aSriastradh } else { 2195d8817e4aSriastradh if (ps->medium.mclk < ps->low.mclk) 2196d8817e4aSriastradh ps->medium.mclk = ps->low.mclk; 2197d8817e4aSriastradh if (ps->medium.vddci < ps->low.vddci) 2198d8817e4aSriastradh ps->medium.vddci = ps->low.vddci; 2199d8817e4aSriastradh if (ps->high.mclk < ps->medium.mclk) 2200d8817e4aSriastradh ps->high.mclk = ps->medium.mclk; 2201d8817e4aSriastradh if (ps->high.vddci < ps->medium.vddci) 2202d8817e4aSriastradh ps->high.vddci = ps->medium.vddci; 2203d8817e4aSriastradh } 2204d8817e4aSriastradh 2205d8817e4aSriastradh btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, 2206d8817e4aSriastradh &ps->medium.sclk, &ps->medium.mclk); 2207d8817e4aSriastradh btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, 2208d8817e4aSriastradh &ps->high.sclk, &ps->high.mclk); 2209d8817e4aSriastradh 2210d8817e4aSriastradh btc_adjust_clock_combinations(rdev, max_limits, &ps->low); 2211d8817e4aSriastradh btc_adjust_clock_combinations(rdev, max_limits, &ps->medium); 2212d8817e4aSriastradh btc_adjust_clock_combinations(rdev, max_limits, &ps->high); 2213d8817e4aSriastradh 2214d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2215d8817e4aSriastradh ps->low.sclk, max_limits->vddc, &ps->low.vddc); 2216d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2217d8817e4aSriastradh ps->low.mclk, max_limits->vddci, &ps->low.vddci); 2218d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2219d8817e4aSriastradh ps->low.mclk, max_limits->vddc, &ps->low.vddc); 2220d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 2221d8817e4aSriastradh rdev->clock.current_dispclk, max_limits->vddc, &ps->low.vddc); 2222d8817e4aSriastradh 2223d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2224d8817e4aSriastradh ps->medium.sclk, max_limits->vddc, &ps->medium.vddc); 2225d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2226d8817e4aSriastradh ps->medium.mclk, max_limits->vddci, &ps->medium.vddci); 2227d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2228d8817e4aSriastradh ps->medium.mclk, max_limits->vddc, &ps->medium.vddc); 2229d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 2230d8817e4aSriastradh rdev->clock.current_dispclk, max_limits->vddc, &ps->medium.vddc); 2231d8817e4aSriastradh 2232d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2233d8817e4aSriastradh ps->high.sclk, max_limits->vddc, &ps->high.vddc); 2234d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2235d8817e4aSriastradh ps->high.mclk, max_limits->vddci, &ps->high.vddci); 2236d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2237d8817e4aSriastradh ps->high.mclk, max_limits->vddc, &ps->high.vddc); 2238d8817e4aSriastradh btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 2239d8817e4aSriastradh rdev->clock.current_dispclk, max_limits->vddc, &ps->high.vddc); 2240d8817e4aSriastradh 2241d8817e4aSriastradh btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci, 2242d8817e4aSriastradh &ps->low.vddc, &ps->low.vddci); 2243d8817e4aSriastradh btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci, 2244d8817e4aSriastradh &ps->medium.vddc, &ps->medium.vddci); 2245d8817e4aSriastradh btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci, 2246d8817e4aSriastradh &ps->high.vddc, &ps->high.vddci); 2247d8817e4aSriastradh 2248d8817e4aSriastradh if ((ps->high.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) && 2249d8817e4aSriastradh (ps->medium.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) && 2250d8817e4aSriastradh (ps->low.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)) 2251d8817e4aSriastradh ps->dc_compatible = true; 2252d8817e4aSriastradh else 2253d8817e4aSriastradh ps->dc_compatible = false; 2254d8817e4aSriastradh 2255d8817e4aSriastradh if (ps->low.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) 2256d8817e4aSriastradh ps->low.flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2; 2257d8817e4aSriastradh if (ps->medium.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) 2258d8817e4aSriastradh ps->medium.flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2; 2259d8817e4aSriastradh if (ps->high.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) 2260d8817e4aSriastradh ps->high.flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2; 2261d8817e4aSriastradh } 2262d8817e4aSriastradh 2263d8817e4aSriastradh static void btc_update_current_ps(struct radeon_device *rdev, 2264d8817e4aSriastradh struct radeon_ps *rps) 2265d8817e4aSriastradh { 2266d8817e4aSriastradh struct rv7xx_ps *new_ps = rv770_get_ps(rps); 2267d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2268d8817e4aSriastradh 2269d8817e4aSriastradh eg_pi->current_rps = *rps; 2270d8817e4aSriastradh eg_pi->current_ps = *new_ps; 2271d8817e4aSriastradh eg_pi->current_rps.ps_priv = &eg_pi->current_ps; 2272d8817e4aSriastradh } 2273d8817e4aSriastradh 2274d8817e4aSriastradh static void btc_update_requested_ps(struct radeon_device *rdev, 2275d8817e4aSriastradh struct radeon_ps *rps) 2276d8817e4aSriastradh { 2277d8817e4aSriastradh struct rv7xx_ps *new_ps = rv770_get_ps(rps); 2278d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2279d8817e4aSriastradh 2280d8817e4aSriastradh eg_pi->requested_rps = *rps; 2281d8817e4aSriastradh eg_pi->requested_ps = *new_ps; 2282d8817e4aSriastradh eg_pi->requested_rps.ps_priv = &eg_pi->requested_ps; 2283d8817e4aSriastradh } 2284d8817e4aSriastradh 2285d8817e4aSriastradh #if 0 2286d8817e4aSriastradh void btc_dpm_reset_asic(struct radeon_device *rdev) 2287d8817e4aSriastradh { 2288d8817e4aSriastradh rv770_restrict_performance_levels_before_switch(rdev); 2289d8817e4aSriastradh btc_disable_ulv(rdev); 2290d8817e4aSriastradh btc_set_boot_state_timing(rdev); 2291d8817e4aSriastradh rv770_set_boot_state(rdev); 2292d8817e4aSriastradh } 2293d8817e4aSriastradh #endif 2294d8817e4aSriastradh 2295d8817e4aSriastradh int btc_dpm_pre_set_power_state(struct radeon_device *rdev) 2296d8817e4aSriastradh { 2297d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2298d8817e4aSriastradh struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 2299d8817e4aSriastradh struct radeon_ps *new_ps = &requested_ps; 2300d8817e4aSriastradh 2301d8817e4aSriastradh btc_update_requested_ps(rdev, new_ps); 2302d8817e4aSriastradh 2303d8817e4aSriastradh btc_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 2304d8817e4aSriastradh 2305d8817e4aSriastradh return 0; 2306d8817e4aSriastradh } 2307d8817e4aSriastradh 2308d8817e4aSriastradh int btc_dpm_set_power_state(struct radeon_device *rdev) 2309d8817e4aSriastradh { 2310d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2311d8817e4aSriastradh struct radeon_ps *new_ps = &eg_pi->requested_rps; 2312d8817e4aSriastradh struct radeon_ps *old_ps = &eg_pi->current_rps; 2313d8817e4aSriastradh int ret; 2314d8817e4aSriastradh 2315d8817e4aSriastradh ret = btc_disable_ulv(rdev); 2316d8817e4aSriastradh btc_set_boot_state_timing(rdev); 2317d8817e4aSriastradh ret = rv770_restrict_performance_levels_before_switch(rdev); 2318d8817e4aSriastradh if (ret) { 2319d8817e4aSriastradh DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n"); 2320d8817e4aSriastradh return ret; 2321d8817e4aSriastradh } 2322d8817e4aSriastradh if (eg_pi->pcie_performance_request) 2323d8817e4aSriastradh cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps); 2324d8817e4aSriastradh 2325d8817e4aSriastradh rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 2326d8817e4aSriastradh ret = rv770_halt_smc(rdev); 2327d8817e4aSriastradh if (ret) { 2328d8817e4aSriastradh DRM_ERROR("rv770_halt_smc failed\n"); 2329d8817e4aSriastradh return ret; 2330d8817e4aSriastradh } 2331d8817e4aSriastradh btc_set_at_for_uvd(rdev, new_ps); 2332d8817e4aSriastradh if (eg_pi->smu_uvd_hs) 2333d8817e4aSriastradh btc_notify_uvd_to_smc(rdev, new_ps); 2334d8817e4aSriastradh ret = cypress_upload_sw_state(rdev, new_ps); 2335d8817e4aSriastradh if (ret) { 2336d8817e4aSriastradh DRM_ERROR("cypress_upload_sw_state failed\n"); 2337d8817e4aSriastradh return ret; 2338d8817e4aSriastradh } 2339d8817e4aSriastradh if (eg_pi->dynamic_ac_timing) { 2340d8817e4aSriastradh ret = cypress_upload_mc_reg_table(rdev, new_ps); 2341d8817e4aSriastradh if (ret) { 2342d8817e4aSriastradh DRM_ERROR("cypress_upload_mc_reg_table failed\n"); 2343d8817e4aSriastradh return ret; 2344d8817e4aSriastradh } 2345d8817e4aSriastradh } 2346d8817e4aSriastradh 2347d8817e4aSriastradh cypress_program_memory_timing_parameters(rdev, new_ps); 2348d8817e4aSriastradh 2349d8817e4aSriastradh ret = rv770_resume_smc(rdev); 2350d8817e4aSriastradh if (ret) { 2351d8817e4aSriastradh DRM_ERROR("rv770_resume_smc failed\n"); 2352d8817e4aSriastradh return ret; 2353d8817e4aSriastradh } 2354d8817e4aSriastradh ret = rv770_set_sw_state(rdev); 2355d8817e4aSriastradh if (ret) { 2356d8817e4aSriastradh DRM_ERROR("rv770_set_sw_state failed\n"); 2357d8817e4aSriastradh return ret; 2358d8817e4aSriastradh } 2359d8817e4aSriastradh rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 2360d8817e4aSriastradh 2361d8817e4aSriastradh if (eg_pi->pcie_performance_request) 2362d8817e4aSriastradh cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 2363d8817e4aSriastradh 2364d8817e4aSriastradh ret = btc_set_power_state_conditionally_enable_ulv(rdev, new_ps); 2365d8817e4aSriastradh if (ret) { 2366d8817e4aSriastradh DRM_ERROR("btc_set_power_state_conditionally_enable_ulv failed\n"); 2367d8817e4aSriastradh return ret; 2368d8817e4aSriastradh } 2369d8817e4aSriastradh 2370d8817e4aSriastradh return 0; 2371d8817e4aSriastradh } 2372d8817e4aSriastradh 2373d8817e4aSriastradh void btc_dpm_post_set_power_state(struct radeon_device *rdev) 2374d8817e4aSriastradh { 2375d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2376d8817e4aSriastradh struct radeon_ps *new_ps = &eg_pi->requested_rps; 2377d8817e4aSriastradh 2378d8817e4aSriastradh btc_update_current_ps(rdev, new_ps); 2379d8817e4aSriastradh } 2380d8817e4aSriastradh 2381d8817e4aSriastradh int btc_dpm_enable(struct radeon_device *rdev) 2382d8817e4aSriastradh { 2383d8817e4aSriastradh struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2384d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2385d8817e4aSriastradh struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 2386d8817e4aSriastradh int ret; 2387d8817e4aSriastradh 2388d8817e4aSriastradh if (pi->gfx_clock_gating) 2389d8817e4aSriastradh btc_cg_clock_gating_default(rdev); 2390d8817e4aSriastradh 2391d8817e4aSriastradh if (btc_dpm_enabled(rdev)) 2392d8817e4aSriastradh return -EINVAL; 2393d8817e4aSriastradh 2394d8817e4aSriastradh if (pi->mg_clock_gating) 2395d8817e4aSriastradh btc_mg_clock_gating_default(rdev); 2396d8817e4aSriastradh 2397d8817e4aSriastradh if (eg_pi->ls_clock_gating) 2398d8817e4aSriastradh btc_ls_clock_gating_default(rdev); 2399d8817e4aSriastradh 2400d8817e4aSriastradh if (pi->voltage_control) { 2401d8817e4aSriastradh rv770_enable_voltage_control(rdev, true); 2402d8817e4aSriastradh ret = cypress_construct_voltage_tables(rdev); 2403d8817e4aSriastradh if (ret) { 2404d8817e4aSriastradh DRM_ERROR("cypress_construct_voltage_tables failed\n"); 2405d8817e4aSriastradh return ret; 2406d8817e4aSriastradh } 2407d8817e4aSriastradh } 2408d8817e4aSriastradh 2409d8817e4aSriastradh if (pi->mvdd_control) { 2410d8817e4aSriastradh ret = cypress_get_mvdd_configuration(rdev); 2411d8817e4aSriastradh if (ret) { 2412d8817e4aSriastradh DRM_ERROR("cypress_get_mvdd_configuration failed\n"); 2413d8817e4aSriastradh return ret; 2414d8817e4aSriastradh } 2415d8817e4aSriastradh } 2416d8817e4aSriastradh 2417d8817e4aSriastradh if (eg_pi->dynamic_ac_timing) { 2418d8817e4aSriastradh ret = btc_initialize_mc_reg_table(rdev); 2419d8817e4aSriastradh if (ret) 2420d8817e4aSriastradh eg_pi->dynamic_ac_timing = false; 2421d8817e4aSriastradh } 2422d8817e4aSriastradh 2423d8817e4aSriastradh if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) 2424d8817e4aSriastradh rv770_enable_backbias(rdev, true); 2425d8817e4aSriastradh 2426d8817e4aSriastradh if (pi->dynamic_ss) 2427d8817e4aSriastradh cypress_enable_spread_spectrum(rdev, true); 2428d8817e4aSriastradh 2429d8817e4aSriastradh if (pi->thermal_protection) 2430d8817e4aSriastradh rv770_enable_thermal_protection(rdev, true); 2431d8817e4aSriastradh 2432d8817e4aSriastradh rv770_setup_bsp(rdev); 2433d8817e4aSriastradh rv770_program_git(rdev); 2434d8817e4aSriastradh rv770_program_tp(rdev); 2435d8817e4aSriastradh rv770_program_tpp(rdev); 2436d8817e4aSriastradh rv770_program_sstp(rdev); 2437d8817e4aSriastradh rv770_program_engine_speed_parameters(rdev); 2438d8817e4aSriastradh cypress_enable_display_gap(rdev); 2439d8817e4aSriastradh rv770_program_vc(rdev); 2440d8817e4aSriastradh 2441d8817e4aSriastradh if (pi->dynamic_pcie_gen2) 2442d8817e4aSriastradh btc_enable_dynamic_pcie_gen2(rdev, true); 2443d8817e4aSriastradh 2444d8817e4aSriastradh ret = rv770_upload_firmware(rdev); 2445d8817e4aSriastradh if (ret) { 2446d8817e4aSriastradh DRM_ERROR("rv770_upload_firmware failed\n"); 2447d8817e4aSriastradh return ret; 2448d8817e4aSriastradh } 2449d8817e4aSriastradh ret = cypress_get_table_locations(rdev); 2450d8817e4aSriastradh if (ret) { 2451d8817e4aSriastradh DRM_ERROR("cypress_get_table_locations failed\n"); 2452d8817e4aSriastradh return ret; 2453d8817e4aSriastradh } 2454d8817e4aSriastradh ret = btc_init_smc_table(rdev, boot_ps); 2455d8817e4aSriastradh if (ret) 2456d8817e4aSriastradh return ret; 2457d8817e4aSriastradh 2458d8817e4aSriastradh if (eg_pi->dynamic_ac_timing) { 2459d8817e4aSriastradh ret = cypress_populate_mc_reg_table(rdev, boot_ps); 2460d8817e4aSriastradh if (ret) { 2461d8817e4aSriastradh DRM_ERROR("cypress_populate_mc_reg_table failed\n"); 2462d8817e4aSriastradh return ret; 2463d8817e4aSriastradh } 2464d8817e4aSriastradh } 2465d8817e4aSriastradh 2466d8817e4aSriastradh cypress_program_response_times(rdev); 2467d8817e4aSriastradh r7xx_start_smc(rdev); 2468d8817e4aSriastradh ret = cypress_notify_smc_display_change(rdev, false); 2469d8817e4aSriastradh if (ret) { 2470d8817e4aSriastradh DRM_ERROR("cypress_notify_smc_display_change failed\n"); 2471d8817e4aSriastradh return ret; 2472d8817e4aSriastradh } 2473d8817e4aSriastradh cypress_enable_sclk_control(rdev, true); 2474d8817e4aSriastradh 2475d8817e4aSriastradh if (eg_pi->memory_transition) 2476d8817e4aSriastradh cypress_enable_mclk_control(rdev, true); 2477d8817e4aSriastradh 2478d8817e4aSriastradh cypress_start_dpm(rdev); 2479d8817e4aSriastradh 2480d8817e4aSriastradh if (pi->gfx_clock_gating) 2481d8817e4aSriastradh btc_cg_clock_gating_enable(rdev, true); 2482d8817e4aSriastradh 2483d8817e4aSriastradh if (pi->mg_clock_gating) 2484d8817e4aSriastradh btc_mg_clock_gating_enable(rdev, true); 2485d8817e4aSriastradh 2486d8817e4aSriastradh if (eg_pi->ls_clock_gating) 2487d8817e4aSriastradh btc_ls_clock_gating_enable(rdev, true); 2488d8817e4aSriastradh 2489d8817e4aSriastradh rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 2490d8817e4aSriastradh 2491d8817e4aSriastradh btc_init_stutter_mode(rdev); 2492d8817e4aSriastradh 2493d8817e4aSriastradh btc_update_current_ps(rdev, rdev->pm.dpm.boot_ps); 2494d8817e4aSriastradh 2495d8817e4aSriastradh return 0; 2496d8817e4aSriastradh }; 2497d8817e4aSriastradh 2498d8817e4aSriastradh void btc_dpm_disable(struct radeon_device *rdev) 2499d8817e4aSriastradh { 2500d8817e4aSriastradh struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2501d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2502d8817e4aSriastradh 2503d8817e4aSriastradh if (!btc_dpm_enabled(rdev)) 2504d8817e4aSriastradh return; 2505d8817e4aSriastradh 2506d8817e4aSriastradh rv770_clear_vc(rdev); 2507d8817e4aSriastradh 2508d8817e4aSriastradh if (pi->thermal_protection) 2509d8817e4aSriastradh rv770_enable_thermal_protection(rdev, false); 2510d8817e4aSriastradh 2511d8817e4aSriastradh if (pi->dynamic_pcie_gen2) 2512d8817e4aSriastradh btc_enable_dynamic_pcie_gen2(rdev, false); 2513d8817e4aSriastradh 2514d8817e4aSriastradh if (rdev->irq.installed && 2515d8817e4aSriastradh r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 2516d8817e4aSriastradh rdev->irq.dpm_thermal = false; 2517d8817e4aSriastradh radeon_irq_set(rdev); 2518d8817e4aSriastradh } 2519d8817e4aSriastradh 2520d8817e4aSriastradh if (pi->gfx_clock_gating) 2521d8817e4aSriastradh btc_cg_clock_gating_enable(rdev, false); 2522d8817e4aSriastradh 2523d8817e4aSriastradh if (pi->mg_clock_gating) 2524d8817e4aSriastradh btc_mg_clock_gating_enable(rdev, false); 2525d8817e4aSriastradh 2526d8817e4aSriastradh if (eg_pi->ls_clock_gating) 2527d8817e4aSriastradh btc_ls_clock_gating_enable(rdev, false); 2528d8817e4aSriastradh 2529d8817e4aSriastradh rv770_stop_dpm(rdev); 2530d8817e4aSriastradh btc_reset_to_default(rdev); 2531d8817e4aSriastradh btc_stop_smc(rdev); 2532d8817e4aSriastradh cypress_enable_spread_spectrum(rdev, false); 2533d8817e4aSriastradh 2534d8817e4aSriastradh btc_update_current_ps(rdev, rdev->pm.dpm.boot_ps); 2535d8817e4aSriastradh } 2536d8817e4aSriastradh 2537d8817e4aSriastradh void btc_dpm_setup_asic(struct radeon_device *rdev) 2538d8817e4aSriastradh { 2539d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2540d8817e4aSriastradh int r; 2541d8817e4aSriastradh 2542d8817e4aSriastradh r = ni_mc_load_microcode(rdev); 2543d8817e4aSriastradh if (r) 2544d8817e4aSriastradh DRM_ERROR("Failed to load MC firmware!\n"); 2545d8817e4aSriastradh rv770_get_memory_type(rdev); 2546d8817e4aSriastradh rv740_read_clock_registers(rdev); 2547d8817e4aSriastradh btc_read_arb_registers(rdev); 2548d8817e4aSriastradh rv770_read_voltage_smio_registers(rdev); 2549d8817e4aSriastradh 2550d8817e4aSriastradh if (eg_pi->pcie_performance_request) 2551d8817e4aSriastradh cypress_advertise_gen2_capability(rdev); 2552d8817e4aSriastradh 2553d8817e4aSriastradh rv770_get_pcie_gen2_status(rdev); 2554d8817e4aSriastradh rv770_enable_acpi_pm(rdev); 2555d8817e4aSriastradh } 2556d8817e4aSriastradh 2557d8817e4aSriastradh int btc_dpm_init(struct radeon_device *rdev) 2558d8817e4aSriastradh { 2559d8817e4aSriastradh struct rv7xx_power_info *pi; 2560d8817e4aSriastradh struct evergreen_power_info *eg_pi; 2561d8817e4aSriastradh struct atom_clock_dividers dividers; 2562d8817e4aSriastradh int ret; 2563d8817e4aSriastradh 2564d8817e4aSriastradh eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL); 2565d8817e4aSriastradh if (eg_pi == NULL) 2566d8817e4aSriastradh return -ENOMEM; 2567d8817e4aSriastradh rdev->pm.dpm.priv = eg_pi; 2568d8817e4aSriastradh pi = &eg_pi->rv7xx; 2569d8817e4aSriastradh 2570d8817e4aSriastradh rv770_get_max_vddc(rdev); 2571d8817e4aSriastradh 2572d8817e4aSriastradh eg_pi->ulv.supported = false; 2573d8817e4aSriastradh pi->acpi_vddc = 0; 2574d8817e4aSriastradh eg_pi->acpi_vddci = 0; 2575d8817e4aSriastradh pi->min_vddc_in_table = 0; 2576d8817e4aSriastradh pi->max_vddc_in_table = 0; 2577d8817e4aSriastradh 2578d8817e4aSriastradh ret = r600_get_platform_caps(rdev); 2579d8817e4aSriastradh if (ret) 2580d8817e4aSriastradh return ret; 2581d8817e4aSriastradh 2582d8817e4aSriastradh ret = rv7xx_parse_power_table(rdev); 2583d8817e4aSriastradh if (ret) 2584d8817e4aSriastradh return ret; 2585d8817e4aSriastradh ret = r600_parse_extended_power_table(rdev); 2586d8817e4aSriastradh if (ret) 2587d8817e4aSriastradh return ret; 2588d8817e4aSriastradh 2589d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 25901571a7a1Sriastradh kcalloc(4, 25911571a7a1Sriastradh sizeof(struct radeon_clock_voltage_dependency_entry), 25921571a7a1Sriastradh GFP_KERNEL); 2593d8817e4aSriastradh if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 2594d8817e4aSriastradh r600_free_extended_power_table(rdev); 2595d8817e4aSriastradh return -ENOMEM; 2596d8817e4aSriastradh } 2597d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 2598d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 2599d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 2600d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 2601d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 800; 2602d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 2603d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 800; 2604d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 2605d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 800; 2606d8817e4aSriastradh 2607d8817e4aSriastradh if (rdev->pm.dpm.voltage_response_time == 0) 2608d8817e4aSriastradh rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 2609d8817e4aSriastradh if (rdev->pm.dpm.backbias_response_time == 0) 2610d8817e4aSriastradh rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 2611d8817e4aSriastradh 2612d8817e4aSriastradh ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 2613d8817e4aSriastradh 0, false, ÷rs); 2614d8817e4aSriastradh if (ret) 2615d8817e4aSriastradh pi->ref_div = dividers.ref_div + 1; 2616d8817e4aSriastradh else 2617d8817e4aSriastradh pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 2618d8817e4aSriastradh 2619d8817e4aSriastradh pi->mclk_strobe_mode_threshold = 40000; 2620d8817e4aSriastradh pi->mclk_edc_enable_threshold = 40000; 2621d8817e4aSriastradh eg_pi->mclk_edc_wr_enable_threshold = 40000; 2622d8817e4aSriastradh 2623d8817e4aSriastradh pi->rlp = RV770_RLP_DFLT; 2624d8817e4aSriastradh pi->rmp = RV770_RMP_DFLT; 2625d8817e4aSriastradh pi->lhp = RV770_LHP_DFLT; 2626d8817e4aSriastradh pi->lmp = RV770_LMP_DFLT; 2627d8817e4aSriastradh 2628d8817e4aSriastradh eg_pi->ats[0].rlp = RV770_RLP_DFLT; 2629d8817e4aSriastradh eg_pi->ats[0].rmp = RV770_RMP_DFLT; 2630d8817e4aSriastradh eg_pi->ats[0].lhp = RV770_LHP_DFLT; 2631d8817e4aSriastradh eg_pi->ats[0].lmp = RV770_LMP_DFLT; 2632d8817e4aSriastradh 2633d8817e4aSriastradh eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT; 2634d8817e4aSriastradh eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT; 2635d8817e4aSriastradh eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT; 2636d8817e4aSriastradh eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT; 2637d8817e4aSriastradh 2638d8817e4aSriastradh eg_pi->smu_uvd_hs = true; 2639d8817e4aSriastradh 2640d8817e4aSriastradh pi->voltage_control = 2641d8817e4aSriastradh radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0); 2642d8817e4aSriastradh 2643d8817e4aSriastradh pi->mvdd_control = 2644d8817e4aSriastradh radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0); 2645d8817e4aSriastradh 2646d8817e4aSriastradh eg_pi->vddci_control = 2647d8817e4aSriastradh radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0); 2648d8817e4aSriastradh 2649d8817e4aSriastradh rv770_get_engine_memory_ss(rdev); 2650d8817e4aSriastradh 2651d8817e4aSriastradh pi->asi = RV770_ASI_DFLT; 2652d8817e4aSriastradh pi->pasi = CYPRESS_HASI_DFLT; 2653d8817e4aSriastradh pi->vrc = CYPRESS_VRC_DFLT; 2654d8817e4aSriastradh 2655d8817e4aSriastradh pi->power_gating = false; 2656d8817e4aSriastradh 2657d8817e4aSriastradh pi->gfx_clock_gating = true; 2658d8817e4aSriastradh 2659d8817e4aSriastradh pi->mg_clock_gating = true; 2660d8817e4aSriastradh pi->mgcgtssm = true; 2661d8817e4aSriastradh eg_pi->ls_clock_gating = false; 2662d8817e4aSriastradh eg_pi->sclk_deep_sleep = false; 2663d8817e4aSriastradh 2664d8817e4aSriastradh pi->dynamic_pcie_gen2 = true; 2665d8817e4aSriastradh 2666d8817e4aSriastradh if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 2667d8817e4aSriastradh pi->thermal_protection = true; 2668d8817e4aSriastradh else 2669d8817e4aSriastradh pi->thermal_protection = false; 2670d8817e4aSriastradh 2671d8817e4aSriastradh pi->display_gap = true; 2672d8817e4aSriastradh 2673d8817e4aSriastradh if (rdev->flags & RADEON_IS_MOBILITY) 2674d8817e4aSriastradh pi->dcodt = true; 2675d8817e4aSriastradh else 2676d8817e4aSriastradh pi->dcodt = false; 2677d8817e4aSriastradh 2678d8817e4aSriastradh pi->ulps = true; 2679d8817e4aSriastradh 2680d8817e4aSriastradh eg_pi->dynamic_ac_timing = true; 2681d8817e4aSriastradh eg_pi->abm = true; 2682d8817e4aSriastradh eg_pi->mcls = true; 2683d8817e4aSriastradh eg_pi->light_sleep = true; 2684d8817e4aSriastradh eg_pi->memory_transition = true; 2685d8817e4aSriastradh #if defined(CONFIG_ACPI) 2686d8817e4aSriastradh eg_pi->pcie_performance_request = 2687d8817e4aSriastradh radeon_acpi_is_pcie_performance_request_supported(rdev); 2688d8817e4aSriastradh #else 2689d8817e4aSriastradh eg_pi->pcie_performance_request = false; 2690d8817e4aSriastradh #endif 2691d8817e4aSriastradh 2692d8817e4aSriastradh if (rdev->family == CHIP_BARTS) 2693d8817e4aSriastradh eg_pi->dll_default_on = true; 2694d8817e4aSriastradh else 2695d8817e4aSriastradh eg_pi->dll_default_on = false; 2696d8817e4aSriastradh 2697d8817e4aSriastradh eg_pi->sclk_deep_sleep = false; 2698d8817e4aSriastradh if (ASIC_IS_LOMBOK(rdev)) 2699d8817e4aSriastradh pi->mclk_stutter_mode_threshold = 30000; 2700d8817e4aSriastradh else 2701d8817e4aSriastradh pi->mclk_stutter_mode_threshold = 0; 2702d8817e4aSriastradh 2703d8817e4aSriastradh pi->sram_end = SMC_RAM_END; 2704d8817e4aSriastradh 2705d8817e4aSriastradh rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 2706d8817e4aSriastradh rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 2707d8817e4aSriastradh rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; 2708d8817e4aSriastradh rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk); 2709d8817e4aSriastradh rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk; 2710d8817e4aSriastradh rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 2711d8817e4aSriastradh rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 2712d8817e4aSriastradh 2713d8817e4aSriastradh if (rdev->family == CHIP_TURKS) 2714d8817e4aSriastradh rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 2715d8817e4aSriastradh else 2716d8817e4aSriastradh rdev->pm.dpm.dyn_state.sclk_mclk_delta = 10000; 2717d8817e4aSriastradh 2718d8817e4aSriastradh /* make sure dc limits are valid */ 2719d8817e4aSriastradh if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 2720d8817e4aSriastradh (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 2721d8817e4aSriastradh rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 2722d8817e4aSriastradh rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2723d8817e4aSriastradh 2724d8817e4aSriastradh return 0; 2725d8817e4aSriastradh } 2726d8817e4aSriastradh 2727d8817e4aSriastradh void btc_dpm_fini(struct radeon_device *rdev) 2728d8817e4aSriastradh { 2729d8817e4aSriastradh int i; 2730d8817e4aSriastradh 2731d8817e4aSriastradh for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 2732d8817e4aSriastradh kfree(rdev->pm.dpm.ps[i].ps_priv); 2733d8817e4aSriastradh } 2734d8817e4aSriastradh kfree(rdev->pm.dpm.ps); 2735d8817e4aSriastradh kfree(rdev->pm.dpm.priv); 2736d8817e4aSriastradh kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 2737d8817e4aSriastradh r600_free_extended_power_table(rdev); 2738d8817e4aSriastradh } 2739d8817e4aSriastradh 2740*677dec6eSriastradh #ifdef CONFIG_DEBUG_FS 2741d8817e4aSriastradh void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 2742d8817e4aSriastradh struct seq_file *m) 2743d8817e4aSriastradh { 2744d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2745d8817e4aSriastradh struct radeon_ps *rps = &eg_pi->current_rps; 2746d8817e4aSriastradh struct rv7xx_ps *ps = rv770_get_ps(rps); 2747d8817e4aSriastradh struct rv7xx_pl *pl; 2748d8817e4aSriastradh u32 current_index = 2749d8817e4aSriastradh (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> 2750d8817e4aSriastradh CURRENT_PROFILE_INDEX_SHIFT; 2751d8817e4aSriastradh 2752d8817e4aSriastradh if (current_index > 2) { 2753d8817e4aSriastradh seq_printf(m, "invalid dpm profile %d\n", current_index); 2754d8817e4aSriastradh } else { 2755d8817e4aSriastradh if (current_index == 0) 2756d8817e4aSriastradh pl = &ps->low; 2757d8817e4aSriastradh else if (current_index == 1) 2758d8817e4aSriastradh pl = &ps->medium; 2759d8817e4aSriastradh else /* current_index == 2 */ 2760d8817e4aSriastradh pl = &ps->high; 2761d8817e4aSriastradh seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 2762d8817e4aSriastradh seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", 2763d8817e4aSriastradh current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); 2764d8817e4aSriastradh } 2765d8817e4aSriastradh } 2766*677dec6eSriastradh #endif /* CONFIG_DEBUG_FS */ 2767d8817e4aSriastradh 2768d8817e4aSriastradh u32 btc_dpm_get_current_sclk(struct radeon_device *rdev) 2769d8817e4aSriastradh { 2770d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2771d8817e4aSriastradh struct radeon_ps *rps = &eg_pi->current_rps; 2772d8817e4aSriastradh struct rv7xx_ps *ps = rv770_get_ps(rps); 2773d8817e4aSriastradh struct rv7xx_pl *pl; 2774d8817e4aSriastradh u32 current_index = 2775d8817e4aSriastradh (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> 2776d8817e4aSriastradh CURRENT_PROFILE_INDEX_SHIFT; 2777d8817e4aSriastradh 2778d8817e4aSriastradh if (current_index > 2) { 2779d8817e4aSriastradh return 0; 2780d8817e4aSriastradh } else { 2781d8817e4aSriastradh if (current_index == 0) 2782d8817e4aSriastradh pl = &ps->low; 2783d8817e4aSriastradh else if (current_index == 1) 2784d8817e4aSriastradh pl = &ps->medium; 2785d8817e4aSriastradh else /* current_index == 2 */ 2786d8817e4aSriastradh pl = &ps->high; 2787d8817e4aSriastradh return pl->sclk; 2788d8817e4aSriastradh } 2789d8817e4aSriastradh } 2790d8817e4aSriastradh 2791d8817e4aSriastradh u32 btc_dpm_get_current_mclk(struct radeon_device *rdev) 2792d8817e4aSriastradh { 2793d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2794d8817e4aSriastradh struct radeon_ps *rps = &eg_pi->current_rps; 2795d8817e4aSriastradh struct rv7xx_ps *ps = rv770_get_ps(rps); 2796d8817e4aSriastradh struct rv7xx_pl *pl; 2797d8817e4aSriastradh u32 current_index = 2798d8817e4aSriastradh (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> 2799d8817e4aSriastradh CURRENT_PROFILE_INDEX_SHIFT; 2800d8817e4aSriastradh 2801d8817e4aSriastradh if (current_index > 2) { 2802d8817e4aSriastradh return 0; 2803d8817e4aSriastradh } else { 2804d8817e4aSriastradh if (current_index == 0) 2805d8817e4aSriastradh pl = &ps->low; 2806d8817e4aSriastradh else if (current_index == 1) 2807d8817e4aSriastradh pl = &ps->medium; 2808d8817e4aSriastradh else /* current_index == 2 */ 2809d8817e4aSriastradh pl = &ps->high; 2810d8817e4aSriastradh return pl->mclk; 2811d8817e4aSriastradh } 2812d8817e4aSriastradh } 2813d8817e4aSriastradh 2814d8817e4aSriastradh u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low) 2815d8817e4aSriastradh { 2816d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2817d8817e4aSriastradh struct rv7xx_ps *requested_state = rv770_get_ps(&eg_pi->requested_rps); 2818d8817e4aSriastradh 2819d8817e4aSriastradh if (low) 2820d8817e4aSriastradh return requested_state->low.sclk; 2821d8817e4aSriastradh else 2822d8817e4aSriastradh return requested_state->high.sclk; 2823d8817e4aSriastradh } 2824d8817e4aSriastradh 2825d8817e4aSriastradh u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low) 2826d8817e4aSriastradh { 2827d8817e4aSriastradh struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2828d8817e4aSriastradh struct rv7xx_ps *requested_state = rv770_get_ps(&eg_pi->requested_rps); 2829d8817e4aSriastradh 2830d8817e4aSriastradh if (low) 2831d8817e4aSriastradh return requested_state->low.mclk; 2832d8817e4aSriastradh else 2833d8817e4aSriastradh return requested_state->high.mclk; 2834d8817e4aSriastradh } 2835