1*677dec6eSriastradh /* $NetBSD: rv6xx_dpm.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2d350ecf5Sriastradh 3cb459498Sriastradh /* 4cb459498Sriastradh * Copyright 2011 Advanced Micro Devices, Inc. 5cb459498Sriastradh * 6cb459498Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 7cb459498Sriastradh * copy of this software and associated documentation files (the "Software"), 8cb459498Sriastradh * to deal in the Software without restriction, including without limitation 9cb459498Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10cb459498Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 11cb459498Sriastradh * Software is furnished to do so, subject to the following conditions: 12cb459498Sriastradh * 13cb459498Sriastradh * The above copyright notice and this permission notice shall be included in 14cb459498Sriastradh * all copies or substantial portions of the Software. 15cb459498Sriastradh * 16cb459498Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17cb459498Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18cb459498Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19cb459498Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20cb459498Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21cb459498Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22cb459498Sriastradh * OTHER DEALINGS IN THE SOFTWARE. 23cb459498Sriastradh * 24cb459498Sriastradh * Authors: Alex Deucher 25cb459498Sriastradh */ 26cb459498Sriastradh 27cb459498Sriastradh #ifndef __RV6XX_DPM_H__ 28cb459498Sriastradh #define __RV6XX_DPM_H__ 29cb459498Sriastradh 30cb459498Sriastradh #include "r600_dpm.h" 31cb459498Sriastradh 32cb459498Sriastradh /* Represents a single SCLK step. */ 33cb459498Sriastradh struct rv6xx_sclk_stepping 34cb459498Sriastradh { 35cb459498Sriastradh u32 vco_frequency; 36cb459498Sriastradh u32 post_divider; 37cb459498Sriastradh }; 38cb459498Sriastradh 39cb459498Sriastradh struct rv6xx_pm_hw_state { 40cb459498Sriastradh u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 41cb459498Sriastradh u32 mclks[R600_PM_NUMBER_OF_MCLKS]; 42cb459498Sriastradh u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS]; 43cb459498Sriastradh bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS]; 44cb459498Sriastradh bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 45cb459498Sriastradh u8 high_sclk_index; 46cb459498Sriastradh u8 medium_sclk_index; 47cb459498Sriastradh u8 low_sclk_index; 48cb459498Sriastradh u8 high_mclk_index; 49cb459498Sriastradh u8 medium_mclk_index; 50cb459498Sriastradh u8 low_mclk_index; 51cb459498Sriastradh u8 high_vddc_index; 52cb459498Sriastradh u8 medium_vddc_index; 53cb459498Sriastradh u8 low_vddc_index; 54cb459498Sriastradh u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 55cb459498Sriastradh u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 56cb459498Sriastradh }; 57cb459498Sriastradh 58cb459498Sriastradh struct rv6xx_power_info { 59cb459498Sriastradh /* flags */ 60cb459498Sriastradh bool voltage_control; 61cb459498Sriastradh bool sclk_ss; 62cb459498Sriastradh bool mclk_ss; 63cb459498Sriastradh bool dynamic_ss; 64cb459498Sriastradh bool dynamic_pcie_gen2; 65cb459498Sriastradh bool thermal_protection; 66cb459498Sriastradh bool display_gap; 67cb459498Sriastradh bool gfx_clock_gating; 68cb459498Sriastradh /* clk values */ 69cb459498Sriastradh u32 fb_div_scale; 70cb459498Sriastradh u32 spll_ref_div; 71cb459498Sriastradh u32 mpll_ref_div; 72cb459498Sriastradh u32 bsu; 73cb459498Sriastradh u32 bsp; 74cb459498Sriastradh /* */ 75cb459498Sriastradh u32 active_auto_throttle_sources; 76cb459498Sriastradh /* current power state */ 77cb459498Sriastradh u32 restricted_levels; 78cb459498Sriastradh struct rv6xx_pm_hw_state hw; 79cb459498Sriastradh }; 80cb459498Sriastradh 81cb459498Sriastradh struct rv6xx_pl { 82cb459498Sriastradh u32 sclk; 83cb459498Sriastradh u32 mclk; 84cb459498Sriastradh u16 vddc; 85cb459498Sriastradh u32 flags; 86cb459498Sriastradh }; 87cb459498Sriastradh 88cb459498Sriastradh struct rv6xx_ps { 89cb459498Sriastradh struct rv6xx_pl high; 90cb459498Sriastradh struct rv6xx_pl medium; 91cb459498Sriastradh struct rv6xx_pl low; 92cb459498Sriastradh }; 93cb459498Sriastradh 94cb459498Sriastradh #define RV6XX_DEFAULT_VCLK_FREQ 40000 /* 10 khz */ 95cb459498Sriastradh #define RV6XX_DEFAULT_DCLK_FREQ 30000 /* 10 khz */ 96cb459498Sriastradh 97cb459498Sriastradh #endif 98