1*677dec6eSriastradh /* $NetBSD: rv740d.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2d350ecf5Sriastradh 3cb459498Sriastradh /* 4cb459498Sriastradh * Copyright 2011 Advanced Micro Devices, Inc. 5cb459498Sriastradh * 6cb459498Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 7cb459498Sriastradh * copy of this software and associated documentation files (the "Software"), 8cb459498Sriastradh * to deal in the Software without restriction, including without limitation 9cb459498Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10cb459498Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 11cb459498Sriastradh * Software is furnished to do so, subject to the following conditions: 12cb459498Sriastradh * 13cb459498Sriastradh * The above copyright notice and this permission notice shall be included in 14cb459498Sriastradh * all copies or substantial portions of the Software. 15cb459498Sriastradh * 16cb459498Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17cb459498Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18cb459498Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19cb459498Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20cb459498Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21cb459498Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22cb459498Sriastradh * OTHER DEALINGS IN THE SOFTWARE. 23cb459498Sriastradh * 24cb459498Sriastradh */ 25cb459498Sriastradh #ifndef RV740_H 26cb459498Sriastradh #define RV740_H 27cb459498Sriastradh 28cb459498Sriastradh #define CG_SPLL_FUNC_CNTL 0x600 29cb459498Sriastradh #define SPLL_RESET (1 << 0) 30cb459498Sriastradh #define SPLL_SLEEP (1 << 1) 31cb459498Sriastradh #define SPLL_BYPASS_EN (1 << 3) 32cb459498Sriastradh #define SPLL_REF_DIV(x) ((x) << 4) 33cb459498Sriastradh #define SPLL_REF_DIV_MASK (0x3f << 4) 34cb459498Sriastradh #define SPLL_PDIV_A(x) ((x) << 20) 35cb459498Sriastradh #define SPLL_PDIV_A_MASK (0x7f << 20) 36cb459498Sriastradh #define CG_SPLL_FUNC_CNTL_2 0x604 37cb459498Sriastradh #define SCLK_MUX_SEL(x) ((x) << 0) 38cb459498Sriastradh #define SCLK_MUX_SEL_MASK (0x1ff << 0) 39cb459498Sriastradh #define CG_SPLL_FUNC_CNTL_3 0x608 40cb459498Sriastradh #define SPLL_FB_DIV(x) ((x) << 0) 41cb459498Sriastradh #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 42cb459498Sriastradh #define SPLL_DITHEN (1 << 28) 43cb459498Sriastradh 44cb459498Sriastradh #define MPLL_CNTL_MODE 0x61c 45cb459498Sriastradh #define SS_SSEN (1 << 24) 46cb459498Sriastradh 47cb459498Sriastradh #define MPLL_AD_FUNC_CNTL 0x624 48cb459498Sriastradh #define CLKF(x) ((x) << 0) 49cb459498Sriastradh #define CLKF_MASK (0x7f << 0) 50cb459498Sriastradh #define CLKR(x) ((x) << 7) 51cb459498Sriastradh #define CLKR_MASK (0x1f << 7) 52cb459498Sriastradh #define CLKFRAC(x) ((x) << 12) 53cb459498Sriastradh #define CLKFRAC_MASK (0x1f << 12) 54cb459498Sriastradh #define YCLK_POST_DIV(x) ((x) << 17) 55cb459498Sriastradh #define YCLK_POST_DIV_MASK (3 << 17) 56cb459498Sriastradh #define IBIAS(x) ((x) << 20) 57cb459498Sriastradh #define IBIAS_MASK (0x3ff << 20) 58cb459498Sriastradh #define RESET (1 << 30) 59cb459498Sriastradh #define PDNB (1 << 31) 60cb459498Sriastradh #define MPLL_AD_FUNC_CNTL_2 0x628 61cb459498Sriastradh #define BYPASS (1 << 19) 62cb459498Sriastradh #define BIAS_GEN_PDNB (1 << 24) 63cb459498Sriastradh #define RESET_EN (1 << 25) 64cb459498Sriastradh #define VCO_MODE (1 << 29) 65cb459498Sriastradh #define MPLL_DQ_FUNC_CNTL 0x62c 66cb459498Sriastradh #define MPLL_DQ_FUNC_CNTL_2 0x630 67cb459498Sriastradh 68cb459498Sriastradh #define MCLK_PWRMGT_CNTL 0x648 69cb459498Sriastradh #define DLL_SPEED(x) ((x) << 0) 70cb459498Sriastradh #define DLL_SPEED_MASK (0x1f << 0) 71cb459498Sriastradh # define MPLL_PWRMGT_OFF (1 << 5) 72cb459498Sriastradh # define DLL_READY (1 << 6) 73cb459498Sriastradh # define MC_INT_CNTL (1 << 7) 74cb459498Sriastradh # define MRDCKA0_SLEEP (1 << 8) 75cb459498Sriastradh # define MRDCKA1_SLEEP (1 << 9) 76cb459498Sriastradh # define MRDCKB0_SLEEP (1 << 10) 77cb459498Sriastradh # define MRDCKB1_SLEEP (1 << 11) 78cb459498Sriastradh # define MRDCKC0_SLEEP (1 << 12) 79cb459498Sriastradh # define MRDCKC1_SLEEP (1 << 13) 80cb459498Sriastradh # define MRDCKD0_SLEEP (1 << 14) 81cb459498Sriastradh # define MRDCKD1_SLEEP (1 << 15) 82cb459498Sriastradh # define MRDCKA0_RESET (1 << 16) 83cb459498Sriastradh # define MRDCKA1_RESET (1 << 17) 84cb459498Sriastradh # define MRDCKB0_RESET (1 << 18) 85cb459498Sriastradh # define MRDCKB1_RESET (1 << 19) 86cb459498Sriastradh # define MRDCKC0_RESET (1 << 20) 87cb459498Sriastradh # define MRDCKC1_RESET (1 << 21) 88cb459498Sriastradh # define MRDCKD0_RESET (1 << 22) 89cb459498Sriastradh # define MRDCKD1_RESET (1 << 23) 90cb459498Sriastradh # define DLL_READY_READ (1 << 24) 91cb459498Sriastradh # define USE_DISPLAY_GAP (1 << 25) 92cb459498Sriastradh # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 93cb459498Sriastradh # define MPLL_TURNOFF_D2 (1 << 28) 94cb459498Sriastradh #define DLL_CNTL 0x64c 95cb459498Sriastradh # define MRDCKA0_BYPASS (1 << 24) 96cb459498Sriastradh # define MRDCKA1_BYPASS (1 << 25) 97cb459498Sriastradh # define MRDCKB0_BYPASS (1 << 26) 98cb459498Sriastradh # define MRDCKB1_BYPASS (1 << 27) 99cb459498Sriastradh # define MRDCKC0_BYPASS (1 << 28) 100cb459498Sriastradh # define MRDCKC1_BYPASS (1 << 29) 101cb459498Sriastradh # define MRDCKD0_BYPASS (1 << 30) 102cb459498Sriastradh # define MRDCKD1_BYPASS (1 << 31) 103cb459498Sriastradh 104cb459498Sriastradh #define CG_SPLL_SPREAD_SPECTRUM 0x790 105cb459498Sriastradh #define SSEN (1 << 0) 106cb459498Sriastradh #define CLK_S(x) ((x) << 4) 107cb459498Sriastradh #define CLK_S_MASK (0xfff << 4) 108cb459498Sriastradh #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 109cb459498Sriastradh #define CLK_V(x) ((x) << 0) 110cb459498Sriastradh #define CLK_V_MASK (0x3ffffff << 0) 111cb459498Sriastradh 112cb459498Sriastradh #define MPLL_SS1 0x85c 113cb459498Sriastradh #define CLKV(x) ((x) << 0) 114cb459498Sriastradh #define CLKV_MASK (0x3ffffff << 0) 115cb459498Sriastradh #define MPLL_SS2 0x860 116cb459498Sriastradh #define CLKS(x) ((x) << 0) 117cb459498Sriastradh #define CLKS_MASK (0xfff << 0) 118cb459498Sriastradh 119cb459498Sriastradh #endif 120