1*b7abd477Sriastradh /* $NetBSD: vmwgfx_fifo.c,v 1.4 2022/10/25 23:34:06 riastradh Exp $ */
2d350ecf5Sriastradh
3677dec6eSriastradh // SPDX-License-Identifier: GPL-2.0 OR MIT
456053ce7Sriastradh /**************************************************************************
556053ce7Sriastradh *
6677dec6eSriastradh * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA
756053ce7Sriastradh *
856053ce7Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a
956053ce7Sriastradh * copy of this software and associated documentation files (the
1056053ce7Sriastradh * "Software"), to deal in the Software without restriction, including
1156053ce7Sriastradh * without limitation the rights to use, copy, modify, merge, publish,
1256053ce7Sriastradh * distribute, sub license, and/or sell copies of the Software, and to
1356053ce7Sriastradh * permit persons to whom the Software is furnished to do so, subject to
1456053ce7Sriastradh * the following conditions:
1556053ce7Sriastradh *
1656053ce7Sriastradh * The above copyright notice and this permission notice (including the
1756053ce7Sriastradh * next paragraph) shall be included in all copies or substantial portions
1856053ce7Sriastradh * of the Software.
1956053ce7Sriastradh *
2056053ce7Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2156053ce7Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2256053ce7Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
2356053ce7Sriastradh * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
2456053ce7Sriastradh * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
2556053ce7Sriastradh * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
2656053ce7Sriastradh * USE OR OTHER DEALINGS IN THE SOFTWARE.
2756053ce7Sriastradh *
2856053ce7Sriastradh **************************************************************************/
2956053ce7Sriastradh
30d350ecf5Sriastradh #include <sys/cdefs.h>
31*b7abd477Sriastradh __KERNEL_RCSID(0, "$NetBSD: vmwgfx_fifo.c,v 1.4 2022/10/25 23:34:06 riastradh Exp $");
32677dec6eSriastradh
33677dec6eSriastradh #include <linux/sched/signal.h>
34677dec6eSriastradh
35677dec6eSriastradh #include <drm/ttm/ttm_placement.h>
36d350ecf5Sriastradh
3756053ce7Sriastradh #include "vmwgfx_drv.h"
3856053ce7Sriastradh
39*b7abd477Sriastradh #include <linux/nbsd-namespace.h>
40*b7abd477Sriastradh
41d350ecf5Sriastradh struct vmw_temp_set_context {
42d350ecf5Sriastradh SVGA3dCmdHeader header;
43d350ecf5Sriastradh SVGA3dCmdDXTempSetContext body;
44d350ecf5Sriastradh };
45d350ecf5Sriastradh
vmw_fifo_have_3d(struct vmw_private * dev_priv)4656053ce7Sriastradh bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
4756053ce7Sriastradh {
48d350ecf5Sriastradh u32 *fifo_mem = dev_priv->mmio_virt;
4956053ce7Sriastradh uint32_t fifo_min, hwversion;
5056053ce7Sriastradh const struct vmw_fifo_state *fifo = &dev_priv->fifo;
5156053ce7Sriastradh
52cb459498Sriastradh if (!(dev_priv->capabilities & SVGA_CAP_3D))
53cb459498Sriastradh return false;
54cb459498Sriastradh
55cb459498Sriastradh if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
56cb459498Sriastradh uint32_t result;
57cb459498Sriastradh
58cb459498Sriastradh if (!dev_priv->has_mob)
59cb459498Sriastradh return false;
60cb459498Sriastradh
61d350ecf5Sriastradh spin_lock(&dev_priv->cap_lock);
62cb459498Sriastradh vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
63cb459498Sriastradh result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
64d350ecf5Sriastradh spin_unlock(&dev_priv->cap_lock);
65cb459498Sriastradh
66cb459498Sriastradh return (result != 0);
67cb459498Sriastradh }
68cb459498Sriastradh
6956053ce7Sriastradh if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
7056053ce7Sriastradh return false;
7156053ce7Sriastradh
72d350ecf5Sriastradh fifo_min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
7356053ce7Sriastradh if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
7456053ce7Sriastradh return false;
7556053ce7Sriastradh
76d350ecf5Sriastradh hwversion = vmw_mmio_read(fifo_mem +
7756053ce7Sriastradh ((fifo->capabilities &
7856053ce7Sriastradh SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
7956053ce7Sriastradh SVGA_FIFO_3D_HWVERSION_REVISED :
8056053ce7Sriastradh SVGA_FIFO_3D_HWVERSION));
8156053ce7Sriastradh
8256053ce7Sriastradh if (hwversion == 0)
8356053ce7Sriastradh return false;
8456053ce7Sriastradh
8556053ce7Sriastradh if (hwversion < SVGA3D_HWVERSION_WS8_B1)
8656053ce7Sriastradh return false;
8756053ce7Sriastradh
88d350ecf5Sriastradh /* Legacy Display Unit does not support surfaces */
89d350ecf5Sriastradh if (dev_priv->active_display_unit == vmw_du_legacy)
9056053ce7Sriastradh return false;
9156053ce7Sriastradh
9256053ce7Sriastradh return true;
9356053ce7Sriastradh }
9456053ce7Sriastradh
vmw_fifo_have_pitchlock(struct vmw_private * dev_priv)9556053ce7Sriastradh bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
9656053ce7Sriastradh {
97d350ecf5Sriastradh u32 *fifo_mem = dev_priv->mmio_virt;
9856053ce7Sriastradh uint32_t caps;
9956053ce7Sriastradh
10056053ce7Sriastradh if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
10156053ce7Sriastradh return false;
10256053ce7Sriastradh
103d350ecf5Sriastradh caps = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
10456053ce7Sriastradh if (caps & SVGA_FIFO_CAP_PITCHLOCK)
10556053ce7Sriastradh return true;
10656053ce7Sriastradh
10756053ce7Sriastradh return false;
10856053ce7Sriastradh }
10956053ce7Sriastradh
vmw_fifo_init(struct vmw_private * dev_priv,struct vmw_fifo_state * fifo)11056053ce7Sriastradh int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
11156053ce7Sriastradh {
112d350ecf5Sriastradh u32 *fifo_mem = dev_priv->mmio_virt;
11356053ce7Sriastradh uint32_t max;
11456053ce7Sriastradh uint32_t min;
11556053ce7Sriastradh
116d350ecf5Sriastradh fifo->dx = false;
11756053ce7Sriastradh fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
11856053ce7Sriastradh fifo->static_buffer = vmalloc(fifo->static_buffer_size);
11956053ce7Sriastradh if (unlikely(fifo->static_buffer == NULL))
12056053ce7Sriastradh return -ENOMEM;
12156053ce7Sriastradh
12256053ce7Sriastradh fifo->dynamic_buffer = NULL;
12356053ce7Sriastradh fifo->reserved_size = 0;
12456053ce7Sriastradh fifo->using_bounce_buffer = false;
12556053ce7Sriastradh
12656053ce7Sriastradh mutex_init(&fifo->fifo_mutex);
12756053ce7Sriastradh init_rwsem(&fifo->rwsem);
12856053ce7Sriastradh
12956053ce7Sriastradh DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
13056053ce7Sriastradh DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
13156053ce7Sriastradh DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
13256053ce7Sriastradh
13356053ce7Sriastradh dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
13456053ce7Sriastradh dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
13556053ce7Sriastradh dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
136d350ecf5Sriastradh
137d350ecf5Sriastradh vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
138d350ecf5Sriastradh SVGA_REG_ENABLE_HIDE);
139d350ecf5Sriastradh vmw_write(dev_priv, SVGA_REG_TRACES, 0);
14056053ce7Sriastradh
14156053ce7Sriastradh min = 4;
14256053ce7Sriastradh if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
14356053ce7Sriastradh min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
14456053ce7Sriastradh min <<= 2;
14556053ce7Sriastradh
14656053ce7Sriastradh if (min < PAGE_SIZE)
14756053ce7Sriastradh min = PAGE_SIZE;
14856053ce7Sriastradh
149d350ecf5Sriastradh vmw_mmio_write(min, fifo_mem + SVGA_FIFO_MIN);
150d350ecf5Sriastradh vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
15156053ce7Sriastradh wmb();
152d350ecf5Sriastradh vmw_mmio_write(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
153d350ecf5Sriastradh vmw_mmio_write(min, fifo_mem + SVGA_FIFO_STOP);
154d350ecf5Sriastradh vmw_mmio_write(0, fifo_mem + SVGA_FIFO_BUSY);
15556053ce7Sriastradh mb();
15656053ce7Sriastradh
15756053ce7Sriastradh vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
15856053ce7Sriastradh
159d350ecf5Sriastradh max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
160d350ecf5Sriastradh min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
161d350ecf5Sriastradh fifo->capabilities = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
16256053ce7Sriastradh
16356053ce7Sriastradh DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
16456053ce7Sriastradh (unsigned int) max,
16556053ce7Sriastradh (unsigned int) min,
16656053ce7Sriastradh (unsigned int) fifo->capabilities);
16756053ce7Sriastradh
16856053ce7Sriastradh atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
169d350ecf5Sriastradh vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
17056053ce7Sriastradh vmw_marker_queue_init(&fifo->marker_queue);
171d350ecf5Sriastradh
172d350ecf5Sriastradh return 0;
17356053ce7Sriastradh }
17456053ce7Sriastradh
vmw_fifo_ping_host(struct vmw_private * dev_priv,uint32_t reason)17556053ce7Sriastradh void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
17656053ce7Sriastradh {
177d350ecf5Sriastradh u32 *fifo_mem = dev_priv->mmio_virt;
17856053ce7Sriastradh
179d350ecf5Sriastradh preempt_disable();
180d350ecf5Sriastradh if (cmpxchg(fifo_mem + SVGA_FIFO_BUSY, 0, 1) == 0)
18156053ce7Sriastradh vmw_write(dev_priv, SVGA_REG_SYNC, reason);
182d350ecf5Sriastradh preempt_enable();
18356053ce7Sriastradh }
18456053ce7Sriastradh
vmw_fifo_release(struct vmw_private * dev_priv,struct vmw_fifo_state * fifo)18556053ce7Sriastradh void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
18656053ce7Sriastradh {
187d350ecf5Sriastradh u32 *fifo_mem = dev_priv->mmio_virt;
18856053ce7Sriastradh
18956053ce7Sriastradh vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
190d350ecf5Sriastradh while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
191d350ecf5Sriastradh ;
19256053ce7Sriastradh
193d350ecf5Sriastradh dev_priv->last_read_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
19456053ce7Sriastradh
19556053ce7Sriastradh vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
19656053ce7Sriastradh dev_priv->config_done_state);
19756053ce7Sriastradh vmw_write(dev_priv, SVGA_REG_ENABLE,
19856053ce7Sriastradh dev_priv->enable_state);
19956053ce7Sriastradh vmw_write(dev_priv, SVGA_REG_TRACES,
20056053ce7Sriastradh dev_priv->traces_state);
20156053ce7Sriastradh
20256053ce7Sriastradh vmw_marker_queue_takedown(&fifo->marker_queue);
20356053ce7Sriastradh
20456053ce7Sriastradh if (likely(fifo->static_buffer != NULL)) {
20556053ce7Sriastradh vfree(fifo->static_buffer);
20656053ce7Sriastradh fifo->static_buffer = NULL;
20756053ce7Sriastradh }
20856053ce7Sriastradh
20956053ce7Sriastradh if (likely(fifo->dynamic_buffer != NULL)) {
21056053ce7Sriastradh vfree(fifo->dynamic_buffer);
21156053ce7Sriastradh fifo->dynamic_buffer = NULL;
21256053ce7Sriastradh }
21356053ce7Sriastradh }
21456053ce7Sriastradh
vmw_fifo_is_full(struct vmw_private * dev_priv,uint32_t bytes)21556053ce7Sriastradh static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
21656053ce7Sriastradh {
217d350ecf5Sriastradh u32 *fifo_mem = dev_priv->mmio_virt;
218d350ecf5Sriastradh uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
219d350ecf5Sriastradh uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
220d350ecf5Sriastradh uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
221d350ecf5Sriastradh uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
22256053ce7Sriastradh
22356053ce7Sriastradh return ((max - next_cmd) + (stop - min) <= bytes);
22456053ce7Sriastradh }
22556053ce7Sriastradh
vmw_fifo_wait_noirq(struct vmw_private * dev_priv,uint32_t bytes,bool interruptible,unsigned long timeout)22656053ce7Sriastradh static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
22756053ce7Sriastradh uint32_t bytes, bool interruptible,
22856053ce7Sriastradh unsigned long timeout)
22956053ce7Sriastradh {
23056053ce7Sriastradh int ret = 0;
23156053ce7Sriastradh unsigned long end_jiffies = jiffies + timeout;
232*b7abd477Sriastradh #ifdef __NetBSD__
233*b7abd477Sriastradh assert_spin_locked(&dev_priv->fifo_lock);
234*b7abd477Sriastradh #else
23556053ce7Sriastradh DEFINE_WAIT(__wait);
236*b7abd477Sriastradh #endif
23756053ce7Sriastradh
23856053ce7Sriastradh DRM_INFO("Fifo wait noirq.\n");
23956053ce7Sriastradh
24056053ce7Sriastradh for (;;) {
241*b7abd477Sriastradh #ifndef __NetBSD__
24256053ce7Sriastradh prepare_to_wait(&dev_priv->fifo_queue, &__wait,
24356053ce7Sriastradh (interruptible) ?
24456053ce7Sriastradh TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
245*b7abd477Sriastradh #endif
24656053ce7Sriastradh if (!vmw_fifo_is_full(dev_priv, bytes))
24756053ce7Sriastradh break;
24856053ce7Sriastradh if (time_after_eq(jiffies, end_jiffies)) {
24956053ce7Sriastradh ret = -EBUSY;
25056053ce7Sriastradh DRM_ERROR("SVGA device lockup.\n");
25156053ce7Sriastradh break;
25256053ce7Sriastradh }
253*b7abd477Sriastradh #ifdef __NetBSD__
254*b7abd477Sriastradh if (interruptible) {
255*b7abd477Sriastradh DRM_SPIN_TIMED_WAIT_UNTIL(ret, &dev_priv->fifo_queue,
256*b7abd477Sriastradh &dev_priv->fifo_lock, 1,
257*b7abd477Sriastradh !vmw_fifo_is_full(dev_priv, bytes));
258*b7abd477Sriastradh } else {
259*b7abd477Sriastradh DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret,
260*b7abd477Sriastradh &dev_priv->fifo_queue,
261*b7abd477Sriastradh &dev_priv->fifo_lock, 1,
262*b7abd477Sriastradh !vmw_fifo_is_full(dev_priv, bytes));
263*b7abd477Sriastradh }
264*b7abd477Sriastradh if (ret) {
265*b7abd477Sriastradh if (ret > 0) /* success */
266*b7abd477Sriastradh ret = 0;
267*b7abd477Sriastradh break;
268*b7abd477Sriastradh }
269*b7abd477Sriastradh /*
270*b7abd477Sriastradh * ret=0 means the wait timed out after one tick, so
271*b7abd477Sriastradh * try again
272*b7abd477Sriastradh */
273*b7abd477Sriastradh #else
27456053ce7Sriastradh schedule_timeout(1);
27556053ce7Sriastradh if (interruptible && signal_pending(current)) {
27656053ce7Sriastradh ret = -ERESTARTSYS;
27756053ce7Sriastradh break;
27856053ce7Sriastradh }
279*b7abd477Sriastradh #endif
28056053ce7Sriastradh }
281*b7abd477Sriastradh #ifdef __NetBSD__
282*b7abd477Sriastradh DRM_SPIN_WAKEUP_ALL(&dev_priv->fifo_queue, &dev_priv->fifo_lock);
283*b7abd477Sriastradh #else
28456053ce7Sriastradh finish_wait(&dev_priv->fifo_queue, &__wait);
28556053ce7Sriastradh wake_up_all(&dev_priv->fifo_queue);
286*b7abd477Sriastradh #endif
28756053ce7Sriastradh DRM_INFO("Fifo noirq exit.\n");
28856053ce7Sriastradh return ret;
28956053ce7Sriastradh }
29056053ce7Sriastradh
vmw_fifo_wait(struct vmw_private * dev_priv,uint32_t bytes,bool interruptible,unsigned long timeout)29156053ce7Sriastradh static int vmw_fifo_wait(struct vmw_private *dev_priv,
29256053ce7Sriastradh uint32_t bytes, bool interruptible,
29356053ce7Sriastradh unsigned long timeout)
29456053ce7Sriastradh {
29556053ce7Sriastradh long ret = 1L;
29656053ce7Sriastradh
297*b7abd477Sriastradh spin_lock(&dev_priv->fifo_lock);
298*b7abd477Sriastradh
299*b7abd477Sriastradh if (likely(!vmw_fifo_is_full(dev_priv, bytes))) {
300*b7abd477Sriastradh spin_unlock(&dev_priv->fifo_lock);
30156053ce7Sriastradh return 0;
302*b7abd477Sriastradh }
30356053ce7Sriastradh
30456053ce7Sriastradh vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
305*b7abd477Sriastradh if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) {
306*b7abd477Sriastradh ret = vmw_fifo_wait_noirq(dev_priv, bytes,
30756053ce7Sriastradh interruptible, timeout);
308*b7abd477Sriastradh spin_unlock(&dev_priv->fifo_lock);
309*b7abd477Sriastradh return ret;
310*b7abd477Sriastradh }
31156053ce7Sriastradh
312d350ecf5Sriastradh vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,
313d350ecf5Sriastradh &dev_priv->fifo_queue_waiters);
31456053ce7Sriastradh
31556053ce7Sriastradh if (interruptible)
316*b7abd477Sriastradh DRM_SPIN_TIMED_WAIT_UNTIL(ret, &dev_priv->fifo_queue,
317*b7abd477Sriastradh &dev_priv->fifo_lock, timeout,
318*b7abd477Sriastradh !vmw_fifo_is_full(dev_priv, bytes));
31956053ce7Sriastradh else
320*b7abd477Sriastradh DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret, &dev_priv->fifo_queue,
321*b7abd477Sriastradh &dev_priv->fifo_lock, timeout,
322*b7abd477Sriastradh !vmw_fifo_is_full(dev_priv, bytes));
32356053ce7Sriastradh
32456053ce7Sriastradh if (unlikely(ret == 0))
32556053ce7Sriastradh ret = -EBUSY;
32656053ce7Sriastradh else if (likely(ret > 0))
32756053ce7Sriastradh ret = 0;
32856053ce7Sriastradh
329d350ecf5Sriastradh vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,
330d350ecf5Sriastradh &dev_priv->fifo_queue_waiters);
33156053ce7Sriastradh
332*b7abd477Sriastradh spin_unlock(&dev_priv->fifo_lock);
333*b7abd477Sriastradh
33456053ce7Sriastradh return ret;
33556053ce7Sriastradh }
33656053ce7Sriastradh
33756053ce7Sriastradh /**
33856053ce7Sriastradh * Reserve @bytes number of bytes in the fifo.
33956053ce7Sriastradh *
34056053ce7Sriastradh * This function will return NULL (error) on two conditions:
34156053ce7Sriastradh * If it timeouts waiting for fifo space, or if @bytes is larger than the
34256053ce7Sriastradh * available fifo space.
34356053ce7Sriastradh *
34456053ce7Sriastradh * Returns:
34556053ce7Sriastradh * Pointer to the fifo, or null on error (possible hardware hang).
34656053ce7Sriastradh */
vmw_local_fifo_reserve(struct vmw_private * dev_priv,uint32_t bytes)347d350ecf5Sriastradh static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv,
348d350ecf5Sriastradh uint32_t bytes)
34956053ce7Sriastradh {
35056053ce7Sriastradh struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
351d350ecf5Sriastradh u32 *fifo_mem = dev_priv->mmio_virt;
35256053ce7Sriastradh uint32_t max;
35356053ce7Sriastradh uint32_t min;
35456053ce7Sriastradh uint32_t next_cmd;
35556053ce7Sriastradh uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
35656053ce7Sriastradh int ret;
35756053ce7Sriastradh
35856053ce7Sriastradh mutex_lock(&fifo_state->fifo_mutex);
359d350ecf5Sriastradh max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
360d350ecf5Sriastradh min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
361d350ecf5Sriastradh next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
36256053ce7Sriastradh
36356053ce7Sriastradh if (unlikely(bytes >= (max - min)))
36456053ce7Sriastradh goto out_err;
36556053ce7Sriastradh
36656053ce7Sriastradh BUG_ON(fifo_state->reserved_size != 0);
36756053ce7Sriastradh BUG_ON(fifo_state->dynamic_buffer != NULL);
36856053ce7Sriastradh
36956053ce7Sriastradh fifo_state->reserved_size = bytes;
37056053ce7Sriastradh
37156053ce7Sriastradh while (1) {
372d350ecf5Sriastradh uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
37356053ce7Sriastradh bool need_bounce = false;
37456053ce7Sriastradh bool reserve_in_place = false;
37556053ce7Sriastradh
37656053ce7Sriastradh if (next_cmd >= stop) {
37756053ce7Sriastradh if (likely((next_cmd + bytes < max ||
37856053ce7Sriastradh (next_cmd + bytes == max && stop > min))))
37956053ce7Sriastradh reserve_in_place = true;
38056053ce7Sriastradh
38156053ce7Sriastradh else if (vmw_fifo_is_full(dev_priv, bytes)) {
38256053ce7Sriastradh ret = vmw_fifo_wait(dev_priv, bytes,
38356053ce7Sriastradh false, 3 * HZ);
38456053ce7Sriastradh if (unlikely(ret != 0))
38556053ce7Sriastradh goto out_err;
38656053ce7Sriastradh } else
38756053ce7Sriastradh need_bounce = true;
38856053ce7Sriastradh
38956053ce7Sriastradh } else {
39056053ce7Sriastradh
39156053ce7Sriastradh if (likely((next_cmd + bytes < stop)))
39256053ce7Sriastradh reserve_in_place = true;
39356053ce7Sriastradh else {
39456053ce7Sriastradh ret = vmw_fifo_wait(dev_priv, bytes,
39556053ce7Sriastradh false, 3 * HZ);
39656053ce7Sriastradh if (unlikely(ret != 0))
39756053ce7Sriastradh goto out_err;
39856053ce7Sriastradh }
39956053ce7Sriastradh }
40056053ce7Sriastradh
40156053ce7Sriastradh if (reserve_in_place) {
40256053ce7Sriastradh if (reserveable || bytes <= sizeof(uint32_t)) {
40356053ce7Sriastradh fifo_state->using_bounce_buffer = false;
40456053ce7Sriastradh
40556053ce7Sriastradh if (reserveable)
406d350ecf5Sriastradh vmw_mmio_write(bytes, fifo_mem +
40756053ce7Sriastradh SVGA_FIFO_RESERVED);
408d350ecf5Sriastradh return (void __force *) (fifo_mem +
409d350ecf5Sriastradh (next_cmd >> 2));
41056053ce7Sriastradh } else {
41156053ce7Sriastradh need_bounce = true;
41256053ce7Sriastradh }
41356053ce7Sriastradh }
41456053ce7Sriastradh
41556053ce7Sriastradh if (need_bounce) {
41656053ce7Sriastradh fifo_state->using_bounce_buffer = true;
41756053ce7Sriastradh if (bytes < fifo_state->static_buffer_size)
41856053ce7Sriastradh return fifo_state->static_buffer;
41956053ce7Sriastradh else {
42056053ce7Sriastradh fifo_state->dynamic_buffer = vmalloc(bytes);
421d350ecf5Sriastradh if (!fifo_state->dynamic_buffer)
422d350ecf5Sriastradh goto out_err;
42356053ce7Sriastradh return fifo_state->dynamic_buffer;
42456053ce7Sriastradh }
42556053ce7Sriastradh }
42656053ce7Sriastradh }
42756053ce7Sriastradh out_err:
42856053ce7Sriastradh fifo_state->reserved_size = 0;
42956053ce7Sriastradh mutex_unlock(&fifo_state->fifo_mutex);
430d350ecf5Sriastradh
43156053ce7Sriastradh return NULL;
43256053ce7Sriastradh }
43356053ce7Sriastradh
vmw_fifo_reserve_dx(struct vmw_private * dev_priv,uint32_t bytes,int ctx_id)434d350ecf5Sriastradh void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes,
435d350ecf5Sriastradh int ctx_id)
436d350ecf5Sriastradh {
437d350ecf5Sriastradh void *ret;
438d350ecf5Sriastradh
439d350ecf5Sriastradh if (dev_priv->cman)
440d350ecf5Sriastradh ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes,
441d350ecf5Sriastradh ctx_id, false, NULL);
442d350ecf5Sriastradh else if (ctx_id == SVGA3D_INVALID_ID)
443d350ecf5Sriastradh ret = vmw_local_fifo_reserve(dev_priv, bytes);
444d350ecf5Sriastradh else {
445d350ecf5Sriastradh WARN(1, "Command buffer has not been allocated.\n");
446d350ecf5Sriastradh ret = NULL;
447d350ecf5Sriastradh }
448677dec6eSriastradh if (IS_ERR_OR_NULL(ret))
449d350ecf5Sriastradh return NULL;
450d350ecf5Sriastradh
451d350ecf5Sriastradh return ret;
452d350ecf5Sriastradh }
453d350ecf5Sriastradh
vmw_fifo_res_copy(struct vmw_fifo_state * fifo_state,u32 * fifo_mem,uint32_t next_cmd,uint32_t max,uint32_t min,uint32_t bytes)45456053ce7Sriastradh static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
455d350ecf5Sriastradh u32 *fifo_mem,
45656053ce7Sriastradh uint32_t next_cmd,
45756053ce7Sriastradh uint32_t max, uint32_t min, uint32_t bytes)
45856053ce7Sriastradh {
45956053ce7Sriastradh uint32_t chunk_size = max - next_cmd;
46056053ce7Sriastradh uint32_t rest;
46156053ce7Sriastradh uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
46256053ce7Sriastradh fifo_state->dynamic_buffer : fifo_state->static_buffer;
46356053ce7Sriastradh
46456053ce7Sriastradh if (bytes < chunk_size)
46556053ce7Sriastradh chunk_size = bytes;
46656053ce7Sriastradh
467d350ecf5Sriastradh vmw_mmio_write(bytes, fifo_mem + SVGA_FIFO_RESERVED);
46856053ce7Sriastradh mb();
469d350ecf5Sriastradh memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
47056053ce7Sriastradh rest = bytes - chunk_size;
47156053ce7Sriastradh if (rest)
472d350ecf5Sriastradh memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), rest);
47356053ce7Sriastradh }
47456053ce7Sriastradh
vmw_fifo_slow_copy(struct vmw_fifo_state * fifo_state,u32 * fifo_mem,uint32_t next_cmd,uint32_t max,uint32_t min,uint32_t bytes)47556053ce7Sriastradh static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
476d350ecf5Sriastradh u32 *fifo_mem,
47756053ce7Sriastradh uint32_t next_cmd,
47856053ce7Sriastradh uint32_t max, uint32_t min, uint32_t bytes)
47956053ce7Sriastradh {
48056053ce7Sriastradh uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
48156053ce7Sriastradh fifo_state->dynamic_buffer : fifo_state->static_buffer;
48256053ce7Sriastradh
48356053ce7Sriastradh while (bytes > 0) {
484d350ecf5Sriastradh vmw_mmio_write(*buffer++, fifo_mem + (next_cmd >> 2));
48556053ce7Sriastradh next_cmd += sizeof(uint32_t);
48656053ce7Sriastradh if (unlikely(next_cmd == max))
48756053ce7Sriastradh next_cmd = min;
48856053ce7Sriastradh mb();
489d350ecf5Sriastradh vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
49056053ce7Sriastradh mb();
49156053ce7Sriastradh bytes -= sizeof(uint32_t);
49256053ce7Sriastradh }
49356053ce7Sriastradh }
49456053ce7Sriastradh
vmw_local_fifo_commit(struct vmw_private * dev_priv,uint32_t bytes)495d350ecf5Sriastradh static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
49656053ce7Sriastradh {
49756053ce7Sriastradh struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
498d350ecf5Sriastradh u32 *fifo_mem = dev_priv->mmio_virt;
499d350ecf5Sriastradh uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
500d350ecf5Sriastradh uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
501d350ecf5Sriastradh uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
50256053ce7Sriastradh bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
50356053ce7Sriastradh
504d350ecf5Sriastradh if (fifo_state->dx)
505d350ecf5Sriastradh bytes += sizeof(struct vmw_temp_set_context);
506d350ecf5Sriastradh
507d350ecf5Sriastradh fifo_state->dx = false;
50856053ce7Sriastradh BUG_ON((bytes & 3) != 0);
50956053ce7Sriastradh BUG_ON(bytes > fifo_state->reserved_size);
51056053ce7Sriastradh
51156053ce7Sriastradh fifo_state->reserved_size = 0;
51256053ce7Sriastradh
51356053ce7Sriastradh if (fifo_state->using_bounce_buffer) {
51456053ce7Sriastradh if (reserveable)
51556053ce7Sriastradh vmw_fifo_res_copy(fifo_state, fifo_mem,
51656053ce7Sriastradh next_cmd, max, min, bytes);
51756053ce7Sriastradh else
51856053ce7Sriastradh vmw_fifo_slow_copy(fifo_state, fifo_mem,
51956053ce7Sriastradh next_cmd, max, min, bytes);
52056053ce7Sriastradh
52156053ce7Sriastradh if (fifo_state->dynamic_buffer) {
52256053ce7Sriastradh vfree(fifo_state->dynamic_buffer);
52356053ce7Sriastradh fifo_state->dynamic_buffer = NULL;
52456053ce7Sriastradh }
52556053ce7Sriastradh
52656053ce7Sriastradh }
52756053ce7Sriastradh
52856053ce7Sriastradh down_write(&fifo_state->rwsem);
52956053ce7Sriastradh if (fifo_state->using_bounce_buffer || reserveable) {
53056053ce7Sriastradh next_cmd += bytes;
53156053ce7Sriastradh if (next_cmd >= max)
53256053ce7Sriastradh next_cmd -= max - min;
53356053ce7Sriastradh mb();
534d350ecf5Sriastradh vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
53556053ce7Sriastradh }
53656053ce7Sriastradh
53756053ce7Sriastradh if (reserveable)
538d350ecf5Sriastradh vmw_mmio_write(0, fifo_mem + SVGA_FIFO_RESERVED);
53956053ce7Sriastradh mb();
54056053ce7Sriastradh up_write(&fifo_state->rwsem);
54156053ce7Sriastradh vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
54256053ce7Sriastradh mutex_unlock(&fifo_state->fifo_mutex);
54356053ce7Sriastradh }
54456053ce7Sriastradh
vmw_fifo_commit(struct vmw_private * dev_priv,uint32_t bytes)545d350ecf5Sriastradh void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
546d350ecf5Sriastradh {
547d350ecf5Sriastradh if (dev_priv->cman)
548d350ecf5Sriastradh vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false);
549d350ecf5Sriastradh else
550d350ecf5Sriastradh vmw_local_fifo_commit(dev_priv, bytes);
551d350ecf5Sriastradh }
552d350ecf5Sriastradh
553d350ecf5Sriastradh
554d350ecf5Sriastradh /**
555d350ecf5Sriastradh * vmw_fifo_commit_flush - Commit fifo space and flush any buffered commands.
556d350ecf5Sriastradh *
557d350ecf5Sriastradh * @dev_priv: Pointer to device private structure.
558d350ecf5Sriastradh * @bytes: Number of bytes to commit.
559d350ecf5Sriastradh */
vmw_fifo_commit_flush(struct vmw_private * dev_priv,uint32_t bytes)560d350ecf5Sriastradh void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)
561d350ecf5Sriastradh {
562d350ecf5Sriastradh if (dev_priv->cman)
563d350ecf5Sriastradh vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true);
564d350ecf5Sriastradh else
565d350ecf5Sriastradh vmw_local_fifo_commit(dev_priv, bytes);
566d350ecf5Sriastradh }
567d350ecf5Sriastradh
568d350ecf5Sriastradh /**
569d350ecf5Sriastradh * vmw_fifo_flush - Flush any buffered commands and make sure command processing
570d350ecf5Sriastradh * starts.
571d350ecf5Sriastradh *
572d350ecf5Sriastradh * @dev_priv: Pointer to device private structure.
573d350ecf5Sriastradh * @interruptible: Whether to wait interruptible if function needs to sleep.
574d350ecf5Sriastradh */
vmw_fifo_flush(struct vmw_private * dev_priv,bool interruptible)575d350ecf5Sriastradh int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible)
576d350ecf5Sriastradh {
577d350ecf5Sriastradh might_sleep();
578d350ecf5Sriastradh
579d350ecf5Sriastradh if (dev_priv->cman)
580d350ecf5Sriastradh return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible);
581d350ecf5Sriastradh else
582d350ecf5Sriastradh return 0;
583d350ecf5Sriastradh }
584d350ecf5Sriastradh
vmw_fifo_send_fence(struct vmw_private * dev_priv,uint32_t * seqno)58556053ce7Sriastradh int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
58656053ce7Sriastradh {
58756053ce7Sriastradh struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
58856053ce7Sriastradh struct svga_fifo_cmd_fence *cmd_fence;
589d350ecf5Sriastradh u32 *fm;
59056053ce7Sriastradh int ret = 0;
591d350ecf5Sriastradh uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence);
59256053ce7Sriastradh
593677dec6eSriastradh fm = VMW_FIFO_RESERVE(dev_priv, bytes);
59456053ce7Sriastradh if (unlikely(fm == NULL)) {
59556053ce7Sriastradh *seqno = atomic_read(&dev_priv->marker_seq);
59656053ce7Sriastradh ret = -ENOMEM;
59756053ce7Sriastradh (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
59856053ce7Sriastradh false, 3*HZ);
59956053ce7Sriastradh goto out_err;
60056053ce7Sriastradh }
60156053ce7Sriastradh
60256053ce7Sriastradh do {
60356053ce7Sriastradh *seqno = atomic_add_return(1, &dev_priv->marker_seq);
60456053ce7Sriastradh } while (*seqno == 0);
60556053ce7Sriastradh
60656053ce7Sriastradh if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
60756053ce7Sriastradh
60856053ce7Sriastradh /*
60956053ce7Sriastradh * Don't request hardware to send a fence. The
61056053ce7Sriastradh * waiting code in vmwgfx_irq.c will emulate this.
61156053ce7Sriastradh */
61256053ce7Sriastradh
61356053ce7Sriastradh vmw_fifo_commit(dev_priv, 0);
61456053ce7Sriastradh return 0;
61556053ce7Sriastradh }
61656053ce7Sriastradh
617d350ecf5Sriastradh *fm++ = SVGA_CMD_FENCE;
618d350ecf5Sriastradh cmd_fence = (struct svga_fifo_cmd_fence *) fm;
619d350ecf5Sriastradh cmd_fence->fence = *seqno;
620d350ecf5Sriastradh vmw_fifo_commit_flush(dev_priv, bytes);
62156053ce7Sriastradh (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
622*b7abd477Sriastradh spin_lock(&dev_priv->fence_lock);
62356053ce7Sriastradh vmw_update_seqno(dev_priv, fifo_state);
624*b7abd477Sriastradh spin_unlock(&dev_priv->fence_lock);
62556053ce7Sriastradh
62656053ce7Sriastradh out_err:
62756053ce7Sriastradh return ret;
62856053ce7Sriastradh }
62956053ce7Sriastradh
63056053ce7Sriastradh /**
631cb459498Sriastradh * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
632cb459498Sriastradh * legacy query commands.
63356053ce7Sriastradh *
63456053ce7Sriastradh * @dev_priv: The device private structure.
63556053ce7Sriastradh * @cid: The hardware context id used for the query.
63656053ce7Sriastradh *
637cb459498Sriastradh * See the vmw_fifo_emit_dummy_query documentation.
63856053ce7Sriastradh */
vmw_fifo_emit_dummy_legacy_query(struct vmw_private * dev_priv,uint32_t cid)639cb459498Sriastradh static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
64056053ce7Sriastradh uint32_t cid)
64156053ce7Sriastradh {
64256053ce7Sriastradh /*
64356053ce7Sriastradh * A query wait without a preceding query end will
64456053ce7Sriastradh * actually finish all queries for this cid
64556053ce7Sriastradh * without writing to the query result structure.
64656053ce7Sriastradh */
64756053ce7Sriastradh
648d350ecf5Sriastradh struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
64956053ce7Sriastradh struct {
65056053ce7Sriastradh SVGA3dCmdHeader header;
65156053ce7Sriastradh SVGA3dCmdWaitForQuery body;
65256053ce7Sriastradh } *cmd;
65356053ce7Sriastradh
654677dec6eSriastradh cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
655677dec6eSriastradh if (unlikely(cmd == NULL))
65656053ce7Sriastradh return -ENOMEM;
65756053ce7Sriastradh
65856053ce7Sriastradh cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
65956053ce7Sriastradh cmd->header.size = sizeof(cmd->body);
66056053ce7Sriastradh cmd->body.cid = cid;
66156053ce7Sriastradh cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
66256053ce7Sriastradh
66356053ce7Sriastradh if (bo->mem.mem_type == TTM_PL_VRAM) {
66456053ce7Sriastradh cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
66556053ce7Sriastradh cmd->body.guestResult.offset = bo->offset;
66656053ce7Sriastradh } else {
66756053ce7Sriastradh cmd->body.guestResult.gmrId = bo->mem.start;
66856053ce7Sriastradh cmd->body.guestResult.offset = 0;
66956053ce7Sriastradh }
67056053ce7Sriastradh
67156053ce7Sriastradh vmw_fifo_commit(dev_priv, sizeof(*cmd));
67256053ce7Sriastradh
67356053ce7Sriastradh return 0;
67456053ce7Sriastradh }
675cb459498Sriastradh
676cb459498Sriastradh /**
677cb459498Sriastradh * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
678cb459498Sriastradh * guest-backed resource query commands.
679cb459498Sriastradh *
680cb459498Sriastradh * @dev_priv: The device private structure.
681cb459498Sriastradh * @cid: The hardware context id used for the query.
682cb459498Sriastradh *
683cb459498Sriastradh * See the vmw_fifo_emit_dummy_query documentation.
684cb459498Sriastradh */
vmw_fifo_emit_dummy_gb_query(struct vmw_private * dev_priv,uint32_t cid)685cb459498Sriastradh static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
686cb459498Sriastradh uint32_t cid)
687cb459498Sriastradh {
688cb459498Sriastradh /*
689cb459498Sriastradh * A query wait without a preceding query end will
690cb459498Sriastradh * actually finish all queries for this cid
691cb459498Sriastradh * without writing to the query result structure.
692cb459498Sriastradh */
693cb459498Sriastradh
694d350ecf5Sriastradh struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
695cb459498Sriastradh struct {
696cb459498Sriastradh SVGA3dCmdHeader header;
697cb459498Sriastradh SVGA3dCmdWaitForGBQuery body;
698cb459498Sriastradh } *cmd;
699cb459498Sriastradh
700677dec6eSriastradh cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
701677dec6eSriastradh if (unlikely(cmd == NULL))
702cb459498Sriastradh return -ENOMEM;
703cb459498Sriastradh
704cb459498Sriastradh cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
705cb459498Sriastradh cmd->header.size = sizeof(cmd->body);
706cb459498Sriastradh cmd->body.cid = cid;
707cb459498Sriastradh cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
708cb459498Sriastradh BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
709cb459498Sriastradh cmd->body.mobid = bo->mem.start;
710cb459498Sriastradh cmd->body.offset = 0;
711cb459498Sriastradh
712cb459498Sriastradh vmw_fifo_commit(dev_priv, sizeof(*cmd));
713cb459498Sriastradh
714cb459498Sriastradh return 0;
715cb459498Sriastradh }
716cb459498Sriastradh
717cb459498Sriastradh
718cb459498Sriastradh /**
719cb459498Sriastradh * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
720cb459498Sriastradh * appropriate resource query commands.
721cb459498Sriastradh *
722cb459498Sriastradh * @dev_priv: The device private structure.
723cb459498Sriastradh * @cid: The hardware context id used for the query.
724cb459498Sriastradh *
725cb459498Sriastradh * This function is used to emit a dummy occlusion query with
726cb459498Sriastradh * no primitives rendered between query begin and query end.
727cb459498Sriastradh * It's used to provide a query barrier, in order to know that when
728cb459498Sriastradh * this query is finished, all preceding queries are also finished.
729cb459498Sriastradh *
730cb459498Sriastradh * A Query results structure should have been initialized at the start
731cb459498Sriastradh * of the dev_priv->dummy_query_bo buffer object. And that buffer object
732cb459498Sriastradh * must also be either reserved or pinned when this function is called.
733cb459498Sriastradh *
734cb459498Sriastradh * Returns -ENOMEM on failure to reserve fifo space.
735cb459498Sriastradh */
vmw_fifo_emit_dummy_query(struct vmw_private * dev_priv,uint32_t cid)736cb459498Sriastradh int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
737cb459498Sriastradh uint32_t cid)
738cb459498Sriastradh {
739cb459498Sriastradh if (dev_priv->has_mob)
740cb459498Sriastradh return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
741cb459498Sriastradh
742cb459498Sriastradh return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
743cb459498Sriastradh }
744