1*3dbba2cfSriastradh /* $NetBSD: pci.h,v 1.56 2022/10/25 23:37:06 riastradh Exp $ */
22adb3a73Sriastradh
32adb3a73Sriastradh /*-
42adb3a73Sriastradh * Copyright (c) 2013 The NetBSD Foundation, Inc.
52adb3a73Sriastradh * All rights reserved.
62adb3a73Sriastradh *
72adb3a73Sriastradh * This code is derived from software contributed to The NetBSD Foundation
82adb3a73Sriastradh * by Taylor R. Campbell.
92adb3a73Sriastradh *
102adb3a73Sriastradh * Redistribution and use in source and binary forms, with or without
112adb3a73Sriastradh * modification, are permitted provided that the following conditions
122adb3a73Sriastradh * are met:
132adb3a73Sriastradh * 1. Redistributions of source code must retain the above copyright
142adb3a73Sriastradh * notice, this list of conditions and the following disclaimer.
152adb3a73Sriastradh * 2. Redistributions in binary form must reproduce the above copyright
162adb3a73Sriastradh * notice, this list of conditions and the following disclaimer in the
172adb3a73Sriastradh * documentation and/or other materials provided with the distribution.
182adb3a73Sriastradh *
192adb3a73Sriastradh * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
202adb3a73Sriastradh * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
212adb3a73Sriastradh * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
222adb3a73Sriastradh * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
232adb3a73Sriastradh * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
242adb3a73Sriastradh * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
252adb3a73Sriastradh * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
262adb3a73Sriastradh * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
272adb3a73Sriastradh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
282adb3a73Sriastradh * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
292adb3a73Sriastradh * POSSIBILITY OF SUCH DAMAGE.
302adb3a73Sriastradh */
312adb3a73Sriastradh
322adb3a73Sriastradh #ifndef _LINUX_PCI_H_
332adb3a73Sriastradh #define _LINUX_PCI_H_
342adb3a73Sriastradh
3549b690a1Snonaka #ifdef _KERNEL_OPT
365c7d226cSnonaka #include "acpica.h"
3749b690a1Snonaka #endif
385c7d226cSnonaka
392adb3a73Sriastradh #include <sys/types.h>
40fceff80cSriastradh #include <sys/param.h>
412adb3a73Sriastradh #include <sys/bus.h>
420fa81a94Sriastradh #include <sys/cdefs.h>
432adb3a73Sriastradh #include <sys/kmem.h>
442adb3a73Sriastradh #include <sys/systm.h>
452adb3a73Sriastradh
46fceff80cSriastradh #include <machine/limits.h>
47fceff80cSriastradh
482adb3a73Sriastradh #include <dev/pci/pcidevs.h>
492adb3a73Sriastradh #include <dev/pci/pcireg.h>
502adb3a73Sriastradh #include <dev/pci/pcivar.h>
51fceff80cSriastradh #include <dev/pci/agpvar.h>
52b19cdf75Smrg #include <dev/pci/ppbvar.h>
532adb3a73Sriastradh
541b077480Smaya #include <linux/device.h>
55375d5351Sriastradh #include <linux/dma-mapping.h>
561b077480Smaya #include <linux/errno.h>
571b077480Smaya #include <linux/io.h>
581a08e23fSriastradh #include <linux/interrupt.h>
592adb3a73Sriastradh #include <linux/ioport.h>
6031781fd8Sriastradh #include <linux/kernel.h>
612adb3a73Sriastradh
62984c4045Sriastradh struct acpi_devnode;
633191a9a0Sriastradh struct pci_driver;
64b19cdf75Smrg struct pci_dev;
653191a9a0Sriastradh
665c7d226cSnonaka struct pci_bus {
67a8b59160Sriastradh /* NetBSD private members */
682805542eSriastradh pci_chipset_tag_t pb_pc;
69a8b59160Sriastradh device_t pb_dev;
70a8b59160Sriastradh
71a8b59160Sriastradh /* Linux API */
72a8b59160Sriastradh u_int number;
73b19cdf75Smrg
74b19cdf75Smrg struct pci_dev *self;
755c7d226cSnonaka };
762adb3a73Sriastradh
772adb3a73Sriastradh struct pci_device_id {
782adb3a73Sriastradh uint32_t vendor;
792adb3a73Sriastradh uint32_t device;
802adb3a73Sriastradh uint32_t subvendor;
812adb3a73Sriastradh uint32_t subdevice;
822adb3a73Sriastradh uint32_t class;
832adb3a73Sriastradh uint32_t class_mask;
842adb3a73Sriastradh unsigned long driver_data;
852adb3a73Sriastradh };
862adb3a73Sriastradh
873b05a10cSriastradh #define PCI_DEVICE(VENDOR, DEVICE) \
883b05a10cSriastradh .vendor = (VENDOR), \
893b05a10cSriastradh .device = (DEVICE)
903b05a10cSriastradh
91a8b59160Sriastradh #define PCI_ANY_ID (~0)
922adb3a73Sriastradh
932adb3a73Sriastradh #define PCI_BASE_CLASS_DISPLAY PCI_CLASS_DISPLAY
942adb3a73Sriastradh
9531781fd8Sriastradh #define PCI_CLASS_DISPLAY_VGA \
9631781fd8Sriastradh ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA)
97d77b1302Sriastradh CTASSERT(PCI_CLASS_DISPLAY_VGA == 0x0300);
98d77b1302Sriastradh
99d77b1302Sriastradh #define PCI_CLASS_DISPLAY_OTHER \
100d77b1302Sriastradh ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_MISC)
101d77b1302Sriastradh CTASSERT(PCI_CLASS_DISPLAY_OTHER == 0x0380);
102d77b1302Sriastradh
1032adb3a73Sriastradh #define PCI_CLASS_BRIDGE_ISA \
1042adb3a73Sriastradh ((PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_ISA)
1052adb3a73Sriastradh CTASSERT(PCI_CLASS_BRIDGE_ISA == 0x0601);
1062adb3a73Sriastradh
1077b7df45fSriastradh /* XXX This is getting silly... */
108a8b59160Sriastradh #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE
1097b7df45fSriastradh #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK
1107b7df45fSriastradh #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI
1117b7df45fSriastradh #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL
1127b7df45fSriastradh #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM
1137b7df45fSriastradh #define PCI_VENDOR_ID_HP PCI_VENDOR_HP
1142adb3a73Sriastradh #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL
115375d5351Sriastradh #define PCI_VENDOR_ID_NVIDIA PCI_VENDOR_NVIDIA
116a8b59160Sriastradh #define PCI_VENDOR_ID_SI PCI_VENDOR_SIS
1177b7df45fSriastradh #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY
1187b7df45fSriastradh #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH
1197b7df45fSriastradh
120ca1dbb91Sriastradh #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
121ca1dbb91Sriastradh
1227b7df45fSriastradh #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_RV100_QY
1232adb3a73Sriastradh
124ca1dbb91Sriastradh #define PCI_SUBDEVICE_ID_QEMU 0x1100
125ca1dbb91Sriastradh
1262adb3a73Sriastradh #define PCI_DEVFN(DEV, FN) \
1272adb3a73Sriastradh (__SHIFTIN((DEV), __BITS(3, 7)) | __SHIFTIN((FN), __BITS(0, 2)))
1284f927c29Sriastradh #define PCI_SLOT(DEVFN) ((int)__SHIFTOUT((DEVFN), __BITS(3, 7)))
1294f927c29Sriastradh #define PCI_FUNC(DEVFN) ((int)__SHIFTOUT((DEVFN), __BITS(0, 2)))
1304f927c29Sriastradh
1314f927c29Sriastradh #define PCI_DEVID(BUS, DEVFN) \
1324f927c29Sriastradh (__SHIFTIN((BUS), __BITS(15, 8)) | __SHIFTIN((DEVFN), __BITS(7, 0)))
1334f927c29Sriastradh #define PCI_BUS_NUM(DEVID) ((int)__SHIFTOUT((DEVID), __BITS(15,8)))
1342adb3a73Sriastradh
135fceff80cSriastradh #define PCI_NUM_RESOURCES ((PCI_MAPREG_END - PCI_MAPREG_START) / 4)
1367b7df45fSriastradh #define DEVICE_COUNT_RESOURCE PCI_NUM_RESOURCES
137fceff80cSriastradh
1382adb3a73Sriastradh #define PCI_CAP_ID_AGP PCI_CAP_AGP
1392adb3a73Sriastradh
140b19cdf75Smrg #define PCI_EXP_LNKCTL PCIE_LCSR
141b19cdf75Smrg #define PCI_EXP_LNKCTL_HAWD PCIE_LCSR_HAWD
142b19cdf75Smrg #define PCI_EXP_DEVSTA (PCIE_DCSR + 2)
143b19cdf75Smrg #define PCI_EXP_DEVSTA_TRPND (PCIE_DCSR_TRANSACTION_PND >> 16)
144b19cdf75Smrg #define PCI_EXP_LNKCTL2 PCIE_LCAP2
145b19cdf75Smrg #define PCI_EXP_LNKCTL2_ENTER_COMP PCIE_LCSR2_ENT_COMPL
146b19cdf75Smrg #define PCI_EXP_LNKCTL2_TX_MARGIN PCIE_LCSR2_TX_MARGIN
147b19cdf75Smrg #define PCI_EXP_LNKCTL2_TLS PCIE_LCSR2_TGT_LSPEED
148b19cdf75Smrg #define PCI_EXP_LNKCTL2_TLS_2_5GT PCIE_LCSR2_TGT_LSPEED_2_5G
149b19cdf75Smrg #define PCI_EXP_LNKCTL2_TLS_5_0GT PCIE_LCSR2_TGT_LSPEED_5G
150b19cdf75Smrg #define PCI_EXP_LNKCTL2_TLS_8_0GT PCIE_LCSR2_TGT_LSPEED_8G
151b19cdf75Smrg #define PCI_EXP_LNKCAP PCIE_LCAP
152b19cdf75Smrg #define PCI_EXP_LNKCAP_CLKPM PCIE_LCAP_CLOCK_PM
153b19cdf75Smrg
154b19cdf75Smrg
155fceff80cSriastradh typedef int pci_power_t;
156fceff80cSriastradh
157fceff80cSriastradh #define PCI_D0 0
158fceff80cSriastradh #define PCI_D1 1
159fceff80cSriastradh #define PCI_D2 2
160fceff80cSriastradh #define PCI_D3hot 3
161fceff80cSriastradh #define PCI_D3cold 4
162fceff80cSriastradh
163fceff80cSriastradh #define __pci_iomem
164fceff80cSriastradh
1652adb3a73Sriastradh struct pci_dev {
1662adb3a73Sriastradh struct pci_attach_args pd_pa;
1672adb3a73Sriastradh int pd_kludges; /* Gotta lose 'em... */
1682adb3a73Sriastradh #define NBPCI_KLUDGE_GET_MUMBLE 0x01
1692adb3a73Sriastradh #define NBPCI_KLUDGE_MAP_ROM 0x02
1702adb3a73Sriastradh bus_space_tag_t pd_rom_bst;
1712adb3a73Sriastradh bus_space_handle_t pd_rom_bsh;
1722adb3a73Sriastradh bus_size_t pd_rom_size;
173522786efSriastradh bus_space_handle_t pd_rom_found_bsh;
17438b13568Sriastradh bus_size_t pd_rom_found_size;
1752adb3a73Sriastradh void *pd_rom_vaddr;
1762adb3a73Sriastradh device_t pd_dev;
17734b84dedSriastradh void *pd_drvdata;
178fceff80cSriastradh struct {
179fceff80cSriastradh pcireg_t type;
180fceff80cSriastradh bus_addr_t addr;
181fceff80cSriastradh bus_size_t size;
182fceff80cSriastradh int flags;
183fceff80cSriastradh bus_space_tag_t bst;
184fceff80cSriastradh bus_space_handle_t bsh;
185fceff80cSriastradh void __pci_iomem *kva;
18666c4b24dSriastradh bool mapped;
187fceff80cSriastradh } pd_resources[PCI_NUM_RESOURCES];
1887b7df45fSriastradh struct pci_conf_state *pd_saved_state;
1895c7d226cSnonaka struct acpi_devnode *pd_ad;
1909311f04fSriastradh pci_intr_handle_t *pd_intr_handles;
191a8b59160Sriastradh unsigned pd_enablecnt;
1929311f04fSriastradh
1939311f04fSriastradh /* Linx API only below */
1942adb3a73Sriastradh struct pci_bus *bus;
1952adb3a73Sriastradh uint32_t devfn;
1962adb3a73Sriastradh uint16_t vendor;
1972adb3a73Sriastradh uint16_t device;
1982adb3a73Sriastradh uint16_t subsystem_vendor;
1992adb3a73Sriastradh uint16_t subsystem_device;
2002adb3a73Sriastradh uint8_t revision;
2012adb3a73Sriastradh uint32_t class;
2022adb3a73Sriastradh bool msi_enabled;
20338d0c67fSriastradh bool no_64bit_msi;
2042adb3a73Sriastradh };
2052adb3a73Sriastradh
2069ea3de94Sriastradh enum pci_bus_speed {
2079ea3de94Sriastradh PCI_SPEED_UNKNOWN,
2089ea3de94Sriastradh PCIE_SPEED_2_5GT,
2099ea3de94Sriastradh PCIE_SPEED_5_0GT,
2109ea3de94Sriastradh PCIE_SPEED_8_0GT,
2119ea3de94Sriastradh PCIE_SPEED_16_0GT,
212d69eb2ccSmrg PCIE_SPEED_32_0GT,
213d69eb2ccSmrg PCIE_SPEED_64_0GT,
214d69eb2ccSmrg };
215d69eb2ccSmrg
216d69eb2ccSmrg /*
217d69eb2ccSmrg * Actually values from the Link Status register, bits 16-19. Don't use
218d69eb2ccSmrg * these as a bit-mask -- these are the only known, valid values.
219d69eb2ccSmrg */
220d69eb2ccSmrg enum pcie_link_width {
221d69eb2ccSmrg PCIE_LNK_WIDTH_RESRV = 0,
222d69eb2ccSmrg PCIE_LNK_X1 = __BIT(0),
223d69eb2ccSmrg PCIE_LNK_X2 = __BIT(1),
224d69eb2ccSmrg PCIE_LNK_X4 = __BIT(2),
225d69eb2ccSmrg PCIE_LNK_X8 = __BIT(3),
226d69eb2ccSmrg PCIE_LNK_X12 = __BITS(2,3),
227d69eb2ccSmrg PCIE_LNK_X16 = __BIT(4),
228d69eb2ccSmrg PCIE_LNK_X32 = __BIT(5),
229d69eb2ccSmrg PCIE_LNK_WIDTH_UNKNOWN = __BITS(0, 7),
2309ea3de94Sriastradh };
2319ea3de94Sriastradh
232d4ca0843Sriastradh #define PCIBIOS_MIN_MEM 0x100000 /* XXX bogus x86 kludge bollocks */
2332adb3a73Sriastradh
2342adb3a73Sriastradh #define __pci_rom_iomem
2352adb3a73Sriastradh
2360cdaa721Sriastradh /* Namespace. */
2370cdaa721Sriastradh #define pci_bus_alloc_resource linux_pci_bus_alloc_resource
2380cdaa721Sriastradh #define pci_bus_read_config_byte linux_pci_bus_read_config_byte
2390cdaa721Sriastradh #define pci_bus_read_config_dword linux_pci_bus_read_config_dword
2400cdaa721Sriastradh #define pci_bus_read_config_word linux_pci_bus_read_config_word
2410cdaa721Sriastradh #define pci_bus_write_config_byte linux_pci_bus_write_config_byte
2420cdaa721Sriastradh #define pci_bus_write_config_dword linux_pci_bus_write_config_dword
2430cdaa721Sriastradh #define pci_bus_write_config_word linux_pci_bus_write_config_word
2440cdaa721Sriastradh #define pci_clear_master linux_pci_clear_master
2450cdaa721Sriastradh #define pci_dev_dev linux_pci_dev_dev
2463b05a10cSriastradh #define pci_dev_present linux_pci_dev_present
2470cdaa721Sriastradh #define pci_dev_put linux_pci_dev_put
2480cdaa721Sriastradh #define pci_disable_msi linux_pci_disable_msi
2490cdaa721Sriastradh #define pci_disable_rom linux_pci_disable_rom
2500cdaa721Sriastradh #define pci_dma_supported linux_pci_dma_supported
2510cdaa721Sriastradh #define pci_domain_nr linux_pci_domain_nr
2520cdaa721Sriastradh #define pci_enable_msi linux_pci_enable_msi
2530cdaa721Sriastradh #define pci_enable_rom linux_pci_enable_rom
2540cdaa721Sriastradh #define pci_find_capability linux_pci_find_capability
2550cdaa721Sriastradh #define pci_get_class linux_pci_get_class
2564c14a7e2Sriastradh #define pci_get_domain_bus_and_slot linux_pci_get_domain_bus_and_slot
2570cdaa721Sriastradh #define pci_get_drvdata linux_pci_get_drvdata
2580cdaa721Sriastradh #define pci_iomap linux_pci_iomap
2590cdaa721Sriastradh #define pci_iounmap linux_pci_iounmap
2600cdaa721Sriastradh #define pci_is_pcie linux_pci_is_pcie
2610cdaa721Sriastradh #define pci_is_root_bus linux_pci_is_root_bus
262aba892b1Sriastradh #define pci_is_thunderbolt_attached linux_pci_is_thunderbolt_attached
2630cdaa721Sriastradh #define pci_map_rom linux_pci_map_rom
264e233a6e6Sriastradh #define pci_name linux_pci_name
2650cdaa721Sriastradh #define pci_platform_rom linux_pci_platform_rom
2660cdaa721Sriastradh #define pci_read_config_byte linux_pci_read_config_byte
2670cdaa721Sriastradh #define pci_read_config_dword linux_pci_read_config_dword
2680cdaa721Sriastradh #define pci_read_config_word linux_pci_read_config_word
269*3dbba2cfSriastradh #define pci_release_region linux_pci_release_region
270*3dbba2cfSriastradh #define pci_release_regions linux_pci_release_regions
271*3dbba2cfSriastradh #define pci_request_region linux_pci_request_region
272*3dbba2cfSriastradh #define pci_request_regions linux_pci_request_regions
2730cdaa721Sriastradh #define pci_resource_end linux_pci_resource_end
2740cdaa721Sriastradh #define pci_resource_flags linux_pci_resource_flags
2750cdaa721Sriastradh #define pci_resource_len linux_pci_resource_len
2760cdaa721Sriastradh #define pci_resource_start linux_pci_resource_start
2770cdaa721Sriastradh #define pci_restore_state linux_pci_restore_state
2780cdaa721Sriastradh #define pci_save_state linux_pci_save_state
27934b84dedSriastradh #define pci_set_drvdata linux_pci_set_drvdata
2800cdaa721Sriastradh #define pci_set_master linux_pci_set_master
2810cdaa721Sriastradh #define pci_unmap_rom linux_pci_unmap_rom
2820cdaa721Sriastradh #define pci_write_config_byte linux_pci_write_config_byte
2830cdaa721Sriastradh #define pci_write_config_dword linux_pci_write_config_dword
2840cdaa721Sriastradh #define pci_write_config_word linux_pci_write_config_word
2850cdaa721Sriastradh #define pcibios_align_resource linux_pcibios_align_resource
286d69eb2ccSmrg #define pcie_get_speed_cap linux_pcie_get_speed_cap
287d69eb2ccSmrg #define pcie_bandwidth_available linux_pcie_bandwidth_available
288b19cdf75Smrg #define pcie_read_config_dword linux_pcie_capability_read_dword
289b19cdf75Smrg #define pcie_read_config_word linux_pcie_capability_read_word
290b19cdf75Smrg #define pcie_write_config_dword linux_pcie_capability_write_dword
291b19cdf75Smrg #define pcie_write_config_word linux_pcie_capability_write_word
2922adb3a73Sriastradh
2930cdaa721Sriastradh /* NetBSD local additions. */
2940cdaa721Sriastradh void linux_pci_dev_init(struct pci_dev *, device_t, device_t,
2950cdaa721Sriastradh const struct pci_attach_args *, int);
2960cdaa721Sriastradh void linux_pci_dev_destroy(struct pci_dev *);
2972adb3a73Sriastradh
2980cdaa721Sriastradh /* NetBSD no-renames because use requires review. */
2990cdaa721Sriastradh int linux_pci_enable_device(struct pci_dev *);
3000cdaa721Sriastradh void linux_pci_disable_device(struct pci_dev *);
301f01da319Sriastradh
3020cdaa721Sriastradh bool pci_is_root_bus(struct pci_bus *);
3030cdaa721Sriastradh int pci_domain_nr(struct pci_bus *);
304f01da319Sriastradh
3050cdaa721Sriastradh device_t pci_dev_dev(struct pci_dev *);
30634b84dedSriastradh void pci_set_drvdata(struct pci_dev *, void *);
30734b84dedSriastradh void * pci_get_drvdata(struct pci_dev *);
308e233a6e6Sriastradh const char * pci_name(struct pci_dev *);
309f01da319Sriastradh
3100cdaa721Sriastradh int pci_find_capability(struct pci_dev *, int);
3110cdaa721Sriastradh bool pci_is_pcie(struct pci_dev *);
3120cdaa721Sriastradh bool pci_dma_supported(struct pci_dev *, uintmax_t);
313aba892b1Sriastradh bool pci_is_thunderbolt_attached(struct pci_dev *);
314f01da319Sriastradh
3150cdaa721Sriastradh int pci_read_config_dword(struct pci_dev *, int, uint32_t *);
3160cdaa721Sriastradh int pci_read_config_word(struct pci_dev *, int, uint16_t *);
3170cdaa721Sriastradh int pci_read_config_byte(struct pci_dev *, int, uint8_t *);
3180cdaa721Sriastradh int pci_write_config_dword(struct pci_dev *, int, uint32_t);
3190cdaa721Sriastradh int pci_write_config_word(struct pci_dev *, int, uint16_t);
3200cdaa721Sriastradh int pci_write_config_byte(struct pci_dev *, int, uint8_t);
3212adb3a73Sriastradh
322b19cdf75Smrg int pcie_capability_read_dword(struct pci_dev *, int, uint32_t *);
323b19cdf75Smrg int pcie_capability_read_word(struct pci_dev *, int, uint16_t *);
324b19cdf75Smrg int pcie_capability_write_dword(struct pci_dev *, int, uint32_t);
325b19cdf75Smrg int pcie_capability_write_word(struct pci_dev *, int, uint16_t);
326b19cdf75Smrg
3270cdaa721Sriastradh int pci_bus_read_config_dword(struct pci_bus *, unsigned, int,
3280cdaa721Sriastradh uint32_t *);
3290cdaa721Sriastradh int pci_bus_read_config_word(struct pci_bus *, unsigned, int,
3300cdaa721Sriastradh uint16_t *);
3310cdaa721Sriastradh int pci_bus_read_config_byte(struct pci_bus *, unsigned, int,
3320cdaa721Sriastradh uint8_t *);
3330cdaa721Sriastradh int pci_bus_write_config_dword(struct pci_bus *, unsigned, int,
3340cdaa721Sriastradh uint32_t);
3350cdaa721Sriastradh int pci_bus_write_config_word(struct pci_bus *, unsigned, int,
3360cdaa721Sriastradh uint16_t);
3370cdaa721Sriastradh int pci_bus_write_config_byte(struct pci_bus *, unsigned, int,
3380cdaa721Sriastradh uint8_t);
3392adb3a73Sriastradh
3400cdaa721Sriastradh int pci_enable_msi(struct pci_dev *);
3410cdaa721Sriastradh void pci_disable_msi(struct pci_dev *);
3420cdaa721Sriastradh void pci_set_master(struct pci_dev *);
3430cdaa721Sriastradh void pci_clear_master(struct pci_dev *);
3442adb3a73Sriastradh
345b19cdf75Smrg int pcie_get_readrq(struct pci_dev *);
346b19cdf75Smrg int pcie_set_readrq(struct pci_dev *, int);
347b19cdf75Smrg
3480cdaa721Sriastradh bus_addr_t pcibios_align_resource(void *, const struct resource *,
3490cdaa721Sriastradh bus_addr_t, bus_size_t);
3500cdaa721Sriastradh int pci_bus_alloc_resource(struct pci_bus *, struct resource *,
3510cdaa721Sriastradh bus_size_t, bus_size_t, bus_addr_t, int,
3520cdaa721Sriastradh bus_addr_t (*)(void *, const struct resource *, bus_addr_t,
3530cdaa721Sriastradh bus_size_t), struct pci_dev *);
35419234e81Sriastradh
3550cdaa721Sriastradh /* XXX Kludges only -- do not use without checking the implementation! */
3564c14a7e2Sriastradh struct pci_dev *pci_get_domain_bus_and_slot(int, int, int);
3570cdaa721Sriastradh struct pci_dev *pci_get_class(uint32_t, struct pci_dev *); /* i915 kludge */
3583b05a10cSriastradh int pci_dev_present(const struct pci_device_id *);
3590cdaa721Sriastradh void pci_dev_put(struct pci_dev *);
36019234e81Sriastradh
3610cdaa721Sriastradh void __pci_rom_iomem *
3620cdaa721Sriastradh pci_map_rom(struct pci_dev *, size_t *);
3630cdaa721Sriastradh void __pci_rom_iomem *
3640cdaa721Sriastradh pci_platform_rom(struct pci_dev *, size_t *);
3650cdaa721Sriastradh void pci_unmap_rom(struct pci_dev *, void __pci_rom_iomem *);
3660cdaa721Sriastradh int pci_enable_rom(struct pci_dev *);
3670cdaa721Sriastradh void pci_disable_rom(struct pci_dev *);
3682adb3a73Sriastradh
369*3dbba2cfSriastradh int pci_request_regions(struct pci_dev *, const char *);
370*3dbba2cfSriastradh void pci_release_regions(struct pci_dev *);
371*3dbba2cfSriastradh int pci_request_region(struct pci_dev *, int, const char *);
372*3dbba2cfSriastradh void pci_release_region(struct pci_dev *, int);
373*3dbba2cfSriastradh
3740cdaa721Sriastradh bus_addr_t pci_resource_start(struct pci_dev *, unsigned);
3750cdaa721Sriastradh bus_size_t pci_resource_len(struct pci_dev *, unsigned);
3760cdaa721Sriastradh bus_addr_t pci_resource_end(struct pci_dev *, unsigned);
3770cdaa721Sriastradh int pci_resource_flags(struct pci_dev *, unsigned);
37819234e81Sriastradh
3790cdaa721Sriastradh void __pci_iomem *
3800cdaa721Sriastradh pci_iomap(struct pci_dev *, unsigned, bus_size_t);
3810cdaa721Sriastradh void pci_iounmap(struct pci_dev *, void __pci_iomem *);
3822adb3a73Sriastradh
3830cdaa721Sriastradh void pci_save_state(struct pci_dev *);
3840cdaa721Sriastradh void pci_restore_state(struct pci_dev *);
3855ea47f5dSriastradh
386d69eb2ccSmrg enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
387d69eb2ccSmrg unsigned pcie_bandwidth_available(struct pci_dev *dev,
388d69eb2ccSmrg struct pci_dev **limiting_dev,
389d69eb2ccSmrg enum pci_bus_speed *speed,
390d69eb2ccSmrg enum pcie_link_width *width);
391d69eb2ccSmrg
3925ea47f5dSriastradh static inline bool
dev_is_pci(struct device * dev)3935ea47f5dSriastradh dev_is_pci(struct device *dev)
3945ea47f5dSriastradh {
3955ea47f5dSriastradh struct device *parent = device_parent(dev);
3965ea47f5dSriastradh
3975ea47f5dSriastradh return parent && device_is_a(parent, "pci");
3985ea47f5dSriastradh }
39966c4b24dSriastradh
4002adb3a73Sriastradh #endif /* _LINUX_PCI_H_ */
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