1*9c4eccf3Sjdolecek /*- 2*9c4eccf3Sjdolecek * BSD LICENSE 3*9c4eccf3Sjdolecek * 4*9c4eccf3Sjdolecek * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5*9c4eccf3Sjdolecek * All rights reserved. 6*9c4eccf3Sjdolecek * 7*9c4eccf3Sjdolecek * Redistribution and use in source and binary forms, with or without 8*9c4eccf3Sjdolecek * modification, are permitted provided that the following conditions 9*9c4eccf3Sjdolecek * are met: 10*9c4eccf3Sjdolecek * 11*9c4eccf3Sjdolecek * * Redistributions of source code must retain the above copyright 12*9c4eccf3Sjdolecek * notice, this list of conditions and the following disclaimer. 13*9c4eccf3Sjdolecek * * Redistributions in binary form must reproduce the above copyright 14*9c4eccf3Sjdolecek * notice, this list of conditions and the following disclaimer in 15*9c4eccf3Sjdolecek * the documentation and/or other materials provided with the 16*9c4eccf3Sjdolecek * distribution. 17*9c4eccf3Sjdolecek * * Neither the name of copyright holder nor the names of its 18*9c4eccf3Sjdolecek * contributors may be used to endorse or promote products derived 19*9c4eccf3Sjdolecek * from this software without specific prior written permission. 20*9c4eccf3Sjdolecek * 21*9c4eccf3Sjdolecek * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22*9c4eccf3Sjdolecek * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23*9c4eccf3Sjdolecek * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24*9c4eccf3Sjdolecek * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25*9c4eccf3Sjdolecek * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26*9c4eccf3Sjdolecek * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27*9c4eccf3Sjdolecek * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28*9c4eccf3Sjdolecek * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29*9c4eccf3Sjdolecek * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30*9c4eccf3Sjdolecek * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31*9c4eccf3Sjdolecek * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32*9c4eccf3Sjdolecek */ 33*9c4eccf3Sjdolecek 34*9c4eccf3Sjdolecek #ifndef _ENA_REGS_H_ 35*9c4eccf3Sjdolecek #define _ENA_REGS_H_ 36*9c4eccf3Sjdolecek 37*9c4eccf3Sjdolecek /* ena_registers offsets */ 38*9c4eccf3Sjdolecek #define ENA_REGS_VERSION_OFF 0x0 39*9c4eccf3Sjdolecek #define ENA_REGS_CONTROLLER_VERSION_OFF 0x4 40*9c4eccf3Sjdolecek #define ENA_REGS_CAPS_OFF 0x8 41*9c4eccf3Sjdolecek #define ENA_REGS_CAPS_EXT_OFF 0xc 42*9c4eccf3Sjdolecek #define ENA_REGS_AQ_BASE_LO_OFF 0x10 43*9c4eccf3Sjdolecek #define ENA_REGS_AQ_BASE_HI_OFF 0x14 44*9c4eccf3Sjdolecek #define ENA_REGS_AQ_CAPS_OFF 0x18 45*9c4eccf3Sjdolecek #define ENA_REGS_ACQ_BASE_LO_OFF 0x20 46*9c4eccf3Sjdolecek #define ENA_REGS_ACQ_BASE_HI_OFF 0x24 47*9c4eccf3Sjdolecek #define ENA_REGS_ACQ_CAPS_OFF 0x28 48*9c4eccf3Sjdolecek #define ENA_REGS_AQ_DB_OFF 0x2c 49*9c4eccf3Sjdolecek #define ENA_REGS_ACQ_TAIL_OFF 0x30 50*9c4eccf3Sjdolecek #define ENA_REGS_AENQ_CAPS_OFF 0x34 51*9c4eccf3Sjdolecek #define ENA_REGS_AENQ_BASE_LO_OFF 0x38 52*9c4eccf3Sjdolecek #define ENA_REGS_AENQ_BASE_HI_OFF 0x3c 53*9c4eccf3Sjdolecek #define ENA_REGS_AENQ_HEAD_DB_OFF 0x40 54*9c4eccf3Sjdolecek #define ENA_REGS_AENQ_TAIL_OFF 0x44 55*9c4eccf3Sjdolecek #define ENA_REGS_INTR_MASK_OFF 0x4c 56*9c4eccf3Sjdolecek #define ENA_REGS_DEV_CTL_OFF 0x54 57*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_OFF 0x58 58*9c4eccf3Sjdolecek #define ENA_REGS_MMIO_REG_READ_OFF 0x5c 59*9c4eccf3Sjdolecek #define ENA_REGS_MMIO_RESP_LO_OFF 0x60 60*9c4eccf3Sjdolecek #define ENA_REGS_MMIO_RESP_HI_OFF 0x64 61*9c4eccf3Sjdolecek #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68 62*9c4eccf3Sjdolecek 63*9c4eccf3Sjdolecek /* version register */ 64*9c4eccf3Sjdolecek #define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff 65*9c4eccf3Sjdolecek #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 8 66*9c4eccf3Sjdolecek #define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00 67*9c4eccf3Sjdolecek 68*9c4eccf3Sjdolecek /* controller_version register */ 69*9c4eccf3Sjdolecek #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff 70*9c4eccf3Sjdolecek #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 8 71*9c4eccf3Sjdolecek #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00 72*9c4eccf3Sjdolecek #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 16 73*9c4eccf3Sjdolecek #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000 74*9c4eccf3Sjdolecek #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 24 75*9c4eccf3Sjdolecek #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000 76*9c4eccf3Sjdolecek 77*9c4eccf3Sjdolecek /* caps register */ 78*9c4eccf3Sjdolecek #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1 79*9c4eccf3Sjdolecek #define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT 1 80*9c4eccf3Sjdolecek #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e 81*9c4eccf3Sjdolecek #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8 82*9c4eccf3Sjdolecek #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00 83*9c4eccf3Sjdolecek #define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16 84*9c4eccf3Sjdolecek #define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000 85*9c4eccf3Sjdolecek 86*9c4eccf3Sjdolecek /* aq_caps register */ 87*9c4eccf3Sjdolecek #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff 88*9c4eccf3Sjdolecek #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 16 89*9c4eccf3Sjdolecek #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000 90*9c4eccf3Sjdolecek 91*9c4eccf3Sjdolecek /* acq_caps register */ 92*9c4eccf3Sjdolecek #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff 93*9c4eccf3Sjdolecek #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 16 94*9c4eccf3Sjdolecek #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff0000 95*9c4eccf3Sjdolecek 96*9c4eccf3Sjdolecek /* aenq_caps register */ 97*9c4eccf3Sjdolecek #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff 98*9c4eccf3Sjdolecek #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 16 99*9c4eccf3Sjdolecek #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff0000 100*9c4eccf3Sjdolecek 101*9c4eccf3Sjdolecek /* dev_ctl register */ 102*9c4eccf3Sjdolecek #define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x1 103*9c4eccf3Sjdolecek #define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT 1 104*9c4eccf3Sjdolecek #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2 105*9c4eccf3Sjdolecek #define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT 2 106*9c4eccf3Sjdolecek #define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4 107*9c4eccf3Sjdolecek #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3 108*9c4eccf3Sjdolecek #define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8 109*9c4eccf3Sjdolecek 110*9c4eccf3Sjdolecek /* dev_sts register */ 111*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_READY_MASK 0x1 112*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1 113*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2 114*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2 115*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4 116*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3 117*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8 118*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4 119*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10 120*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5 121*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20 122*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6 123*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40 124*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7 125*9c4eccf3Sjdolecek #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80 126*9c4eccf3Sjdolecek 127*9c4eccf3Sjdolecek /* mmio_reg_read register */ 128*9c4eccf3Sjdolecek #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff 129*9c4eccf3Sjdolecek #define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16 130*9c4eccf3Sjdolecek #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000 131*9c4eccf3Sjdolecek 132*9c4eccf3Sjdolecek /* rss_ind_entry_update register */ 133*9c4eccf3Sjdolecek #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff 134*9c4eccf3Sjdolecek #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16 135*9c4eccf3Sjdolecek #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000 136*9c4eccf3Sjdolecek 137*9c4eccf3Sjdolecek #endif /*_ENA_REGS_H_ */ 138