184c8294dSjmcneill// SPDX-License-Identifier: GPL-2.0 284c8294dSjmcneill/* 384c8294dSjmcneill * Device tree for Winterland IceBoard 484c8294dSjmcneill * 5*9ed2a30eSjmcneill * https://mcgillcosmology.com 6*9ed2a30eSjmcneill * https://threespeedlogic.com 784c8294dSjmcneill * 884c8294dSjmcneill * This is an ARM + FPGA instrumentation board used at telescopes in 984c8294dSjmcneill * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO 1084c8294dSjmcneill * observatory in British Columbia (CHIME). 1184c8294dSjmcneill * 1284c8294dSjmcneill * Copyright (c) 2019 Three-Speed Logic, Inc. <gsmecher@threespeedlogic.com> 1384c8294dSjmcneill */ 1484c8294dSjmcneill 1584c8294dSjmcneill/dts-v1/; 1684c8294dSjmcneill 1784c8294dSjmcneill#include "dm814x.dtsi" 1884c8294dSjmcneill#include <dt-bindings/interrupt-controller/irq.h> 1984c8294dSjmcneill 2084c8294dSjmcneill/ { 2184c8294dSjmcneill model = "Winterland IceBoard"; 2284c8294dSjmcneill compatible = "ti,dm8148", "ti,dm814"; 2384c8294dSjmcneill 2484c8294dSjmcneill chosen { 2584c8294dSjmcneill stdout-path = "serial1:115200n8"; 2684c8294dSjmcneill bootargs = "earlycon"; 2784c8294dSjmcneill }; 2884c8294dSjmcneill 2984c8294dSjmcneill memory@80000000 { 3084c8294dSjmcneill device_type = "memory"; 3184c8294dSjmcneill reg = <0x80000000 0x40000000>; /* 1 GB */ 3284c8294dSjmcneill }; 3384c8294dSjmcneill 3484c8294dSjmcneill vmmcsd_fixed: fixedregulator0 { 3584c8294dSjmcneill compatible = "regulator-fixed"; 3684c8294dSjmcneill regulator-name = "vmmcsd_fixed"; 3784c8294dSjmcneill regulator-min-microvolt = <3300000>; 3884c8294dSjmcneill regulator-max-microvolt = <3300000>; 3984c8294dSjmcneill regulator-always-on; 4084c8294dSjmcneill }; 4184c8294dSjmcneill}; 4284c8294dSjmcneill 4384c8294dSjmcneill/* The MAC provides internal delay for the transmit path ONLY, which is enabled 4484c8294dSjmcneill * provided no -id/-txid/-rxid suffix is provided to "phy-mode". 4584c8294dSjmcneill * 4684c8294dSjmcneill * The receive path is delayed at the PHY. The recommended register settings 4784c8294dSjmcneill * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the 4884c8294dSjmcneill * conversion code in the kernel lies: the PHY's registers are 120 ps per tap, 4984c8294dSjmcneill * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to 5084c8294dSjmcneill * obtain the correct register settings. 5184c8294dSjmcneill */ 5284c8294dSjmcneill&mac { dual_emac = <1>; }; 5384c8294dSjmcneill&cpsw_emac0 { 5484c8294dSjmcneill phy-handle = <ðphy0>; 5584c8294dSjmcneill phy-mode = "rgmii"; 5684c8294dSjmcneill dual_emac_res_vlan = <1>; 5784c8294dSjmcneill}; 5884c8294dSjmcneill&cpsw_emac1 { 5984c8294dSjmcneill phy-handle = <ðphy1>; 6084c8294dSjmcneill phy-mode = "rgmii"; 6184c8294dSjmcneill dual_emac_res_vlan = <2>; 6284c8294dSjmcneill}; 6384c8294dSjmcneill 6484c8294dSjmcneill&davinci_mdio { 6584c8294dSjmcneill ethphy0: ethernet-phy@0 { 6684c8294dSjmcneill reg = <0x2>; 6784c8294dSjmcneill 6884c8294dSjmcneill rxc-skew-ps = <3000>; 6984c8294dSjmcneill rxdv-skew-ps = <0>; 7084c8294dSjmcneill 7184c8294dSjmcneill rxd3-skew-ps = <0>; 7284c8294dSjmcneill rxd2-skew-ps = <0>; 7384c8294dSjmcneill rxd1-skew-ps = <0>; 7484c8294dSjmcneill rxd0-skew-ps = <0>; 7584c8294dSjmcneill 7684c8294dSjmcneill phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; 7784c8294dSjmcneill }; 7884c8294dSjmcneill 7984c8294dSjmcneill ethphy1: ethernet-phy@1 { 8084c8294dSjmcneill reg = <0x1>; 8184c8294dSjmcneill 8284c8294dSjmcneill rxc-skew-ps = <3000>; 8384c8294dSjmcneill rxdv-skew-ps = <0>; 8484c8294dSjmcneill 8584c8294dSjmcneill rxd3-skew-ps = <0>; 8684c8294dSjmcneill rxd2-skew-ps = <0>; 8784c8294dSjmcneill rxd1-skew-ps = <0>; 8884c8294dSjmcneill rxd0-skew-ps = <0>; 8984c8294dSjmcneill 9084c8294dSjmcneill phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 9184c8294dSjmcneill }; 9284c8294dSjmcneill}; 9384c8294dSjmcneill 9484c8294dSjmcneill&mmc1 { status = "disabled"; }; 9584c8294dSjmcneill&mmc2 { 9684c8294dSjmcneill pinctrl-names = "default"; 9784c8294dSjmcneill pinctrl-0 = <&mmc2_pins>; 9884c8294dSjmcneill vmmc-supply = <&vmmcsd_fixed>; 9984c8294dSjmcneill bus-width = <4>; 10084c8294dSjmcneill}; 10184c8294dSjmcneill&mmc3 { status = "disabled"; }; 10284c8294dSjmcneill 10384c8294dSjmcneill&i2c1 { 10484c8294dSjmcneill /* Most I2C activity happens through this port, with the sole exception 10584c8294dSjmcneill * of the backplane. Since there are multiply assigned addresses, the 10684c8294dSjmcneill * "i2c-mux-idle-disconnect" is important. 10784c8294dSjmcneill */ 10884c8294dSjmcneill 10984c8294dSjmcneill pca9548@70 { 11084c8294dSjmcneill compatible = "nxp,pca9548"; 11184c8294dSjmcneill reg = <0x70>; 11284c8294dSjmcneill #address-cells = <1>; 11384c8294dSjmcneill #size-cells = <0>; 11409fa6529Sskrll i2c-mux-idle-disconnect; 11584c8294dSjmcneill 11684c8294dSjmcneill i2c@0 { 11784c8294dSjmcneill /* FMC A */ 11884c8294dSjmcneill #address-cells = <1>; 11984c8294dSjmcneill #size-cells = <0>; 12084c8294dSjmcneill reg = <0>; 12184c8294dSjmcneill }; 12284c8294dSjmcneill 12384c8294dSjmcneill i2c@1 { 12484c8294dSjmcneill /* FMC B */ 12584c8294dSjmcneill #address-cells = <1>; 12684c8294dSjmcneill #size-cells = <0>; 12784c8294dSjmcneill reg = <1>; 12884c8294dSjmcneill }; 12984c8294dSjmcneill 13084c8294dSjmcneill i2c@2 { 13184c8294dSjmcneill /* QSFP A */ 13284c8294dSjmcneill #address-cells = <1>; 13384c8294dSjmcneill #size-cells = <0>; 13484c8294dSjmcneill reg = <2>; 13584c8294dSjmcneill }; 13684c8294dSjmcneill 13784c8294dSjmcneill i2c@3 { 13884c8294dSjmcneill /* QSFP B */ 13984c8294dSjmcneill #address-cells = <1>; 14084c8294dSjmcneill #size-cells = <0>; 14184c8294dSjmcneill reg = <3>; 14284c8294dSjmcneill }; 14384c8294dSjmcneill 14484c8294dSjmcneill i2c@4 { 14584c8294dSjmcneill /* SFP */ 14684c8294dSjmcneill #address-cells = <1>; 14784c8294dSjmcneill #size-cells = <0>; 14884c8294dSjmcneill reg = <4>; 14984c8294dSjmcneill }; 15084c8294dSjmcneill 15184c8294dSjmcneill i2c@5 { 15284c8294dSjmcneill #address-cells = <1>; 15384c8294dSjmcneill #size-cells = <0>; 15484c8294dSjmcneill reg = <5>; 15584c8294dSjmcneill 15684c8294dSjmcneill ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; 15784c8294dSjmcneill ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; 15884c8294dSjmcneill ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; }; 15984c8294dSjmcneill 16084c8294dSjmcneill ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; }; 16184c8294dSjmcneill ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; }; 16284c8294dSjmcneill ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; }; 16384c8294dSjmcneill 16484c8294dSjmcneill ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; }; 16584c8294dSjmcneill ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; }; 16684c8294dSjmcneill ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; }; 16784c8294dSjmcneill ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; }; 16884c8294dSjmcneill ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; }; 16984c8294dSjmcneill ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; }; 17084c8294dSjmcneill ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; }; 17184c8294dSjmcneill ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; }; 17284c8294dSjmcneill ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; }; 17384c8294dSjmcneill }; 17484c8294dSjmcneill 17584c8294dSjmcneill i2c@6 { 17684c8294dSjmcneill /* Backplane */ 17784c8294dSjmcneill #address-cells = <1>; 17884c8294dSjmcneill #size-cells = <0>; 17984c8294dSjmcneill reg = <6>; 18084c8294dSjmcneill }; 18184c8294dSjmcneill 18284c8294dSjmcneill i2c@7 { 18384c8294dSjmcneill #address-cells = <1>; 18484c8294dSjmcneill #size-cells = <0>; 18584c8294dSjmcneill reg = <7>; 18684c8294dSjmcneill 18784c8294dSjmcneill u41: pca9575@20 { 18884c8294dSjmcneill compatible = "nxp,pca9575"; 18984c8294dSjmcneill reg = <0x20>; 19084c8294dSjmcneill gpio-controller; 19184c8294dSjmcneill #gpio-cells = <2>; 19284c8294dSjmcneill 19384c8294dSjmcneill gpio-line-names = 19484c8294dSjmcneill "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C", 19584c8294dSjmcneill "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", 19684c8294dSjmcneill "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", 19784c8294dSjmcneill "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; 198*9ed2a30eSjmcneill reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 19984c8294dSjmcneill }; 20084c8294dSjmcneill 20184c8294dSjmcneill u42: pca9575@21 { 20284c8294dSjmcneill compatible = "nxp,pca9575"; 20384c8294dSjmcneill reg = <0x21>; 20484c8294dSjmcneill gpio-controller; 20584c8294dSjmcneill #gpio-cells = <2>; 20684c8294dSjmcneill gpio-line-names = 20784c8294dSjmcneill "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL", 20884c8294dSjmcneill "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", 20984c8294dSjmcneill "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", 21084c8294dSjmcneill "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; 211*9ed2a30eSjmcneill reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 21284c8294dSjmcneill }; 21384c8294dSjmcneill 21484c8294dSjmcneill u48: pca9575@22 { 21584c8294dSjmcneill compatible = "nxp,pca9575"; 21684c8294dSjmcneill reg=<0x22>; 21784c8294dSjmcneill gpio-controller; 21884c8294dSjmcneill #gpio-cells = <2>; 21984c8294dSjmcneill 22084c8294dSjmcneill sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>, 22184c8294dSjmcneill <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>; 22284c8294dSjmcneill led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>, 22384c8294dSjmcneill <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>; 22484c8294dSjmcneill 22584c8294dSjmcneill gpio-line-names = 22684c8294dSjmcneill "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4", 22784c8294dSjmcneill "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", 22884c8294dSjmcneill "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", 22984c8294dSjmcneill "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; 230*9ed2a30eSjmcneill reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 23184c8294dSjmcneill }; 23284c8294dSjmcneill 23384c8294dSjmcneill u59: pca9575@23 { 23484c8294dSjmcneill compatible = "nxp,pca9575"; 23584c8294dSjmcneill reg=<0x23>; 23684c8294dSjmcneill gpio-controller; 23784c8294dSjmcneill #gpio-cells = <2>; 23884c8294dSjmcneill gpio-line-names = 23984c8294dSjmcneill "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12", 24084c8294dSjmcneill "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", 24184c8294dSjmcneill "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", 24284c8294dSjmcneill "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; 243*9ed2a30eSjmcneill reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 24484c8294dSjmcneill }; 24584c8294dSjmcneill 24684c8294dSjmcneill tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; 24784c8294dSjmcneill tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; }; 24884c8294dSjmcneill tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; }; 24984c8294dSjmcneill tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; }; 25084c8294dSjmcneill 25184c8294dSjmcneill /* EEPROM bank and serial number are treated as separate devices */ 25284c8294dSjmcneill at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; }; 25384c8294dSjmcneill at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; }; 25484c8294dSjmcneill }; 25584c8294dSjmcneill }; 25684c8294dSjmcneill}; 25784c8294dSjmcneill 25884c8294dSjmcneill&i2c2 { 25984c8294dSjmcneill pca9548@71 { 26084c8294dSjmcneill compatible = "nxp,pca9548"; 26184c8294dSjmcneill reg = <0x71>; 26284c8294dSjmcneill #address-cells = <1>; 26384c8294dSjmcneill #size-cells = <0>; 26484c8294dSjmcneill 26584c8294dSjmcneill i2c@6 { 26684c8294dSjmcneill /* Backplane */ 26784c8294dSjmcneill #address-cells = <1>; 26884c8294dSjmcneill #size-cells = <0>; 26984c8294dSjmcneill reg = <6>; 27084c8294dSjmcneill multi-master; 27184c8294dSjmcneill 27284c8294dSjmcneill /* All backplanes should have this -- it's how we know they're there. */ 27384c8294dSjmcneill at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; }; 27484c8294dSjmcneill at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; }; 27584c8294dSjmcneill 27684c8294dSjmcneill /* 16 slot backplane */ 27784c8294dSjmcneill tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; }; 27884c8294dSjmcneill tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; }; 27984c8294dSjmcneill ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; }; 28084c8294dSjmcneill amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; }; 28184c8294dSjmcneill 28284c8294dSjmcneill /* Single slot backplane */ 28384c8294dSjmcneill }; 28484c8294dSjmcneill }; 28584c8294dSjmcneill}; 28684c8294dSjmcneill 28784c8294dSjmcneill&pincntl { 28884c8294dSjmcneill mmc2_pins: pinmux_mmc2_pins { 28984c8294dSjmcneill pinctrl-single,pins = < 29084c8294dSjmcneill DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ 29184c8294dSjmcneill DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ 29284c8294dSjmcneill DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ 29384c8294dSjmcneill DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ 29484c8294dSjmcneill DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ 29584c8294dSjmcneill DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ 29684c8294dSjmcneill DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */ 29784c8294dSjmcneill DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */ 29884c8294dSjmcneill DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */ 29984c8294dSjmcneill >; 30084c8294dSjmcneill }; 30184c8294dSjmcneill 30284c8294dSjmcneill usb0_pins: pinmux_usb0_pins { 30384c8294dSjmcneill pinctrl-single,pins = < 30484c8294dSjmcneill DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ 30584c8294dSjmcneill >; 30684c8294dSjmcneill }; 30784c8294dSjmcneill 30884c8294dSjmcneill usb1_pins: pinmux_usb1_pins { 30984c8294dSjmcneill pinctrl-single,pins = < 31084c8294dSjmcneill DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ 31184c8294dSjmcneill >; 31284c8294dSjmcneill }; 31384c8294dSjmcneill 31484c8294dSjmcneill gpio1_pins: pinmux_gpio1_pins { 31584c8294dSjmcneill pinctrl-single,pins = < 31684c8294dSjmcneill DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ 31784c8294dSjmcneill DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ 31884c8294dSjmcneill DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */ 31984c8294dSjmcneill 32084c8294dSjmcneill DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */ 32184c8294dSjmcneill DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */ 32284c8294dSjmcneill DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */ 32384c8294dSjmcneill DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */ 32484c8294dSjmcneill DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */ 32584c8294dSjmcneill 32684c8294dSjmcneill DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */ 32784c8294dSjmcneill DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */ 32884c8294dSjmcneill DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */ 32984c8294dSjmcneill DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */ 33084c8294dSjmcneill DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */ 33184c8294dSjmcneill 33284c8294dSjmcneill DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */ 33384c8294dSjmcneill DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */ 33484c8294dSjmcneill DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */ 33584c8294dSjmcneill DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */ 33684c8294dSjmcneill >; 33784c8294dSjmcneill }; 33884c8294dSjmcneill 33984c8294dSjmcneill gpio2_pins: pinmux_gpio2_pins { 34084c8294dSjmcneill pinctrl-single,pins = < 34184c8294dSjmcneill DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ 34284c8294dSjmcneill DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ 34384c8294dSjmcneill DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */ 34484c8294dSjmcneill DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */ 34584c8294dSjmcneill 34684c8294dSjmcneill //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */ 34784c8294dSjmcneill //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */ 34884c8294dSjmcneill DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */ 34984c8294dSjmcneill >; 35084c8294dSjmcneill }; 35184c8294dSjmcneill 35284c8294dSjmcneill gpio4_pins: pinmux_gpio4_pins { 35384c8294dSjmcneill pinctrl-single,pins = < 35484c8294dSjmcneill /* The PLL doesn't react well to the SPI controller reset, so 35584c8294dSjmcneill * we force the CS lines to pull up as GPIOs until we're ready. 35684c8294dSjmcneill * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3 35784c8294dSjmcneill */ 35884c8294dSjmcneill DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */ 35984c8294dSjmcneill DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */ 36084c8294dSjmcneill DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */ 36184c8294dSjmcneill DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */ 36284c8294dSjmcneill DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */ 36384c8294dSjmcneill DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */ 36484c8294dSjmcneill >; 36584c8294dSjmcneill }; 36684c8294dSjmcneill 36784c8294dSjmcneill spi2_pins: pinmux_spi2_pins { 36884c8294dSjmcneill pinctrl-single,pins = < 36984c8294dSjmcneill DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ 37084c8294dSjmcneill DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ 37184c8294dSjmcneill >; 37284c8294dSjmcneill }; 37384c8294dSjmcneill 37484c8294dSjmcneill spi4_pins: pinmux_spi4_pins { 37584c8294dSjmcneill pinctrl-single,pins = < 37684c8294dSjmcneill DM814X_IOPAD(0x0a7c, 0x20) 37784c8294dSjmcneill DM814X_IOPAD(0x0b74, 0x20) 37884c8294dSjmcneill DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20) 37984c8294dSjmcneill DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20) 38084c8294dSjmcneill DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20) 38184c8294dSjmcneill >; 38284c8294dSjmcneill }; 38384c8294dSjmcneill}; 38484c8294dSjmcneill 38584c8294dSjmcneill&gpio1 { 38684c8294dSjmcneill pinctrl-names = "default"; 38784c8294dSjmcneill pinctrl-0 = <&gpio1_pins>; 38884c8294dSjmcneill gpio-line-names = 38984c8294dSjmcneill "", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */ 39084c8294dSjmcneill "", "", "", "", /* 4-7 */ 39184c8294dSjmcneill "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */ 39284c8294dSjmcneill "", "", "", "FMCA_TRST", /* 12-15 */ 39384c8294dSjmcneill "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */ 39484c8294dSjmcneill "FMCB_TRST", "", "", "", /* 20-23 */ 39584c8294dSjmcneill "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */ 39684c8294dSjmcneill "", "", "", ""; /* 28-31 */ 39784c8294dSjmcneill}; 39884c8294dSjmcneill 39984c8294dSjmcneill&gpio2 { 40084c8294dSjmcneill pinctrl-names = "default"; 40184c8294dSjmcneill pinctrl-0 = <&gpio2_pins>; 40284c8294dSjmcneill gpio-line-names = 40384c8294dSjmcneill "PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */ 40484c8294dSjmcneill "", "", "", "PHYB_IRQ_N", /* 4-7 */ 40584c8294dSjmcneill "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */ 40684c8294dSjmcneill}; 40784c8294dSjmcneill 40884c8294dSjmcneill&gpio3 { 40984c8294dSjmcneill pinctrl-names = "default"; 41084c8294dSjmcneill /*pinctrl-0 = <&gpio3_pins>;*/ 41184c8294dSjmcneill gpio-line-names = 41284c8294dSjmcneill "", "", "ARMClkSel0", "", /* 0-3 */ 41384c8294dSjmcneill "EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */ 41484c8294dSjmcneill}; 41584c8294dSjmcneill 41684c8294dSjmcneill&gpio4 { 41784c8294dSjmcneill pinctrl-names = "default"; 41884c8294dSjmcneill pinctrl-0 = <&gpio4_pins>; 41984c8294dSjmcneill gpio-line-names = 42084c8294dSjmcneill "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3", 42184c8294dSjmcneill "BP_ARM_GPIO4", "BP_ARM_GPIO5"; 42284c8294dSjmcneill}; 42384c8294dSjmcneill 42484c8294dSjmcneill&usb0 { 42584c8294dSjmcneill pinctrl-names = "default"; 42684c8294dSjmcneill pinctrl-0 = <&usb0_pins>; 42784c8294dSjmcneill dr_mode = "host"; 42884c8294dSjmcneill}; 42984c8294dSjmcneill 43084c8294dSjmcneill&usb1 { 43184c8294dSjmcneill pinctrl-names = "default"; 43284c8294dSjmcneill pinctrl-0 = <&usb1_pins>; 43384c8294dSjmcneill dr_mode = "host"; 43484c8294dSjmcneill}; 43584c8294dSjmcneill 43684c8294dSjmcneill&mcspi1 { 43784c8294dSjmcneill s25fl256@0 { 43884c8294dSjmcneill #address-cells = <1>; 43984c8294dSjmcneill #size-cells = <1>; 44084c8294dSjmcneill compatible = "jedec,spi-nor"; 44184c8294dSjmcneill reg = <0>; 44284c8294dSjmcneill spi-max-frequency = <40000000>; 44384c8294dSjmcneill 44484c8294dSjmcneill fsbl@0 { 44584c8294dSjmcneill /* 256 kB */ 44684c8294dSjmcneill label = "U-Boot-min"; 44784c8294dSjmcneill reg = <0 0x40000>; 44884c8294dSjmcneill }; 44984c8294dSjmcneill ssbl@1 { 45084c8294dSjmcneill /* 512 kB */ 45184c8294dSjmcneill label = "U-Boot"; 45284c8294dSjmcneill reg = <0x40000 0x80000>; 45384c8294dSjmcneill }; 45484c8294dSjmcneill bootenv@2 { 45584c8294dSjmcneill /* 256 kB */ 45684c8294dSjmcneill label = "U-Boot Env"; 45784c8294dSjmcneill reg = <0xc0000 0x40000>; 45884c8294dSjmcneill }; 45984c8294dSjmcneill kernel@3 { 46084c8294dSjmcneill /* 4 MB */ 46184c8294dSjmcneill label = "Kernel"; 46284c8294dSjmcneill reg = <0x100000 0x400000>; 46384c8294dSjmcneill }; 46484c8294dSjmcneill ipmi@4 { 46584c8294dSjmcneill label = "IPMI FRU"; 46684c8294dSjmcneill reg = <0x500000 0x40000>; 46784c8294dSjmcneill }; 46884c8294dSjmcneill fs@5 { 46984c8294dSjmcneill label = "File System"; 47084c8294dSjmcneill reg = <0x540000 0x1ac0000>; 47184c8294dSjmcneill }; 47284c8294dSjmcneill }; 47384c8294dSjmcneill}; 47484c8294dSjmcneill 47584c8294dSjmcneill&mcspi3 { 47684c8294dSjmcneill /* DMA event numbers stolen from MCASP */ 47784c8294dSjmcneill dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17 47884c8294dSjmcneill &edma_xbar 10 0 18 &edma_xbar 11 0 19>; 47984c8294dSjmcneill dma-names = "tx0", "rx0", "tx1", "rx1"; 48084c8294dSjmcneill}; 48184c8294dSjmcneill 48284c8294dSjmcneill&mcspi4 { 48384c8294dSjmcneill pinctrl-names = "default"; 48484c8294dSjmcneill pinctrl-0 = <&spi4_pins>; 48584c8294dSjmcneill 48684c8294dSjmcneill /* DMA event numbers stolen from MCASP, MCBSP */ 48784c8294dSjmcneill dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>; 48884c8294dSjmcneill dma-names = "tx0", "rx0"; 48984c8294dSjmcneill}; 490