1// SPDX-License-Identifier: GPL-2.0 2#include "skeleton.dtsi" 3 4/ { 5 model = "Aspeed BMC"; 6 compatible = "aspeed,ast2400"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&vic>; 10 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c6 = &i2c6; 19 i2c7 = &i2c7; 20 i2c8 = &i2c8; 21 i2c9 = &i2c9; 22 i2c10 = &i2c10; 23 i2c11 = &i2c11; 24 i2c12 = &i2c12; 25 i2c13 = &i2c13; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 serial3 = &uart4; 30 serial4 = &uart5; 31 serial5 = &vuart; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,arm926ej-s"; 40 device_type = "cpu"; 41 reg = <0>; 42 }; 43 }; 44 45 ahb { 46 compatible = "simple-bus"; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges; 50 51 fmc: flash-controller@1e620000 { 52 reg = < 0x1e620000 0x94 53 0x20000000 0x10000000 >; 54 #address-cells = <1>; 55 #size-cells = <0>; 56 compatible = "aspeed,ast2400-fmc"; 57 status = "disabled"; 58 interrupts = <19>; 59 flash@0 { 60 reg = < 0 >; 61 compatible = "jedec,spi-nor"; 62 status = "disabled"; 63 }; 64 }; 65 66 spi: flash-controller@1e630000 { 67 reg = < 0x1e630000 0x18 68 0x30000000 0x10000000 >; 69 #address-cells = <1>; 70 #size-cells = <0>; 71 compatible = "aspeed,ast2400-spi"; 72 status = "disabled"; 73 flash@0 { 74 reg = < 0 >; 75 compatible = "jedec,spi-nor"; 76 status = "disabled"; 77 }; 78 }; 79 80 vic: interrupt-controller@1e6c0080 { 81 compatible = "aspeed,ast2400-vic"; 82 interrupt-controller; 83 #interrupt-cells = <1>; 84 valid-sources = <0xffffffff 0x0007ffff>; 85 reg = <0x1e6c0080 0x80>; 86 }; 87 88 mac0: ethernet@1e660000 { 89 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 90 reg = <0x1e660000 0x180>; 91 interrupts = <2>; 92 status = "disabled"; 93 }; 94 95 mac1: ethernet@1e680000 { 96 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 97 reg = <0x1e680000 0x180>; 98 interrupts = <3>; 99 status = "disabled"; 100 }; 101 102 apb { 103 compatible = "simple-bus"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges; 107 108 syscon: syscon@1e6e2000 { 109 compatible = "aspeed,g4-scu", "syscon", "simple-mfd"; 110 reg = <0x1e6e2000 0x1a8>; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 114 clk_clkin: clk_clkin { 115 #clock-cells = <0>; 116 compatible = "fixed-clock"; 117 clock-frequency = <48000000>; 118 }; 119 120 clk_hpll: clk_hpll@70 { 121 #clock-cells = <0>; 122 compatible = "aspeed,g4-hpll-clock", "fixed-clock"; 123 reg = <0x70>; 124 clocks = <&clk_clkin>; 125 clock-frequency = <384000000>; 126 }; 127 128 clk_ahb: clk_ahb@70 { 129 #clock-cells = <0>; 130 compatible = "aspeed,g4-ahb-clock", "fixed-clock"; 131 reg = <0x70>; 132 clocks = <&clk_hpll>; 133 clock-frequency = <192000000>; 134 }; 135 136 clk_apb: clk_apb@8 { 137 #clock-cells = <0>; 138 compatible = "aspeed,g4-apb-clock", "fixed-clock"; 139 reg = <0x08>; 140 clocks = <&clk_hpll>; 141 clock-frequency = <48000000>; 142 }; 143 144 clk_uart: clk_uart@2c{ 145 #clock-cells = <0>; 146 compatible = "aspeed,g4-uart-clock", "fixed-clock"; 147 reg = <0x2c>; 148 clock-frequency = <24000000>; 149 }; 150 151 pinctrl: pinctrl { 152 compatible = "aspeed,g4-pinctrl"; 153 }; 154 }; 155 156 adc: adc@1e6e9000 { 157 compatible = "aspeed,ast2400-adc"; 158 reg = <0x1e6e9000 0xb0>; 159 clocks = <&clk_apb>; 160 #io-channel-cells = <1>; 161 status = "disabled"; 162 }; 163 164 sram@1e720000 { 165 compatible = "mmio-sram"; 166 reg = <0x1e720000 0x8000>; // 32K 167 }; 168 169 gpio: gpio@1e780000 { 170 #gpio-cells = <2>; 171 gpio-controller; 172 compatible = "aspeed,ast2400-gpio"; 173 reg = <0x1e780000 0x1000>; 174 interrupts = <20>; 175 gpio-ranges = <&pinctrl 0 0 220>; 176 interrupt-controller; 177 }; 178 179 timer: timer@1e782000 { 180 /* This timer is a Faraday FTTMR010 derivative */ 181 compatible = "aspeed,ast2400-timer"; 182 reg = <0x1e782000 0x90>; 183 interrupts = <16 17 18 35 36 37 38 39>; 184 clocks = <&clk_apb>; 185 clock-names = "PCLK"; 186 }; 187 188 uart1: serial@1e783000 { 189 compatible = "ns16550a"; 190 reg = <0x1e783000 0x20>; 191 reg-shift = <2>; 192 interrupts = <9>; 193 clocks = <&clk_uart>; 194 no-loopback-test; 195 status = "disabled"; 196 }; 197 198 uart5: serial@1e784000 { 199 compatible = "ns16550a"; 200 reg = <0x1e784000 0x20>; 201 reg-shift = <2>; 202 interrupts = <10>; 203 clocks = <&clk_uart>; 204 no-loopback-test; 205 status = "disabled"; 206 }; 207 208 wdt1: watchdog@1e785000 { 209 compatible = "aspeed,ast2400-wdt"; 210 reg = <0x1e785000 0x1c>; 211 }; 212 213 wdt2: watchdog@1e785020 { 214 compatible = "aspeed,ast2400-wdt"; 215 reg = <0x1e785020 0x1c>; 216 }; 217 218 vuart: serial@1e787000 { 219 compatible = "aspeed,ast2400-vuart"; 220 reg = <0x1e787000 0x40>; 221 reg-shift = <2>; 222 interrupts = <10>; 223 clocks = <&clk_uart>; 224 no-loopback-test; 225 status = "disabled"; 226 }; 227 228 uart2: serial@1e78d000 { 229 compatible = "ns16550a"; 230 reg = <0x1e78d000 0x20>; 231 reg-shift = <2>; 232 interrupts = <32>; 233 clocks = <&clk_uart>; 234 no-loopback-test; 235 status = "disabled"; 236 }; 237 238 uart3: serial@1e78e000 { 239 compatible = "ns16550a"; 240 reg = <0x1e78e000 0x20>; 241 reg-shift = <2>; 242 interrupts = <33>; 243 clocks = <&clk_uart>; 244 no-loopback-test; 245 status = "disabled"; 246 }; 247 248 uart4: serial@1e78f000 { 249 compatible = "ns16550a"; 250 reg = <0x1e78f000 0x20>; 251 reg-shift = <2>; 252 interrupts = <34>; 253 clocks = <&clk_uart>; 254 no-loopback-test; 255 status = "disabled"; 256 }; 257 258 i2c: i2c@1e78a000 { 259 compatible = "simple-bus"; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges = <0 0x1e78a000 0x1000>; 263 }; 264 }; 265 }; 266}; 267 268&i2c { 269 i2c_ic: interrupt-controller@0 { 270 #interrupt-cells = <1>; 271 compatible = "aspeed,ast2400-i2c-ic"; 272 reg = <0x0 0x40>; 273 interrupts = <12>; 274 interrupt-controller; 275 }; 276 277 i2c0: i2c-bus@40 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 #interrupt-cells = <1>; 281 282 reg = <0x40 0x40>; 283 compatible = "aspeed,ast2400-i2c-bus"; 284 clocks = <&clk_apb>; 285 bus-frequency = <100000>; 286 interrupts = <0>; 287 interrupt-parent = <&i2c_ic>; 288 status = "disabled"; 289 /* Does not need pinctrl properties */ 290 }; 291 292 i2c1: i2c-bus@80 { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 #interrupt-cells = <1>; 296 297 reg = <0x80 0x40>; 298 compatible = "aspeed,ast2400-i2c-bus"; 299 clocks = <&clk_apb>; 300 bus-frequency = <100000>; 301 interrupts = <1>; 302 interrupt-parent = <&i2c_ic>; 303 status = "disabled"; 304 /* Does not need pinctrl properties */ 305 }; 306 307 i2c2: i2c-bus@c0 { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 #interrupt-cells = <1>; 311 312 reg = <0xc0 0x40>; 313 compatible = "aspeed,ast2400-i2c-bus"; 314 clocks = <&clk_apb>; 315 bus-frequency = <100000>; 316 interrupts = <2>; 317 interrupt-parent = <&i2c_ic>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_i2c3_default>; 320 status = "disabled"; 321 }; 322 323 i2c3: i2c-bus@100 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 #interrupt-cells = <1>; 327 328 reg = <0x100 0x40>; 329 compatible = "aspeed,ast2400-i2c-bus"; 330 clocks = <&clk_apb>; 331 bus-frequency = <100000>; 332 interrupts = <3>; 333 interrupt-parent = <&i2c_ic>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_i2c4_default>; 336 status = "disabled"; 337 }; 338 339 i2c4: i2c-bus@140 { 340 #address-cells = <1>; 341 #size-cells = <0>; 342 #interrupt-cells = <1>; 343 344 reg = <0x140 0x40>; 345 compatible = "aspeed,ast2400-i2c-bus"; 346 clocks = <&clk_apb>; 347 bus-frequency = <100000>; 348 interrupts = <4>; 349 interrupt-parent = <&i2c_ic>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pinctrl_i2c5_default>; 352 status = "disabled"; 353 }; 354 355 i2c5: i2c-bus@180 { 356 #address-cells = <1>; 357 #size-cells = <0>; 358 #interrupt-cells = <1>; 359 360 reg = <0x180 0x40>; 361 compatible = "aspeed,ast2400-i2c-bus"; 362 clocks = <&clk_apb>; 363 bus-frequency = <100000>; 364 interrupts = <5>; 365 interrupt-parent = <&i2c_ic>; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pinctrl_i2c6_default>; 368 status = "disabled"; 369 }; 370 371 i2c6: i2c-bus@1c0 { 372 #address-cells = <1>; 373 #size-cells = <0>; 374 #interrupt-cells = <1>; 375 376 reg = <0x1c0 0x40>; 377 compatible = "aspeed,ast2400-i2c-bus"; 378 clocks = <&clk_apb>; 379 bus-frequency = <100000>; 380 interrupts = <6>; 381 interrupt-parent = <&i2c_ic>; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&pinctrl_i2c7_default>; 384 status = "disabled"; 385 }; 386 387 i2c7: i2c-bus@300 { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 #interrupt-cells = <1>; 391 392 reg = <0x300 0x40>; 393 compatible = "aspeed,ast2400-i2c-bus"; 394 clocks = <&clk_apb>; 395 bus-frequency = <100000>; 396 interrupts = <7>; 397 interrupt-parent = <&i2c_ic>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&pinctrl_i2c8_default>; 400 status = "disabled"; 401 }; 402 403 i2c8: i2c-bus@340 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 #interrupt-cells = <1>; 407 408 reg = <0x340 0x40>; 409 compatible = "aspeed,ast2400-i2c-bus"; 410 clocks = <&clk_apb>; 411 bus-frequency = <100000>; 412 interrupts = <8>; 413 interrupt-parent = <&i2c_ic>; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&pinctrl_i2c9_default>; 416 status = "disabled"; 417 }; 418 419 i2c9: i2c-bus@380 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 #interrupt-cells = <1>; 423 424 reg = <0x380 0x40>; 425 compatible = "aspeed,ast2400-i2c-bus"; 426 clocks = <&clk_apb>; 427 bus-frequency = <100000>; 428 interrupts = <9>; 429 interrupt-parent = <&i2c_ic>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&pinctrl_i2c10_default>; 432 status = "disabled"; 433 }; 434 435 i2c10: i2c-bus@3c0 { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 #interrupt-cells = <1>; 439 440 reg = <0x3c0 0x40>; 441 compatible = "aspeed,ast2400-i2c-bus"; 442 clocks = <&clk_apb>; 443 bus-frequency = <100000>; 444 interrupts = <10>; 445 interrupt-parent = <&i2c_ic>; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&pinctrl_i2c11_default>; 448 status = "disabled"; 449 }; 450 451 i2c11: i2c-bus@400 { 452 #address-cells = <1>; 453 #size-cells = <0>; 454 #interrupt-cells = <1>; 455 456 reg = <0x400 0x40>; 457 compatible = "aspeed,ast2400-i2c-bus"; 458 clocks = <&clk_apb>; 459 bus-frequency = <100000>; 460 interrupts = <11>; 461 interrupt-parent = <&i2c_ic>; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pinctrl_i2c12_default>; 464 status = "disabled"; 465 }; 466 467 i2c12: i2c-bus@440 { 468 #address-cells = <1>; 469 #size-cells = <0>; 470 #interrupt-cells = <1>; 471 472 reg = <0x440 0x40>; 473 compatible = "aspeed,ast2400-i2c-bus"; 474 clocks = <&clk_apb>; 475 bus-frequency = <100000>; 476 interrupts = <12>; 477 interrupt-parent = <&i2c_ic>; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&pinctrl_i2c13_default>; 480 status = "disabled"; 481 }; 482 483 i2c13: i2c-bus@480 { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 #interrupt-cells = <1>; 487 488 reg = <0x480 0x40>; 489 compatible = "aspeed,ast2400-i2c-bus"; 490 clocks = <&clk_apb>; 491 bus-frequency = <100000>; 492 interrupts = <13>; 493 interrupt-parent = <&i2c_ic>; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pinctrl_i2c14_default>; 496 status = "disabled"; 497 }; 498}; 499 500&pinctrl { 501 pinctrl_acpi_default: acpi_default { 502 function = "ACPI"; 503 groups = "ACPI"; 504 }; 505 506 pinctrl_adc0_default: adc0_default { 507 function = "ADC0"; 508 groups = "ADC0"; 509 }; 510 511 pinctrl_adc1_default: adc1_default { 512 function = "ADC1"; 513 groups = "ADC1"; 514 }; 515 516 pinctrl_adc10_default: adc10_default { 517 function = "ADC10"; 518 groups = "ADC10"; 519 }; 520 521 pinctrl_adc11_default: adc11_default { 522 function = "ADC11"; 523 groups = "ADC11"; 524 }; 525 526 pinctrl_adc12_default: adc12_default { 527 function = "ADC12"; 528 groups = "ADC12"; 529 }; 530 531 pinctrl_adc13_default: adc13_default { 532 function = "ADC13"; 533 groups = "ADC13"; 534 }; 535 536 pinctrl_adc14_default: adc14_default { 537 function = "ADC14"; 538 groups = "ADC14"; 539 }; 540 541 pinctrl_adc15_default: adc15_default { 542 function = "ADC15"; 543 groups = "ADC15"; 544 }; 545 546 pinctrl_adc2_default: adc2_default { 547 function = "ADC2"; 548 groups = "ADC2"; 549 }; 550 551 pinctrl_adc3_default: adc3_default { 552 function = "ADC3"; 553 groups = "ADC3"; 554 }; 555 556 pinctrl_adc4_default: adc4_default { 557 function = "ADC4"; 558 groups = "ADC4"; 559 }; 560 561 pinctrl_adc5_default: adc5_default { 562 function = "ADC5"; 563 groups = "ADC5"; 564 }; 565 566 pinctrl_adc6_default: adc6_default { 567 function = "ADC6"; 568 groups = "ADC6"; 569 }; 570 571 pinctrl_adc7_default: adc7_default { 572 function = "ADC7"; 573 groups = "ADC7"; 574 }; 575 576 pinctrl_adc8_default: adc8_default { 577 function = "ADC8"; 578 groups = "ADC8"; 579 }; 580 581 pinctrl_adc9_default: adc9_default { 582 function = "ADC9"; 583 groups = "ADC9"; 584 }; 585 586 pinctrl_bmcint_default: bmcint_default { 587 function = "BMCINT"; 588 groups = "BMCINT"; 589 }; 590 591 pinctrl_ddcclk_default: ddcclk_default { 592 function = "DDCCLK"; 593 groups = "DDCCLK"; 594 }; 595 596 pinctrl_ddcdat_default: ddcdat_default { 597 function = "DDCDAT"; 598 groups = "DDCDAT"; 599 }; 600 601 pinctrl_extrst_default: extrst_default { 602 function = "EXTRST"; 603 groups = "EXTRST"; 604 }; 605 606 pinctrl_flack_default: flack_default { 607 function = "FLACK"; 608 groups = "FLACK"; 609 }; 610 611 pinctrl_flbusy_default: flbusy_default { 612 function = "FLBUSY"; 613 groups = "FLBUSY"; 614 }; 615 616 pinctrl_flwp_default: flwp_default { 617 function = "FLWP"; 618 groups = "FLWP"; 619 }; 620 621 pinctrl_gpid_default: gpid_default { 622 function = "GPID"; 623 groups = "GPID"; 624 }; 625 626 pinctrl_gpid0_default: gpid0_default { 627 function = "GPID0"; 628 groups = "GPID0"; 629 }; 630 631 pinctrl_gpid2_default: gpid2_default { 632 function = "GPID2"; 633 groups = "GPID2"; 634 }; 635 636 pinctrl_gpid4_default: gpid4_default { 637 function = "GPID4"; 638 groups = "GPID4"; 639 }; 640 641 pinctrl_gpid6_default: gpid6_default { 642 function = "GPID6"; 643 groups = "GPID6"; 644 }; 645 646 pinctrl_gpie0_default: gpie0_default { 647 function = "GPIE0"; 648 groups = "GPIE0"; 649 }; 650 651 pinctrl_gpie2_default: gpie2_default { 652 function = "GPIE2"; 653 groups = "GPIE2"; 654 }; 655 656 pinctrl_gpie4_default: gpie4_default { 657 function = "GPIE4"; 658 groups = "GPIE4"; 659 }; 660 661 pinctrl_gpie6_default: gpie6_default { 662 function = "GPIE6"; 663 groups = "GPIE6"; 664 }; 665 666 pinctrl_i2c10_default: i2c10_default { 667 function = "I2C10"; 668 groups = "I2C10"; 669 }; 670 671 pinctrl_i2c11_default: i2c11_default { 672 function = "I2C11"; 673 groups = "I2C11"; 674 }; 675 676 pinctrl_i2c12_default: i2c12_default { 677 function = "I2C12"; 678 groups = "I2C12"; 679 }; 680 681 pinctrl_i2c13_default: i2c13_default { 682 function = "I2C13"; 683 groups = "I2C13"; 684 }; 685 686 pinctrl_i2c14_default: i2c14_default { 687 function = "I2C14"; 688 groups = "I2C14"; 689 }; 690 691 pinctrl_i2c3_default: i2c3_default { 692 function = "I2C3"; 693 groups = "I2C3"; 694 }; 695 696 pinctrl_i2c4_default: i2c4_default { 697 function = "I2C4"; 698 groups = "I2C4"; 699 }; 700 701 pinctrl_i2c5_default: i2c5_default { 702 function = "I2C5"; 703 groups = "I2C5"; 704 }; 705 706 pinctrl_i2c6_default: i2c6_default { 707 function = "I2C6"; 708 groups = "I2C6"; 709 }; 710 711 pinctrl_i2c7_default: i2c7_default { 712 function = "I2C7"; 713 groups = "I2C7"; 714 }; 715 716 pinctrl_i2c8_default: i2c8_default { 717 function = "I2C8"; 718 groups = "I2C8"; 719 }; 720 721 pinctrl_i2c9_default: i2c9_default { 722 function = "I2C9"; 723 groups = "I2C9"; 724 }; 725 726 pinctrl_lpcpd_default: lpcpd_default { 727 function = "LPCPD"; 728 groups = "LPCPD"; 729 }; 730 731 pinctrl_lpcpme_default: lpcpme_default { 732 function = "LPCPME"; 733 groups = "LPCPME"; 734 }; 735 736 pinctrl_lpcrst_default: lpcrst_default { 737 function = "LPCRST"; 738 groups = "LPCRST"; 739 }; 740 741 pinctrl_lpcsmi_default: lpcsmi_default { 742 function = "LPCSMI"; 743 groups = "LPCSMI"; 744 }; 745 746 pinctrl_mac1link_default: mac1link_default { 747 function = "MAC1LINK"; 748 groups = "MAC1LINK"; 749 }; 750 751 pinctrl_mac2link_default: mac2link_default { 752 function = "MAC2LINK"; 753 groups = "MAC2LINK"; 754 }; 755 756 pinctrl_mdio1_default: mdio1_default { 757 function = "MDIO1"; 758 groups = "MDIO1"; 759 }; 760 761 pinctrl_mdio2_default: mdio2_default { 762 function = "MDIO2"; 763 groups = "MDIO2"; 764 }; 765 766 pinctrl_ncts1_default: ncts1_default { 767 function = "NCTS1"; 768 groups = "NCTS1"; 769 }; 770 771 pinctrl_ncts2_default: ncts2_default { 772 function = "NCTS2"; 773 groups = "NCTS2"; 774 }; 775 776 pinctrl_ncts3_default: ncts3_default { 777 function = "NCTS3"; 778 groups = "NCTS3"; 779 }; 780 781 pinctrl_ncts4_default: ncts4_default { 782 function = "NCTS4"; 783 groups = "NCTS4"; 784 }; 785 786 pinctrl_ndcd1_default: ndcd1_default { 787 function = "NDCD1"; 788 groups = "NDCD1"; 789 }; 790 791 pinctrl_ndcd2_default: ndcd2_default { 792 function = "NDCD2"; 793 groups = "NDCD2"; 794 }; 795 796 pinctrl_ndcd3_default: ndcd3_default { 797 function = "NDCD3"; 798 groups = "NDCD3"; 799 }; 800 801 pinctrl_ndcd4_default: ndcd4_default { 802 function = "NDCD4"; 803 groups = "NDCD4"; 804 }; 805 806 pinctrl_ndsr1_default: ndsr1_default { 807 function = "NDSR1"; 808 groups = "NDSR1"; 809 }; 810 811 pinctrl_ndsr2_default: ndsr2_default { 812 function = "NDSR2"; 813 groups = "NDSR2"; 814 }; 815 816 pinctrl_ndsr3_default: ndsr3_default { 817 function = "NDSR3"; 818 groups = "NDSR3"; 819 }; 820 821 pinctrl_ndsr4_default: ndsr4_default { 822 function = "NDSR4"; 823 groups = "NDSR4"; 824 }; 825 826 pinctrl_ndtr1_default: ndtr1_default { 827 function = "NDTR1"; 828 groups = "NDTR1"; 829 }; 830 831 pinctrl_ndtr2_default: ndtr2_default { 832 function = "NDTR2"; 833 groups = "NDTR2"; 834 }; 835 836 pinctrl_ndtr3_default: ndtr3_default { 837 function = "NDTR3"; 838 groups = "NDTR3"; 839 }; 840 841 pinctrl_ndtr4_default: ndtr4_default { 842 function = "NDTR4"; 843 groups = "NDTR4"; 844 }; 845 846 pinctrl_ndts4_default: ndts4_default { 847 function = "NDTS4"; 848 groups = "NDTS4"; 849 }; 850 851 pinctrl_nri1_default: nri1_default { 852 function = "NRI1"; 853 groups = "NRI1"; 854 }; 855 856 pinctrl_nri2_default: nri2_default { 857 function = "NRI2"; 858 groups = "NRI2"; 859 }; 860 861 pinctrl_nri3_default: nri3_default { 862 function = "NRI3"; 863 groups = "NRI3"; 864 }; 865 866 pinctrl_nri4_default: nri4_default { 867 function = "NRI4"; 868 groups = "NRI4"; 869 }; 870 871 pinctrl_nrts1_default: nrts1_default { 872 function = "NRTS1"; 873 groups = "NRTS1"; 874 }; 875 876 pinctrl_nrts2_default: nrts2_default { 877 function = "NRTS2"; 878 groups = "NRTS2"; 879 }; 880 881 pinctrl_nrts3_default: nrts3_default { 882 function = "NRTS3"; 883 groups = "NRTS3"; 884 }; 885 886 pinctrl_oscclk_default: oscclk_default { 887 function = "OSCCLK"; 888 groups = "OSCCLK"; 889 }; 890 891 pinctrl_pwm0_default: pwm0_default { 892 function = "PWM0"; 893 groups = "PWM0"; 894 }; 895 896 pinctrl_pwm1_default: pwm1_default { 897 function = "PWM1"; 898 groups = "PWM1"; 899 }; 900 901 pinctrl_pwm2_default: pwm2_default { 902 function = "PWM2"; 903 groups = "PWM2"; 904 }; 905 906 pinctrl_pwm3_default: pwm3_default { 907 function = "PWM3"; 908 groups = "PWM3"; 909 }; 910 911 pinctrl_pwm4_default: pwm4_default { 912 function = "PWM4"; 913 groups = "PWM4"; 914 }; 915 916 pinctrl_pwm5_default: pwm5_default { 917 function = "PWM5"; 918 groups = "PWM5"; 919 }; 920 921 pinctrl_pwm6_default: pwm6_default { 922 function = "PWM6"; 923 groups = "PWM6"; 924 }; 925 926 pinctrl_pwm7_default: pwm7_default { 927 function = "PWM7"; 928 groups = "PWM7"; 929 }; 930 931 pinctrl_rgmii1_default: rgmii1_default { 932 function = "RGMII1"; 933 groups = "RGMII1"; 934 }; 935 936 pinctrl_rgmii2_default: rgmii2_default { 937 function = "RGMII2"; 938 groups = "RGMII2"; 939 }; 940 941 pinctrl_rmii1_default: rmii1_default { 942 function = "RMII1"; 943 groups = "RMII1"; 944 }; 945 946 pinctrl_rmii2_default: rmii2_default { 947 function = "RMII2"; 948 groups = "RMII2"; 949 }; 950 951 pinctrl_rom16_default: rom16_default { 952 function = "ROM16"; 953 groups = "ROM16"; 954 }; 955 956 pinctrl_rom8_default: rom8_default { 957 function = "ROM8"; 958 groups = "ROM8"; 959 }; 960 961 pinctrl_romcs1_default: romcs1_default { 962 function = "ROMCS1"; 963 groups = "ROMCS1"; 964 }; 965 966 pinctrl_romcs2_default: romcs2_default { 967 function = "ROMCS2"; 968 groups = "ROMCS2"; 969 }; 970 971 pinctrl_romcs3_default: romcs3_default { 972 function = "ROMCS3"; 973 groups = "ROMCS3"; 974 }; 975 976 pinctrl_romcs4_default: romcs4_default { 977 function = "ROMCS4"; 978 groups = "ROMCS4"; 979 }; 980 981 pinctrl_rxd1_default: rxd1_default { 982 function = "RXD1"; 983 groups = "RXD1"; 984 }; 985 986 pinctrl_rxd2_default: rxd2_default { 987 function = "RXD2"; 988 groups = "RXD2"; 989 }; 990 991 pinctrl_rxd3_default: rxd3_default { 992 function = "RXD3"; 993 groups = "RXD3"; 994 }; 995 996 pinctrl_rxd4_default: rxd4_default { 997 function = "RXD4"; 998 groups = "RXD4"; 999 }; 1000 1001 pinctrl_salt1_default: salt1_default { 1002 function = "SALT1"; 1003 groups = "SALT1"; 1004 }; 1005 1006 pinctrl_salt2_default: salt2_default { 1007 function = "SALT2"; 1008 groups = "SALT2"; 1009 }; 1010 1011 pinctrl_salt3_default: salt3_default { 1012 function = "SALT3"; 1013 groups = "SALT3"; 1014 }; 1015 1016 pinctrl_salt4_default: salt4_default { 1017 function = "SALT4"; 1018 groups = "SALT4"; 1019 }; 1020 1021 pinctrl_sd1_default: sd1_default { 1022 function = "SD1"; 1023 groups = "SD1"; 1024 }; 1025 1026 pinctrl_sd2_default: sd2_default { 1027 function = "SD2"; 1028 groups = "SD2"; 1029 }; 1030 1031 pinctrl_sgpmck_default: sgpmck_default { 1032 function = "SGPMCK"; 1033 groups = "SGPMCK"; 1034 }; 1035 1036 pinctrl_sgpmi_default: sgpmi_default { 1037 function = "SGPMI"; 1038 groups = "SGPMI"; 1039 }; 1040 1041 pinctrl_sgpmld_default: sgpmld_default { 1042 function = "SGPMLD"; 1043 groups = "SGPMLD"; 1044 }; 1045 1046 pinctrl_sgpmo_default: sgpmo_default { 1047 function = "SGPMO"; 1048 groups = "SGPMO"; 1049 }; 1050 1051 pinctrl_sgpsck_default: sgpsck_default { 1052 function = "SGPSCK"; 1053 groups = "SGPSCK"; 1054 }; 1055 1056 pinctrl_sgpsi0_default: sgpsi0_default { 1057 function = "SGPSI0"; 1058 groups = "SGPSI0"; 1059 }; 1060 1061 pinctrl_sgpsi1_default: sgpsi1_default { 1062 function = "SGPSI1"; 1063 groups = "SGPSI1"; 1064 }; 1065 1066 pinctrl_sgpsld_default: sgpsld_default { 1067 function = "SGPSLD"; 1068 groups = "SGPSLD"; 1069 }; 1070 1071 pinctrl_sioonctrl_default: sioonctrl_default { 1072 function = "SIOONCTRL"; 1073 groups = "SIOONCTRL"; 1074 }; 1075 1076 pinctrl_siopbi_default: siopbi_default { 1077 function = "SIOPBI"; 1078 groups = "SIOPBI"; 1079 }; 1080 1081 pinctrl_siopbo_default: siopbo_default { 1082 function = "SIOPBO"; 1083 groups = "SIOPBO"; 1084 }; 1085 1086 pinctrl_siopwreq_default: siopwreq_default { 1087 function = "SIOPWREQ"; 1088 groups = "SIOPWREQ"; 1089 }; 1090 1091 pinctrl_siopwrgd_default: siopwrgd_default { 1092 function = "SIOPWRGD"; 1093 groups = "SIOPWRGD"; 1094 }; 1095 1096 pinctrl_sios3_default: sios3_default { 1097 function = "SIOS3"; 1098 groups = "SIOS3"; 1099 }; 1100 1101 pinctrl_sios5_default: sios5_default { 1102 function = "SIOS5"; 1103 groups = "SIOS5"; 1104 }; 1105 1106 pinctrl_siosci_default: siosci_default { 1107 function = "SIOSCI"; 1108 groups = "SIOSCI"; 1109 }; 1110 1111 pinctrl_spi1_default: spi1_default { 1112 function = "SPI1"; 1113 groups = "SPI1"; 1114 }; 1115 1116 pinctrl_spi1debug_default: spi1debug_default { 1117 function = "SPI1DEBUG"; 1118 groups = "SPI1DEBUG"; 1119 }; 1120 1121 pinctrl_spi1passthru_default: spi1passthru_default { 1122 function = "SPI1PASSTHRU"; 1123 groups = "SPI1PASSTHRU"; 1124 }; 1125 1126 pinctrl_spics1_default: spics1_default { 1127 function = "SPICS1"; 1128 groups = "SPICS1"; 1129 }; 1130 1131 pinctrl_timer3_default: timer3_default { 1132 function = "TIMER3"; 1133 groups = "TIMER3"; 1134 }; 1135 1136 pinctrl_timer4_default: timer4_default { 1137 function = "TIMER4"; 1138 groups = "TIMER4"; 1139 }; 1140 1141 pinctrl_timer5_default: timer5_default { 1142 function = "TIMER5"; 1143 groups = "TIMER5"; 1144 }; 1145 1146 pinctrl_timer6_default: timer6_default { 1147 function = "TIMER6"; 1148 groups = "TIMER6"; 1149 }; 1150 1151 pinctrl_timer7_default: timer7_default { 1152 function = "TIMER7"; 1153 groups = "TIMER7"; 1154 }; 1155 1156 pinctrl_timer8_default: timer8_default { 1157 function = "TIMER8"; 1158 groups = "TIMER8"; 1159 }; 1160 1161 pinctrl_txd1_default: txd1_default { 1162 function = "TXD1"; 1163 groups = "TXD1"; 1164 }; 1165 1166 pinctrl_txd2_default: txd2_default { 1167 function = "TXD2"; 1168 groups = "TXD2"; 1169 }; 1170 1171 pinctrl_txd3_default: txd3_default { 1172 function = "TXD3"; 1173 groups = "TXD3"; 1174 }; 1175 1176 pinctrl_txd4_default: txd4_default { 1177 function = "TXD4"; 1178 groups = "TXD4"; 1179 }; 1180 1181 pinctrl_uart6_default: uart6_default { 1182 function = "UART6"; 1183 groups = "UART6"; 1184 }; 1185 1186 pinctrl_usbcki_default: usbcki_default { 1187 function = "USBCKI"; 1188 groups = "USBCKI"; 1189 }; 1190 1191 pinctrl_vgabios_rom_default: vgabios_rom_default { 1192 function = "VGABIOS_ROM"; 1193 groups = "VGABIOS_ROM"; 1194 }; 1195 1196 pinctrl_vgahs_default: vgahs_default { 1197 function = "VGAHS"; 1198 groups = "VGAHS"; 1199 }; 1200 1201 pinctrl_vgavs_default: vgavs_default { 1202 function = "VGAVS"; 1203 groups = "VGAVS"; 1204 }; 1205 1206 pinctrl_vpi18_default: vpi18_default { 1207 function = "VPI18"; 1208 groups = "VPI18"; 1209 }; 1210 1211 pinctrl_vpi24_default: vpi24_default { 1212 function = "VPI24"; 1213 groups = "VPI24"; 1214 }; 1215 1216 pinctrl_vpi30_default: vpi30_default { 1217 function = "VPI30"; 1218 groups = "VPI30"; 1219 }; 1220 1221 pinctrl_vpo12_default: vpo12_default { 1222 function = "VPO12"; 1223 groups = "VPO12"; 1224 }; 1225 1226 pinctrl_vpo24_default: vpo24_default { 1227 function = "VPO24"; 1228 groups = "VPO24"; 1229 }; 1230 1231 pinctrl_wdtrst1_default: wdtrst1_default { 1232 function = "WDTRST1"; 1233 groups = "WDTRST1"; 1234 }; 1235 1236 pinctrl_wdtrst2_default: wdtrst2_default { 1237 function = "WDTRST2"; 1238 groups = "WDTRST2"; 1239 }; 1240}; 1241