1a27cda6cSjmcneill// SPDX-License-Identifier: GPL-2.0+ 2a27cda6cSjmcneill// 3a27cda6cSjmcneill// Copyright 2012 Freescale Semiconductor, Inc. 4f46c7ed4Sjmcneill 5f46c7ed4Sjmcneill#include "imx23-pinfunc.h" 6f46c7ed4Sjmcneill 7f46c7ed4Sjmcneill/ { 8f46c7ed4Sjmcneill #address-cells = <1>; 9f46c7ed4Sjmcneill #size-cells = <1>; 10f46c7ed4Sjmcneill 11f46c7ed4Sjmcneill interrupt-parent = <&icoll>; 12f46c7ed4Sjmcneill /* 13f46c7ed4Sjmcneill * The decompressor and also some bootloaders rely on a 14f46c7ed4Sjmcneill * pre-existing /chosen node to be available to insert the 15f46c7ed4Sjmcneill * command line and merge other ATAGS info. 16f46c7ed4Sjmcneill */ 17f46c7ed4Sjmcneill chosen {}; 18f46c7ed4Sjmcneill 19f46c7ed4Sjmcneill aliases { 20f46c7ed4Sjmcneill gpio0 = &gpio0; 21f46c7ed4Sjmcneill gpio1 = &gpio1; 22f46c7ed4Sjmcneill gpio2 = &gpio2; 23f46c7ed4Sjmcneill serial0 = &auart0; 24f46c7ed4Sjmcneill serial1 = &auart1; 25f46c7ed4Sjmcneill spi0 = &ssp0; 26f46c7ed4Sjmcneill spi1 = &ssp1; 27f46c7ed4Sjmcneill usbphy0 = &usbphy0; 28f46c7ed4Sjmcneill }; 29f46c7ed4Sjmcneill 30f46c7ed4Sjmcneill cpus { 31f46c7ed4Sjmcneill #address-cells = <1>; 32f46c7ed4Sjmcneill #size-cells = <0>; 33f46c7ed4Sjmcneill 34f46c7ed4Sjmcneill cpu@0 { 35f46c7ed4Sjmcneill compatible = "arm,arm926ej-s"; 36f46c7ed4Sjmcneill device_type = "cpu"; 37f46c7ed4Sjmcneill reg = <0>; 38f46c7ed4Sjmcneill }; 39f46c7ed4Sjmcneill }; 40f46c7ed4Sjmcneill 41f46c7ed4Sjmcneill apb@80000000 { 42f46c7ed4Sjmcneill compatible = "simple-bus"; 43f46c7ed4Sjmcneill #address-cells = <1>; 44f46c7ed4Sjmcneill #size-cells = <1>; 45f46c7ed4Sjmcneill reg = <0x80000000 0x80000>; 46f46c7ed4Sjmcneill ranges; 47f46c7ed4Sjmcneill 48f46c7ed4Sjmcneill apbh@80000000 { 49f46c7ed4Sjmcneill compatible = "simple-bus"; 50f46c7ed4Sjmcneill #address-cells = <1>; 51f46c7ed4Sjmcneill #size-cells = <1>; 52f46c7ed4Sjmcneill reg = <0x80000000 0x40000>; 53f46c7ed4Sjmcneill ranges; 54f46c7ed4Sjmcneill 55f46c7ed4Sjmcneill icoll: interrupt-controller@80000000 { 56f46c7ed4Sjmcneill compatible = "fsl,imx23-icoll", "fsl,icoll"; 57f46c7ed4Sjmcneill interrupt-controller; 58f46c7ed4Sjmcneill #interrupt-cells = <1>; 59f46c7ed4Sjmcneill reg = <0x80000000 0x2000>; 60f46c7ed4Sjmcneill }; 61f46c7ed4Sjmcneill 62f46c7ed4Sjmcneill dma_apbh: dma-apbh@80004000 { 63f46c7ed4Sjmcneill compatible = "fsl,imx23-dma-apbh"; 64f46c7ed4Sjmcneill reg = <0x80004000 0x2000>; 65f46c7ed4Sjmcneill interrupts = <0 14 20 0 66f46c7ed4Sjmcneill 13 13 13 13>; 67f46c7ed4Sjmcneill interrupt-names = "empty", "ssp0", "ssp1", "empty", 68f46c7ed4Sjmcneill "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 69f46c7ed4Sjmcneill #dma-cells = <1>; 70f46c7ed4Sjmcneill dma-channels = <8>; 71f46c7ed4Sjmcneill clocks = <&clks 15>; 72f46c7ed4Sjmcneill }; 73f46c7ed4Sjmcneill 74f46c7ed4Sjmcneill ecc@80008000 { 75f46c7ed4Sjmcneill reg = <0x80008000 0x2000>; 76f46c7ed4Sjmcneill status = "disabled"; 77f46c7ed4Sjmcneill }; 78f46c7ed4Sjmcneill 79*9ed2a30eSjmcneill nand-controller@8000c000 { 80f46c7ed4Sjmcneill compatible = "fsl,imx23-gpmi-nand"; 81f46c7ed4Sjmcneill #address-cells = <1>; 82f46c7ed4Sjmcneill #size-cells = <1>; 83f46c7ed4Sjmcneill reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; 84f46c7ed4Sjmcneill reg-names = "gpmi-nand", "bch"; 85f46c7ed4Sjmcneill interrupts = <56>; 86f46c7ed4Sjmcneill interrupt-names = "bch"; 87f46c7ed4Sjmcneill clocks = <&clks 34>; 88f46c7ed4Sjmcneill clock-names = "gpmi_io"; 89f46c7ed4Sjmcneill dmas = <&dma_apbh 4>; 90f46c7ed4Sjmcneill dma-names = "rx-tx"; 91f46c7ed4Sjmcneill status = "disabled"; 92f46c7ed4Sjmcneill }; 93f46c7ed4Sjmcneill 94182157ecSjmcneill ssp0: spi@80010000 { 95f46c7ed4Sjmcneill reg = <0x80010000 0x2000>; 96f46c7ed4Sjmcneill interrupts = <15>; 97f46c7ed4Sjmcneill clocks = <&clks 33>; 98f46c7ed4Sjmcneill dmas = <&dma_apbh 1>; 99f46c7ed4Sjmcneill dma-names = "rx-tx"; 100f46c7ed4Sjmcneill status = "disabled"; 101f46c7ed4Sjmcneill }; 102f46c7ed4Sjmcneill 103f46c7ed4Sjmcneill etm@80014000 { 104f46c7ed4Sjmcneill reg = <0x80014000 0x2000>; 105f46c7ed4Sjmcneill status = "disabled"; 106f46c7ed4Sjmcneill }; 107f46c7ed4Sjmcneill 108f46c7ed4Sjmcneill pinctrl@80018000 { 109f46c7ed4Sjmcneill #address-cells = <1>; 110f46c7ed4Sjmcneill #size-cells = <0>; 111f46c7ed4Sjmcneill compatible = "fsl,imx23-pinctrl", "simple-bus"; 112f46c7ed4Sjmcneill reg = <0x80018000 0x2000>; 113f46c7ed4Sjmcneill 114f46c7ed4Sjmcneill gpio0: gpio@0 { 115f46c7ed4Sjmcneill compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; 116f46c7ed4Sjmcneill reg = <0>; 117f46c7ed4Sjmcneill interrupts = <16>; 118f46c7ed4Sjmcneill gpio-controller; 119f46c7ed4Sjmcneill #gpio-cells = <2>; 120f46c7ed4Sjmcneill interrupt-controller; 121f46c7ed4Sjmcneill #interrupt-cells = <2>; 122f46c7ed4Sjmcneill }; 123f46c7ed4Sjmcneill 124f46c7ed4Sjmcneill gpio1: gpio@1 { 125f46c7ed4Sjmcneill compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; 126f46c7ed4Sjmcneill reg = <1>; 127f46c7ed4Sjmcneill interrupts = <17>; 128f46c7ed4Sjmcneill gpio-controller; 129f46c7ed4Sjmcneill #gpio-cells = <2>; 130f46c7ed4Sjmcneill interrupt-controller; 131f46c7ed4Sjmcneill #interrupt-cells = <2>; 132f46c7ed4Sjmcneill }; 133f46c7ed4Sjmcneill 134f46c7ed4Sjmcneill gpio2: gpio@2 { 135f46c7ed4Sjmcneill compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; 136f46c7ed4Sjmcneill reg = <2>; 137f46c7ed4Sjmcneill interrupts = <18>; 138f46c7ed4Sjmcneill gpio-controller; 139f46c7ed4Sjmcneill #gpio-cells = <2>; 140f46c7ed4Sjmcneill interrupt-controller; 141f46c7ed4Sjmcneill #interrupt-cells = <2>; 142f46c7ed4Sjmcneill }; 143f46c7ed4Sjmcneill 144f46c7ed4Sjmcneill duart_pins_a: duart@0 { 145f46c7ed4Sjmcneill reg = <0>; 146f46c7ed4Sjmcneill fsl,pinmux-ids = < 147f46c7ed4Sjmcneill MX23_PAD_PWM0__DUART_RX 148f46c7ed4Sjmcneill MX23_PAD_PWM1__DUART_TX 149f46c7ed4Sjmcneill >; 150f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_4mA>; 151f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 152f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_DISABLE>; 153f46c7ed4Sjmcneill }; 154f46c7ed4Sjmcneill 155f46c7ed4Sjmcneill auart0_pins_a: auart0@0 { 156f46c7ed4Sjmcneill reg = <0>; 157f46c7ed4Sjmcneill fsl,pinmux-ids = < 158f46c7ed4Sjmcneill MX23_PAD_AUART1_RX__AUART1_RX 159f46c7ed4Sjmcneill MX23_PAD_AUART1_TX__AUART1_TX 160f46c7ed4Sjmcneill MX23_PAD_AUART1_CTS__AUART1_CTS 161f46c7ed4Sjmcneill MX23_PAD_AUART1_RTS__AUART1_RTS 162f46c7ed4Sjmcneill >; 163f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_4mA>; 164f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 165f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_DISABLE>; 166f46c7ed4Sjmcneill }; 167f46c7ed4Sjmcneill 168f46c7ed4Sjmcneill auart0_2pins_a: auart0-2pins@0 { 169f46c7ed4Sjmcneill reg = <0>; 170f46c7ed4Sjmcneill fsl,pinmux-ids = < 171f46c7ed4Sjmcneill MX23_PAD_I2C_SCL__AUART1_TX 172f46c7ed4Sjmcneill MX23_PAD_I2C_SDA__AUART1_RX 173f46c7ed4Sjmcneill >; 174f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_4mA>; 175f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 176f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_DISABLE>; 177f46c7ed4Sjmcneill }; 178f46c7ed4Sjmcneill 179f46c7ed4Sjmcneill auart1_2pins_a: auart1-2pins@0 { 180f46c7ed4Sjmcneill reg = <0>; 181f46c7ed4Sjmcneill fsl,pinmux-ids = < 182f46c7ed4Sjmcneill MX23_PAD_GPMI_D14__AUART2_RX 183f46c7ed4Sjmcneill MX23_PAD_GPMI_D15__AUART2_TX 184f46c7ed4Sjmcneill >; 185f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_4mA>; 186f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 187f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_DISABLE>; 188f46c7ed4Sjmcneill }; 189f46c7ed4Sjmcneill 190f46c7ed4Sjmcneill gpmi_pins_a: gpmi-nand@0 { 191f46c7ed4Sjmcneill reg = <0>; 192f46c7ed4Sjmcneill fsl,pinmux-ids = < 193f46c7ed4Sjmcneill MX23_PAD_GPMI_D00__GPMI_D00 194f46c7ed4Sjmcneill MX23_PAD_GPMI_D01__GPMI_D01 195f46c7ed4Sjmcneill MX23_PAD_GPMI_D02__GPMI_D02 196f46c7ed4Sjmcneill MX23_PAD_GPMI_D03__GPMI_D03 197f46c7ed4Sjmcneill MX23_PAD_GPMI_D04__GPMI_D04 198f46c7ed4Sjmcneill MX23_PAD_GPMI_D05__GPMI_D05 199f46c7ed4Sjmcneill MX23_PAD_GPMI_D06__GPMI_D06 200f46c7ed4Sjmcneill MX23_PAD_GPMI_D07__GPMI_D07 201f46c7ed4Sjmcneill MX23_PAD_GPMI_CLE__GPMI_CLE 202f46c7ed4Sjmcneill MX23_PAD_GPMI_ALE__GPMI_ALE 203f46c7ed4Sjmcneill MX23_PAD_GPMI_RDY0__GPMI_RDY0 204f46c7ed4Sjmcneill MX23_PAD_GPMI_RDY1__GPMI_RDY1 205f46c7ed4Sjmcneill MX23_PAD_GPMI_WPN__GPMI_WPN 206f46c7ed4Sjmcneill MX23_PAD_GPMI_WRN__GPMI_WRN 207f46c7ed4Sjmcneill MX23_PAD_GPMI_RDN__GPMI_RDN 208f46c7ed4Sjmcneill MX23_PAD_GPMI_CE1N__GPMI_CE1N 209f46c7ed4Sjmcneill MX23_PAD_GPMI_CE0N__GPMI_CE0N 210f46c7ed4Sjmcneill >; 211f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_4mA>; 212f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 213f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_DISABLE>; 214f46c7ed4Sjmcneill }; 215f46c7ed4Sjmcneill 216cf2d964bSjmcneill gpmi_pins_fixup: gpmi-pins-fixup@0 { 217cf2d964bSjmcneill reg = <0>; 218f46c7ed4Sjmcneill fsl,pinmux-ids = < 219f46c7ed4Sjmcneill MX23_PAD_GPMI_WPN__GPMI_WPN 220f46c7ed4Sjmcneill MX23_PAD_GPMI_WRN__GPMI_WRN 221f46c7ed4Sjmcneill MX23_PAD_GPMI_RDN__GPMI_RDN 222f46c7ed4Sjmcneill >; 223f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_12mA>; 224f46c7ed4Sjmcneill }; 225f46c7ed4Sjmcneill 226f46c7ed4Sjmcneill mmc0_4bit_pins_a: mmc0-4bit@0 { 227f46c7ed4Sjmcneill reg = <0>; 228f46c7ed4Sjmcneill fsl,pinmux-ids = < 229f46c7ed4Sjmcneill MX23_PAD_SSP1_DATA0__SSP1_DATA0 230f46c7ed4Sjmcneill MX23_PAD_SSP1_DATA1__SSP1_DATA1 231f46c7ed4Sjmcneill MX23_PAD_SSP1_DATA2__SSP1_DATA2 232f46c7ed4Sjmcneill MX23_PAD_SSP1_DATA3__SSP1_DATA3 233f46c7ed4Sjmcneill MX23_PAD_SSP1_CMD__SSP1_CMD 234f46c7ed4Sjmcneill MX23_PAD_SSP1_SCK__SSP1_SCK 235f46c7ed4Sjmcneill >; 236f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_8mA>; 237f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 238f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_ENABLE>; 239f46c7ed4Sjmcneill }; 240f46c7ed4Sjmcneill 241f46c7ed4Sjmcneill mmc0_8bit_pins_a: mmc0-8bit@0 { 242f46c7ed4Sjmcneill reg = <0>; 243f46c7ed4Sjmcneill fsl,pinmux-ids = < 244f46c7ed4Sjmcneill MX23_PAD_SSP1_DATA0__SSP1_DATA0 245f46c7ed4Sjmcneill MX23_PAD_SSP1_DATA1__SSP1_DATA1 246f46c7ed4Sjmcneill MX23_PAD_SSP1_DATA2__SSP1_DATA2 247f46c7ed4Sjmcneill MX23_PAD_SSP1_DATA3__SSP1_DATA3 248f46c7ed4Sjmcneill MX23_PAD_GPMI_D08__SSP1_DATA4 249f46c7ed4Sjmcneill MX23_PAD_GPMI_D09__SSP1_DATA5 250f46c7ed4Sjmcneill MX23_PAD_GPMI_D10__SSP1_DATA6 251f46c7ed4Sjmcneill MX23_PAD_GPMI_D11__SSP1_DATA7 252f46c7ed4Sjmcneill MX23_PAD_SSP1_CMD__SSP1_CMD 253f46c7ed4Sjmcneill MX23_PAD_SSP1_DETECT__SSP1_DETECT 254f46c7ed4Sjmcneill MX23_PAD_SSP1_SCK__SSP1_SCK 255f46c7ed4Sjmcneill >; 256f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_8mA>; 257f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 258f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_ENABLE>; 259f46c7ed4Sjmcneill }; 260f46c7ed4Sjmcneill 261cf2d964bSjmcneill mmc0_pins_fixup: mmc0-pins-fixup@0 { 262cf2d964bSjmcneill reg = <0>; 263f46c7ed4Sjmcneill fsl,pinmux-ids = < 264f46c7ed4Sjmcneill MX23_PAD_SSP1_DETECT__SSP1_DETECT 265f46c7ed4Sjmcneill MX23_PAD_SSP1_SCK__SSP1_SCK 266f46c7ed4Sjmcneill >; 267f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_DISABLE>; 268f46c7ed4Sjmcneill }; 269f46c7ed4Sjmcneill 270*9ed2a30eSjmcneill mmc0_sck_cfg: mmc0-sck-cfg@0 { 271*9ed2a30eSjmcneill reg = <0>; 272*9ed2a30eSjmcneill fsl,pinmux-ids = < 273*9ed2a30eSjmcneill MX23_PAD_SSP1_SCK__SSP1_SCK 274*9ed2a30eSjmcneill >; 275*9ed2a30eSjmcneill fsl,pull-up = <MXS_PULL_DISABLE>; 276*9ed2a30eSjmcneill }; 277*9ed2a30eSjmcneill 278f46c7ed4Sjmcneill mmc1_4bit_pins_a: mmc1-4bit@0 { 279f46c7ed4Sjmcneill reg = <0>; 280f46c7ed4Sjmcneill fsl,pinmux-ids = < 281f46c7ed4Sjmcneill MX23_PAD_GPMI_D00__SSP2_DATA0 282f46c7ed4Sjmcneill MX23_PAD_GPMI_D01__SSP2_DATA1 283f46c7ed4Sjmcneill MX23_PAD_GPMI_D02__SSP2_DATA2 284f46c7ed4Sjmcneill MX23_PAD_GPMI_D03__SSP2_DATA3 285f46c7ed4Sjmcneill MX23_PAD_GPMI_RDY1__SSP2_CMD 286f46c7ed4Sjmcneill MX23_PAD_GPMI_WRN__SSP2_SCK 287f46c7ed4Sjmcneill >; 288f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_8mA>; 289f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 290f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_ENABLE>; 291f46c7ed4Sjmcneill }; 292f46c7ed4Sjmcneill 293f46c7ed4Sjmcneill mmc1_8bit_pins_a: mmc1-8bit@0 { 294f46c7ed4Sjmcneill reg = <0>; 295f46c7ed4Sjmcneill fsl,pinmux-ids = < 296f46c7ed4Sjmcneill MX23_PAD_GPMI_D00__SSP2_DATA0 297f46c7ed4Sjmcneill MX23_PAD_GPMI_D01__SSP2_DATA1 298f46c7ed4Sjmcneill MX23_PAD_GPMI_D02__SSP2_DATA2 299f46c7ed4Sjmcneill MX23_PAD_GPMI_D03__SSP2_DATA3 300f46c7ed4Sjmcneill MX23_PAD_GPMI_D04__SSP2_DATA4 301f46c7ed4Sjmcneill MX23_PAD_GPMI_D05__SSP2_DATA5 302f46c7ed4Sjmcneill MX23_PAD_GPMI_D06__SSP2_DATA6 303f46c7ed4Sjmcneill MX23_PAD_GPMI_D07__SSP2_DATA7 304f46c7ed4Sjmcneill MX23_PAD_GPMI_RDY1__SSP2_CMD 305f46c7ed4Sjmcneill MX23_PAD_GPMI_WRN__SSP2_SCK 306f46c7ed4Sjmcneill >; 307f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_8mA>; 308f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 309f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_ENABLE>; 310f46c7ed4Sjmcneill }; 311f46c7ed4Sjmcneill 312f46c7ed4Sjmcneill pwm2_pins_a: pwm2@0 { 313f46c7ed4Sjmcneill reg = <0>; 314f46c7ed4Sjmcneill fsl,pinmux-ids = < 315f46c7ed4Sjmcneill MX23_PAD_PWM2__PWM2 316f46c7ed4Sjmcneill >; 317f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_4mA>; 318f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 319f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_DISABLE>; 320f46c7ed4Sjmcneill }; 321f46c7ed4Sjmcneill 322f46c7ed4Sjmcneill lcdif_24bit_pins_a: lcdif-24bit@0 { 323f46c7ed4Sjmcneill reg = <0>; 324f46c7ed4Sjmcneill fsl,pinmux-ids = < 325f46c7ed4Sjmcneill MX23_PAD_LCD_D00__LCD_D00 326f46c7ed4Sjmcneill MX23_PAD_LCD_D01__LCD_D01 327f46c7ed4Sjmcneill MX23_PAD_LCD_D02__LCD_D02 328f46c7ed4Sjmcneill MX23_PAD_LCD_D03__LCD_D03 329f46c7ed4Sjmcneill MX23_PAD_LCD_D04__LCD_D04 330f46c7ed4Sjmcneill MX23_PAD_LCD_D05__LCD_D05 331f46c7ed4Sjmcneill MX23_PAD_LCD_D06__LCD_D06 332f46c7ed4Sjmcneill MX23_PAD_LCD_D07__LCD_D07 333f46c7ed4Sjmcneill MX23_PAD_LCD_D08__LCD_D08 334f46c7ed4Sjmcneill MX23_PAD_LCD_D09__LCD_D09 335f46c7ed4Sjmcneill MX23_PAD_LCD_D10__LCD_D10 336f46c7ed4Sjmcneill MX23_PAD_LCD_D11__LCD_D11 337f46c7ed4Sjmcneill MX23_PAD_LCD_D12__LCD_D12 338f46c7ed4Sjmcneill MX23_PAD_LCD_D13__LCD_D13 339f46c7ed4Sjmcneill MX23_PAD_LCD_D14__LCD_D14 340f46c7ed4Sjmcneill MX23_PAD_LCD_D15__LCD_D15 341f46c7ed4Sjmcneill MX23_PAD_LCD_D16__LCD_D16 342f46c7ed4Sjmcneill MX23_PAD_LCD_D17__LCD_D17 343f46c7ed4Sjmcneill MX23_PAD_GPMI_D08__LCD_D18 344f46c7ed4Sjmcneill MX23_PAD_GPMI_D09__LCD_D19 345f46c7ed4Sjmcneill MX23_PAD_GPMI_D10__LCD_D20 346f46c7ed4Sjmcneill MX23_PAD_GPMI_D11__LCD_D21 347f46c7ed4Sjmcneill MX23_PAD_GPMI_D12__LCD_D22 348f46c7ed4Sjmcneill MX23_PAD_GPMI_D13__LCD_D23 349f46c7ed4Sjmcneill MX23_PAD_LCD_DOTCK__LCD_DOTCK 350f46c7ed4Sjmcneill MX23_PAD_LCD_ENABLE__LCD_ENABLE 351f46c7ed4Sjmcneill MX23_PAD_LCD_HSYNC__LCD_HSYNC 352f46c7ed4Sjmcneill MX23_PAD_LCD_VSYNC__LCD_VSYNC 353f46c7ed4Sjmcneill >; 354f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_4mA>; 355f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 356f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_DISABLE>; 357f46c7ed4Sjmcneill }; 358f46c7ed4Sjmcneill 359f46c7ed4Sjmcneill spi2_pins_a: spi2@0 { 360f46c7ed4Sjmcneill reg = <0>; 361f46c7ed4Sjmcneill fsl,pinmux-ids = < 362f46c7ed4Sjmcneill MX23_PAD_GPMI_WRN__SSP2_SCK 363f46c7ed4Sjmcneill MX23_PAD_GPMI_RDY1__SSP2_CMD 364f46c7ed4Sjmcneill MX23_PAD_GPMI_D00__SSP2_DATA0 365f46c7ed4Sjmcneill MX23_PAD_GPMI_D03__SSP2_DATA3 366f46c7ed4Sjmcneill >; 367f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_8mA>; 368f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 369f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_ENABLE>; 370f46c7ed4Sjmcneill }; 371f46c7ed4Sjmcneill 372f46c7ed4Sjmcneill i2c_pins_a: i2c@0 { 373f46c7ed4Sjmcneill reg = <0>; 374f46c7ed4Sjmcneill fsl,pinmux-ids = < 375f46c7ed4Sjmcneill MX23_PAD_I2C_SCL__I2C_SCL 376f46c7ed4Sjmcneill MX23_PAD_I2C_SDA__I2C_SDA 377f46c7ed4Sjmcneill >; 378f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_8mA>; 379f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 380f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_ENABLE>; 381f46c7ed4Sjmcneill }; 382f46c7ed4Sjmcneill 383f46c7ed4Sjmcneill i2c_pins_b: i2c@1 { 384f46c7ed4Sjmcneill reg = <1>; 385f46c7ed4Sjmcneill fsl,pinmux-ids = < 386f46c7ed4Sjmcneill MX23_PAD_LCD_ENABLE__I2C_SCL 387f46c7ed4Sjmcneill MX23_PAD_LCD_HSYNC__I2C_SDA 388f46c7ed4Sjmcneill >; 389f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_8mA>; 390f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 391f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_ENABLE>; 392f46c7ed4Sjmcneill }; 393f46c7ed4Sjmcneill 394f46c7ed4Sjmcneill i2c_pins_c: i2c@2 { 395f46c7ed4Sjmcneill reg = <2>; 396f46c7ed4Sjmcneill fsl,pinmux-ids = < 397f46c7ed4Sjmcneill MX23_PAD_SSP1_DATA1__I2C_SCL 398f46c7ed4Sjmcneill MX23_PAD_SSP1_DATA2__I2C_SDA 399f46c7ed4Sjmcneill >; 400f46c7ed4Sjmcneill fsl,drive-strength = <MXS_DRIVE_8mA>; 401f46c7ed4Sjmcneill fsl,voltage = <MXS_VOLTAGE_HIGH>; 402f46c7ed4Sjmcneill fsl,pull-up = <MXS_PULL_ENABLE>; 403f46c7ed4Sjmcneill }; 404f46c7ed4Sjmcneill }; 405f46c7ed4Sjmcneill 406f46c7ed4Sjmcneill digctl@8001c000 { 407f46c7ed4Sjmcneill compatible = "fsl,imx23-digctl"; 408f46c7ed4Sjmcneill reg = <0x8001c000 2000>; 409f46c7ed4Sjmcneill status = "disabled"; 410f46c7ed4Sjmcneill }; 411f46c7ed4Sjmcneill 412f46c7ed4Sjmcneill emi@80020000 { 413f46c7ed4Sjmcneill reg = <0x80020000 0x2000>; 414f46c7ed4Sjmcneill status = "disabled"; 415f46c7ed4Sjmcneill }; 416f46c7ed4Sjmcneill 417f46c7ed4Sjmcneill dma_apbx: dma-apbx@80024000 { 418f46c7ed4Sjmcneill compatible = "fsl,imx23-dma-apbx"; 419f46c7ed4Sjmcneill reg = <0x80024000 0x2000>; 420f46c7ed4Sjmcneill interrupts = <7 5 9 26 421f46c7ed4Sjmcneill 19 0 25 23 422f46c7ed4Sjmcneill 60 58 9 0 423f46c7ed4Sjmcneill 0 0 0 0>; 424f46c7ed4Sjmcneill interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c", 425f46c7ed4Sjmcneill "saif0", "empty", "auart0-rx", "auart0-tx", 426f46c7ed4Sjmcneill "auart1-rx", "auart1-tx", "saif1", "empty", 427f46c7ed4Sjmcneill "empty", "empty", "empty", "empty"; 428f46c7ed4Sjmcneill #dma-cells = <1>; 429f46c7ed4Sjmcneill dma-channels = <16>; 430f46c7ed4Sjmcneill clocks = <&clks 16>; 431f46c7ed4Sjmcneill }; 432f46c7ed4Sjmcneill 433*9ed2a30eSjmcneill dcp: crypto@80028000 { 434f46c7ed4Sjmcneill compatible = "fsl,imx23-dcp"; 435f46c7ed4Sjmcneill reg = <0x80028000 0x2000>; 436f46c7ed4Sjmcneill interrupts = <53 54>; 437f46c7ed4Sjmcneill status = "okay"; 438f46c7ed4Sjmcneill }; 439f46c7ed4Sjmcneill 440f46c7ed4Sjmcneill pxp@8002a000 { 441f46c7ed4Sjmcneill reg = <0x8002a000 0x2000>; 442f46c7ed4Sjmcneill status = "disabled"; 443f46c7ed4Sjmcneill }; 444f46c7ed4Sjmcneill 445*9ed2a30eSjmcneill efuse@8002c000 { 446f46c7ed4Sjmcneill compatible = "fsl,imx23-ocotp", "fsl,ocotp"; 447f46c7ed4Sjmcneill #address-cells = <1>; 448f46c7ed4Sjmcneill #size-cells = <1>; 449f46c7ed4Sjmcneill reg = <0x8002c000 0x2000>; 450f46c7ed4Sjmcneill clocks = <&clks 15>; 451f46c7ed4Sjmcneill }; 452f46c7ed4Sjmcneill 453f46c7ed4Sjmcneill axi-ahb@8002e000 { 454f46c7ed4Sjmcneill reg = <0x8002e000 0x2000>; 455f46c7ed4Sjmcneill status = "disabled"; 456f46c7ed4Sjmcneill }; 457f46c7ed4Sjmcneill 458f46c7ed4Sjmcneill lcdif@80030000 { 459f46c7ed4Sjmcneill compatible = "fsl,imx23-lcdif"; 460f46c7ed4Sjmcneill reg = <0x80030000 2000>; 461f46c7ed4Sjmcneill interrupts = <46 45>; 462f46c7ed4Sjmcneill clocks = <&clks 38>; 463f46c7ed4Sjmcneill status = "disabled"; 464f46c7ed4Sjmcneill }; 465f46c7ed4Sjmcneill 466182157ecSjmcneill ssp1: spi@80034000 { 467f46c7ed4Sjmcneill reg = <0x80034000 0x2000>; 468f46c7ed4Sjmcneill interrupts = <2>; 469f46c7ed4Sjmcneill clocks = <&clks 33>; 470f46c7ed4Sjmcneill dmas = <&dma_apbh 2>; 471f46c7ed4Sjmcneill dma-names = "rx-tx"; 472f46c7ed4Sjmcneill status = "disabled"; 473f46c7ed4Sjmcneill }; 474f46c7ed4Sjmcneill 475f46c7ed4Sjmcneill tvenc@80038000 { 476f46c7ed4Sjmcneill reg = <0x80038000 0x2000>; 477f46c7ed4Sjmcneill status = "disabled"; 478f46c7ed4Sjmcneill }; 479f46c7ed4Sjmcneill }; 480f46c7ed4Sjmcneill 481f46c7ed4Sjmcneill apbx@80040000 { 482f46c7ed4Sjmcneill compatible = "simple-bus"; 483f46c7ed4Sjmcneill #address-cells = <1>; 484f46c7ed4Sjmcneill #size-cells = <1>; 485f46c7ed4Sjmcneill reg = <0x80040000 0x40000>; 486f46c7ed4Sjmcneill ranges; 487f46c7ed4Sjmcneill 488f46c7ed4Sjmcneill clks: clkctrl@80040000 { 489f46c7ed4Sjmcneill compatible = "fsl,imx23-clkctrl", "fsl,clkctrl"; 490f46c7ed4Sjmcneill reg = <0x80040000 0x2000>; 491f46c7ed4Sjmcneill #clock-cells = <1>; 492f46c7ed4Sjmcneill }; 493f46c7ed4Sjmcneill 494f46c7ed4Sjmcneill saif0: saif@80042000 { 495f46c7ed4Sjmcneill reg = <0x80042000 0x2000>; 496f46c7ed4Sjmcneill dmas = <&dma_apbx 4>; 497f46c7ed4Sjmcneill dma-names = "rx-tx"; 498f46c7ed4Sjmcneill status = "disabled"; 499f46c7ed4Sjmcneill }; 500f46c7ed4Sjmcneill 501f46c7ed4Sjmcneill power@80044000 { 502f46c7ed4Sjmcneill reg = <0x80044000 0x2000>; 503f46c7ed4Sjmcneill status = "disabled"; 504f46c7ed4Sjmcneill }; 505f46c7ed4Sjmcneill 506f46c7ed4Sjmcneill saif1: saif@80046000 { 507f46c7ed4Sjmcneill reg = <0x80046000 0x2000>; 508f46c7ed4Sjmcneill dmas = <&dma_apbx 10>; 509f46c7ed4Sjmcneill dma-names = "rx-tx"; 510f46c7ed4Sjmcneill status = "disabled"; 511f46c7ed4Sjmcneill }; 512f46c7ed4Sjmcneill 513f46c7ed4Sjmcneill audio-out@80048000 { 514f46c7ed4Sjmcneill reg = <0x80048000 0x2000>; 515f46c7ed4Sjmcneill dmas = <&dma_apbx 1>; 516f46c7ed4Sjmcneill dma-names = "tx"; 517f46c7ed4Sjmcneill status = "disabled"; 518f46c7ed4Sjmcneill }; 519f46c7ed4Sjmcneill 520f46c7ed4Sjmcneill audio-in@8004c000 { 521f46c7ed4Sjmcneill reg = <0x8004c000 0x2000>; 522f46c7ed4Sjmcneill dmas = <&dma_apbx 0>; 523f46c7ed4Sjmcneill dma-names = "rx"; 524f46c7ed4Sjmcneill status = "disabled"; 525f46c7ed4Sjmcneill }; 526f46c7ed4Sjmcneill 527f46c7ed4Sjmcneill lradc: lradc@80050000 { 528f46c7ed4Sjmcneill compatible = "fsl,imx23-lradc"; 529f46c7ed4Sjmcneill reg = <0x80050000 0x2000>; 530f46c7ed4Sjmcneill interrupts = <36 37 38 39 40 41 42 43 44>; 531f46c7ed4Sjmcneill status = "disabled"; 532f46c7ed4Sjmcneill clocks = <&clks 26>; 533f46c7ed4Sjmcneill #io-channel-cells = <1>; 534f46c7ed4Sjmcneill }; 535f46c7ed4Sjmcneill 536f46c7ed4Sjmcneill spdif@80054000 { 537f46c7ed4Sjmcneill reg = <0x80054000 2000>; 538f46c7ed4Sjmcneill dmas = <&dma_apbx 2>; 539f46c7ed4Sjmcneill dma-names = "tx"; 540f46c7ed4Sjmcneill status = "disabled"; 541f46c7ed4Sjmcneill }; 542f46c7ed4Sjmcneill 543f46c7ed4Sjmcneill i2c: i2c@80058000 { 544f46c7ed4Sjmcneill #address-cells = <1>; 545f46c7ed4Sjmcneill #size-cells = <0>; 546f46c7ed4Sjmcneill compatible = "fsl,imx23-i2c"; 547f46c7ed4Sjmcneill reg = <0x80058000 0x2000>; 548f46c7ed4Sjmcneill interrupts = <27>; 549f46c7ed4Sjmcneill clock-frequency = <100000>; 550f46c7ed4Sjmcneill dmas = <&dma_apbx 3>; 551f46c7ed4Sjmcneill dma-names = "rx-tx"; 552f46c7ed4Sjmcneill status = "disabled"; 553f46c7ed4Sjmcneill }; 554f46c7ed4Sjmcneill 555f46c7ed4Sjmcneill rtc@8005c000 { 556f46c7ed4Sjmcneill compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc"; 557f46c7ed4Sjmcneill reg = <0x8005c000 0x2000>; 558f46c7ed4Sjmcneill interrupts = <22>; 559f46c7ed4Sjmcneill }; 560f46c7ed4Sjmcneill 561f46c7ed4Sjmcneill pwm: pwm@80064000 { 562f46c7ed4Sjmcneill compatible = "fsl,imx23-pwm"; 563f46c7ed4Sjmcneill reg = <0x80064000 0x2000>; 564f46c7ed4Sjmcneill clocks = <&clks 30>; 565f46c7ed4Sjmcneill #pwm-cells = <2>; 566f46c7ed4Sjmcneill fsl,pwm-number = <5>; 567f46c7ed4Sjmcneill status = "disabled"; 568f46c7ed4Sjmcneill }; 569f46c7ed4Sjmcneill 570f46c7ed4Sjmcneill timrot@80068000 { 571f46c7ed4Sjmcneill compatible = "fsl,imx23-timrot", "fsl,timrot"; 572f46c7ed4Sjmcneill reg = <0x80068000 0x2000>; 573f46c7ed4Sjmcneill interrupts = <28 29 30 31>; 574f46c7ed4Sjmcneill clocks = <&clks 28>; 575f46c7ed4Sjmcneill }; 576f46c7ed4Sjmcneill 577f46c7ed4Sjmcneill auart0: serial@8006c000 { 578f46c7ed4Sjmcneill compatible = "fsl,imx23-auart"; 579f46c7ed4Sjmcneill reg = <0x8006c000 0x2000>; 580f46c7ed4Sjmcneill interrupts = <24>; 581f46c7ed4Sjmcneill clocks = <&clks 32>; 582f46c7ed4Sjmcneill dmas = <&dma_apbx 6>, <&dma_apbx 7>; 583f46c7ed4Sjmcneill dma-names = "rx", "tx"; 584f46c7ed4Sjmcneill status = "disabled"; 585f46c7ed4Sjmcneill }; 586f46c7ed4Sjmcneill 587f46c7ed4Sjmcneill auart1: serial@8006e000 { 588f46c7ed4Sjmcneill compatible = "fsl,imx23-auart"; 589f46c7ed4Sjmcneill reg = <0x8006e000 0x2000>; 590f46c7ed4Sjmcneill interrupts = <59>; 591f46c7ed4Sjmcneill clocks = <&clks 32>; 592f46c7ed4Sjmcneill dmas = <&dma_apbx 8>, <&dma_apbx 9>; 593f46c7ed4Sjmcneill dma-names = "rx", "tx"; 594f46c7ed4Sjmcneill status = "disabled"; 595f46c7ed4Sjmcneill }; 596f46c7ed4Sjmcneill 597f46c7ed4Sjmcneill duart: serial@80070000 { 598f46c7ed4Sjmcneill compatible = "arm,pl011", "arm,primecell"; 599f46c7ed4Sjmcneill reg = <0x80070000 0x2000>; 600f46c7ed4Sjmcneill interrupts = <0>; 601f46c7ed4Sjmcneill clocks = <&clks 32>, <&clks 16>; 602f46c7ed4Sjmcneill clock-names = "uart", "apb_pclk"; 603f46c7ed4Sjmcneill status = "disabled"; 604f46c7ed4Sjmcneill }; 605f46c7ed4Sjmcneill 606f46c7ed4Sjmcneill usbphy0: usbphy@8007c000 { 607f46c7ed4Sjmcneill compatible = "fsl,imx23-usbphy"; 608f46c7ed4Sjmcneill reg = <0x8007c000 0x2000>; 609f46c7ed4Sjmcneill clocks = <&clks 41>; 610f46c7ed4Sjmcneill status = "disabled"; 611f46c7ed4Sjmcneill }; 612f46c7ed4Sjmcneill }; 613f46c7ed4Sjmcneill }; 614f46c7ed4Sjmcneill 615f46c7ed4Sjmcneill ahb@80080000 { 616f46c7ed4Sjmcneill compatible = "simple-bus"; 617f46c7ed4Sjmcneill #address-cells = <1>; 618f46c7ed4Sjmcneill #size-cells = <1>; 619f46c7ed4Sjmcneill reg = <0x80080000 0x80000>; 620f46c7ed4Sjmcneill ranges; 621f46c7ed4Sjmcneill 622f46c7ed4Sjmcneill usb0: usb@80080000 { 623f46c7ed4Sjmcneill compatible = "fsl,imx23-usb", "fsl,imx27-usb"; 624f46c7ed4Sjmcneill reg = <0x80080000 0x40000>; 625f46c7ed4Sjmcneill interrupts = <11>; 626f46c7ed4Sjmcneill fsl,usbphy = <&usbphy0>; 627f46c7ed4Sjmcneill clocks = <&clks 40>; 628f46c7ed4Sjmcneill status = "disabled"; 629f46c7ed4Sjmcneill }; 630f46c7ed4Sjmcneill }; 631f46c7ed4Sjmcneill 632f46c7ed4Sjmcneill iio-hwmon { 633f46c7ed4Sjmcneill compatible = "iio-hwmon"; 634f46c7ed4Sjmcneill io-channels = <&lradc 8>; 635f46c7ed4Sjmcneill }; 636f46c7ed4Sjmcneill}; 637