10cc12ebdSjmcneill// SPDX-License-Identifier: GPL-2.0
2f46c7ed4Sjmcneill/* The pxa3xx skeleton simply augments the 2xx version */
3f46c7ed4Sjmcneill#include "pxa2xx.dtsi"
4f46c7ed4Sjmcneill#include "dt-bindings/clock/pxa-clock.h"
5f46c7ed4Sjmcneill
6f46c7ed4Sjmcneill/ {
7f46c7ed4Sjmcneill	model = "Marvell PXA27x familiy SoC";
8f46c7ed4Sjmcneill	compatible = "marvell,pxa27x";
9f46c7ed4Sjmcneill
10f46c7ed4Sjmcneill	pxabus {
11f46c7ed4Sjmcneill		pdma: dma-controller@40000000 {
12f46c7ed4Sjmcneill			compatible = "marvell,pdma-1.0";
13f46c7ed4Sjmcneill			reg = <0x40000000 0x10000>;
14f46c7ed4Sjmcneill			interrupts = <25>;
15f46c7ed4Sjmcneill			#dma-channels = <32>;
16f46c7ed4Sjmcneill			#dma-cells = <2>;
17f46c7ed4Sjmcneill			#dma-requests = <75>;
18f46c7ed4Sjmcneill			status = "okay";
19f46c7ed4Sjmcneill		};
20f46c7ed4Sjmcneill
21f46c7ed4Sjmcneill		pxairq: interrupt-controller@40d00000 {
22f46c7ed4Sjmcneill			marvell,intc-priority;
23f46c7ed4Sjmcneill			marvell,intc-nr-irqs = <34>;
24f46c7ed4Sjmcneill		};
25f46c7ed4Sjmcneill
26f46c7ed4Sjmcneill		pinctrl: pinctrl@40e00000 {
27f46c7ed4Sjmcneill			reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
28f46c7ed4Sjmcneill			       0x40f00020 0x10>;
29f46c7ed4Sjmcneill			compatible = "marvell,pxa27x-pinctrl";
30f46c7ed4Sjmcneill		};
31f46c7ed4Sjmcneill
32f46c7ed4Sjmcneill		gpio: gpio@40e00000 {
33f46c7ed4Sjmcneill			compatible = "intel,pxa27x-gpio";
34f46c7ed4Sjmcneill			gpio-ranges = <&pinctrl 0 0 128>;
35f46c7ed4Sjmcneill			clocks = <&clks CLK_NONE>;
36f46c7ed4Sjmcneill		};
37f46c7ed4Sjmcneill
38*84c8294dSjmcneill		usb0: usb@4c000000 {
39f46c7ed4Sjmcneill			compatible = "marvell,pxa-ohci";
40f46c7ed4Sjmcneill			reg = <0x4c000000 0x10000>;
41f46c7ed4Sjmcneill			interrupts = <3>;
42f46c7ed4Sjmcneill			clocks = <&clks CLK_USBHOST>;
43f46c7ed4Sjmcneill			status = "disabled";
44f46c7ed4Sjmcneill		};
45f46c7ed4Sjmcneill
46f46c7ed4Sjmcneill		pwm0: pwm@40b00000 {
47f46c7ed4Sjmcneill			compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
48f46c7ed4Sjmcneill			reg = <0x40b00000 0x10>;
49f46c7ed4Sjmcneill			#pwm-cells = <1>;
50f46c7ed4Sjmcneill			clocks = <&clks CLK_PWM0>;
51f46c7ed4Sjmcneill		};
52f46c7ed4Sjmcneill
53f46c7ed4Sjmcneill		pwm1: pwm@40b00010 {
54f46c7ed4Sjmcneill			compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
55f46c7ed4Sjmcneill			reg = <0x40b00010 0x10>;
56f46c7ed4Sjmcneill			#pwm-cells = <1>;
57f46c7ed4Sjmcneill			clocks = <&clks CLK_PWM1>;
58f46c7ed4Sjmcneill		};
59f46c7ed4Sjmcneill
60f46c7ed4Sjmcneill		pwm2: pwm@40c00000 {
61f46c7ed4Sjmcneill			compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
62f46c7ed4Sjmcneill			reg = <0x40c00000 0x10>;
63f46c7ed4Sjmcneill			#pwm-cells = <1>;
64f46c7ed4Sjmcneill			clocks = <&clks CLK_PWM0>;
65f46c7ed4Sjmcneill		};
66f46c7ed4Sjmcneill
67f46c7ed4Sjmcneill		pwm3: pwm@40c00010 {
68f46c7ed4Sjmcneill			compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
69f46c7ed4Sjmcneill			reg = <0x40c00010 0x10>;
70f46c7ed4Sjmcneill			#pwm-cells = <1>;
71f46c7ed4Sjmcneill			clocks = <&clks CLK_PWM1>;
72f46c7ed4Sjmcneill		};
73f46c7ed4Sjmcneill
74182157ecSjmcneill		pwri2c: i2c@40f00180 {
75f46c7ed4Sjmcneill			compatible = "mrvl,pxa-i2c";
76f46c7ed4Sjmcneill			reg = <0x40f00180 0x24>;
77f46c7ed4Sjmcneill			interrupts = <6>;
78f46c7ed4Sjmcneill			clocks = <&clks CLK_PWRI2C>;
79f46c7ed4Sjmcneill			#address-cells = <0x1>;
80f46c7ed4Sjmcneill			#size-cells = <0>;
81f46c7ed4Sjmcneill			status = "disabled";
82f46c7ed4Sjmcneill		};
83f46c7ed4Sjmcneill
84f46c7ed4Sjmcneill		pxa27x_udc: udc@40600000 {
85f46c7ed4Sjmcneill			compatible = "marvell,pxa270-udc";
86f46c7ed4Sjmcneill			reg = <0x40600000 0x10000>;
87f46c7ed4Sjmcneill			interrupts = <11>;
88f46c7ed4Sjmcneill			clocks = <&clks CLK_USB>;
89f46c7ed4Sjmcneill			status = "disabled";
90f46c7ed4Sjmcneill		};
91f46c7ed4Sjmcneill
92f46c7ed4Sjmcneill		keypad: keypad@41500000 {
93f46c7ed4Sjmcneill			compatible = "marvell,pxa27x-keypad";
94f46c7ed4Sjmcneill			reg = <0x41500000 0x4c>;
95f46c7ed4Sjmcneill			interrupts = <4>;
96f46c7ed4Sjmcneill			clocks = <&clks CLK_KEYPAD>;
97f46c7ed4Sjmcneill			status = "disabled";
98f46c7ed4Sjmcneill		};
99f46c7ed4Sjmcneill
100f46c7ed4Sjmcneill		pxa_camera: imaging@50000000 {
101f46c7ed4Sjmcneill			compatible = "marvell,pxa270-qci";
102f46c7ed4Sjmcneill			reg = <0x50000000 0x1000>;
103f46c7ed4Sjmcneill			interrupts = <33>;
104f46c7ed4Sjmcneill			dmas = <&pdma 68 0	/* Y channel */
105f46c7ed4Sjmcneill				&pdma 69 0	/* U channel */
106f46c7ed4Sjmcneill				&pdma 70 0>;	/* V channel */
107f46c7ed4Sjmcneill			dma-names = "CI_Y", "CI_U", "CI_V";
108f46c7ed4Sjmcneill
109f46c7ed4Sjmcneill			clocks = <&clks CLK_CAMERA>;
110f46c7ed4Sjmcneill			clock-names = "ciclk";
111f46c7ed4Sjmcneill			clock-frequency = <5000000>;
112f46c7ed4Sjmcneill			clock-output-names = "qci_mclk";
113f46c7ed4Sjmcneill
114f46c7ed4Sjmcneill			status = "disabled";
115f46c7ed4Sjmcneill		};
116182157ecSjmcneill
117182157ecSjmcneill		rtc@40900000 {
118182157ecSjmcneill			clocks = <&clks CLK_OSC32k768>;
119182157ecSjmcneill		};
120f46c7ed4Sjmcneill	};
121f46c7ed4Sjmcneill
122f46c7ed4Sjmcneill	clocks {
123f46c7ed4Sjmcneill	       /*
124f46c7ed4Sjmcneill		* The muxing of external clocks/internal dividers for osc* clock
125f46c7ed4Sjmcneill		* sources has been hidden under the carpet by now.
126f46c7ed4Sjmcneill		*/
127f46c7ed4Sjmcneill		#address-cells = <1>;
128f46c7ed4Sjmcneill		#size-cells = <1>;
129f46c7ed4Sjmcneill		ranges;
130f46c7ed4Sjmcneill
131f46c7ed4Sjmcneill		clks: pxa2xx_clks@41300004 {
132f46c7ed4Sjmcneill			compatible = "marvell,pxa270-clocks";
133f46c7ed4Sjmcneill			#clock-cells = <1>;
134f46c7ed4Sjmcneill			status = "okay";
135f46c7ed4Sjmcneill		};
136f46c7ed4Sjmcneill	};
137f46c7ed4Sjmcneill
138f46c7ed4Sjmcneill	timer@40a00000 {
139f46c7ed4Sjmcneill		compatible = "marvell,pxa-timer";
140f46c7ed4Sjmcneill		reg = <0x40a00000 0x20>;
141f46c7ed4Sjmcneill		interrupts = <26>;
142f46c7ed4Sjmcneill		clocks = <&clks CLK_OSTIMER>;
143f46c7ed4Sjmcneill		status = "okay";
144f46c7ed4Sjmcneill	};
145f46c7ed4Sjmcneill
146f46c7ed4Sjmcneill	pxa270_opp_table: opp_table0 {
147f46c7ed4Sjmcneill		compatible = "operating-points-v2";
148f46c7ed4Sjmcneill
14905c11c73Sjmcneill		opp-104000000 {
150f46c7ed4Sjmcneill			opp-hz = /bits/ 64 <104000000>;
151f46c7ed4Sjmcneill			opp-microvolt = <900000 900000 1705000>;
152f46c7ed4Sjmcneill			clock-latency-ns = <20>;
153f46c7ed4Sjmcneill		};
15405c11c73Sjmcneill		opp-156000000 {
155f46c7ed4Sjmcneill			opp-hz = /bits/ 64 <156000000>;
156f46c7ed4Sjmcneill			opp-microvolt = <1000000 1000000 1705000>;
157f46c7ed4Sjmcneill			clock-latency-ns = <20>;
158f46c7ed4Sjmcneill		};
15905c11c73Sjmcneill		opp-208000000 {
160f46c7ed4Sjmcneill			opp-hz = /bits/ 64 <208000000>;
161f46c7ed4Sjmcneill			opp-microvolt = <1180000 1180000 1705000>;
162f46c7ed4Sjmcneill			clock-latency-ns = <20>;
163f46c7ed4Sjmcneill		};
16405c11c73Sjmcneill		opp-312000000 {
165f46c7ed4Sjmcneill			opp-hz = /bits/ 64 <312000000>;
166f46c7ed4Sjmcneill			opp-microvolt = <1250000 1250000 1705000>;
167f46c7ed4Sjmcneill			clock-latency-ns = <20>;
168f46c7ed4Sjmcneill		};
16905c11c73Sjmcneill		opp-416000000 {
170f46c7ed4Sjmcneill			opp-hz = /bits/ 64 <416000000>;
171f46c7ed4Sjmcneill			opp-microvolt = <1350000 1350000 1705000>;
172f46c7ed4Sjmcneill			clock-latency-ns = <20>;
173f46c7ed4Sjmcneill		};
17405c11c73Sjmcneill		opp-520000000 {
175f46c7ed4Sjmcneill			opp-hz = /bits/ 64 <520000000>;
176f46c7ed4Sjmcneill			opp-microvolt = <1450000 1450000 1705000>;
177f46c7ed4Sjmcneill			clock-latency-ns = <20>;
178f46c7ed4Sjmcneill		};
17905c11c73Sjmcneill		opp-624000000 {
180f46c7ed4Sjmcneill			opp-hz = /bits/ 64 <624000000>;
181f46c7ed4Sjmcneill			opp-microvolt = <1550000 1550000 1705000>;
182f46c7ed4Sjmcneill			clock-latency-ns = <20>;
183f46c7ed4Sjmcneill		};
184f46c7ed4Sjmcneill	};
185f46c7ed4Sjmcneill};
186