1*9ed2a30eSjmcneill// SPDX-License-Identifier: GPL-2.0-only 2*9ed2a30eSjmcneill/* 3*9ed2a30eSjmcneill * Copyright (c) 2020 HiSilicon Limited. 4*9ed2a30eSjmcneill * 5*9ed2a30eSjmcneill * DTS file for Hisilicon SD5203 Board 6*9ed2a30eSjmcneill */ 7*9ed2a30eSjmcneill 8*9ed2a30eSjmcneill/dts-v1/; 9*9ed2a30eSjmcneill 10*9ed2a30eSjmcneill/ { 11*9ed2a30eSjmcneill model = "Hisilicon SD5203"; 12*9ed2a30eSjmcneill compatible = "H836ASDJ", "hisilicon,sd5203"; 13*9ed2a30eSjmcneill interrupt-parent = <&vic>; 14*9ed2a30eSjmcneill #address-cells = <1>; 15*9ed2a30eSjmcneill #size-cells = <1>; 16*9ed2a30eSjmcneill 17*9ed2a30eSjmcneill chosen { 18*9ed2a30eSjmcneill bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; 19*9ed2a30eSjmcneill }; 20*9ed2a30eSjmcneill 21*9ed2a30eSjmcneill aliases { 22*9ed2a30eSjmcneill serial0 = &uart0; 23*9ed2a30eSjmcneill }; 24*9ed2a30eSjmcneill 25*9ed2a30eSjmcneill cpus { 26*9ed2a30eSjmcneill #address-cells = <1>; 27*9ed2a30eSjmcneill #size-cells = <0>; 28*9ed2a30eSjmcneill 29*9ed2a30eSjmcneill cpu0 { 30*9ed2a30eSjmcneill device_type = "cpu"; 31*9ed2a30eSjmcneill compatible = "arm,arm926ej-s"; 32*9ed2a30eSjmcneill reg = <0x0>; 33*9ed2a30eSjmcneill }; 34*9ed2a30eSjmcneill }; 35*9ed2a30eSjmcneill 36*9ed2a30eSjmcneill memory@30000000 { 37*9ed2a30eSjmcneill device_type = "memory"; 38*9ed2a30eSjmcneill reg = <0x30000000 0x8000000>; 39*9ed2a30eSjmcneill }; 40*9ed2a30eSjmcneill 41*9ed2a30eSjmcneill soc { 42*9ed2a30eSjmcneill #address-cells = <1>; 43*9ed2a30eSjmcneill #size-cells = <1>; 44*9ed2a30eSjmcneill compatible = "simple-bus"; 45*9ed2a30eSjmcneill ranges; 46*9ed2a30eSjmcneill 47*9ed2a30eSjmcneill vic: interrupt-controller@10130000 { 48*9ed2a30eSjmcneill compatible = "snps,dw-apb-ictl"; 49*9ed2a30eSjmcneill reg = <0x10130000 0x1000>; 50*9ed2a30eSjmcneill interrupt-controller; 51*9ed2a30eSjmcneill #interrupt-cells = <1>; 52*9ed2a30eSjmcneill }; 53*9ed2a30eSjmcneill 54*9ed2a30eSjmcneill refclk125mhz: refclk125mhz { 55*9ed2a30eSjmcneill compatible = "fixed-clock"; 56*9ed2a30eSjmcneill #clock-cells = <0>; 57*9ed2a30eSjmcneill clock-frequency = <125000000>; 58*9ed2a30eSjmcneill }; 59*9ed2a30eSjmcneill 60*9ed2a30eSjmcneill timer0: timer@16002000 { 61*9ed2a30eSjmcneill compatible = "arm,sp804", "arm,primecell"; 62*9ed2a30eSjmcneill reg = <0x16002000 0x1000>; 63*9ed2a30eSjmcneill interrupts = <4>; 64*9ed2a30eSjmcneill clocks = <&refclk125mhz>; 65*9ed2a30eSjmcneill clock-names = "apb_pclk"; 66*9ed2a30eSjmcneill }; 67*9ed2a30eSjmcneill 68*9ed2a30eSjmcneill timer1: timer@16003000 { 69*9ed2a30eSjmcneill compatible = "arm,sp804", "arm,primecell"; 70*9ed2a30eSjmcneill reg = <0x16003000 0x1000>; 71*9ed2a30eSjmcneill interrupts = <5>; 72*9ed2a30eSjmcneill clocks = <&refclk125mhz>; 73*9ed2a30eSjmcneill clock-names = "apb_pclk"; 74*9ed2a30eSjmcneill }; 75*9ed2a30eSjmcneill 76*9ed2a30eSjmcneill uart0: serial@1600d000 { 77*9ed2a30eSjmcneill compatible = "snps,dw-apb-uart"; 78*9ed2a30eSjmcneill reg = <0x1600d000 0x1000>; 79*9ed2a30eSjmcneill bus_id = "uart0"; 80*9ed2a30eSjmcneill clocks = <&refclk125mhz>; 81*9ed2a30eSjmcneill clock-names = "baudclk", "apb_pclk"; 82*9ed2a30eSjmcneill reg-shift = <2>; 83*9ed2a30eSjmcneill interrupts = <17>; 84*9ed2a30eSjmcneill }; 85*9ed2a30eSjmcneill 86*9ed2a30eSjmcneill uart1: serial@1600c000 { 87*9ed2a30eSjmcneill compatible = "snps,dw-apb-uart"; 88*9ed2a30eSjmcneill reg = <0x1600c000 0x1000>; 89*9ed2a30eSjmcneill clocks = <&refclk125mhz>; 90*9ed2a30eSjmcneill clock-names = "baudclk", "apb_pclk"; 91*9ed2a30eSjmcneill reg-shift = <2>; 92*9ed2a30eSjmcneill interrupts = <16>; 93*9ed2a30eSjmcneill status = "disabled"; 94*9ed2a30eSjmcneill }; 95*9ed2a30eSjmcneill }; 96*9ed2a30eSjmcneill}; 97