1*09fa6529Sskrll// SPDX-License-Identifier: GPL-2.0-or-later 28fb04b9bSjmcneill/* 38fb04b9bSjmcneill * dtsi file for Cavium ThunderX2 CN99XX processor 48fb04b9bSjmcneill * 58fb04b9bSjmcneill * Copyright (c) 2017 Cavium Inc. 68fb04b9bSjmcneill * Copyright (c) 2013-2016 Broadcom 78fb04b9bSjmcneill * Author: Zi Shen Lim <zlim@broadcom.com> 88fb04b9bSjmcneill */ 98fb04b9bSjmcneill 108fb04b9bSjmcneill#include <dt-bindings/interrupt-controller/arm-gic.h> 118fb04b9bSjmcneill 128fb04b9bSjmcneill/ { 138fb04b9bSjmcneill model = "Cavium ThunderX2 CN99XX"; 148fb04b9bSjmcneill compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; 158fb04b9bSjmcneill interrupt-parent = <&gic>; 168fb04b9bSjmcneill #address-cells = <2>; 178fb04b9bSjmcneill #size-cells = <2>; 188fb04b9bSjmcneill 198fb04b9bSjmcneill /* just 4 cpus now, 128 needed in full config */ 208fb04b9bSjmcneill cpus { 218fb04b9bSjmcneill #address-cells = <0x2>; 228fb04b9bSjmcneill #size-cells = <0x0>; 238fb04b9bSjmcneill 248fb04b9bSjmcneill cpu@0 { 258fb04b9bSjmcneill device_type = "cpu"; 2684c8294dSjmcneill compatible = "cavium,thunder2", "brcm,vulcan"; 278fb04b9bSjmcneill reg = <0x0 0x0>; 288fb04b9bSjmcneill enable-method = "psci"; 298fb04b9bSjmcneill }; 308fb04b9bSjmcneill 318fb04b9bSjmcneill cpu@1 { 328fb04b9bSjmcneill device_type = "cpu"; 3384c8294dSjmcneill compatible = "cavium,thunder2", "brcm,vulcan"; 348fb04b9bSjmcneill reg = <0x0 0x1>; 358fb04b9bSjmcneill enable-method = "psci"; 368fb04b9bSjmcneill }; 378fb04b9bSjmcneill 388fb04b9bSjmcneill cpu@2 { 398fb04b9bSjmcneill device_type = "cpu"; 4084c8294dSjmcneill compatible = "cavium,thunder2", "brcm,vulcan"; 418fb04b9bSjmcneill reg = <0x0 0x2>; 428fb04b9bSjmcneill enable-method = "psci"; 438fb04b9bSjmcneill }; 448fb04b9bSjmcneill 458fb04b9bSjmcneill cpu@3 { 468fb04b9bSjmcneill device_type = "cpu"; 4784c8294dSjmcneill compatible = "cavium,thunder2", "brcm,vulcan"; 488fb04b9bSjmcneill reg = <0x0 0x3>; 498fb04b9bSjmcneill enable-method = "psci"; 508fb04b9bSjmcneill }; 518fb04b9bSjmcneill }; 528fb04b9bSjmcneill 538fb04b9bSjmcneill psci { 548fb04b9bSjmcneill compatible = "arm,psci-0.2"; 558fb04b9bSjmcneill method = "smc"; 568fb04b9bSjmcneill }; 578fb04b9bSjmcneill 588fb04b9bSjmcneill gic: interrupt-controller@400080000 { 598fb04b9bSjmcneill compatible = "arm,gic-v3"; 608fb04b9bSjmcneill #interrupt-cells = <3>; 618fb04b9bSjmcneill #address-cells = <2>; 628fb04b9bSjmcneill #size-cells = <2>; 638fb04b9bSjmcneill ranges; 648fb04b9bSjmcneill interrupt-controller; 658fb04b9bSjmcneill #redistributor-regions = <1>; 668fb04b9bSjmcneill reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ 678fb04b9bSjmcneill <0x04 0x01000000 0x0 0x1000000>; /* GICR */ 688fb04b9bSjmcneill interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 698fb04b9bSjmcneill 708fb04b9bSjmcneill gicits: gic-its@40010000 { 718fb04b9bSjmcneill compatible = "arm,gic-v3-its"; 728fb04b9bSjmcneill msi-controller; 738fb04b9bSjmcneill reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ 748fb04b9bSjmcneill }; 758fb04b9bSjmcneill }; 768fb04b9bSjmcneill 778fb04b9bSjmcneill timer { 788fb04b9bSjmcneill compatible = "arm,armv8-timer"; 798fb04b9bSjmcneill interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 808fb04b9bSjmcneill <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 818fb04b9bSjmcneill <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 828fb04b9bSjmcneill <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 838fb04b9bSjmcneill }; 848fb04b9bSjmcneill 858fb04b9bSjmcneill pmu { 868fb04b9bSjmcneill compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; 878fb04b9bSjmcneill interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ 888fb04b9bSjmcneill }; 898fb04b9bSjmcneill 908fb04b9bSjmcneill clk125mhz: uart_clk125mhz { 918fb04b9bSjmcneill compatible = "fixed-clock"; 928fb04b9bSjmcneill #clock-cells = <0>; 938fb04b9bSjmcneill clock-frequency = <125000000>; 948fb04b9bSjmcneill clock-output-names = "clk125mhz"; 958fb04b9bSjmcneill }; 968fb04b9bSjmcneill 97cf2d964bSjmcneill pcie@30000000 { 988fb04b9bSjmcneill compatible = "pci-host-ecam-generic"; 998fb04b9bSjmcneill device_type = "pci"; 1008fb04b9bSjmcneill #interrupt-cells = <1>; 1018fb04b9bSjmcneill #address-cells = <3>; 1028fb04b9bSjmcneill #size-cells = <2>; 1038fb04b9bSjmcneill 1048fb04b9bSjmcneill /* ECAM at 0x3000_0000 - 0x4000_0000 */ 1058fb04b9bSjmcneill reg = <0x0 0x30000000 0x0 0x10000000>; 1068fb04b9bSjmcneill reg-names = "PCI ECAM"; 1078fb04b9bSjmcneill 1088fb04b9bSjmcneill /* 1098fb04b9bSjmcneill * PCI ranges: 1108fb04b9bSjmcneill * IO no supported 1118fb04b9bSjmcneill * MEM 0x4000_0000 - 0x6000_0000 1128fb04b9bSjmcneill * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 1138fb04b9bSjmcneill */ 1148fb04b9bSjmcneill ranges = 1158fb04b9bSjmcneill <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 1168fb04b9bSjmcneill 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; 117cf2d964bSjmcneill bus-range = <0 0xff>; 1188fb04b9bSjmcneill interrupt-map-mask = <0 0 0 7>; 1198fb04b9bSjmcneill interrupt-map = 1208fb04b9bSjmcneill /* addr pin ic icaddr icintr */ 1218fb04b9bSjmcneill <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 1228fb04b9bSjmcneill 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 1238fb04b9bSjmcneill 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 1248fb04b9bSjmcneill 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1258fb04b9bSjmcneill msi-parent = <&gicits>; 1268fb04b9bSjmcneill dma-coherent; 1278fb04b9bSjmcneill }; 1288fb04b9bSjmcneill 1298fb04b9bSjmcneill soc { 1308fb04b9bSjmcneill compatible = "simple-bus"; 1318fb04b9bSjmcneill #address-cells = <2>; 1328fb04b9bSjmcneill #size-cells = <2>; 1338fb04b9bSjmcneill ranges; 1348fb04b9bSjmcneill 1358fb04b9bSjmcneill uart0: serial@402020000 { 1368fb04b9bSjmcneill compatible = "arm,pl011", "arm,primecell"; 1378fb04b9bSjmcneill reg = <0x04 0x02020000 0x0 0x1000>; 1388fb04b9bSjmcneill interrupt-parent = <&gic>; 1398fb04b9bSjmcneill interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1408fb04b9bSjmcneill clocks = <&clk125mhz>; 1418fb04b9bSjmcneill clock-names = "apb_pclk"; 1428fb04b9bSjmcneill }; 1438fb04b9bSjmcneill }; 1448fb04b9bSjmcneill 1458fb04b9bSjmcneill}; 146