1cf2d964bSjmcneill// SPDX-License-Identifier: GPL-2.0
2f46c7ed4Sjmcneill/*
3*9ed2a30eSjmcneill * Samsung Exynos5433 TM2E board device tree source
4f46c7ed4Sjmcneill *
5f46c7ed4Sjmcneill * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6f46c7ed4Sjmcneill *
7f46c7ed4Sjmcneill * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
8f46c7ed4Sjmcneill * Samsung Exynos5433 SoC.
9f46c7ed4Sjmcneill */
10f46c7ed4Sjmcneill
11f46c7ed4Sjmcneill#include "exynos5433-tm2-common.dtsi"
12f46c7ed4Sjmcneill
13f46c7ed4Sjmcneill/ {
14f46c7ed4Sjmcneill	model = "Samsung TM2E board";
15f46c7ed4Sjmcneill	compatible = "samsung,tm2e", "samsung,exynos5433";
16f46c7ed4Sjmcneill};
17f46c7ed4Sjmcneill
18f46c7ed4Sjmcneill&cmu_disp {
19f46c7ed4Sjmcneill	/*
20f46c7ed4Sjmcneill	 * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
21f46c7ed4Sjmcneill	 * clocks properties for DISP CMU for each board to keep them together
22f46c7ed4Sjmcneill	 * for easier review and maintenance.
23f46c7ed4Sjmcneill	 */
24f46c7ed4Sjmcneill	assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
25f46c7ed4Sjmcneill			  <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
26f46c7ed4Sjmcneill			  <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
27f46c7ed4Sjmcneill			  <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
28f46c7ed4Sjmcneill			  <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
29f46c7ed4Sjmcneill			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
30f46c7ed4Sjmcneill			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
31f46c7ed4Sjmcneill			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
32f46c7ed4Sjmcneill			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
33f46c7ed4Sjmcneill			  <&cmu_disp CLK_MOUT_DISP_PLL>,
34f46c7ed4Sjmcneill			  <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
35f46c7ed4Sjmcneill			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
36f46c7ed4Sjmcneill			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
37f46c7ed4Sjmcneill	assigned-clock-parents = <0>, <0>,
38f46c7ed4Sjmcneill				 <&cmu_mif CLK_ACLK_DISP_333>,
39f46c7ed4Sjmcneill				 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
40f46c7ed4Sjmcneill				 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
41f46c7ed4Sjmcneill				 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
42f46c7ed4Sjmcneill				 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
43f46c7ed4Sjmcneill				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
44f46c7ed4Sjmcneill				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
45f46c7ed4Sjmcneill				 <&cmu_disp CLK_FOUT_DISP_PLL>,
46f46c7ed4Sjmcneill				 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
47f46c7ed4Sjmcneill				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
48f46c7ed4Sjmcneill				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
49f46c7ed4Sjmcneill	assigned-clock-rates = <278000000>, <400000000>;
50f46c7ed4Sjmcneill};
51f46c7ed4Sjmcneill
528fb04b9bSjmcneill&dsi {
538fb04b9bSjmcneill	panel@0 {
548fb04b9bSjmcneill		compatible = "samsung,s6e3hf2";
558fb04b9bSjmcneill		reg = <0>;
568fb04b9bSjmcneill		vdd3-supply = <&ldo27_reg>;
578fb04b9bSjmcneill		vci-supply = <&ldo28_reg>;
588fb04b9bSjmcneill		reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
598fb04b9bSjmcneill		enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
608fb04b9bSjmcneill	};
618fb04b9bSjmcneill};
628fb04b9bSjmcneill
63f46c7ed4Sjmcneill&ldo31_reg {
64f46c7ed4Sjmcneill	regulator-name = "TSP_VDD_1.8V_AP";
65f46c7ed4Sjmcneill	regulator-min-microvolt = <1800000>;
66f46c7ed4Sjmcneill	regulator-max-microvolt = <1800000>;
67f46c7ed4Sjmcneill};
68f46c7ed4Sjmcneill
69f46c7ed4Sjmcneill&ldo38_reg {
70f46c7ed4Sjmcneill	regulator-name = "VCC_3.3V_MOTOR_AP";
71f46c7ed4Sjmcneill	regulator-min-microvolt = <3300000>;
72f46c7ed4Sjmcneill	regulator-max-microvolt = <3300000>;
73f46c7ed4Sjmcneill};
748fb04b9bSjmcneill
758fb04b9bSjmcneill&stmfts {
768fb04b9bSjmcneill	touchscreen-size-x = <1599>;
778fb04b9bSjmcneill	touchscreen-size-y = <2559>;
788fb04b9bSjmcneill	touch-key-connected;
798fb04b9bSjmcneill	ledvdd-supply = <&ldo33_reg>;
808fb04b9bSjmcneill};
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