109fa6529Sskrll// SPDX-License-Identifier: GPL-2.0-only 2f46c7ed4Sjmcneill/** 3f46c7ed4Sjmcneill * dts file for Hisilicon D05 Development Board 4f46c7ed4Sjmcneill * 5*9ed2a30eSjmcneill * Copyright (C) 2016 HiSilicon Ltd. 6f46c7ed4Sjmcneill */ 7f46c7ed4Sjmcneill 8f46c7ed4Sjmcneill#include <dt-bindings/interrupt-controller/arm-gic.h> 9f46c7ed4Sjmcneill 10f46c7ed4Sjmcneill/ { 11f46c7ed4Sjmcneill compatible = "hisilicon,hip07-d05"; 12f46c7ed4Sjmcneill interrupt-parent = <&gic>; 13f46c7ed4Sjmcneill #address-cells = <2>; 14f46c7ed4Sjmcneill #size-cells = <2>; 15f46c7ed4Sjmcneill 16f46c7ed4Sjmcneill psci { 17f46c7ed4Sjmcneill compatible = "arm,psci-0.2"; 18f46c7ed4Sjmcneill method = "smc"; 19f46c7ed4Sjmcneill }; 20f46c7ed4Sjmcneill 21f46c7ed4Sjmcneill cpus { 22f46c7ed4Sjmcneill #address-cells = <1>; 23f46c7ed4Sjmcneill #size-cells = <0>; 24f46c7ed4Sjmcneill 25f46c7ed4Sjmcneill cpu-map { 26f46c7ed4Sjmcneill cluster0 { 27f46c7ed4Sjmcneill core0 { 28f46c7ed4Sjmcneill cpu = <&cpu0>; 29f46c7ed4Sjmcneill }; 30f46c7ed4Sjmcneill core1 { 31f46c7ed4Sjmcneill cpu = <&cpu1>; 32f46c7ed4Sjmcneill }; 33f46c7ed4Sjmcneill core2 { 34f46c7ed4Sjmcneill cpu = <&cpu2>; 35f46c7ed4Sjmcneill }; 36f46c7ed4Sjmcneill core3 { 37f46c7ed4Sjmcneill cpu = <&cpu3>; 38f46c7ed4Sjmcneill }; 39f46c7ed4Sjmcneill }; 40f46c7ed4Sjmcneill 41f46c7ed4Sjmcneill cluster1 { 42f46c7ed4Sjmcneill core0 { 43f46c7ed4Sjmcneill cpu = <&cpu4>; 44f46c7ed4Sjmcneill }; 45f46c7ed4Sjmcneill core1 { 46f46c7ed4Sjmcneill cpu = <&cpu5>; 47f46c7ed4Sjmcneill }; 48f46c7ed4Sjmcneill core2 { 49f46c7ed4Sjmcneill cpu = <&cpu6>; 50f46c7ed4Sjmcneill }; 51f46c7ed4Sjmcneill core3 { 52f46c7ed4Sjmcneill cpu = <&cpu7>; 53f46c7ed4Sjmcneill }; 54f46c7ed4Sjmcneill }; 55f46c7ed4Sjmcneill 56f46c7ed4Sjmcneill cluster2 { 57f46c7ed4Sjmcneill core0 { 58f46c7ed4Sjmcneill cpu = <&cpu8>; 59f46c7ed4Sjmcneill }; 60f46c7ed4Sjmcneill core1 { 61f46c7ed4Sjmcneill cpu = <&cpu9>; 62f46c7ed4Sjmcneill }; 63f46c7ed4Sjmcneill core2 { 64f46c7ed4Sjmcneill cpu = <&cpu10>; 65f46c7ed4Sjmcneill }; 66f46c7ed4Sjmcneill core3 { 67f46c7ed4Sjmcneill cpu = <&cpu11>; 68f46c7ed4Sjmcneill }; 69f46c7ed4Sjmcneill }; 70f46c7ed4Sjmcneill 71f46c7ed4Sjmcneill cluster3 { 72f46c7ed4Sjmcneill core0 { 73f46c7ed4Sjmcneill cpu = <&cpu12>; 74f46c7ed4Sjmcneill }; 75f46c7ed4Sjmcneill core1 { 76f46c7ed4Sjmcneill cpu = <&cpu13>; 77f46c7ed4Sjmcneill }; 78f46c7ed4Sjmcneill core2 { 79f46c7ed4Sjmcneill cpu = <&cpu14>; 80f46c7ed4Sjmcneill }; 81f46c7ed4Sjmcneill core3 { 82f46c7ed4Sjmcneill cpu = <&cpu15>; 83f46c7ed4Sjmcneill }; 84f46c7ed4Sjmcneill }; 85f46c7ed4Sjmcneill 86f46c7ed4Sjmcneill cluster4 { 87f46c7ed4Sjmcneill core0 { 88f46c7ed4Sjmcneill cpu = <&cpu16>; 89f46c7ed4Sjmcneill }; 90f46c7ed4Sjmcneill core1 { 91f46c7ed4Sjmcneill cpu = <&cpu17>; 92f46c7ed4Sjmcneill }; 93f46c7ed4Sjmcneill core2 { 94f46c7ed4Sjmcneill cpu = <&cpu18>; 95f46c7ed4Sjmcneill }; 96f46c7ed4Sjmcneill core3 { 97f46c7ed4Sjmcneill cpu = <&cpu19>; 98f46c7ed4Sjmcneill }; 99f46c7ed4Sjmcneill }; 100f46c7ed4Sjmcneill 101f46c7ed4Sjmcneill cluster5 { 102f46c7ed4Sjmcneill core0 { 103f46c7ed4Sjmcneill cpu = <&cpu20>; 104f46c7ed4Sjmcneill }; 105f46c7ed4Sjmcneill core1 { 106f46c7ed4Sjmcneill cpu = <&cpu21>; 107f46c7ed4Sjmcneill }; 108f46c7ed4Sjmcneill core2 { 109f46c7ed4Sjmcneill cpu = <&cpu22>; 110f46c7ed4Sjmcneill }; 111f46c7ed4Sjmcneill core3 { 112f46c7ed4Sjmcneill cpu = <&cpu23>; 113f46c7ed4Sjmcneill }; 114f46c7ed4Sjmcneill }; 115f46c7ed4Sjmcneill 116f46c7ed4Sjmcneill cluster6 { 117f46c7ed4Sjmcneill core0 { 118f46c7ed4Sjmcneill cpu = <&cpu24>; 119f46c7ed4Sjmcneill }; 120f46c7ed4Sjmcneill core1 { 121f46c7ed4Sjmcneill cpu = <&cpu25>; 122f46c7ed4Sjmcneill }; 123f46c7ed4Sjmcneill core2 { 124f46c7ed4Sjmcneill cpu = <&cpu26>; 125f46c7ed4Sjmcneill }; 126f46c7ed4Sjmcneill core3 { 127f46c7ed4Sjmcneill cpu = <&cpu27>; 128f46c7ed4Sjmcneill }; 129f46c7ed4Sjmcneill }; 130f46c7ed4Sjmcneill 131f46c7ed4Sjmcneill cluster7 { 132f46c7ed4Sjmcneill core0 { 133f46c7ed4Sjmcneill cpu = <&cpu28>; 134f46c7ed4Sjmcneill }; 135f46c7ed4Sjmcneill core1 { 136f46c7ed4Sjmcneill cpu = <&cpu29>; 137f46c7ed4Sjmcneill }; 138f46c7ed4Sjmcneill core2 { 139f46c7ed4Sjmcneill cpu = <&cpu30>; 140f46c7ed4Sjmcneill }; 141f46c7ed4Sjmcneill core3 { 142f46c7ed4Sjmcneill cpu = <&cpu31>; 143f46c7ed4Sjmcneill }; 144f46c7ed4Sjmcneill }; 145f46c7ed4Sjmcneill 146f46c7ed4Sjmcneill cluster8 { 147f46c7ed4Sjmcneill core0 { 148f46c7ed4Sjmcneill cpu = <&cpu32>; 149f46c7ed4Sjmcneill }; 150f46c7ed4Sjmcneill core1 { 151f46c7ed4Sjmcneill cpu = <&cpu33>; 152f46c7ed4Sjmcneill }; 153f46c7ed4Sjmcneill core2 { 154f46c7ed4Sjmcneill cpu = <&cpu34>; 155f46c7ed4Sjmcneill }; 156f46c7ed4Sjmcneill core3 { 157f46c7ed4Sjmcneill cpu = <&cpu35>; 158f46c7ed4Sjmcneill }; 159f46c7ed4Sjmcneill }; 160f46c7ed4Sjmcneill 161f46c7ed4Sjmcneill cluster9 { 162f46c7ed4Sjmcneill core0 { 163f46c7ed4Sjmcneill cpu = <&cpu36>; 164f46c7ed4Sjmcneill }; 165f46c7ed4Sjmcneill core1 { 166f46c7ed4Sjmcneill cpu = <&cpu37>; 167f46c7ed4Sjmcneill }; 168f46c7ed4Sjmcneill core2 { 169f46c7ed4Sjmcneill cpu = <&cpu38>; 170f46c7ed4Sjmcneill }; 171f46c7ed4Sjmcneill core3 { 172f46c7ed4Sjmcneill cpu = <&cpu39>; 173f46c7ed4Sjmcneill }; 174f46c7ed4Sjmcneill }; 175f46c7ed4Sjmcneill 176f46c7ed4Sjmcneill cluster10 { 177f46c7ed4Sjmcneill core0 { 178f46c7ed4Sjmcneill cpu = <&cpu40>; 179f46c7ed4Sjmcneill }; 180f46c7ed4Sjmcneill core1 { 181f46c7ed4Sjmcneill cpu = <&cpu41>; 182f46c7ed4Sjmcneill }; 183f46c7ed4Sjmcneill core2 { 184f46c7ed4Sjmcneill cpu = <&cpu42>; 185f46c7ed4Sjmcneill }; 186f46c7ed4Sjmcneill core3 { 187f46c7ed4Sjmcneill cpu = <&cpu43>; 188f46c7ed4Sjmcneill }; 189f46c7ed4Sjmcneill }; 190f46c7ed4Sjmcneill 191f46c7ed4Sjmcneill cluster11 { 192f46c7ed4Sjmcneill core0 { 193f46c7ed4Sjmcneill cpu = <&cpu44>; 194f46c7ed4Sjmcneill }; 195f46c7ed4Sjmcneill core1 { 196f46c7ed4Sjmcneill cpu = <&cpu45>; 197f46c7ed4Sjmcneill }; 198f46c7ed4Sjmcneill core2 { 199f46c7ed4Sjmcneill cpu = <&cpu46>; 200f46c7ed4Sjmcneill }; 201f46c7ed4Sjmcneill core3 { 202f46c7ed4Sjmcneill cpu = <&cpu47>; 203f46c7ed4Sjmcneill }; 204f46c7ed4Sjmcneill }; 205f46c7ed4Sjmcneill 206f46c7ed4Sjmcneill cluster12 { 207f46c7ed4Sjmcneill core0 { 208f46c7ed4Sjmcneill cpu = <&cpu48>; 209f46c7ed4Sjmcneill }; 210f46c7ed4Sjmcneill core1 { 211f46c7ed4Sjmcneill cpu = <&cpu49>; 212f46c7ed4Sjmcneill }; 213f46c7ed4Sjmcneill core2 { 214f46c7ed4Sjmcneill cpu = <&cpu50>; 215f46c7ed4Sjmcneill }; 216f46c7ed4Sjmcneill core3 { 217f46c7ed4Sjmcneill cpu = <&cpu51>; 218f46c7ed4Sjmcneill }; 219f46c7ed4Sjmcneill }; 220f46c7ed4Sjmcneill 221f46c7ed4Sjmcneill cluster13 { 222f46c7ed4Sjmcneill core0 { 223f46c7ed4Sjmcneill cpu = <&cpu52>; 224f46c7ed4Sjmcneill }; 225f46c7ed4Sjmcneill core1 { 226f46c7ed4Sjmcneill cpu = <&cpu53>; 227f46c7ed4Sjmcneill }; 228f46c7ed4Sjmcneill core2 { 229f46c7ed4Sjmcneill cpu = <&cpu54>; 230f46c7ed4Sjmcneill }; 231f46c7ed4Sjmcneill core3 { 232f46c7ed4Sjmcneill cpu = <&cpu55>; 233f46c7ed4Sjmcneill }; 234f46c7ed4Sjmcneill }; 235f46c7ed4Sjmcneill 236f46c7ed4Sjmcneill cluster14 { 237f46c7ed4Sjmcneill core0 { 238f46c7ed4Sjmcneill cpu = <&cpu56>; 239f46c7ed4Sjmcneill }; 240f46c7ed4Sjmcneill core1 { 241f46c7ed4Sjmcneill cpu = <&cpu57>; 242f46c7ed4Sjmcneill }; 243f46c7ed4Sjmcneill core2 { 244f46c7ed4Sjmcneill cpu = <&cpu58>; 245f46c7ed4Sjmcneill }; 246f46c7ed4Sjmcneill core3 { 247f46c7ed4Sjmcneill cpu = <&cpu59>; 248f46c7ed4Sjmcneill }; 249f46c7ed4Sjmcneill }; 250f46c7ed4Sjmcneill 251f46c7ed4Sjmcneill cluster15 { 252f46c7ed4Sjmcneill core0 { 253f46c7ed4Sjmcneill cpu = <&cpu60>; 254f46c7ed4Sjmcneill }; 255f46c7ed4Sjmcneill core1 { 256f46c7ed4Sjmcneill cpu = <&cpu61>; 257f46c7ed4Sjmcneill }; 258f46c7ed4Sjmcneill core2 { 259f46c7ed4Sjmcneill cpu = <&cpu62>; 260f46c7ed4Sjmcneill }; 261f46c7ed4Sjmcneill core3 { 262f46c7ed4Sjmcneill cpu = <&cpu63>; 263f46c7ed4Sjmcneill }; 264f46c7ed4Sjmcneill }; 265f46c7ed4Sjmcneill }; 266f46c7ed4Sjmcneill 267f46c7ed4Sjmcneill cpu0: cpu@10000 { 268f46c7ed4Sjmcneill device_type = "cpu"; 26984c8294dSjmcneill compatible = "arm,cortex-a72"; 270f46c7ed4Sjmcneill reg = <0x10000>; 271f46c7ed4Sjmcneill enable-method = "psci"; 272f46c7ed4Sjmcneill next-level-cache = <&cluster0_l2>; 273f46c7ed4Sjmcneill numa-node-id = <0>; 274f46c7ed4Sjmcneill }; 275f46c7ed4Sjmcneill 276f46c7ed4Sjmcneill cpu1: cpu@10001 { 277f46c7ed4Sjmcneill device_type = "cpu"; 27884c8294dSjmcneill compatible = "arm,cortex-a72"; 279f46c7ed4Sjmcneill reg = <0x10001>; 280f46c7ed4Sjmcneill enable-method = "psci"; 281f46c7ed4Sjmcneill next-level-cache = <&cluster0_l2>; 282f46c7ed4Sjmcneill numa-node-id = <0>; 283f46c7ed4Sjmcneill }; 284f46c7ed4Sjmcneill 285f46c7ed4Sjmcneill cpu2: cpu@10002 { 286f46c7ed4Sjmcneill device_type = "cpu"; 28784c8294dSjmcneill compatible = "arm,cortex-a72"; 288f46c7ed4Sjmcneill reg = <0x10002>; 289f46c7ed4Sjmcneill enable-method = "psci"; 290f46c7ed4Sjmcneill next-level-cache = <&cluster0_l2>; 291f46c7ed4Sjmcneill numa-node-id = <0>; 292f46c7ed4Sjmcneill }; 293f46c7ed4Sjmcneill 294f46c7ed4Sjmcneill cpu3: cpu@10003 { 295f46c7ed4Sjmcneill device_type = "cpu"; 29684c8294dSjmcneill compatible = "arm,cortex-a72"; 297f46c7ed4Sjmcneill reg = <0x10003>; 298f46c7ed4Sjmcneill enable-method = "psci"; 299f46c7ed4Sjmcneill next-level-cache = <&cluster0_l2>; 300f46c7ed4Sjmcneill numa-node-id = <0>; 301f46c7ed4Sjmcneill }; 302f46c7ed4Sjmcneill 303f46c7ed4Sjmcneill cpu4: cpu@10100 { 304f46c7ed4Sjmcneill device_type = "cpu"; 30584c8294dSjmcneill compatible = "arm,cortex-a72"; 306f46c7ed4Sjmcneill reg = <0x10100>; 307f46c7ed4Sjmcneill enable-method = "psci"; 308f46c7ed4Sjmcneill next-level-cache = <&cluster1_l2>; 309f46c7ed4Sjmcneill numa-node-id = <0>; 310f46c7ed4Sjmcneill }; 311f46c7ed4Sjmcneill 312f46c7ed4Sjmcneill cpu5: cpu@10101 { 313f46c7ed4Sjmcneill device_type = "cpu"; 31484c8294dSjmcneill compatible = "arm,cortex-a72"; 315f46c7ed4Sjmcneill reg = <0x10101>; 316f46c7ed4Sjmcneill enable-method = "psci"; 317f46c7ed4Sjmcneill next-level-cache = <&cluster1_l2>; 318f46c7ed4Sjmcneill numa-node-id = <0>; 319f46c7ed4Sjmcneill }; 320f46c7ed4Sjmcneill 321f46c7ed4Sjmcneill cpu6: cpu@10102 { 322f46c7ed4Sjmcneill device_type = "cpu"; 32384c8294dSjmcneill compatible = "arm,cortex-a72"; 324f46c7ed4Sjmcneill reg = <0x10102>; 325f46c7ed4Sjmcneill enable-method = "psci"; 326f46c7ed4Sjmcneill next-level-cache = <&cluster1_l2>; 327f46c7ed4Sjmcneill numa-node-id = <0>; 328f46c7ed4Sjmcneill }; 329f46c7ed4Sjmcneill 330f46c7ed4Sjmcneill cpu7: cpu@10103 { 331f46c7ed4Sjmcneill device_type = "cpu"; 33284c8294dSjmcneill compatible = "arm,cortex-a72"; 333f46c7ed4Sjmcneill reg = <0x10103>; 334f46c7ed4Sjmcneill enable-method = "psci"; 335f46c7ed4Sjmcneill next-level-cache = <&cluster1_l2>; 336f46c7ed4Sjmcneill numa-node-id = <0>; 337f46c7ed4Sjmcneill }; 338f46c7ed4Sjmcneill 339f46c7ed4Sjmcneill cpu8: cpu@10200 { 340f46c7ed4Sjmcneill device_type = "cpu"; 34184c8294dSjmcneill compatible = "arm,cortex-a72"; 342f46c7ed4Sjmcneill reg = <0x10200>; 343f46c7ed4Sjmcneill enable-method = "psci"; 344f46c7ed4Sjmcneill next-level-cache = <&cluster2_l2>; 345f46c7ed4Sjmcneill numa-node-id = <0>; 346f46c7ed4Sjmcneill }; 347f46c7ed4Sjmcneill 348f46c7ed4Sjmcneill cpu9: cpu@10201 { 349f46c7ed4Sjmcneill device_type = "cpu"; 35084c8294dSjmcneill compatible = "arm,cortex-a72"; 351f46c7ed4Sjmcneill reg = <0x10201>; 352f46c7ed4Sjmcneill enable-method = "psci"; 353f46c7ed4Sjmcneill next-level-cache = <&cluster2_l2>; 354f46c7ed4Sjmcneill numa-node-id = <0>; 355f46c7ed4Sjmcneill }; 356f46c7ed4Sjmcneill 357f46c7ed4Sjmcneill cpu10: cpu@10202 { 358f46c7ed4Sjmcneill device_type = "cpu"; 35984c8294dSjmcneill compatible = "arm,cortex-a72"; 360f46c7ed4Sjmcneill reg = <0x10202>; 361f46c7ed4Sjmcneill enable-method = "psci"; 362f46c7ed4Sjmcneill next-level-cache = <&cluster2_l2>; 363f46c7ed4Sjmcneill numa-node-id = <0>; 364f46c7ed4Sjmcneill }; 365f46c7ed4Sjmcneill 366f46c7ed4Sjmcneill cpu11: cpu@10203 { 367f46c7ed4Sjmcneill device_type = "cpu"; 36884c8294dSjmcneill compatible = "arm,cortex-a72"; 369f46c7ed4Sjmcneill reg = <0x10203>; 370f46c7ed4Sjmcneill enable-method = "psci"; 371f46c7ed4Sjmcneill next-level-cache = <&cluster2_l2>; 372f46c7ed4Sjmcneill numa-node-id = <0>; 373f46c7ed4Sjmcneill }; 374f46c7ed4Sjmcneill 375f46c7ed4Sjmcneill cpu12: cpu@10300 { 376f46c7ed4Sjmcneill device_type = "cpu"; 37784c8294dSjmcneill compatible = "arm,cortex-a72"; 378f46c7ed4Sjmcneill reg = <0x10300>; 379f46c7ed4Sjmcneill enable-method = "psci"; 380f46c7ed4Sjmcneill next-level-cache = <&cluster3_l2>; 381f46c7ed4Sjmcneill numa-node-id = <0>; 382f46c7ed4Sjmcneill }; 383f46c7ed4Sjmcneill 384f46c7ed4Sjmcneill cpu13: cpu@10301 { 385f46c7ed4Sjmcneill device_type = "cpu"; 38684c8294dSjmcneill compatible = "arm,cortex-a72"; 387f46c7ed4Sjmcneill reg = <0x10301>; 388f46c7ed4Sjmcneill enable-method = "psci"; 389f46c7ed4Sjmcneill next-level-cache = <&cluster3_l2>; 390f46c7ed4Sjmcneill numa-node-id = <0>; 391f46c7ed4Sjmcneill }; 392f46c7ed4Sjmcneill 393f46c7ed4Sjmcneill cpu14: cpu@10302 { 394f46c7ed4Sjmcneill device_type = "cpu"; 39584c8294dSjmcneill compatible = "arm,cortex-a72"; 396f46c7ed4Sjmcneill reg = <0x10302>; 397f46c7ed4Sjmcneill enable-method = "psci"; 398f46c7ed4Sjmcneill next-level-cache = <&cluster3_l2>; 399f46c7ed4Sjmcneill numa-node-id = <0>; 400f46c7ed4Sjmcneill }; 401f46c7ed4Sjmcneill 402f46c7ed4Sjmcneill cpu15: cpu@10303 { 403f46c7ed4Sjmcneill device_type = "cpu"; 40484c8294dSjmcneill compatible = "arm,cortex-a72"; 405f46c7ed4Sjmcneill reg = <0x10303>; 406f46c7ed4Sjmcneill enable-method = "psci"; 407f46c7ed4Sjmcneill next-level-cache = <&cluster3_l2>; 408f46c7ed4Sjmcneill numa-node-id = <0>; 409f46c7ed4Sjmcneill }; 410f46c7ed4Sjmcneill 411f46c7ed4Sjmcneill cpu16: cpu@30000 { 412f46c7ed4Sjmcneill device_type = "cpu"; 41384c8294dSjmcneill compatible = "arm,cortex-a72"; 414f46c7ed4Sjmcneill reg = <0x30000>; 415f46c7ed4Sjmcneill enable-method = "psci"; 416f46c7ed4Sjmcneill next-level-cache = <&cluster4_l2>; 417f46c7ed4Sjmcneill numa-node-id = <1>; 418f46c7ed4Sjmcneill }; 419f46c7ed4Sjmcneill 420f46c7ed4Sjmcneill cpu17: cpu@30001 { 421f46c7ed4Sjmcneill device_type = "cpu"; 42284c8294dSjmcneill compatible = "arm,cortex-a72"; 423f46c7ed4Sjmcneill reg = <0x30001>; 424f46c7ed4Sjmcneill enable-method = "psci"; 425f46c7ed4Sjmcneill next-level-cache = <&cluster4_l2>; 426f46c7ed4Sjmcneill numa-node-id = <1>; 427f46c7ed4Sjmcneill }; 428f46c7ed4Sjmcneill 429f46c7ed4Sjmcneill cpu18: cpu@30002 { 430f46c7ed4Sjmcneill device_type = "cpu"; 43184c8294dSjmcneill compatible = "arm,cortex-a72"; 432f46c7ed4Sjmcneill reg = <0x30002>; 433f46c7ed4Sjmcneill enable-method = "psci"; 434f46c7ed4Sjmcneill next-level-cache = <&cluster4_l2>; 435f46c7ed4Sjmcneill numa-node-id = <1>; 436f46c7ed4Sjmcneill }; 437f46c7ed4Sjmcneill 438f46c7ed4Sjmcneill cpu19: cpu@30003 { 439f46c7ed4Sjmcneill device_type = "cpu"; 44084c8294dSjmcneill compatible = "arm,cortex-a72"; 441f46c7ed4Sjmcneill reg = <0x30003>; 442f46c7ed4Sjmcneill enable-method = "psci"; 443f46c7ed4Sjmcneill next-level-cache = <&cluster4_l2>; 444f46c7ed4Sjmcneill numa-node-id = <1>; 445f46c7ed4Sjmcneill }; 446f46c7ed4Sjmcneill 447f46c7ed4Sjmcneill cpu20: cpu@30100 { 448f46c7ed4Sjmcneill device_type = "cpu"; 44984c8294dSjmcneill compatible = "arm,cortex-a72"; 450f46c7ed4Sjmcneill reg = <0x30100>; 451f46c7ed4Sjmcneill enable-method = "psci"; 452f46c7ed4Sjmcneill next-level-cache = <&cluster5_l2>; 453f46c7ed4Sjmcneill numa-node-id = <1>; 454f46c7ed4Sjmcneill }; 455f46c7ed4Sjmcneill 456f46c7ed4Sjmcneill cpu21: cpu@30101 { 457f46c7ed4Sjmcneill device_type = "cpu"; 45884c8294dSjmcneill compatible = "arm,cortex-a72"; 459f46c7ed4Sjmcneill reg = <0x30101>; 460f46c7ed4Sjmcneill enable-method = "psci"; 461f46c7ed4Sjmcneill next-level-cache = <&cluster5_l2>; 462f46c7ed4Sjmcneill numa-node-id = <1>; 463f46c7ed4Sjmcneill }; 464f46c7ed4Sjmcneill 465f46c7ed4Sjmcneill cpu22: cpu@30102 { 466f46c7ed4Sjmcneill device_type = "cpu"; 46784c8294dSjmcneill compatible = "arm,cortex-a72"; 468f46c7ed4Sjmcneill reg = <0x30102>; 469f46c7ed4Sjmcneill enable-method = "psci"; 470f46c7ed4Sjmcneill next-level-cache = <&cluster5_l2>; 471f46c7ed4Sjmcneill numa-node-id = <1>; 472f46c7ed4Sjmcneill }; 473f46c7ed4Sjmcneill 474f46c7ed4Sjmcneill cpu23: cpu@30103 { 475f46c7ed4Sjmcneill device_type = "cpu"; 47684c8294dSjmcneill compatible = "arm,cortex-a72"; 477f46c7ed4Sjmcneill reg = <0x30103>; 478f46c7ed4Sjmcneill enable-method = "psci"; 479f46c7ed4Sjmcneill next-level-cache = <&cluster5_l2>; 480f46c7ed4Sjmcneill numa-node-id = <1>; 481f46c7ed4Sjmcneill }; 482f46c7ed4Sjmcneill 483f46c7ed4Sjmcneill cpu24: cpu@30200 { 484f46c7ed4Sjmcneill device_type = "cpu"; 48584c8294dSjmcneill compatible = "arm,cortex-a72"; 486f46c7ed4Sjmcneill reg = <0x30200>; 487f46c7ed4Sjmcneill enable-method = "psci"; 488f46c7ed4Sjmcneill next-level-cache = <&cluster6_l2>; 489f46c7ed4Sjmcneill numa-node-id = <1>; 490f46c7ed4Sjmcneill }; 491f46c7ed4Sjmcneill 492f46c7ed4Sjmcneill cpu25: cpu@30201 { 493f46c7ed4Sjmcneill device_type = "cpu"; 49484c8294dSjmcneill compatible = "arm,cortex-a72"; 495f46c7ed4Sjmcneill reg = <0x30201>; 496f46c7ed4Sjmcneill enable-method = "psci"; 497f46c7ed4Sjmcneill next-level-cache = <&cluster6_l2>; 498f46c7ed4Sjmcneill numa-node-id = <1>; 499f46c7ed4Sjmcneill }; 500f46c7ed4Sjmcneill 501f46c7ed4Sjmcneill cpu26: cpu@30202 { 502f46c7ed4Sjmcneill device_type = "cpu"; 50384c8294dSjmcneill compatible = "arm,cortex-a72"; 504f46c7ed4Sjmcneill reg = <0x30202>; 505f46c7ed4Sjmcneill enable-method = "psci"; 506f46c7ed4Sjmcneill next-level-cache = <&cluster6_l2>; 507f46c7ed4Sjmcneill numa-node-id = <1>; 508f46c7ed4Sjmcneill }; 509f46c7ed4Sjmcneill 510f46c7ed4Sjmcneill cpu27: cpu@30203 { 511f46c7ed4Sjmcneill device_type = "cpu"; 51284c8294dSjmcneill compatible = "arm,cortex-a72"; 513f46c7ed4Sjmcneill reg = <0x30203>; 514f46c7ed4Sjmcneill enable-method = "psci"; 515f46c7ed4Sjmcneill next-level-cache = <&cluster6_l2>; 516f46c7ed4Sjmcneill numa-node-id = <1>; 517f46c7ed4Sjmcneill }; 518f46c7ed4Sjmcneill 519f46c7ed4Sjmcneill cpu28: cpu@30300 { 520f46c7ed4Sjmcneill device_type = "cpu"; 52184c8294dSjmcneill compatible = "arm,cortex-a72"; 522f46c7ed4Sjmcneill reg = <0x30300>; 523f46c7ed4Sjmcneill enable-method = "psci"; 524f46c7ed4Sjmcneill next-level-cache = <&cluster7_l2>; 525f46c7ed4Sjmcneill numa-node-id = <1>; 526f46c7ed4Sjmcneill }; 527f46c7ed4Sjmcneill 528f46c7ed4Sjmcneill cpu29: cpu@30301 { 529f46c7ed4Sjmcneill device_type = "cpu"; 53084c8294dSjmcneill compatible = "arm,cortex-a72"; 531f46c7ed4Sjmcneill reg = <0x30301>; 532f46c7ed4Sjmcneill enable-method = "psci"; 533f46c7ed4Sjmcneill next-level-cache = <&cluster7_l2>; 534f46c7ed4Sjmcneill numa-node-id = <1>; 535f46c7ed4Sjmcneill }; 536f46c7ed4Sjmcneill 537f46c7ed4Sjmcneill cpu30: cpu@30302 { 538f46c7ed4Sjmcneill device_type = "cpu"; 53984c8294dSjmcneill compatible = "arm,cortex-a72"; 540f46c7ed4Sjmcneill reg = <0x30302>; 541f46c7ed4Sjmcneill enable-method = "psci"; 542f46c7ed4Sjmcneill next-level-cache = <&cluster7_l2>; 543f46c7ed4Sjmcneill numa-node-id = <1>; 544f46c7ed4Sjmcneill }; 545f46c7ed4Sjmcneill 546f46c7ed4Sjmcneill cpu31: cpu@30303 { 547f46c7ed4Sjmcneill device_type = "cpu"; 54884c8294dSjmcneill compatible = "arm,cortex-a72"; 549f46c7ed4Sjmcneill reg = <0x30303>; 550f46c7ed4Sjmcneill enable-method = "psci"; 551f46c7ed4Sjmcneill next-level-cache = <&cluster7_l2>; 552f46c7ed4Sjmcneill numa-node-id = <1>; 553f46c7ed4Sjmcneill }; 554f46c7ed4Sjmcneill 555f46c7ed4Sjmcneill cpu32: cpu@50000 { 556f46c7ed4Sjmcneill device_type = "cpu"; 55784c8294dSjmcneill compatible = "arm,cortex-a72"; 558f46c7ed4Sjmcneill reg = <0x50000>; 559f46c7ed4Sjmcneill enable-method = "psci"; 560f46c7ed4Sjmcneill next-level-cache = <&cluster8_l2>; 561f46c7ed4Sjmcneill numa-node-id = <2>; 562f46c7ed4Sjmcneill }; 563f46c7ed4Sjmcneill 564f46c7ed4Sjmcneill cpu33: cpu@50001 { 565f46c7ed4Sjmcneill device_type = "cpu"; 56684c8294dSjmcneill compatible = "arm,cortex-a72"; 567f46c7ed4Sjmcneill reg = <0x50001>; 568f46c7ed4Sjmcneill enable-method = "psci"; 569f46c7ed4Sjmcneill next-level-cache = <&cluster8_l2>; 570f46c7ed4Sjmcneill numa-node-id = <2>; 571f46c7ed4Sjmcneill }; 572f46c7ed4Sjmcneill 573f46c7ed4Sjmcneill cpu34: cpu@50002 { 574f46c7ed4Sjmcneill device_type = "cpu"; 57584c8294dSjmcneill compatible = "arm,cortex-a72"; 576f46c7ed4Sjmcneill reg = <0x50002>; 577f46c7ed4Sjmcneill enable-method = "psci"; 578f46c7ed4Sjmcneill next-level-cache = <&cluster8_l2>; 579f46c7ed4Sjmcneill numa-node-id = <2>; 580f46c7ed4Sjmcneill }; 581f46c7ed4Sjmcneill 582f46c7ed4Sjmcneill cpu35: cpu@50003 { 583f46c7ed4Sjmcneill device_type = "cpu"; 58484c8294dSjmcneill compatible = "arm,cortex-a72"; 585f46c7ed4Sjmcneill reg = <0x50003>; 586f46c7ed4Sjmcneill enable-method = "psci"; 587f46c7ed4Sjmcneill next-level-cache = <&cluster8_l2>; 588f46c7ed4Sjmcneill numa-node-id = <2>; 589f46c7ed4Sjmcneill }; 590f46c7ed4Sjmcneill 591f46c7ed4Sjmcneill cpu36: cpu@50100 { 592f46c7ed4Sjmcneill device_type = "cpu"; 59384c8294dSjmcneill compatible = "arm,cortex-a72"; 594f46c7ed4Sjmcneill reg = <0x50100>; 595f46c7ed4Sjmcneill enable-method = "psci"; 596f46c7ed4Sjmcneill next-level-cache = <&cluster9_l2>; 597f46c7ed4Sjmcneill numa-node-id = <2>; 598f46c7ed4Sjmcneill }; 599f46c7ed4Sjmcneill 600f46c7ed4Sjmcneill cpu37: cpu@50101 { 601f46c7ed4Sjmcneill device_type = "cpu"; 60284c8294dSjmcneill compatible = "arm,cortex-a72"; 603f46c7ed4Sjmcneill reg = <0x50101>; 604f46c7ed4Sjmcneill enable-method = "psci"; 605f46c7ed4Sjmcneill next-level-cache = <&cluster9_l2>; 606f46c7ed4Sjmcneill numa-node-id = <2>; 607f46c7ed4Sjmcneill }; 608f46c7ed4Sjmcneill 609f46c7ed4Sjmcneill cpu38: cpu@50102 { 610f46c7ed4Sjmcneill device_type = "cpu"; 61184c8294dSjmcneill compatible = "arm,cortex-a72"; 612f46c7ed4Sjmcneill reg = <0x50102>; 613f46c7ed4Sjmcneill enable-method = "psci"; 614f46c7ed4Sjmcneill next-level-cache = <&cluster9_l2>; 615f46c7ed4Sjmcneill numa-node-id = <2>; 616f46c7ed4Sjmcneill }; 617f46c7ed4Sjmcneill 618f46c7ed4Sjmcneill cpu39: cpu@50103 { 619f46c7ed4Sjmcneill device_type = "cpu"; 62084c8294dSjmcneill compatible = "arm,cortex-a72"; 621f46c7ed4Sjmcneill reg = <0x50103>; 622f46c7ed4Sjmcneill enable-method = "psci"; 623f46c7ed4Sjmcneill next-level-cache = <&cluster9_l2>; 624f46c7ed4Sjmcneill numa-node-id = <2>; 625f46c7ed4Sjmcneill }; 626f46c7ed4Sjmcneill 627f46c7ed4Sjmcneill cpu40: cpu@50200 { 628f46c7ed4Sjmcneill device_type = "cpu"; 62984c8294dSjmcneill compatible = "arm,cortex-a72"; 630f46c7ed4Sjmcneill reg = <0x50200>; 631f46c7ed4Sjmcneill enable-method = "psci"; 632f46c7ed4Sjmcneill next-level-cache = <&cluster10_l2>; 633f46c7ed4Sjmcneill numa-node-id = <2>; 634f46c7ed4Sjmcneill }; 635f46c7ed4Sjmcneill 636f46c7ed4Sjmcneill cpu41: cpu@50201 { 637f46c7ed4Sjmcneill device_type = "cpu"; 63884c8294dSjmcneill compatible = "arm,cortex-a72"; 639f46c7ed4Sjmcneill reg = <0x50201>; 640f46c7ed4Sjmcneill enable-method = "psci"; 641f46c7ed4Sjmcneill next-level-cache = <&cluster10_l2>; 642f46c7ed4Sjmcneill numa-node-id = <2>; 643f46c7ed4Sjmcneill }; 644f46c7ed4Sjmcneill 645f46c7ed4Sjmcneill cpu42: cpu@50202 { 646f46c7ed4Sjmcneill device_type = "cpu"; 64784c8294dSjmcneill compatible = "arm,cortex-a72"; 648f46c7ed4Sjmcneill reg = <0x50202>; 649f46c7ed4Sjmcneill enable-method = "psci"; 650f46c7ed4Sjmcneill next-level-cache = <&cluster10_l2>; 651f46c7ed4Sjmcneill numa-node-id = <2>; 652f46c7ed4Sjmcneill }; 653f46c7ed4Sjmcneill 654f46c7ed4Sjmcneill cpu43: cpu@50203 { 655f46c7ed4Sjmcneill device_type = "cpu"; 65684c8294dSjmcneill compatible = "arm,cortex-a72"; 657f46c7ed4Sjmcneill reg = <0x50203>; 658f46c7ed4Sjmcneill enable-method = "psci"; 659f46c7ed4Sjmcneill next-level-cache = <&cluster10_l2>; 660f46c7ed4Sjmcneill numa-node-id = <2>; 661f46c7ed4Sjmcneill }; 662f46c7ed4Sjmcneill 663f46c7ed4Sjmcneill cpu44: cpu@50300 { 664f46c7ed4Sjmcneill device_type = "cpu"; 66584c8294dSjmcneill compatible = "arm,cortex-a72"; 666f46c7ed4Sjmcneill reg = <0x50300>; 667f46c7ed4Sjmcneill enable-method = "psci"; 668f46c7ed4Sjmcneill next-level-cache = <&cluster11_l2>; 669f46c7ed4Sjmcneill numa-node-id = <2>; 670f46c7ed4Sjmcneill }; 671f46c7ed4Sjmcneill 672f46c7ed4Sjmcneill cpu45: cpu@50301 { 673f46c7ed4Sjmcneill device_type = "cpu"; 67484c8294dSjmcneill compatible = "arm,cortex-a72"; 675f46c7ed4Sjmcneill reg = <0x50301>; 676f46c7ed4Sjmcneill enable-method = "psci"; 677f46c7ed4Sjmcneill next-level-cache = <&cluster11_l2>; 678f46c7ed4Sjmcneill numa-node-id = <2>; 679f46c7ed4Sjmcneill }; 680f46c7ed4Sjmcneill 681f46c7ed4Sjmcneill cpu46: cpu@50302 { 682f46c7ed4Sjmcneill device_type = "cpu"; 68384c8294dSjmcneill compatible = "arm,cortex-a72"; 684f46c7ed4Sjmcneill reg = <0x50302>; 685f46c7ed4Sjmcneill enable-method = "psci"; 686f46c7ed4Sjmcneill next-level-cache = <&cluster11_l2>; 687f46c7ed4Sjmcneill numa-node-id = <2>; 688f46c7ed4Sjmcneill }; 689f46c7ed4Sjmcneill 690f46c7ed4Sjmcneill cpu47: cpu@50303 { 691f46c7ed4Sjmcneill device_type = "cpu"; 69284c8294dSjmcneill compatible = "arm,cortex-a72"; 693f46c7ed4Sjmcneill reg = <0x50303>; 694f46c7ed4Sjmcneill enable-method = "psci"; 695f46c7ed4Sjmcneill next-level-cache = <&cluster11_l2>; 696f46c7ed4Sjmcneill numa-node-id = <2>; 697f46c7ed4Sjmcneill }; 698f46c7ed4Sjmcneill 699f46c7ed4Sjmcneill cpu48: cpu@70000 { 700f46c7ed4Sjmcneill device_type = "cpu"; 70184c8294dSjmcneill compatible = "arm,cortex-a72"; 702f46c7ed4Sjmcneill reg = <0x70000>; 703f46c7ed4Sjmcneill enable-method = "psci"; 704f46c7ed4Sjmcneill next-level-cache = <&cluster12_l2>; 705f46c7ed4Sjmcneill numa-node-id = <3>; 706f46c7ed4Sjmcneill }; 707f46c7ed4Sjmcneill 708f46c7ed4Sjmcneill cpu49: cpu@70001 { 709f46c7ed4Sjmcneill device_type = "cpu"; 71084c8294dSjmcneill compatible = "arm,cortex-a72"; 711f46c7ed4Sjmcneill reg = <0x70001>; 712f46c7ed4Sjmcneill enable-method = "psci"; 713f46c7ed4Sjmcneill next-level-cache = <&cluster12_l2>; 714f46c7ed4Sjmcneill numa-node-id = <3>; 715f46c7ed4Sjmcneill }; 716f46c7ed4Sjmcneill 717f46c7ed4Sjmcneill cpu50: cpu@70002 { 718f46c7ed4Sjmcneill device_type = "cpu"; 71984c8294dSjmcneill compatible = "arm,cortex-a72"; 720f46c7ed4Sjmcneill reg = <0x70002>; 721f46c7ed4Sjmcneill enable-method = "psci"; 722f46c7ed4Sjmcneill next-level-cache = <&cluster12_l2>; 723f46c7ed4Sjmcneill numa-node-id = <3>; 724f46c7ed4Sjmcneill }; 725f46c7ed4Sjmcneill 726f46c7ed4Sjmcneill cpu51: cpu@70003 { 727f46c7ed4Sjmcneill device_type = "cpu"; 72884c8294dSjmcneill compatible = "arm,cortex-a72"; 729f46c7ed4Sjmcneill reg = <0x70003>; 730f46c7ed4Sjmcneill enable-method = "psci"; 731f46c7ed4Sjmcneill next-level-cache = <&cluster12_l2>; 732f46c7ed4Sjmcneill numa-node-id = <3>; 733f46c7ed4Sjmcneill }; 734f46c7ed4Sjmcneill 735f46c7ed4Sjmcneill cpu52: cpu@70100 { 736f46c7ed4Sjmcneill device_type = "cpu"; 73784c8294dSjmcneill compatible = "arm,cortex-a72"; 738f46c7ed4Sjmcneill reg = <0x70100>; 739f46c7ed4Sjmcneill enable-method = "psci"; 740f46c7ed4Sjmcneill next-level-cache = <&cluster13_l2>; 741f46c7ed4Sjmcneill numa-node-id = <3>; 742f46c7ed4Sjmcneill }; 743f46c7ed4Sjmcneill 744f46c7ed4Sjmcneill cpu53: cpu@70101 { 745f46c7ed4Sjmcneill device_type = "cpu"; 74684c8294dSjmcneill compatible = "arm,cortex-a72"; 747f46c7ed4Sjmcneill reg = <0x70101>; 748f46c7ed4Sjmcneill enable-method = "psci"; 749f46c7ed4Sjmcneill next-level-cache = <&cluster13_l2>; 750f46c7ed4Sjmcneill numa-node-id = <3>; 751f46c7ed4Sjmcneill }; 752f46c7ed4Sjmcneill 753f46c7ed4Sjmcneill cpu54: cpu@70102 { 754f46c7ed4Sjmcneill device_type = "cpu"; 75584c8294dSjmcneill compatible = "arm,cortex-a72"; 756f46c7ed4Sjmcneill reg = <0x70102>; 757f46c7ed4Sjmcneill enable-method = "psci"; 758f46c7ed4Sjmcneill next-level-cache = <&cluster13_l2>; 759f46c7ed4Sjmcneill numa-node-id = <3>; 760f46c7ed4Sjmcneill }; 761f46c7ed4Sjmcneill 762f46c7ed4Sjmcneill cpu55: cpu@70103 { 763f46c7ed4Sjmcneill device_type = "cpu"; 76484c8294dSjmcneill compatible = "arm,cortex-a72"; 765f46c7ed4Sjmcneill reg = <0x70103>; 766f46c7ed4Sjmcneill enable-method = "psci"; 767f46c7ed4Sjmcneill next-level-cache = <&cluster13_l2>; 768f46c7ed4Sjmcneill numa-node-id = <3>; 769f46c7ed4Sjmcneill }; 770f46c7ed4Sjmcneill 771f46c7ed4Sjmcneill cpu56: cpu@70200 { 772f46c7ed4Sjmcneill device_type = "cpu"; 77384c8294dSjmcneill compatible = "arm,cortex-a72"; 774f46c7ed4Sjmcneill reg = <0x70200>; 775f46c7ed4Sjmcneill enable-method = "psci"; 776f46c7ed4Sjmcneill next-level-cache = <&cluster14_l2>; 777f46c7ed4Sjmcneill numa-node-id = <3>; 778f46c7ed4Sjmcneill }; 779f46c7ed4Sjmcneill 780f46c7ed4Sjmcneill cpu57: cpu@70201 { 781f46c7ed4Sjmcneill device_type = "cpu"; 78284c8294dSjmcneill compatible = "arm,cortex-a72"; 783f46c7ed4Sjmcneill reg = <0x70201>; 784f46c7ed4Sjmcneill enable-method = "psci"; 785f46c7ed4Sjmcneill next-level-cache = <&cluster14_l2>; 786f46c7ed4Sjmcneill numa-node-id = <3>; 787f46c7ed4Sjmcneill }; 788f46c7ed4Sjmcneill 789f46c7ed4Sjmcneill cpu58: cpu@70202 { 790f46c7ed4Sjmcneill device_type = "cpu"; 79184c8294dSjmcneill compatible = "arm,cortex-a72"; 792f46c7ed4Sjmcneill reg = <0x70202>; 793f46c7ed4Sjmcneill enable-method = "psci"; 794f46c7ed4Sjmcneill next-level-cache = <&cluster14_l2>; 795f46c7ed4Sjmcneill numa-node-id = <3>; 796f46c7ed4Sjmcneill }; 797f46c7ed4Sjmcneill 798f46c7ed4Sjmcneill cpu59: cpu@70203 { 799f46c7ed4Sjmcneill device_type = "cpu"; 80084c8294dSjmcneill compatible = "arm,cortex-a72"; 801f46c7ed4Sjmcneill reg = <0x70203>; 802f46c7ed4Sjmcneill enable-method = "psci"; 803f46c7ed4Sjmcneill next-level-cache = <&cluster14_l2>; 804f46c7ed4Sjmcneill numa-node-id = <3>; 805f46c7ed4Sjmcneill }; 806f46c7ed4Sjmcneill 807f46c7ed4Sjmcneill cpu60: cpu@70300 { 808f46c7ed4Sjmcneill device_type = "cpu"; 80984c8294dSjmcneill compatible = "arm,cortex-a72"; 810f46c7ed4Sjmcneill reg = <0x70300>; 811f46c7ed4Sjmcneill enable-method = "psci"; 812f46c7ed4Sjmcneill next-level-cache = <&cluster15_l2>; 813f46c7ed4Sjmcneill numa-node-id = <3>; 814f46c7ed4Sjmcneill }; 815f46c7ed4Sjmcneill 816f46c7ed4Sjmcneill cpu61: cpu@70301 { 817f46c7ed4Sjmcneill device_type = "cpu"; 81884c8294dSjmcneill compatible = "arm,cortex-a72"; 819f46c7ed4Sjmcneill reg = <0x70301>; 820f46c7ed4Sjmcneill enable-method = "psci"; 821f46c7ed4Sjmcneill next-level-cache = <&cluster15_l2>; 822f46c7ed4Sjmcneill numa-node-id = <3>; 823f46c7ed4Sjmcneill }; 824f46c7ed4Sjmcneill 825f46c7ed4Sjmcneill cpu62: cpu@70302 { 826f46c7ed4Sjmcneill device_type = "cpu"; 82784c8294dSjmcneill compatible = "arm,cortex-a72"; 828f46c7ed4Sjmcneill reg = <0x70302>; 829f46c7ed4Sjmcneill enable-method = "psci"; 830f46c7ed4Sjmcneill next-level-cache = <&cluster15_l2>; 831f46c7ed4Sjmcneill numa-node-id = <3>; 832f46c7ed4Sjmcneill }; 833f46c7ed4Sjmcneill 834f46c7ed4Sjmcneill cpu63: cpu@70303 { 835f46c7ed4Sjmcneill device_type = "cpu"; 83684c8294dSjmcneill compatible = "arm,cortex-a72"; 837f46c7ed4Sjmcneill reg = <0x70303>; 838f46c7ed4Sjmcneill enable-method = "psci"; 839f46c7ed4Sjmcneill next-level-cache = <&cluster15_l2>; 840f46c7ed4Sjmcneill numa-node-id = <3>; 841f46c7ed4Sjmcneill }; 842f46c7ed4Sjmcneill 843f46c7ed4Sjmcneill cluster0_l2: l2-cache0 { 844f46c7ed4Sjmcneill compatible = "cache"; 845f46c7ed4Sjmcneill }; 846f46c7ed4Sjmcneill 847f46c7ed4Sjmcneill cluster1_l2: l2-cache1 { 848f46c7ed4Sjmcneill compatible = "cache"; 849f46c7ed4Sjmcneill }; 850f46c7ed4Sjmcneill 851f46c7ed4Sjmcneill cluster2_l2: l2-cache2 { 852f46c7ed4Sjmcneill compatible = "cache"; 853f46c7ed4Sjmcneill }; 854f46c7ed4Sjmcneill 855f46c7ed4Sjmcneill cluster3_l2: l2-cache3 { 856f46c7ed4Sjmcneill compatible = "cache"; 857f46c7ed4Sjmcneill }; 858f46c7ed4Sjmcneill 859f46c7ed4Sjmcneill cluster4_l2: l2-cache4 { 860f46c7ed4Sjmcneill compatible = "cache"; 861f46c7ed4Sjmcneill }; 862f46c7ed4Sjmcneill 863f46c7ed4Sjmcneill cluster5_l2: l2-cache5 { 864f46c7ed4Sjmcneill compatible = "cache"; 865f46c7ed4Sjmcneill }; 866f46c7ed4Sjmcneill 867f46c7ed4Sjmcneill cluster6_l2: l2-cache6 { 868f46c7ed4Sjmcneill compatible = "cache"; 869f46c7ed4Sjmcneill }; 870f46c7ed4Sjmcneill 871f46c7ed4Sjmcneill cluster7_l2: l2-cache7 { 872f46c7ed4Sjmcneill compatible = "cache"; 873f46c7ed4Sjmcneill }; 874f46c7ed4Sjmcneill 875f46c7ed4Sjmcneill cluster8_l2: l2-cache8 { 876f46c7ed4Sjmcneill compatible = "cache"; 877f46c7ed4Sjmcneill }; 878f46c7ed4Sjmcneill 879f46c7ed4Sjmcneill cluster9_l2: l2-cache9 { 880f46c7ed4Sjmcneill compatible = "cache"; 881f46c7ed4Sjmcneill }; 882f46c7ed4Sjmcneill 883f46c7ed4Sjmcneill cluster10_l2: l2-cache10 { 884f46c7ed4Sjmcneill compatible = "cache"; 885f46c7ed4Sjmcneill }; 886f46c7ed4Sjmcneill 887f46c7ed4Sjmcneill cluster11_l2: l2-cache11 { 888f46c7ed4Sjmcneill compatible = "cache"; 889f46c7ed4Sjmcneill }; 890f46c7ed4Sjmcneill 891f46c7ed4Sjmcneill cluster12_l2: l2-cache12 { 892f46c7ed4Sjmcneill compatible = "cache"; 893f46c7ed4Sjmcneill }; 894f46c7ed4Sjmcneill 895f46c7ed4Sjmcneill cluster13_l2: l2-cache13 { 896f46c7ed4Sjmcneill compatible = "cache"; 897f46c7ed4Sjmcneill }; 898f46c7ed4Sjmcneill 899f46c7ed4Sjmcneill cluster14_l2: l2-cache14 { 900f46c7ed4Sjmcneill compatible = "cache"; 901f46c7ed4Sjmcneill }; 902f46c7ed4Sjmcneill 903f46c7ed4Sjmcneill cluster15_l2: l2-cache15 { 904f46c7ed4Sjmcneill compatible = "cache"; 905f46c7ed4Sjmcneill }; 906f46c7ed4Sjmcneill }; 907f46c7ed4Sjmcneill 908f46c7ed4Sjmcneill gic: interrupt-controller@4d000000 { 909f46c7ed4Sjmcneill compatible = "arm,gic-v3"; 910f46c7ed4Sjmcneill #interrupt-cells = <3>; 911f46c7ed4Sjmcneill #address-cells = <2>; 912f46c7ed4Sjmcneill #size-cells = <2>; 913f46c7ed4Sjmcneill ranges; 914f46c7ed4Sjmcneill interrupt-controller; 915f46c7ed4Sjmcneill #redistributor-regions = <4>; 916f46c7ed4Sjmcneill redistributor-stride = <0x0 0x40000>; 917f46c7ed4Sjmcneill reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */ 918f46c7ed4Sjmcneill <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */ 919f46c7ed4Sjmcneill <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */ 920f46c7ed4Sjmcneill <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */ 921f46c7ed4Sjmcneill <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */ 922f46c7ed4Sjmcneill <0x0 0xfe000000 0x0 0x10000>, /* GICC */ 923f46c7ed4Sjmcneill <0x0 0xfe010000 0x0 0x10000>, /* GICH */ 924f46c7ed4Sjmcneill <0x0 0xfe020000 0x0 0x10000>; /* GICV */ 925f46c7ed4Sjmcneill interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 926f46c7ed4Sjmcneill 927*9ed2a30eSjmcneill p0_its_peri_a: msi-controller@4c000000 { 928f46c7ed4Sjmcneill compatible = "arm,gic-v3-its"; 929f46c7ed4Sjmcneill msi-controller; 930f46c7ed4Sjmcneill #msi-cells = <1>; 931f46c7ed4Sjmcneill reg = <0x0 0x4c000000 0x0 0x40000>; 932f46c7ed4Sjmcneill }; 933f46c7ed4Sjmcneill 934*9ed2a30eSjmcneill p0_its_peri_b: msi-controller@6c000000 { 935f46c7ed4Sjmcneill compatible = "arm,gic-v3-its"; 936f46c7ed4Sjmcneill msi-controller; 937f46c7ed4Sjmcneill #msi-cells = <1>; 938f46c7ed4Sjmcneill reg = <0x0 0x6c000000 0x0 0x40000>; 939f46c7ed4Sjmcneill }; 940f46c7ed4Sjmcneill 941*9ed2a30eSjmcneill p0_its_dsa_a: msi-controller@c6000000 { 942f46c7ed4Sjmcneill compatible = "arm,gic-v3-its"; 943f46c7ed4Sjmcneill msi-controller; 944f46c7ed4Sjmcneill #msi-cells = <1>; 945f46c7ed4Sjmcneill reg = <0x0 0xc6000000 0x0 0x40000>; 946f46c7ed4Sjmcneill }; 947f46c7ed4Sjmcneill 948*9ed2a30eSjmcneill p0_its_dsa_b: msi-controller@8c6000000 { 949f46c7ed4Sjmcneill compatible = "arm,gic-v3-its"; 950f46c7ed4Sjmcneill msi-controller; 951f46c7ed4Sjmcneill #msi-cells = <1>; 952f46c7ed4Sjmcneill reg = <0x8 0xc6000000 0x0 0x40000>; 953f46c7ed4Sjmcneill }; 954f46c7ed4Sjmcneill 955*9ed2a30eSjmcneill p1_its_peri_a: msi-controller@4004c000000 { 956f46c7ed4Sjmcneill compatible = "arm,gic-v3-its"; 957f46c7ed4Sjmcneill msi-controller; 958f46c7ed4Sjmcneill #msi-cells = <1>; 959f46c7ed4Sjmcneill reg = <0x400 0x4c000000 0x0 0x40000>; 960f46c7ed4Sjmcneill }; 961f46c7ed4Sjmcneill 962*9ed2a30eSjmcneill p1_its_peri_b: msi-controller@4006c000000 { 963f46c7ed4Sjmcneill compatible = "arm,gic-v3-its"; 964f46c7ed4Sjmcneill msi-controller; 965f46c7ed4Sjmcneill #msi-cells = <1>; 966f46c7ed4Sjmcneill reg = <0x400 0x6c000000 0x0 0x40000>; 967f46c7ed4Sjmcneill }; 968f46c7ed4Sjmcneill 969*9ed2a30eSjmcneill p1_its_dsa_a: msi-controller@400c6000000 { 970f46c7ed4Sjmcneill compatible = "arm,gic-v3-its"; 971f46c7ed4Sjmcneill msi-controller; 972f46c7ed4Sjmcneill #msi-cells = <1>; 973f46c7ed4Sjmcneill reg = <0x400 0xc6000000 0x0 0x40000>; 974f46c7ed4Sjmcneill }; 975f46c7ed4Sjmcneill 976*9ed2a30eSjmcneill p1_its_dsa_b: msi-controller@408c6000000 { 977f46c7ed4Sjmcneill compatible = "arm,gic-v3-its"; 978f46c7ed4Sjmcneill msi-controller; 979f46c7ed4Sjmcneill #msi-cells = <1>; 980f46c7ed4Sjmcneill reg = <0x408 0xc6000000 0x0 0x40000>; 981f46c7ed4Sjmcneill }; 982f46c7ed4Sjmcneill }; 983f46c7ed4Sjmcneill 984f46c7ed4Sjmcneill timer { 985f46c7ed4Sjmcneill compatible = "arm,armv8-timer"; 986f46c7ed4Sjmcneill interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 987f46c7ed4Sjmcneill <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 988f46c7ed4Sjmcneill <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 989f46c7ed4Sjmcneill <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 990f46c7ed4Sjmcneill }; 991f46c7ed4Sjmcneill 992f46c7ed4Sjmcneill pmu { 993f46c7ed4Sjmcneill compatible = "arm,cortex-a72-pmu"; 994f46c7ed4Sjmcneill interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 995f46c7ed4Sjmcneill }; 996f46c7ed4Sjmcneill 997f46c7ed4Sjmcneill p0_mbigen_peri_b: interrupt-controller@60080000 { 998f46c7ed4Sjmcneill compatible = "hisilicon,mbigen-v2"; 999f46c7ed4Sjmcneill reg = <0x0 0x60080000 0x0 0x10000>; 1000f46c7ed4Sjmcneill 1001f46c7ed4Sjmcneill mbigen_uart: uart_intc { 1002f46c7ed4Sjmcneill msi-parent = <&p0_its_peri_b 0x120c7>; 1003f46c7ed4Sjmcneill interrupt-controller; 1004f46c7ed4Sjmcneill #interrupt-cells = <2>; 1005f46c7ed4Sjmcneill num-pins = <1>; 1006f46c7ed4Sjmcneill }; 1007f46c7ed4Sjmcneill }; 1008f46c7ed4Sjmcneill 1009f46c7ed4Sjmcneill p0_mbigen_pcie_a: interrupt-controller@a0080000 { 1010f46c7ed4Sjmcneill compatible = "hisilicon,mbigen-v2"; 1011f46c7ed4Sjmcneill reg = <0x0 0xa0080000 0x0 0x10000>; 1012f46c7ed4Sjmcneill 10138fb04b9bSjmcneill mbigen_pcie2_a: intc_pcie2_a { 10148fb04b9bSjmcneill msi-parent = <&p0_its_dsa_a 0x40087>; 10158fb04b9bSjmcneill interrupt-controller; 10168fb04b9bSjmcneill #interrupt-cells = <2>; 10178fb04b9bSjmcneill num-pins = <10>; 10188fb04b9bSjmcneill }; 10198fb04b9bSjmcneill 10208fb04b9bSjmcneill mbigen_sas1: intc_sas1 { 10218fb04b9bSjmcneill msi-parent = <&p0_its_dsa_a 0x40000>; 10228fb04b9bSjmcneill interrupt-controller; 10238fb04b9bSjmcneill #interrupt-cells = <2>; 10248fb04b9bSjmcneill num-pins = <128>; 10258fb04b9bSjmcneill }; 10268fb04b9bSjmcneill 10278fb04b9bSjmcneill mbigen_sas2: intc_sas2 { 10288fb04b9bSjmcneill msi-parent = <&p0_its_dsa_a 0x40040>; 10298fb04b9bSjmcneill interrupt-controller; 10308fb04b9bSjmcneill #interrupt-cells = <2>; 10318fb04b9bSjmcneill num-pins = <128>; 10328fb04b9bSjmcneill }; 10338fb04b9bSjmcneill 10348fb04b9bSjmcneill mbigen_smmu_pcie: intc_smmu_pcie { 10358fb04b9bSjmcneill msi-parent = <&p0_its_dsa_a 0x40b0c>; 10368fb04b9bSjmcneill interrupt-controller; 10378fb04b9bSjmcneill #interrupt-cells = <2>; 10388fb04b9bSjmcneill num-pins = <3>; 10398fb04b9bSjmcneill }; 10408fb04b9bSjmcneill 1041f46c7ed4Sjmcneill mbigen_usb: intc_usb { 1042f46c7ed4Sjmcneill msi-parent = <&p0_its_dsa_a 0x40080>; 1043f46c7ed4Sjmcneill interrupt-controller; 1044f46c7ed4Sjmcneill #interrupt-cells = <2>; 1045f46c7ed4Sjmcneill num-pins = <2>; 1046f46c7ed4Sjmcneill }; 1047f46c7ed4Sjmcneill }; 1048182157ecSjmcneill p0_mbigen_alg_a:interrupt-controller@d0080000 { 1049182157ecSjmcneill compatible = "hisilicon,mbigen-v2"; 1050182157ecSjmcneill reg = <0x0 0xd0080000 0x0 0x10000>; 1051f46c7ed4Sjmcneill 1052182157ecSjmcneill p0_mbigen_sec_a: intc_sec { 1053182157ecSjmcneill msi-parent = <&p0_its_dsa_a 0x40400>; 1054182157ecSjmcneill interrupt-controller; 1055182157ecSjmcneill #interrupt-cells = <2>; 1056182157ecSjmcneill num-pins = <33>; 1057182157ecSjmcneill }; 1058182157ecSjmcneill p0_mbigen_smmu_alg_a: intc_smmu_alg { 1059182157ecSjmcneill msi-parent = <&p0_its_dsa_a 0x40b1b>; 1060182157ecSjmcneill interrupt-controller; 1061182157ecSjmcneill #interrupt-cells = <2>; 1062182157ecSjmcneill num-pins = <3>; 1063182157ecSjmcneill }; 1064182157ecSjmcneill }; 1065182157ecSjmcneill p0_mbigen_alg_b:interrupt-controller@8,d0080000 { 1066182157ecSjmcneill compatible = "hisilicon,mbigen-v2"; 1067182157ecSjmcneill reg = <0x8 0xd0080000 0x0 0x10000>; 1068182157ecSjmcneill 1069182157ecSjmcneill p0_mbigen_sec_b: intc_sec { 1070182157ecSjmcneill msi-parent = <&p0_its_dsa_b 0x42400>; 1071182157ecSjmcneill interrupt-controller; 1072182157ecSjmcneill #interrupt-cells = <2>; 1073182157ecSjmcneill num-pins = <33>; 1074182157ecSjmcneill }; 1075182157ecSjmcneill p0_mbigen_smmu_alg_b: intc_smmu_alg { 1076182157ecSjmcneill msi-parent = <&p0_its_dsa_b 0x42b1b>; 1077182157ecSjmcneill interrupt-controller; 1078182157ecSjmcneill #interrupt-cells = <2>; 1079182157ecSjmcneill num-pins = <3>; 1080182157ecSjmcneill }; 1081182157ecSjmcneill }; 1082182157ecSjmcneill p1_mbigen_alg_a:interrupt-controller@400,d0080000 { 1083182157ecSjmcneill compatible = "hisilicon,mbigen-v2"; 1084182157ecSjmcneill reg = <0x400 0xd0080000 0x0 0x10000>; 1085182157ecSjmcneill 1086182157ecSjmcneill p1_mbigen_sec_a: intc_sec { 1087182157ecSjmcneill msi-parent = <&p1_its_dsa_a 0x44400>; 1088182157ecSjmcneill interrupt-controller; 1089182157ecSjmcneill #interrupt-cells = <2>; 1090182157ecSjmcneill num-pins = <33>; 1091182157ecSjmcneill }; 1092182157ecSjmcneill p1_mbigen_smmu_alg_a: intc_smmu_alg { 1093182157ecSjmcneill msi-parent = <&p1_its_dsa_a 0x44b1b>; 1094182157ecSjmcneill interrupt-controller; 1095182157ecSjmcneill #interrupt-cells = <2>; 1096182157ecSjmcneill num-pins = <3>; 1097182157ecSjmcneill }; 1098182157ecSjmcneill }; 1099182157ecSjmcneill p1_mbigen_alg_b:interrupt-controller@408,d0080000 { 1100182157ecSjmcneill compatible = "hisilicon,mbigen-v2"; 1101182157ecSjmcneill reg = <0x408 0xd0080000 0x0 0x10000>; 1102182157ecSjmcneill 1103182157ecSjmcneill p1_mbigen_sec_b: intc_sec { 1104182157ecSjmcneill msi-parent = <&p1_its_dsa_b 0x46400>; 1105182157ecSjmcneill interrupt-controller; 1106182157ecSjmcneill #interrupt-cells = <2>; 1107182157ecSjmcneill num-pins = <33>; 1108182157ecSjmcneill }; 1109182157ecSjmcneill p1_mbigen_smmu_alg_b: intc_smmu_alg { 1110182157ecSjmcneill msi-parent = <&p1_its_dsa_b 0x46b1b>; 1111182157ecSjmcneill interrupt-controller; 1112182157ecSjmcneill #interrupt-cells = <2>; 1113182157ecSjmcneill num-pins = <3>; 1114182157ecSjmcneill }; 1115182157ecSjmcneill }; 11168fb04b9bSjmcneill p0_mbigen_dsa_a: interrupt-controller@c0080000 { 11178fb04b9bSjmcneill compatible = "hisilicon,mbigen-v2"; 11188fb04b9bSjmcneill reg = <0x0 0xc0080000 0x0 0x10000>; 11198fb04b9bSjmcneill 11208fb04b9bSjmcneill mbigen_dsaf0: intc_dsaf0 { 11218fb04b9bSjmcneill msi-parent = <&p0_its_dsa_a 0x40800>; 11228fb04b9bSjmcneill interrupt-controller; 11238fb04b9bSjmcneill #interrupt-cells = <2>; 11248fb04b9bSjmcneill num-pins = <409>; 11258fb04b9bSjmcneill }; 11268fb04b9bSjmcneill 11278fb04b9bSjmcneill mbigen_dsa_roce: intc-roce { 11288fb04b9bSjmcneill msi-parent = <&p0_its_dsa_a 0x40B1E>; 11298fb04b9bSjmcneill interrupt-controller; 11308fb04b9bSjmcneill #interrupt-cells = <2>; 11318fb04b9bSjmcneill num-pins = <34>; 11328fb04b9bSjmcneill }; 11338fb04b9bSjmcneill 11348fb04b9bSjmcneill mbigen_sas0: intc-sas0 { 11358fb04b9bSjmcneill msi-parent = <&p0_its_dsa_a 0x40900>; 11368fb04b9bSjmcneill interrupt-controller; 11378fb04b9bSjmcneill #interrupt-cells = <2>; 11388fb04b9bSjmcneill num-pins = <128>; 11398fb04b9bSjmcneill }; 11408fb04b9bSjmcneill 11418fb04b9bSjmcneill mbigen_smmu_dsa: intc_smmu_dsa { 11428fb04b9bSjmcneill msi-parent = <&p0_its_dsa_a 0x40b20>; 11438fb04b9bSjmcneill interrupt-controller; 11448fb04b9bSjmcneill #interrupt-cells = <2>; 11458fb04b9bSjmcneill num-pins = <3>; 11468fb04b9bSjmcneill }; 11478fb04b9bSjmcneill }; 11488fb04b9bSjmcneill 1149cf2d964bSjmcneill /** 1150cf2d964bSjmcneill * HiSilicon erratum 161010801: This describes the limitation 1151cf2d964bSjmcneill * of HiSilicon platforms hip06/hip07 to support the SMMUv3 1152cf2d964bSjmcneill * mappings for PCIe MSI transactions. 1153cf2d964bSjmcneill * PCIe controller on these platforms has to differentiate the 1154cf2d964bSjmcneill * MSI payload against other DMA payload and has to modify the 1155cf2d964bSjmcneill * MSI payload. This makes it difficult for these platforms to 1156cf2d964bSjmcneill * have a SMMU translation for MSI. In order to workaround this, 1157cf2d964bSjmcneill * ARM SMMUv3 driver requires a quirk to treat the MSI regions 1158cf2d964bSjmcneill * separately. Such a quirk is currently missing for DT based 1159cf2d964bSjmcneill * systems. Hence please make sure that the smmu pcie node on 1160cf2d964bSjmcneill * hip07 is disabled as this will break the PCIe functionality 1161cf2d964bSjmcneill * when iommu-map entry is used along with the PCIe node. 1162cf2d964bSjmcneill * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html 1163cf2d964bSjmcneill */ 1164*9ed2a30eSjmcneill smmu0: iommu@a0040000 { 1165cf2d964bSjmcneill compatible = "arm,smmu-v3"; 1166cf2d964bSjmcneill reg = <0x0 0xa0040000 0x0 0x20000>; 1167cf2d964bSjmcneill #iommu-cells = <1>; 1168cf2d964bSjmcneill dma-coherent; 1169cf2d964bSjmcneill hisilicon,broken-prefetch-cmd; 1170cf2d964bSjmcneill status = "disabled"; 1171cf2d964bSjmcneill }; 1172*9ed2a30eSjmcneill p0_smmu_alg_a: iommu@d0040000 { 1173182157ecSjmcneill compatible = "arm,smmu-v3"; 1174182157ecSjmcneill reg = <0x0 0xd0040000 0x0 0x20000>; 1175182157ecSjmcneill interrupt-parent = <&p0_mbigen_smmu_alg_a>; 1176182157ecSjmcneill interrupts = <733 1>, 1177182157ecSjmcneill <734 1>, 1178182157ecSjmcneill <735 1>; 1179182157ecSjmcneill interrupt-names = "eventq", "gerror", "priq"; 1180182157ecSjmcneill #iommu-cells = <1>; 1181182157ecSjmcneill dma-coherent; 1182182157ecSjmcneill hisilicon,broken-prefetch-cmd; 1183182157ecSjmcneill }; 1184*9ed2a30eSjmcneill p0_smmu_alg_b: iommu@8d0040000 { 1185182157ecSjmcneill compatible = "arm,smmu-v3"; 1186182157ecSjmcneill reg = <0x8 0xd0040000 0x0 0x20000>; 1187182157ecSjmcneill interrupt-parent = <&p0_mbigen_smmu_alg_b>; 1188182157ecSjmcneill interrupts = <733 1>, 1189182157ecSjmcneill <734 1>, 1190182157ecSjmcneill <735 1>; 1191182157ecSjmcneill interrupt-names = "eventq", "gerror", "priq"; 1192182157ecSjmcneill #iommu-cells = <1>; 1193182157ecSjmcneill dma-coherent; 1194182157ecSjmcneill hisilicon,broken-prefetch-cmd; 1195182157ecSjmcneill }; 1196*9ed2a30eSjmcneill p1_smmu_alg_a: iommu@400d0040000 { 1197182157ecSjmcneill compatible = "arm,smmu-v3"; 1198182157ecSjmcneill reg = <0x400 0xd0040000 0x0 0x20000>; 1199182157ecSjmcneill interrupt-parent = <&p1_mbigen_smmu_alg_a>; 1200182157ecSjmcneill interrupts = <733 1>, 1201182157ecSjmcneill <734 1>, 1202182157ecSjmcneill <735 1>; 1203182157ecSjmcneill interrupt-names = "eventq", "gerror", "priq"; 1204182157ecSjmcneill #iommu-cells = <1>; 1205182157ecSjmcneill dma-coherent; 1206182157ecSjmcneill hisilicon,broken-prefetch-cmd; 1207182157ecSjmcneill }; 1208*9ed2a30eSjmcneill p1_smmu_alg_b: iommu@408d0040000 { 1209182157ecSjmcneill compatible = "arm,smmu-v3"; 1210182157ecSjmcneill reg = <0x408 0xd0040000 0x0 0x20000>; 1211182157ecSjmcneill interrupt-parent = <&p1_mbigen_smmu_alg_b>; 1212182157ecSjmcneill interrupts = <733 1>, 1213182157ecSjmcneill <734 1>, 1214182157ecSjmcneill <735 1>; 1215182157ecSjmcneill interrupt-names = "eventq", "gerror", "priq"; 1216182157ecSjmcneill #iommu-cells = <1>; 1217182157ecSjmcneill dma-coherent; 1218182157ecSjmcneill hisilicon,broken-prefetch-cmd; 1219182157ecSjmcneill }; 1220cf2d964bSjmcneill 1221f46c7ed4Sjmcneill soc { 1222f46c7ed4Sjmcneill compatible = "simple-bus"; 1223f46c7ed4Sjmcneill #address-cells = <2>; 1224f46c7ed4Sjmcneill #size-cells = <2>; 1225f46c7ed4Sjmcneill ranges; 1226f46c7ed4Sjmcneill 1227a27cda6cSjmcneill isa@a01b0000 { 1228a27cda6cSjmcneill compatible = "hisilicon,hip07-lpc"; 1229a27cda6cSjmcneill #size-cells = <1>; 1230a27cda6cSjmcneill #address-cells = <2>; 1231a27cda6cSjmcneill reg = <0x0 0xa01b0000 0x0 0x1000>; 1232a27cda6cSjmcneill 1233a27cda6cSjmcneill ipmi0: bt@e4 { 1234a27cda6cSjmcneill compatible = "ipmi-bt"; 1235a27cda6cSjmcneill device_type = "ipmi"; 1236a27cda6cSjmcneill reg = <0x01 0xe4 0x04>; 1237a27cda6cSjmcneill status = "disabled"; 1238a27cda6cSjmcneill }; 1239a27cda6cSjmcneill }; 1240a27cda6cSjmcneill 1241f46c7ed4Sjmcneill uart0: uart@602b0000 { 1242f46c7ed4Sjmcneill compatible = "arm,sbsa-uart"; 1243f46c7ed4Sjmcneill reg = <0x0 0x602b0000 0x0 0x1000>; 1244f46c7ed4Sjmcneill interrupt-parent = <&mbigen_uart>; 1245f46c7ed4Sjmcneill interrupts = <807 4>; 1246f46c7ed4Sjmcneill current-speed = <115200>; 1247f46c7ed4Sjmcneill reg-io-width = <4>; 1248f46c7ed4Sjmcneill status = "disabled"; 1249f46c7ed4Sjmcneill }; 1250f46c7ed4Sjmcneill 1251*9ed2a30eSjmcneill usb_ohci: usb@a7030000 { 1252f46c7ed4Sjmcneill compatible = "generic-ohci"; 1253f46c7ed4Sjmcneill reg = <0x0 0xa7030000 0x0 0x10000>; 1254f46c7ed4Sjmcneill interrupt-parent = <&mbigen_usb>; 1255f46c7ed4Sjmcneill interrupts = <640 4>; 1256f46c7ed4Sjmcneill dma-coherent; 1257f46c7ed4Sjmcneill status = "disabled"; 1258f46c7ed4Sjmcneill }; 1259f46c7ed4Sjmcneill 1260*9ed2a30eSjmcneill usb_ehci: usb@a7020000 { 1261f46c7ed4Sjmcneill compatible = "generic-ehci"; 1262f46c7ed4Sjmcneill reg = <0x0 0xa7020000 0x0 0x10000>; 1263f46c7ed4Sjmcneill interrupt-parent = <&mbigen_usb>; 1264f46c7ed4Sjmcneill interrupts = <641 4>; 1265f46c7ed4Sjmcneill dma-coherent; 1266f46c7ed4Sjmcneill status = "disabled"; 1267f46c7ed4Sjmcneill }; 12688fb04b9bSjmcneill 12698fb04b9bSjmcneill peri_c_subctrl: sub_ctrl_c@60000000 { 12708fb04b9bSjmcneill compatible = "hisilicon,peri-subctrl","syscon"; 12718fb04b9bSjmcneill reg = <0 0x60000000 0x0 0x10000>; 12728fb04b9bSjmcneill }; 12738fb04b9bSjmcneill 12748fb04b9bSjmcneill dsa_subctrl: dsa_subctrl@c0000000 { 12758fb04b9bSjmcneill compatible = "hisilicon,dsa-subctrl", "syscon"; 12768fb04b9bSjmcneill reg = <0x0 0xc0000000 0x0 0x10000>; 12778fb04b9bSjmcneill }; 12788fb04b9bSjmcneill 1279cf2d964bSjmcneill dsa_cpld: dsa_cpld@78000010 { 1280cf2d964bSjmcneill compatible = "syscon"; 1281cf2d964bSjmcneill reg = <0x0 0x78000010 0x0 0x100>; 1282cf2d964bSjmcneill reg-io-width = <2>; 1283cf2d964bSjmcneill }; 1284cf2d964bSjmcneill 12858fb04b9bSjmcneill pcie_subctl: pcie_subctl@a0000000 { 12868fb04b9bSjmcneill compatible = "hisilicon,pcie-sas-subctrl", "syscon"; 12878fb04b9bSjmcneill reg = <0x0 0xa0000000 0x0 0x10000>; 12888fb04b9bSjmcneill }; 12898fb04b9bSjmcneill 12908fb04b9bSjmcneill serdes_ctrl: sds_ctrl@c2200000 { 12918fb04b9bSjmcneill compatible = "syscon"; 12928fb04b9bSjmcneill reg = <0 0xc2200000 0x0 0x80000>; 12938fb04b9bSjmcneill }; 12948fb04b9bSjmcneill 12958fb04b9bSjmcneill mdio@603c0000 { 12968fb04b9bSjmcneill compatible = "hisilicon,hns-mdio"; 12978fb04b9bSjmcneill reg = <0x0 0x603c0000 0x0 0x1000>; 12988fb04b9bSjmcneill subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 12998fb04b9bSjmcneill 0x531c 0x5a1c>; 13008fb04b9bSjmcneill #address-cells = <1>; 13018fb04b9bSjmcneill #size-cells = <0>; 13028fb04b9bSjmcneill 13038fb04b9bSjmcneill phy0: ethernet-phy@0 { 13048fb04b9bSjmcneill compatible = "ethernet-phy-ieee802.3-c22"; 13058fb04b9bSjmcneill reg = <0>; 13068fb04b9bSjmcneill }; 13078fb04b9bSjmcneill 13088fb04b9bSjmcneill phy1: ethernet-phy@1 { 13098fb04b9bSjmcneill compatible = "ethernet-phy-ieee802.3-c22"; 13108fb04b9bSjmcneill reg = <1>; 13118fb04b9bSjmcneill }; 13128fb04b9bSjmcneill }; 13138fb04b9bSjmcneill 13148fb04b9bSjmcneill dsaf0: dsa@c7000000 { 13158fb04b9bSjmcneill #address-cells = <1>; 13168fb04b9bSjmcneill #size-cells = <0>; 13178fb04b9bSjmcneill compatible = "hisilicon,hns-dsaf-v2"; 13188fb04b9bSjmcneill mode = "6port-16rss"; 1319*9ed2a30eSjmcneill reg = <0x0 0xc5000000 0x0 0x890000>, 1320*9ed2a30eSjmcneill <0x0 0xc7000000 0x0 0x600000>; 13218fb04b9bSjmcneill reg-names = "ppe-base", "dsaf-base"; 13228fb04b9bSjmcneill interrupt-parent = <&mbigen_dsaf0>; 13238fb04b9bSjmcneill subctrl-syscon = <&dsa_subctrl>; 13248fb04b9bSjmcneill reset-field-offset = <0>; 13258fb04b9bSjmcneill interrupts = 13268fb04b9bSjmcneill <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, 13278fb04b9bSjmcneill <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, 13288fb04b9bSjmcneill <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, 13298fb04b9bSjmcneill <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, 13308fb04b9bSjmcneill <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, 13318fb04b9bSjmcneill <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, 13328fb04b9bSjmcneill <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, 13338fb04b9bSjmcneill <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, 13348fb04b9bSjmcneill <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, 13358fb04b9bSjmcneill <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, 13368fb04b9bSjmcneill <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, 13378fb04b9bSjmcneill <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, 13388fb04b9bSjmcneill <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, 13398fb04b9bSjmcneill <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, 13408fb04b9bSjmcneill <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, 13418fb04b9bSjmcneill <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, 13428fb04b9bSjmcneill <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, 13438fb04b9bSjmcneill <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, 13448fb04b9bSjmcneill <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, 13458fb04b9bSjmcneill <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, 13468fb04b9bSjmcneill <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, 13478fb04b9bSjmcneill <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, 13488fb04b9bSjmcneill <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, 13498fb04b9bSjmcneill <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, 13508fb04b9bSjmcneill <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, 13518fb04b9bSjmcneill <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, 13528fb04b9bSjmcneill <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, 13538fb04b9bSjmcneill <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, 13548fb04b9bSjmcneill <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, 13558fb04b9bSjmcneill <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, 13568fb04b9bSjmcneill <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, 13578fb04b9bSjmcneill <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, 13588fb04b9bSjmcneill <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, 13598fb04b9bSjmcneill <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, 13608fb04b9bSjmcneill <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, 13618fb04b9bSjmcneill <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, 13628fb04b9bSjmcneill <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, 13638fb04b9bSjmcneill <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, 13648fb04b9bSjmcneill <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, 13658fb04b9bSjmcneill <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, 13668fb04b9bSjmcneill <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, 13678fb04b9bSjmcneill <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, 13688fb04b9bSjmcneill <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, 13698fb04b9bSjmcneill <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, 13708fb04b9bSjmcneill <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, 13718fb04b9bSjmcneill <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, 13728fb04b9bSjmcneill <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, 13738fb04b9bSjmcneill <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, 13748fb04b9bSjmcneill <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, 13758fb04b9bSjmcneill <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, 13768fb04b9bSjmcneill <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, 13778fb04b9bSjmcneill <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, 13788fb04b9bSjmcneill <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, 13798fb04b9bSjmcneill <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, 13808fb04b9bSjmcneill <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, 13818fb04b9bSjmcneill <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, 13828fb04b9bSjmcneill <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, 13838fb04b9bSjmcneill <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, 13848fb04b9bSjmcneill <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, 13858fb04b9bSjmcneill <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, 13868fb04b9bSjmcneill <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, 13878fb04b9bSjmcneill <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, 13888fb04b9bSjmcneill <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, 13898fb04b9bSjmcneill <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, 13908fb04b9bSjmcneill <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, 13918fb04b9bSjmcneill <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, 13928fb04b9bSjmcneill <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, 13938fb04b9bSjmcneill <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, 13948fb04b9bSjmcneill <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, 13958fb04b9bSjmcneill <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, 13968fb04b9bSjmcneill <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, 13978fb04b9bSjmcneill <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, 13988fb04b9bSjmcneill <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, 13998fb04b9bSjmcneill <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, 14008fb04b9bSjmcneill <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, 14018fb04b9bSjmcneill <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, 14028fb04b9bSjmcneill <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, 14038fb04b9bSjmcneill <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, 14048fb04b9bSjmcneill <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, 14058fb04b9bSjmcneill <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, 14068fb04b9bSjmcneill <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, 14078fb04b9bSjmcneill <1340 1>, <1341 1>, <1342 1>, <1343 1>; 14088fb04b9bSjmcneill 14098fb04b9bSjmcneill desc-num = <0x400>; 14108fb04b9bSjmcneill buf-size = <0x1000>; 14118fb04b9bSjmcneill dma-coherent; 14128fb04b9bSjmcneill 14138fb04b9bSjmcneill port@0 { 14148fb04b9bSjmcneill reg = <0>; 14158fb04b9bSjmcneill serdes-syscon = <&serdes_ctrl>; 1416cf2d964bSjmcneill cpld-syscon = <&dsa_cpld 0x0>; 14178fb04b9bSjmcneill port-rst-offset = <0>; 14188fb04b9bSjmcneill port-mode-offset = <0>; 14198fb04b9bSjmcneill mc-mac-mask = [ff f0 00 00 00 00]; 14208fb04b9bSjmcneill media-type = "fiber"; 14218fb04b9bSjmcneill }; 14228fb04b9bSjmcneill 14238fb04b9bSjmcneill port@1 { 14248fb04b9bSjmcneill reg = <1>; 14258fb04b9bSjmcneill serdes-syscon= <&serdes_ctrl>; 1426cf2d964bSjmcneill cpld-syscon = <&dsa_cpld 0x4>; 14278fb04b9bSjmcneill port-rst-offset = <1>; 14288fb04b9bSjmcneill port-mode-offset = <1>; 14298fb04b9bSjmcneill mc-mac-mask = [ff f0 00 00 00 00]; 14308fb04b9bSjmcneill media-type = "fiber"; 14318fb04b9bSjmcneill }; 14328fb04b9bSjmcneill 14338fb04b9bSjmcneill port@4 { 14348fb04b9bSjmcneill reg = <4>; 14358fb04b9bSjmcneill phy-handle = <&phy0>; 14368fb04b9bSjmcneill serdes-syscon= <&serdes_ctrl>; 14378fb04b9bSjmcneill port-rst-offset = <4>; 14388fb04b9bSjmcneill port-mode-offset = <2>; 14398fb04b9bSjmcneill mc-mac-mask = [ff f0 00 00 00 00]; 14408fb04b9bSjmcneill media-type = "copper"; 14418fb04b9bSjmcneill }; 14428fb04b9bSjmcneill 14438fb04b9bSjmcneill port@5 { 14448fb04b9bSjmcneill reg = <5>; 14458fb04b9bSjmcneill phy-handle = <&phy1>; 14468fb04b9bSjmcneill serdes-syscon= <&serdes_ctrl>; 14478fb04b9bSjmcneill port-rst-offset = <5>; 14488fb04b9bSjmcneill port-mode-offset = <3>; 14498fb04b9bSjmcneill mc-mac-mask = [ff f0 00 00 00 00]; 14508fb04b9bSjmcneill media-type = "copper"; 14518fb04b9bSjmcneill }; 14528fb04b9bSjmcneill }; 14538fb04b9bSjmcneill 14548fb04b9bSjmcneill eth0: ethernet@4{ 14558fb04b9bSjmcneill compatible = "hisilicon,hns-nic-v2"; 14568fb04b9bSjmcneill ae-handle = <&dsaf0>; 14578fb04b9bSjmcneill port-idx-in-ae = <4>; 14588fb04b9bSjmcneill local-mac-address = [00 00 00 00 00 00]; 14598fb04b9bSjmcneill status = "disabled"; 14608fb04b9bSjmcneill dma-coherent; 14618fb04b9bSjmcneill }; 14628fb04b9bSjmcneill 14638fb04b9bSjmcneill eth1: ethernet@5{ 14648fb04b9bSjmcneill compatible = "hisilicon,hns-nic-v2"; 14658fb04b9bSjmcneill ae-handle = <&dsaf0>; 14668fb04b9bSjmcneill port-idx-in-ae = <5>; 14678fb04b9bSjmcneill local-mac-address = [00 00 00 00 00 00]; 14688fb04b9bSjmcneill status = "disabled"; 14698fb04b9bSjmcneill dma-coherent; 14708fb04b9bSjmcneill }; 14718fb04b9bSjmcneill 14728fb04b9bSjmcneill eth2: ethernet@0{ 14738fb04b9bSjmcneill compatible = "hisilicon,hns-nic-v2"; 14748fb04b9bSjmcneill ae-handle = <&dsaf0>; 14758fb04b9bSjmcneill port-idx-in-ae = <0>; 14768fb04b9bSjmcneill local-mac-address = [00 00 00 00 00 00]; 14778fb04b9bSjmcneill status = "disabled"; 14788fb04b9bSjmcneill dma-coherent; 14798fb04b9bSjmcneill }; 14808fb04b9bSjmcneill 14818fb04b9bSjmcneill eth3: ethernet@1{ 14828fb04b9bSjmcneill compatible = "hisilicon,hns-nic-v2"; 14838fb04b9bSjmcneill ae-handle = <&dsaf0>; 14848fb04b9bSjmcneill port-idx-in-ae = <1>; 14858fb04b9bSjmcneill local-mac-address = [00 00 00 00 00 00]; 14868fb04b9bSjmcneill status = "disabled"; 14878fb04b9bSjmcneill dma-coherent; 14888fb04b9bSjmcneill }; 14898fb04b9bSjmcneill 14908fb04b9bSjmcneill infiniband@c4000000 { 14918fb04b9bSjmcneill compatible = "hisilicon,hns-roce-v1"; 14928fb04b9bSjmcneill reg = <0x0 0xc4000000 0x0 0x100000>; 14938fb04b9bSjmcneill dma-coherent; 14948fb04b9bSjmcneill eth-handle = <ð2 ð3 0 0 ð0 ð1>; 14958fb04b9bSjmcneill dsaf-handle = <&dsaf0>; 14968fb04b9bSjmcneill node-guid = [00 9A CD 00 00 01 02 03]; 14978fb04b9bSjmcneill #address-cells = <2>; 14988fb04b9bSjmcneill #size-cells = <2>; 14998fb04b9bSjmcneill interrupt-parent = <&mbigen_dsa_roce>; 15008fb04b9bSjmcneill interrupts = <722 1>, 15018fb04b9bSjmcneill <723 1>, 15028fb04b9bSjmcneill <724 1>, 15038fb04b9bSjmcneill <725 1>, 15048fb04b9bSjmcneill <726 1>, 15058fb04b9bSjmcneill <727 1>, 15068fb04b9bSjmcneill <728 1>, 15078fb04b9bSjmcneill <729 1>, 15088fb04b9bSjmcneill <730 1>, 15098fb04b9bSjmcneill <731 1>, 15108fb04b9bSjmcneill <732 1>, 15118fb04b9bSjmcneill <733 1>, 15128fb04b9bSjmcneill <734 1>, 15138fb04b9bSjmcneill <735 1>, 15148fb04b9bSjmcneill <736 1>, 15158fb04b9bSjmcneill <737 1>, 15168fb04b9bSjmcneill <738 1>, 15178fb04b9bSjmcneill <739 1>, 15188fb04b9bSjmcneill <740 1>, 15198fb04b9bSjmcneill <741 1>, 15208fb04b9bSjmcneill <742 1>, 15218fb04b9bSjmcneill <743 1>, 15228fb04b9bSjmcneill <744 1>, 15238fb04b9bSjmcneill <745 1>, 15248fb04b9bSjmcneill <746 1>, 15258fb04b9bSjmcneill <747 1>, 15268fb04b9bSjmcneill <748 1>, 15278fb04b9bSjmcneill <749 1>, 15288fb04b9bSjmcneill <750 1>, 15298fb04b9bSjmcneill <751 1>, 15308fb04b9bSjmcneill <752 1>, 15318fb04b9bSjmcneill <753 1>, 15328fb04b9bSjmcneill <785 1>, 15338fb04b9bSjmcneill <754 4>; 15348fb04b9bSjmcneill 15358fb04b9bSjmcneill interrupt-names = "hns-roce-comp-0", 15368fb04b9bSjmcneill "hns-roce-comp-1", 15378fb04b9bSjmcneill "hns-roce-comp-2", 15388fb04b9bSjmcneill "hns-roce-comp-3", 15398fb04b9bSjmcneill "hns-roce-comp-4", 15408fb04b9bSjmcneill "hns-roce-comp-5", 15418fb04b9bSjmcneill "hns-roce-comp-6", 15428fb04b9bSjmcneill "hns-roce-comp-7", 15438fb04b9bSjmcneill "hns-roce-comp-8", 15448fb04b9bSjmcneill "hns-roce-comp-9", 15458fb04b9bSjmcneill "hns-roce-comp-10", 15468fb04b9bSjmcneill "hns-roce-comp-11", 15478fb04b9bSjmcneill "hns-roce-comp-12", 15488fb04b9bSjmcneill "hns-roce-comp-13", 15498fb04b9bSjmcneill "hns-roce-comp-14", 15508fb04b9bSjmcneill "hns-roce-comp-15", 15518fb04b9bSjmcneill "hns-roce-comp-16", 15528fb04b9bSjmcneill "hns-roce-comp-17", 15538fb04b9bSjmcneill "hns-roce-comp-18", 15548fb04b9bSjmcneill "hns-roce-comp-19", 15558fb04b9bSjmcneill "hns-roce-comp-20", 15568fb04b9bSjmcneill "hns-roce-comp-21", 15578fb04b9bSjmcneill "hns-roce-comp-22", 15588fb04b9bSjmcneill "hns-roce-comp-23", 15598fb04b9bSjmcneill "hns-roce-comp-24", 15608fb04b9bSjmcneill "hns-roce-comp-25", 15618fb04b9bSjmcneill "hns-roce-comp-26", 15628fb04b9bSjmcneill "hns-roce-comp-27", 15638fb04b9bSjmcneill "hns-roce-comp-28", 15648fb04b9bSjmcneill "hns-roce-comp-29", 15658fb04b9bSjmcneill "hns-roce-comp-30", 15668fb04b9bSjmcneill "hns-roce-comp-31", 15678fb04b9bSjmcneill "hns-roce-async", 15688fb04b9bSjmcneill "hns-roce-common"; 15698fb04b9bSjmcneill }; 15708fb04b9bSjmcneill 15718fb04b9bSjmcneill sas0: sas@c3000000 { 15728fb04b9bSjmcneill compatible = "hisilicon,hip07-sas-v2"; 15738fb04b9bSjmcneill reg = <0 0xc3000000 0 0x10000>; 15748fb04b9bSjmcneill sas-addr = [50 01 88 20 16 00 00 00]; 15758fb04b9bSjmcneill hisilicon,sas-syscon = <&dsa_subctrl>; 15768fb04b9bSjmcneill ctrl-reset-reg = <0xa60>; 15778fb04b9bSjmcneill ctrl-reset-sts-reg = <0x5a30>; 15788fb04b9bSjmcneill ctrl-clock-ena-reg = <0x338>; 15798fb04b9bSjmcneill queue-count = <16>; 15808fb04b9bSjmcneill phy-count = <8>; 15818fb04b9bSjmcneill dma-coherent; 15828fb04b9bSjmcneill interrupt-parent = <&mbigen_sas0>; 15838fb04b9bSjmcneill interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, 15848fb04b9bSjmcneill <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, 15858fb04b9bSjmcneill <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, 15868fb04b9bSjmcneill <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, 15878fb04b9bSjmcneill <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, 15888fb04b9bSjmcneill <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, 15898fb04b9bSjmcneill <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, 15908fb04b9bSjmcneill <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, 15918fb04b9bSjmcneill <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, 15928fb04b9bSjmcneill <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, 15938fb04b9bSjmcneill <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, 15948fb04b9bSjmcneill <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, 15958fb04b9bSjmcneill <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, 15968fb04b9bSjmcneill <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, 15978fb04b9bSjmcneill <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, 15988fb04b9bSjmcneill <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, 15998fb04b9bSjmcneill <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, 16008fb04b9bSjmcneill <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, 16018fb04b9bSjmcneill <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, 16028fb04b9bSjmcneill <159 4>,<601 1>,<602 1>,<603 1>,<604 1>, 16038fb04b9bSjmcneill <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, 16048fb04b9bSjmcneill <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, 16058fb04b9bSjmcneill <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, 16068fb04b9bSjmcneill <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, 16078fb04b9bSjmcneill <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, 16088fb04b9bSjmcneill <630 1>,<631 1>,<632 1>; 16098fb04b9bSjmcneill status = "disabled"; 16108fb04b9bSjmcneill }; 16118fb04b9bSjmcneill 16128fb04b9bSjmcneill sas1: sas@a2000000 { 16138fb04b9bSjmcneill compatible = "hisilicon,hip07-sas-v2"; 16148fb04b9bSjmcneill reg = <0 0xa2000000 0 0x10000>; 16158fb04b9bSjmcneill sas-addr = [50 01 88 20 16 00 00 00]; 16168fb04b9bSjmcneill hisilicon,sas-syscon = <&pcie_subctl>; 16178fb04b9bSjmcneill hip06-sas-v2-quirk-amt; 16188fb04b9bSjmcneill ctrl-reset-reg = <0xa18>; 16198fb04b9bSjmcneill ctrl-reset-sts-reg = <0x5a0c>; 16208fb04b9bSjmcneill ctrl-clock-ena-reg = <0x318>; 16218fb04b9bSjmcneill queue-count = <16>; 16228fb04b9bSjmcneill phy-count = <8>; 16238fb04b9bSjmcneill dma-coherent; 16248fb04b9bSjmcneill interrupt-parent = <&mbigen_sas1>; 16258fb04b9bSjmcneill interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, 16268fb04b9bSjmcneill <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, 16278fb04b9bSjmcneill <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, 16288fb04b9bSjmcneill <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, 16298fb04b9bSjmcneill <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, 16308fb04b9bSjmcneill <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, 16318fb04b9bSjmcneill <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, 16328fb04b9bSjmcneill <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, 16338fb04b9bSjmcneill <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, 16348fb04b9bSjmcneill <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, 16358fb04b9bSjmcneill <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, 16368fb04b9bSjmcneill <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, 16378fb04b9bSjmcneill <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, 16388fb04b9bSjmcneill <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, 16398fb04b9bSjmcneill <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, 16408fb04b9bSjmcneill <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, 16418fb04b9bSjmcneill <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, 16428fb04b9bSjmcneill <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, 16438fb04b9bSjmcneill <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, 16448fb04b9bSjmcneill <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, 16458fb04b9bSjmcneill <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, 16468fb04b9bSjmcneill <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, 16478fb04b9bSjmcneill <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, 16488fb04b9bSjmcneill <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, 16498fb04b9bSjmcneill <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, 16508fb04b9bSjmcneill <605 1>,<606 1>,<607 1>; 16518fb04b9bSjmcneill status = "disabled"; 16528fb04b9bSjmcneill }; 16538fb04b9bSjmcneill 16548fb04b9bSjmcneill sas2: sas@a3000000 { 16558fb04b9bSjmcneill compatible = "hisilicon,hip07-sas-v2"; 16568fb04b9bSjmcneill reg = <0 0xa3000000 0 0x10000>; 16578fb04b9bSjmcneill sas-addr = [50 01 88 20 16 00 00 00]; 16588fb04b9bSjmcneill hisilicon,sas-syscon = <&pcie_subctl>; 16598fb04b9bSjmcneill ctrl-reset-reg = <0xae0>; 16608fb04b9bSjmcneill ctrl-reset-sts-reg = <0x5a70>; 16618fb04b9bSjmcneill ctrl-clock-ena-reg = <0x3a8>; 16628fb04b9bSjmcneill queue-count = <16>; 16638fb04b9bSjmcneill phy-count = <9>; 16648fb04b9bSjmcneill dma-coherent; 16658fb04b9bSjmcneill interrupt-parent = <&mbigen_sas2>; 16668fb04b9bSjmcneill interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, 16678fb04b9bSjmcneill <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, 16688fb04b9bSjmcneill <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, 16698fb04b9bSjmcneill <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, 16708fb04b9bSjmcneill <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, 16718fb04b9bSjmcneill <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, 16728fb04b9bSjmcneill <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, 16738fb04b9bSjmcneill <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, 16748fb04b9bSjmcneill <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, 16758fb04b9bSjmcneill <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, 16768fb04b9bSjmcneill <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, 16778fb04b9bSjmcneill <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, 16788fb04b9bSjmcneill <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, 16798fb04b9bSjmcneill <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, 16808fb04b9bSjmcneill <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, 16818fb04b9bSjmcneill <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, 16828fb04b9bSjmcneill <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, 16838fb04b9bSjmcneill <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, 16848fb04b9bSjmcneill <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, 16858fb04b9bSjmcneill <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, 16868fb04b9bSjmcneill <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, 16878fb04b9bSjmcneill <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, 16888fb04b9bSjmcneill <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, 16898fb04b9bSjmcneill <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, 16908fb04b9bSjmcneill <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, 16918fb04b9bSjmcneill <637 1>,<638 1>,<639 1>; 16928fb04b9bSjmcneill status = "disabled"; 16938fb04b9bSjmcneill }; 169405c11c73Sjmcneill 169505c11c73Sjmcneill p0_pcie2_a: pcie@a00a0000 { 169605c11c73Sjmcneill compatible = "hisilicon,hip07-pcie-ecam"; 169705c11c73Sjmcneill reg = <0 0xaf800000 0 0x800000>, 169805c11c73Sjmcneill <0 0xa00a0000 0 0x10000>; 169905c11c73Sjmcneill bus-range = <0xf8 0xff>; 170005c11c73Sjmcneill msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>; 170105c11c73Sjmcneill msi-map-mask = <0xffff>; 170205c11c73Sjmcneill #address-cells = <3>; 170305c11c73Sjmcneill #size-cells = <2>; 170405c11c73Sjmcneill device_type = "pci"; 170505c11c73Sjmcneill dma-coherent; 1706*9ed2a30eSjmcneill ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000>, 1707*9ed2a30eSjmcneill <0x01000000 0 0 0 0xaf7f0000 0 0x10000>; 170805c11c73Sjmcneill #interrupt-cells = <1>; 170905c11c73Sjmcneill interrupt-map-mask = <0xf800 0 0 7>; 171005c11c73Sjmcneill interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4 171105c11c73Sjmcneill 0x0 0 0 2 &mbigen_pcie2_a 671 4 171205c11c73Sjmcneill 0x0 0 0 3 &mbigen_pcie2_a 671 4 171305c11c73Sjmcneill 0x0 0 0 4 &mbigen_pcie2_a 671 4>; 171405c11c73Sjmcneill status = "disabled"; 171505c11c73Sjmcneill }; 1716182157ecSjmcneill p0_sec_a: crypto@d2000000 { 1717182157ecSjmcneill compatible = "hisilicon,hip07-sec"; 1718*9ed2a30eSjmcneill reg = <0x0 0xd0000000 0x0 0x10000>, 1719*9ed2a30eSjmcneill <0x0 0xd2000000 0x0 0x10000>, 1720*9ed2a30eSjmcneill <0x0 0xd2010000 0x0 0x10000>, 1721*9ed2a30eSjmcneill <0x0 0xd2020000 0x0 0x10000>, 1722*9ed2a30eSjmcneill <0x0 0xd2030000 0x0 0x10000>, 1723*9ed2a30eSjmcneill <0x0 0xd2040000 0x0 0x10000>, 1724*9ed2a30eSjmcneill <0x0 0xd2050000 0x0 0x10000>, 1725*9ed2a30eSjmcneill <0x0 0xd2060000 0x0 0x10000>, 1726*9ed2a30eSjmcneill <0x0 0xd2070000 0x0 0x10000>, 1727*9ed2a30eSjmcneill <0x0 0xd2080000 0x0 0x10000>, 1728*9ed2a30eSjmcneill <0x0 0xd2090000 0x0 0x10000>, 1729*9ed2a30eSjmcneill <0x0 0xd20a0000 0x0 0x10000>, 1730*9ed2a30eSjmcneill <0x0 0xd20b0000 0x0 0x10000>, 1731*9ed2a30eSjmcneill <0x0 0xd20c0000 0x0 0x10000>, 1732*9ed2a30eSjmcneill <0x0 0xd20d0000 0x0 0x10000>, 1733*9ed2a30eSjmcneill <0x0 0xd20e0000 0x0 0x10000>, 1734*9ed2a30eSjmcneill <0x0 0xd20f0000 0x0 0x10000>, 1735*9ed2a30eSjmcneill <0x0 0xd2100000 0x0 0x10000>; 1736182157ecSjmcneill interrupt-parent = <&p0_mbigen_sec_a>; 1737182157ecSjmcneill iommus = <&p0_smmu_alg_a 0x600>; 1738182157ecSjmcneill dma-coherent; 1739182157ecSjmcneill interrupts = <576 4>, 1740182157ecSjmcneill <577 1>, <578 4>, 1741182157ecSjmcneill <579 1>, <580 4>, 1742182157ecSjmcneill <581 1>, <582 4>, 1743182157ecSjmcneill <583 1>, <584 4>, 1744182157ecSjmcneill <585 1>, <586 4>, 1745182157ecSjmcneill <587 1>, <588 4>, 1746182157ecSjmcneill <589 1>, <590 4>, 1747182157ecSjmcneill <591 1>, <592 4>, 1748182157ecSjmcneill <593 1>, <594 4>, 1749182157ecSjmcneill <595 1>, <596 4>, 1750182157ecSjmcneill <597 1>, <598 4>, 1751182157ecSjmcneill <599 1>, <600 4>, 1752182157ecSjmcneill <601 1>, <602 4>, 1753182157ecSjmcneill <603 1>, <604 4>, 1754182157ecSjmcneill <605 1>, <606 4>, 1755182157ecSjmcneill <607 1>, <608 4>; 1756182157ecSjmcneill }; 1757182157ecSjmcneill p0_sec_b: crypto@8,d2000000 { 1758182157ecSjmcneill compatible = "hisilicon,hip07-sec"; 1759*9ed2a30eSjmcneill reg = <0x8 0xd0000000 0x0 0x10000>, 1760*9ed2a30eSjmcneill <0x8 0xd2000000 0x0 0x10000>, 1761*9ed2a30eSjmcneill <0x8 0xd2010000 0x0 0x10000>, 1762*9ed2a30eSjmcneill <0x8 0xd2020000 0x0 0x10000>, 1763*9ed2a30eSjmcneill <0x8 0xd2030000 0x0 0x10000>, 1764*9ed2a30eSjmcneill <0x8 0xd2040000 0x0 0x10000>, 1765*9ed2a30eSjmcneill <0x8 0xd2050000 0x0 0x10000>, 1766*9ed2a30eSjmcneill <0x8 0xd2060000 0x0 0x10000>, 1767*9ed2a30eSjmcneill <0x8 0xd2070000 0x0 0x10000>, 1768*9ed2a30eSjmcneill <0x8 0xd2080000 0x0 0x10000>, 1769*9ed2a30eSjmcneill <0x8 0xd2090000 0x0 0x10000>, 1770*9ed2a30eSjmcneill <0x8 0xd20a0000 0x0 0x10000>, 1771*9ed2a30eSjmcneill <0x8 0xd20b0000 0x0 0x10000>, 1772*9ed2a30eSjmcneill <0x8 0xd20c0000 0x0 0x10000>, 1773*9ed2a30eSjmcneill <0x8 0xd20d0000 0x0 0x10000>, 1774*9ed2a30eSjmcneill <0x8 0xd20e0000 0x0 0x10000>, 1775*9ed2a30eSjmcneill <0x8 0xd20f0000 0x0 0x10000>, 1776*9ed2a30eSjmcneill <0x8 0xd2100000 0x0 0x10000>; 1777182157ecSjmcneill interrupt-parent = <&p0_mbigen_sec_b>; 1778182157ecSjmcneill iommus = <&p0_smmu_alg_b 0x600>; 1779182157ecSjmcneill dma-coherent; 1780182157ecSjmcneill interrupts = <576 4>, 1781182157ecSjmcneill <577 1>, <578 4>, 1782182157ecSjmcneill <579 1>, <580 4>, 1783182157ecSjmcneill <581 1>, <582 4>, 1784182157ecSjmcneill <583 1>, <584 4>, 1785182157ecSjmcneill <585 1>, <586 4>, 1786182157ecSjmcneill <587 1>, <588 4>, 1787182157ecSjmcneill <589 1>, <590 4>, 1788182157ecSjmcneill <591 1>, <592 4>, 1789182157ecSjmcneill <593 1>, <594 4>, 1790182157ecSjmcneill <595 1>, <596 4>, 1791182157ecSjmcneill <597 1>, <598 4>, 1792182157ecSjmcneill <599 1>, <600 4>, 1793182157ecSjmcneill <601 1>, <602 4>, 1794182157ecSjmcneill <603 1>, <604 4>, 1795182157ecSjmcneill <605 1>, <606 4>, 1796182157ecSjmcneill <607 1>, <608 4>; 1797182157ecSjmcneill }; 1798182157ecSjmcneill p1_sec_a: crypto@400,d2000000 { 1799182157ecSjmcneill compatible = "hisilicon,hip07-sec"; 1800*9ed2a30eSjmcneill reg = <0x400 0xd0000000 0x0 0x10000>, 1801*9ed2a30eSjmcneill <0x400 0xd2000000 0x0 0x10000>, 1802*9ed2a30eSjmcneill <0x400 0xd2010000 0x0 0x10000>, 1803*9ed2a30eSjmcneill <0x400 0xd2020000 0x0 0x10000>, 1804*9ed2a30eSjmcneill <0x400 0xd2030000 0x0 0x10000>, 1805*9ed2a30eSjmcneill <0x400 0xd2040000 0x0 0x10000>, 1806*9ed2a30eSjmcneill <0x400 0xd2050000 0x0 0x10000>, 1807*9ed2a30eSjmcneill <0x400 0xd2060000 0x0 0x10000>, 1808*9ed2a30eSjmcneill <0x400 0xd2070000 0x0 0x10000>, 1809*9ed2a30eSjmcneill <0x400 0xd2080000 0x0 0x10000>, 1810*9ed2a30eSjmcneill <0x400 0xd2090000 0x0 0x10000>, 1811*9ed2a30eSjmcneill <0x400 0xd20a0000 0x0 0x10000>, 1812*9ed2a30eSjmcneill <0x400 0xd20b0000 0x0 0x10000>, 1813*9ed2a30eSjmcneill <0x400 0xd20c0000 0x0 0x10000>, 1814*9ed2a30eSjmcneill <0x400 0xd20d0000 0x0 0x10000>, 1815*9ed2a30eSjmcneill <0x400 0xd20e0000 0x0 0x10000>, 1816*9ed2a30eSjmcneill <0x400 0xd20f0000 0x0 0x10000>, 1817*9ed2a30eSjmcneill <0x400 0xd2100000 0x0 0x10000>; 1818182157ecSjmcneill interrupt-parent = <&p1_mbigen_sec_a>; 1819182157ecSjmcneill iommus = <&p1_smmu_alg_a 0x600>; 1820182157ecSjmcneill dma-coherent; 1821182157ecSjmcneill interrupts = <576 4>, 1822182157ecSjmcneill <577 1>, <578 4>, 1823182157ecSjmcneill <579 1>, <580 4>, 1824182157ecSjmcneill <581 1>, <582 4>, 1825182157ecSjmcneill <583 1>, <584 4>, 1826182157ecSjmcneill <585 1>, <586 4>, 1827182157ecSjmcneill <587 1>, <588 4>, 1828182157ecSjmcneill <589 1>, <590 4>, 1829182157ecSjmcneill <591 1>, <592 4>, 1830182157ecSjmcneill <593 1>, <594 4>, 1831182157ecSjmcneill <595 1>, <596 4>, 1832182157ecSjmcneill <597 1>, <598 4>, 1833182157ecSjmcneill <599 1>, <600 4>, 1834182157ecSjmcneill <601 1>, <602 4>, 1835182157ecSjmcneill <603 1>, <604 4>, 1836182157ecSjmcneill <605 1>, <606 4>, 1837182157ecSjmcneill <607 1>, <608 4>; 1838182157ecSjmcneill }; 1839182157ecSjmcneill p1_sec_b: crypto@408,d2000000 { 1840182157ecSjmcneill compatible = "hisilicon,hip07-sec"; 1841*9ed2a30eSjmcneill reg = <0x408 0xd0000000 0x0 0x10000>, 1842*9ed2a30eSjmcneill <0x408 0xd2000000 0x0 0x10000>, 1843*9ed2a30eSjmcneill <0x408 0xd2010000 0x0 0x10000>, 1844*9ed2a30eSjmcneill <0x408 0xd2020000 0x0 0x10000>, 1845*9ed2a30eSjmcneill <0x408 0xd2030000 0x0 0x10000>, 1846*9ed2a30eSjmcneill <0x408 0xd2040000 0x0 0x10000>, 1847*9ed2a30eSjmcneill <0x408 0xd2050000 0x0 0x10000>, 1848*9ed2a30eSjmcneill <0x408 0xd2060000 0x0 0x10000>, 1849*9ed2a30eSjmcneill <0x408 0xd2070000 0x0 0x10000>, 1850*9ed2a30eSjmcneill <0x408 0xd2080000 0x0 0x10000>, 1851*9ed2a30eSjmcneill <0x408 0xd2090000 0x0 0x10000>, 1852*9ed2a30eSjmcneill <0x408 0xd20a0000 0x0 0x10000>, 1853*9ed2a30eSjmcneill <0x408 0xd20b0000 0x0 0x10000>, 1854*9ed2a30eSjmcneill <0x408 0xd20c0000 0x0 0x10000>, 1855*9ed2a30eSjmcneill <0x408 0xd20d0000 0x0 0x10000>, 1856*9ed2a30eSjmcneill <0x408 0xd20e0000 0x0 0x10000>, 1857*9ed2a30eSjmcneill <0x408 0xd20f0000 0x0 0x10000>, 1858*9ed2a30eSjmcneill <0x408 0xd2100000 0x0 0x10000>; 1859182157ecSjmcneill interrupt-parent = <&p1_mbigen_sec_b>; 1860182157ecSjmcneill iommus = <&p1_smmu_alg_b 0x600>; 1861182157ecSjmcneill dma-coherent; 1862182157ecSjmcneill interrupts = <576 4>, 1863182157ecSjmcneill <577 1>, <578 4>, 1864182157ecSjmcneill <579 1>, <580 4>, 1865182157ecSjmcneill <581 1>, <582 4>, 1866182157ecSjmcneill <583 1>, <584 4>, 1867182157ecSjmcneill <585 1>, <586 4>, 1868182157ecSjmcneill <587 1>, <588 4>, 1869182157ecSjmcneill <589 1>, <590 4>, 1870182157ecSjmcneill <591 1>, <592 4>, 1871182157ecSjmcneill <593 1>, <594 4>, 1872182157ecSjmcneill <595 1>, <596 4>, 1873182157ecSjmcneill <597 1>, <598 4>, 1874182157ecSjmcneill <599 1>, <600 4>, 1875182157ecSjmcneill <601 1>, <602 4>, 1876182157ecSjmcneill <603 1>, <604 4>, 1877182157ecSjmcneill <605 1>, <606 4>, 1878182157ecSjmcneill <607 1>, <608 4>; 1879182157ecSjmcneill }; 1880182157ecSjmcneill 1881f46c7ed4Sjmcneill }; 1882f46c7ed4Sjmcneill}; 1883