11e10b93dSalc /*
21e10b93dSalc * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
31e10b93dSalc * Copyright (c) 2002-2006 Atheros Communications, Inc.
41e10b93dSalc *
51e10b93dSalc * Permission to use, copy, modify, and/or distribute this software for any
61e10b93dSalc * purpose with or without fee is hereby granted, provided that the above
71e10b93dSalc * copyright notice and this permission notice appear in all copies.
81e10b93dSalc *
91e10b93dSalc * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
101e10b93dSalc * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
111e10b93dSalc * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
121e10b93dSalc * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
131e10b93dSalc * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
141e10b93dSalc * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
151e10b93dSalc * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
161e10b93dSalc *
17*f24695abScegger * $Id: ar5211_reset.c,v 1.4 2011/03/07 11:25:42 cegger Exp $
181e10b93dSalc */
191e10b93dSalc #include "opt_ah.h"
201e10b93dSalc
211e10b93dSalc /*
221e10b93dSalc * Chips specific device attachment and device info collection
231e10b93dSalc * Connects Init Reg Vectors, EEPROM Data, and device Functions.
241e10b93dSalc */
251e10b93dSalc #include "ah.h"
261e10b93dSalc #include "ah_internal.h"
271e10b93dSalc #include "ah_devid.h"
281e10b93dSalc
291e10b93dSalc #include "ar5211/ar5211.h"
301e10b93dSalc #include "ar5211/ar5211reg.h"
311e10b93dSalc #include "ar5211/ar5211phy.h"
321e10b93dSalc
331e10b93dSalc #include "ah_eeprom_v3.h"
341e10b93dSalc
351e10b93dSalc /* Add static register initialization vectors */
361e10b93dSalc #include "ar5211/boss.ini"
371e10b93dSalc
381e10b93dSalc /*
391e10b93dSalc * Structure to hold 11b tuning information for Beanie/Sombrero
401e10b93dSalc * 16 MHz mode, divider ratio = 198 = NP+S. N=16, S=4 or 6, P=12
411e10b93dSalc */
421e10b93dSalc typedef struct {
431e10b93dSalc uint32_t refClkSel; /* reference clock, 1 for 16 MHz */
441e10b93dSalc uint32_t channelSelect; /* P[7:4]S[3:0] bits */
451e10b93dSalc uint16_t channel5111; /* 11a channel for 5111 */
461e10b93dSalc } CHAN_INFO_2GHZ;
471e10b93dSalc
481e10b93dSalc #define CI_2GHZ_INDEX_CORRECTION 19
49a9d4fb0bSalc static const CHAN_INFO_2GHZ chan2GHzData[] = {
501e10b93dSalc { 1, 0x46, 96 }, /* 2312 -19 */
511e10b93dSalc { 1, 0x46, 97 }, /* 2317 -18 */
521e10b93dSalc { 1, 0x46, 98 }, /* 2322 -17 */
531e10b93dSalc { 1, 0x46, 99 }, /* 2327 -16 */
541e10b93dSalc { 1, 0x46, 100 }, /* 2332 -15 */
551e10b93dSalc { 1, 0x46, 101 }, /* 2337 -14 */
561e10b93dSalc { 1, 0x46, 102 }, /* 2342 -13 */
571e10b93dSalc { 1, 0x46, 103 }, /* 2347 -12 */
581e10b93dSalc { 1, 0x46, 104 }, /* 2352 -11 */
591e10b93dSalc { 1, 0x46, 105 }, /* 2357 -10 */
601e10b93dSalc { 1, 0x46, 106 }, /* 2362 -9 */
611e10b93dSalc { 1, 0x46, 107 }, /* 2367 -8 */
621e10b93dSalc { 1, 0x46, 108 }, /* 2372 -7 */
631e10b93dSalc /* index -6 to 0 are pad to make this a nolookup table */
641e10b93dSalc { 1, 0x46, 116 }, /* -6 */
651e10b93dSalc { 1, 0x46, 116 }, /* -5 */
661e10b93dSalc { 1, 0x46, 116 }, /* -4 */
671e10b93dSalc { 1, 0x46, 116 }, /* -3 */
681e10b93dSalc { 1, 0x46, 116 }, /* -2 */
691e10b93dSalc { 1, 0x46, 116 }, /* -1 */
701e10b93dSalc { 1, 0x46, 116 }, /* 0 */
711e10b93dSalc { 1, 0x46, 116 }, /* 2412 1 */
721e10b93dSalc { 1, 0x46, 117 }, /* 2417 2 */
731e10b93dSalc { 1, 0x46, 118 }, /* 2422 3 */
741e10b93dSalc { 1, 0x46, 119 }, /* 2427 4 */
751e10b93dSalc { 1, 0x46, 120 }, /* 2432 5 */
761e10b93dSalc { 1, 0x46, 121 }, /* 2437 6 */
771e10b93dSalc { 1, 0x46, 122 }, /* 2442 7 */
781e10b93dSalc { 1, 0x46, 123 }, /* 2447 8 */
791e10b93dSalc { 1, 0x46, 124 }, /* 2452 9 */
801e10b93dSalc { 1, 0x46, 125 }, /* 2457 10 */
811e10b93dSalc { 1, 0x46, 126 }, /* 2462 11 */
821e10b93dSalc { 1, 0x46, 127 }, /* 2467 12 */
831e10b93dSalc { 1, 0x46, 128 }, /* 2472 13 */
841e10b93dSalc { 1, 0x44, 124 }, /* 2484 14 */
851e10b93dSalc { 1, 0x46, 136 }, /* 2512 15 */
861e10b93dSalc { 1, 0x46, 140 }, /* 2532 16 */
871e10b93dSalc { 1, 0x46, 144 }, /* 2552 17 */
881e10b93dSalc { 1, 0x46, 148 }, /* 2572 18 */
891e10b93dSalc { 1, 0x46, 152 }, /* 2592 19 */
901e10b93dSalc { 1, 0x46, 156 }, /* 2612 20 */
911e10b93dSalc { 1, 0x46, 160 }, /* 2632 21 */
921e10b93dSalc { 1, 0x46, 164 }, /* 2652 22 */
931e10b93dSalc { 1, 0x46, 168 }, /* 2672 23 */
941e10b93dSalc { 1, 0x46, 172 }, /* 2692 24 */
951e10b93dSalc { 1, 0x46, 176 }, /* 2712 25 */
961e10b93dSalc { 1, 0x46, 180 } /* 2732 26 */
971e10b93dSalc };
981e10b93dSalc
991e10b93dSalc /* Power timeouts in usec to wait for chip to wake-up. */
1001e10b93dSalc #define POWER_UP_TIME 2000
1011e10b93dSalc
1021e10b93dSalc #define DELAY_PLL_SETTLE 300 /* 300 us */
1031e10b93dSalc #define DELAY_BASE_ACTIVATE 100 /* 100 us */
1041e10b93dSalc
1051e10b93dSalc #define NUM_RATES 8
1061e10b93dSalc
1071e10b93dSalc static HAL_BOOL ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask);
1081e10b93dSalc static HAL_BOOL ar5211SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
1091e10b93dSalc static int16_t ar5211RunNoiseFloor(struct ath_hal *,
1101e10b93dSalc uint8_t runTime, int16_t startingNF);
1111e10b93dSalc static HAL_BOOL ar5211IsNfGood(struct ath_hal *, HAL_CHANNEL_INTERNAL *chan);
1121e10b93dSalc static HAL_BOOL ar5211SetRf6and7(struct ath_hal *, HAL_CHANNEL *chan);
1131e10b93dSalc static HAL_BOOL ar5211SetBoardValues(struct ath_hal *, HAL_CHANNEL *chan);
1141e10b93dSalc static void ar5211SetPowerTable(struct ath_hal *,
1151e10b93dSalc PCDACS_EEPROM *pSrcStruct, uint16_t channel);
1161e10b93dSalc static void ar5211SetRateTable(struct ath_hal *,
1171e10b93dSalc RD_EDGES_POWER *pRdEdgesPower, TRGT_POWER_INFO *pPowerInfo,
1181e10b93dSalc uint16_t numChannels, HAL_CHANNEL *chan);
1191e10b93dSalc static uint16_t ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue,
1201e10b93dSalc const PCDACS_EEPROM *pSrcStruct);
1211e10b93dSalc static HAL_BOOL ar5211FindValueInList(uint16_t channel, uint16_t pcdacValue,
1221e10b93dSalc const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue);
1231e10b93dSalc static uint16_t ar5211GetInterpolatedValue(uint16_t target,
1241e10b93dSalc uint16_t srcLeft, uint16_t srcRight,
1251e10b93dSalc uint16_t targetLeft, uint16_t targetRight, HAL_BOOL scaleUp);
1261e10b93dSalc static void ar5211GetLowerUpperValues(uint16_t value,
1271e10b93dSalc const uint16_t *pList, uint16_t listSize,
1281e10b93dSalc uint16_t *pLowerValue, uint16_t *pUpperValue);
1291e10b93dSalc static void ar5211GetLowerUpperPcdacs(uint16_t pcdac,
1301e10b93dSalc uint16_t channel, const PCDACS_EEPROM *pSrcStruct,
1311e10b93dSalc uint16_t *pLowerPcdac, uint16_t *pUpperPcdac);
1321e10b93dSalc
1331e10b93dSalc static void ar5211SetRfgain(struct ath_hal *, const GAIN_VALUES *);;
1341e10b93dSalc static void ar5211RequestRfgain(struct ath_hal *);
1351e10b93dSalc static HAL_BOOL ar5211InvalidGainReadback(struct ath_hal *, GAIN_VALUES *);
1361e10b93dSalc static HAL_BOOL ar5211IsGainAdjustNeeded(struct ath_hal *, const GAIN_VALUES *);
1371e10b93dSalc static int32_t ar5211AdjustGain(struct ath_hal *, GAIN_VALUES *);
1381e10b93dSalc static void ar5211SetOperatingMode(struct ath_hal *, int opmode);
1391e10b93dSalc
1401e10b93dSalc /*
1411e10b93dSalc * Places the device in and out of reset and then places sane
1421e10b93dSalc * values in the registers based on EEPROM config, initialization
1431e10b93dSalc * vectors (as determined by the mode), and station configuration
1441e10b93dSalc *
1451e10b93dSalc * bChannelChange is used to preserve DMA/PCU registers across
1461e10b93dSalc * a HW Reset during channel change.
1471e10b93dSalc */
1481e10b93dSalc HAL_BOOL
ar5211Reset(struct ath_hal * ah,HAL_OPMODE opmode,HAL_CHANNEL * chan,HAL_BOOL bChannelChange,HAL_STATUS * status)1491e10b93dSalc ar5211Reset(struct ath_hal *ah, HAL_OPMODE opmode,
1501e10b93dSalc HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
1511e10b93dSalc {
1521e10b93dSalc uint32_t softLedCfg, softLedState;
1531e10b93dSalc #define N(a) (sizeof (a) /sizeof (a[0]))
1541e10b93dSalc #define FAIL(_code) do { ecode = _code; goto bad; } while (0)
1551e10b93dSalc struct ath_hal_5211 *ahp = AH5211(ah);
1561e10b93dSalc HAL_CHANNEL_INTERNAL *ichan;
1571e10b93dSalc uint32_t i, ledstate;
1581e10b93dSalc HAL_STATUS ecode;
1591e10b93dSalc int q;
1601e10b93dSalc
1611e10b93dSalc uint32_t data, synthDelay;
1621e10b93dSalc uint32_t macStaId1;
1631e10b93dSalc uint16_t modesIndex = 0, freqIndex = 0;
1641e10b93dSalc uint32_t saveFrameSeqCount[AR_NUM_DCU];
1651e10b93dSalc uint32_t saveTsfLow = 0, saveTsfHigh = 0;
1661e10b93dSalc uint32_t saveDefAntenna;
1671e10b93dSalc
1681e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RESET,
1691e10b93dSalc "%s: opmode %u channel %u/0x%x %s channel\n",
1701e10b93dSalc __func__, opmode, chan->channel, chan->channelFlags,
1711e10b93dSalc bChannelChange ? "change" : "same");
1721e10b93dSalc
1731e10b93dSalc OS_MARK(ah, AH_MARK_RESET, bChannelChange);
1741e10b93dSalc #define IS(_c,_f) (((_c)->channelFlags & _f) || 0)
1751e10b93dSalc if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan,CHANNEL_5GHZ)) == 0) {
1761e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
1771e10b93dSalc "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
1781e10b93dSalc __func__, chan->channel, chan->channelFlags);
1791e10b93dSalc FAIL(HAL_EINVAL);
1801e10b93dSalc }
1811e10b93dSalc if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) {
1821e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
1831e10b93dSalc "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n",
1841e10b93dSalc __func__, chan->channel, chan->channelFlags);
1851e10b93dSalc FAIL(HAL_EINVAL);
1861e10b93dSalc }
1871e10b93dSalc #undef IS
1881e10b93dSalc /*
1891e10b93dSalc * Map public channel to private.
1901e10b93dSalc */
1911e10b93dSalc ichan = ath_hal_checkchannel(ah, chan);
1921e10b93dSalc if (ichan == AH_NULL) {
1931e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
1941e10b93dSalc "%s: invalid channel %u/0x%x; no mapping\n",
1951e10b93dSalc __func__, chan->channel, chan->channelFlags);
1961e10b93dSalc FAIL(HAL_EINVAL);
1971e10b93dSalc }
1981e10b93dSalc switch (opmode) {
1991e10b93dSalc case HAL_M_STA:
2001e10b93dSalc case HAL_M_IBSS:
2011e10b93dSalc case HAL_M_HOSTAP:
2021e10b93dSalc case HAL_M_MONITOR:
2031e10b93dSalc break;
2041e10b93dSalc default:
2051e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
2061e10b93dSalc "%s: invalid operating mode %u\n", __func__, opmode);
2071e10b93dSalc FAIL(HAL_EINVAL);
2081e10b93dSalc break;
2091e10b93dSalc }
2101e10b93dSalc HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3);
2111e10b93dSalc
2121e10b93dSalc /* Preserve certain DMA hardware registers on a channel change */
2131e10b93dSalc if (bChannelChange) {
2141e10b93dSalc /*
2151e10b93dSalc * Need to save/restore the TSF because of an issue
2161e10b93dSalc * that accelerates the TSF during a chip reset.
2171e10b93dSalc *
2181e10b93dSalc * We could use system timer routines to more
2191e10b93dSalc * accurately restore the TSF, but
2201e10b93dSalc * 1. Timer routines on certain platforms are
2211e10b93dSalc * not accurate enough (e.g. 1 ms resolution).
2221e10b93dSalc * 2. It would still not be accurate.
2231e10b93dSalc *
2241e10b93dSalc * The most important aspect of this workaround,
2251e10b93dSalc * is that, after reset, the TSF is behind
2261e10b93dSalc * other STAs TSFs. This will allow the STA to
2271e10b93dSalc * properly resynchronize its TSF in adhoc mode.
2281e10b93dSalc */
2291e10b93dSalc saveTsfLow = OS_REG_READ(ah, AR_TSF_L32);
2301e10b93dSalc saveTsfHigh = OS_REG_READ(ah, AR_TSF_U32);
2311e10b93dSalc
2321e10b93dSalc /* Read frame sequence count */
2331e10b93dSalc if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
2341e10b93dSalc saveFrameSeqCount[0] = OS_REG_READ(ah, AR_D0_SEQNUM);
2351e10b93dSalc } else {
2361e10b93dSalc for (i = 0; i < AR_NUM_DCU; i++)
2371e10b93dSalc saveFrameSeqCount[i] = OS_REG_READ(ah, AR_DSEQNUM(i));
2381e10b93dSalc }
2391e10b93dSalc if (!(ichan->privFlags & CHANNEL_DFS))
2401e10b93dSalc ichan->privFlags &= ~CHANNEL_INTERFERENCE;
2411e10b93dSalc chan->channelFlags = ichan->channelFlags;
2421e10b93dSalc chan->privFlags = ichan->privFlags;
2431e10b93dSalc }
2441e10b93dSalc
2451e10b93dSalc /*
2461e10b93dSalc * Preserve the antenna on a channel change
2471e10b93dSalc */
2481e10b93dSalc saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
2491e10b93dSalc if (saveDefAntenna == 0)
2501e10b93dSalc saveDefAntenna = 1;
2511e10b93dSalc
2521e10b93dSalc /* Save hardware flag before chip reset clears the register */
2531e10b93dSalc macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2541e10b93dSalc
2551e10b93dSalc /* Save led state from pci config register */
2561e10b93dSalc ledstate = OS_REG_READ(ah, AR_PCICFG) &
2571e10b93dSalc (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK |
2581e10b93dSalc AR_PCICFG_LEDSLOW);
2591e10b93dSalc softLedCfg = OS_REG_READ(ah, AR_GPIOCR);
2601e10b93dSalc softLedState = OS_REG_READ(ah, AR_GPIODO);
2611e10b93dSalc
2621e10b93dSalc if (!ar5211ChipReset(ah, chan->channelFlags)) {
2631e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
2641e10b93dSalc FAIL(HAL_EIO);
2651e10b93dSalc }
2661e10b93dSalc
2671e10b93dSalc /* Setup the indices for the next set of register array writes */
2681e10b93dSalc switch (chan->channelFlags & CHANNEL_ALL) {
2691e10b93dSalc case CHANNEL_A:
2701e10b93dSalc modesIndex = 1;
2711e10b93dSalc freqIndex = 1;
2721e10b93dSalc break;
2731e10b93dSalc case CHANNEL_T:
2741e10b93dSalc modesIndex = 2;
2751e10b93dSalc freqIndex = 1;
2761e10b93dSalc break;
2771e10b93dSalc case CHANNEL_B:
2781e10b93dSalc modesIndex = 3;
2791e10b93dSalc freqIndex = 2;
2801e10b93dSalc break;
2811e10b93dSalc case CHANNEL_PUREG:
2821e10b93dSalc modesIndex = 4;
2831e10b93dSalc freqIndex = 2;
2841e10b93dSalc break;
2851e10b93dSalc default:
2861e10b93dSalc /* Ah, a new wireless mode */
2871e10b93dSalc HALASSERT(0);
2881e10b93dSalc break;
2891e10b93dSalc }
2901e10b93dSalc
2911e10b93dSalc /* Set correct Baseband to analog shift setting to access analog chips. */
2921e10b93dSalc if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
2931e10b93dSalc OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
2941e10b93dSalc } else {
2951e10b93dSalc OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);
2961e10b93dSalc }
2971e10b93dSalc
2981e10b93dSalc /* Write parameters specific to AR5211 */
2991e10b93dSalc if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
3001e10b93dSalc if (IS_CHAN_2GHZ(chan) &&
3011e10b93dSalc AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1) {
3021e10b93dSalc HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
3031e10b93dSalc uint32_t ob2GHz, db2GHz;
3041e10b93dSalc
3051e10b93dSalc if (IS_CHAN_CCK(chan)) {
3061e10b93dSalc ob2GHz = ee->ee_ob2GHz[0];
3071e10b93dSalc db2GHz = ee->ee_db2GHz[0];
3081e10b93dSalc } else {
3091e10b93dSalc ob2GHz = ee->ee_ob2GHz[1];
3101e10b93dSalc db2GHz = ee->ee_db2GHz[1];
3111e10b93dSalc }
3121e10b93dSalc ob2GHz = ath_hal_reverseBits(ob2GHz, 3);
3131e10b93dSalc db2GHz = ath_hal_reverseBits(db2GHz, 3);
3141e10b93dSalc ar5211Mode2_4[25][freqIndex] =
3151e10b93dSalc (ar5211Mode2_4[25][freqIndex] & ~0xC0) |
3161e10b93dSalc ((ob2GHz << 6) & 0xC0);
3171e10b93dSalc ar5211Mode2_4[26][freqIndex] =
3181e10b93dSalc (ar5211Mode2_4[26][freqIndex] & ~0x0F) |
3191e10b93dSalc (((ob2GHz >> 2) & 0x1) |
3201e10b93dSalc ((db2GHz << 1) & 0x0E));
3211e10b93dSalc }
3221e10b93dSalc for (i = 0; i < N(ar5211Mode2_4); i++)
3231e10b93dSalc OS_REG_WRITE(ah, ar5211Mode2_4[i][0],
3241e10b93dSalc ar5211Mode2_4[i][freqIndex]);
3251e10b93dSalc }
3261e10b93dSalc
3271e10b93dSalc /* Write the analog registers 6 and 7 before other config */
3281e10b93dSalc ar5211SetRf6and7(ah, chan);
3291e10b93dSalc
3301e10b93dSalc /* Write registers that vary across all modes */
3311e10b93dSalc for (i = 0; i < N(ar5211Modes); i++)
3321e10b93dSalc OS_REG_WRITE(ah, ar5211Modes[i][0], ar5211Modes[i][modesIndex]);
3331e10b93dSalc
3341e10b93dSalc /* Write RFGain Parameters that differ between 2.4 and 5 GHz */
3351e10b93dSalc for (i = 0; i < N(ar5211BB_RfGain); i++)
3361e10b93dSalc OS_REG_WRITE(ah, ar5211BB_RfGain[i][0], ar5211BB_RfGain[i][freqIndex]);
3371e10b93dSalc
3381e10b93dSalc /* Write Common Array Parameters */
3391e10b93dSalc for (i = 0; i < N(ar5211Common); i++) {
3401e10b93dSalc uint32_t reg = ar5211Common[i][0];
3411e10b93dSalc /* On channel change, don't reset the PCU registers */
3421e10b93dSalc if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))
3431e10b93dSalc OS_REG_WRITE(ah, reg, ar5211Common[i][1]);
3441e10b93dSalc }
3451e10b93dSalc
3461e10b93dSalc /* Fix pre-AR5211 register values, this includes AR5311s. */
3471e10b93dSalc if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
3481e10b93dSalc /*
3491e10b93dSalc * The TX and RX latency values have changed locations
3501e10b93dSalc * within the USEC register in AR5211. Since they're
3511e10b93dSalc * set via the .ini, for both AR5211 and AR5311, they
3521e10b93dSalc * are written properly here for AR5311.
3531e10b93dSalc */
3541e10b93dSalc data = OS_REG_READ(ah, AR_USEC);
3551e10b93dSalc /* Must be 0 for proper write in AR5311 */
3561e10b93dSalc HALASSERT((data & 0x00700000) == 0);
3571e10b93dSalc OS_REG_WRITE(ah, AR_USEC,
3581e10b93dSalc (data & (AR_USEC_M | AR_USEC_32_M | AR5311_USEC_TX_LAT_M)) |
3591e10b93dSalc ((29 << AR5311_USEC_RX_LAT_S) & AR5311_USEC_RX_LAT_M));
3601e10b93dSalc /* The following registers exist only on AR5311. */
3611e10b93dSalc OS_REG_WRITE(ah, AR5311_QDCLKGATE, 0);
3621e10b93dSalc
3631e10b93dSalc /* Set proper ADC & DAC delays for AR5311. */
3641e10b93dSalc OS_REG_WRITE(ah, 0x00009878, 0x00000008);
3651e10b93dSalc
3661e10b93dSalc /* Enable the PCU FIFO corruption ECO on AR5311. */
3671e10b93dSalc OS_REG_WRITE(ah, AR_DIAG_SW,
3681e10b93dSalc OS_REG_READ(ah, AR_DIAG_SW) | AR5311_DIAG_SW_USE_ECO);
3691e10b93dSalc }
3701e10b93dSalc
3711e10b93dSalc /* Restore certain DMA hardware registers on a channel change */
3721e10b93dSalc if (bChannelChange) {
3731e10b93dSalc /* Restore TSF */
3741e10b93dSalc OS_REG_WRITE(ah, AR_TSF_L32, saveTsfLow);
3751e10b93dSalc OS_REG_WRITE(ah, AR_TSF_U32, saveTsfHigh);
3761e10b93dSalc
3771e10b93dSalc if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
3781e10b93dSalc OS_REG_WRITE(ah, AR_D0_SEQNUM, saveFrameSeqCount[0]);
3791e10b93dSalc } else {
3801e10b93dSalc for (i = 0; i < AR_NUM_DCU; i++)
3811e10b93dSalc OS_REG_WRITE(ah, AR_DSEQNUM(i), saveFrameSeqCount[i]);
3821e10b93dSalc }
3831e10b93dSalc }
3841e10b93dSalc
3851e10b93dSalc OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
3861e10b93dSalc OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
3871e10b93dSalc | macStaId1
3881e10b93dSalc );
3891e10b93dSalc ar5211SetOperatingMode(ah, opmode);
3901e10b93dSalc
3911e10b93dSalc /* Restore previous led state */
3921e10b93dSalc OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);
3931e10b93dSalc OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg);
3941e10b93dSalc OS_REG_WRITE(ah, AR_GPIODO, softLedState);
3951e10b93dSalc
3961e10b93dSalc /* Restore previous antenna */
3971e10b93dSalc OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3981e10b93dSalc
3991e10b93dSalc OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
4001e10b93dSalc OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
4011e10b93dSalc
4021e10b93dSalc /* Restore bmiss rssi & count thresholds */
4031e10b93dSalc OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
4041e10b93dSalc
4051e10b93dSalc OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
4061e10b93dSalc
4071e10b93dSalc /*
4081e10b93dSalc * for pre-Production Oahu only.
4091e10b93dSalc * Disable clock gating in all DMA blocks. Helps when using
4101e10b93dSalc * 11B and AES but results in higher power consumption.
4111e10b93dSalc */
4121e10b93dSalc if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_OAHU &&
4131e10b93dSalc AH_PRIVATE(ah)->ah_macRev < AR_SREV_OAHU_PROD) {
4141e10b93dSalc OS_REG_WRITE(ah, AR_CFG,
4151e10b93dSalc OS_REG_READ(ah, AR_CFG) | AR_CFG_CLK_GATE_DIS);
4161e10b93dSalc }
4171e10b93dSalc
4181e10b93dSalc /* Setup the transmit power values. */
4191e10b93dSalc if (!ar5211SetTransmitPower(ah, chan)) {
4201e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
4211e10b93dSalc "%s: error init'ing transmit power\n", __func__);
4221e10b93dSalc FAIL(HAL_EIO);
4231e10b93dSalc }
4241e10b93dSalc
4251e10b93dSalc /*
4261e10b93dSalc * Configurable OFDM spoofing for 11n compatibility; used
4271e10b93dSalc * only when operating in station mode.
4281e10b93dSalc */
4291e10b93dSalc if (opmode != HAL_M_HOSTAP &&
4301e10b93dSalc (AH_PRIVATE(ah)->ah_11nCompat & HAL_DIAG_11N_SERVICES) != 0) {
4311e10b93dSalc /* NB: override the .ini setting */
4321e10b93dSalc OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
4331e10b93dSalc AR_PHY_FRAME_CTL_ERR_SERV,
4341e10b93dSalc MS(AH_PRIVATE(ah)->ah_11nCompat, HAL_DIAG_11N_SERVICES)&1);
4351e10b93dSalc }
4361e10b93dSalc
4371e10b93dSalc /* Setup board specific options for EEPROM version 3 */
4381e10b93dSalc ar5211SetBoardValues(ah, chan);
4391e10b93dSalc
4401e10b93dSalc if (!ar5211SetChannel(ah, ichan)) {
4411e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",
4421e10b93dSalc __func__);
4431e10b93dSalc FAIL(HAL_EIO);
4441e10b93dSalc }
4451e10b93dSalc
4461e10b93dSalc /* Activate the PHY */
4471e10b93dSalc if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B && IS_CHAN_2GHZ(chan))
4481e10b93dSalc OS_REG_WRITE(ah, 0xd808, 0x502); /* required for FPGA */
4491e10b93dSalc OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
4501e10b93dSalc
4511e10b93dSalc /*
4521e10b93dSalc * Wait for the frequency synth to settle (synth goes on
4531e10b93dSalc * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
4541e10b93dSalc * Value is in 100ns increments.
4551e10b93dSalc */
4561e10b93dSalc data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_M;
4571e10b93dSalc if (IS_CHAN_CCK(chan)) {
4581e10b93dSalc synthDelay = (4 * data) / 22;
4591e10b93dSalc } else {
4601e10b93dSalc synthDelay = data / 10;
4611e10b93dSalc }
4621e10b93dSalc /*
4631e10b93dSalc * There is an issue if the AP starts the calibration before
4641e10b93dSalc * the baseband timeout completes. This could result in the
4651e10b93dSalc * rxclear false triggering. Add an extra delay to ensure this
4661e10b93dSalc * this does not happen.
4671e10b93dSalc */
4681e10b93dSalc OS_DELAY(synthDelay + DELAY_BASE_ACTIVATE);
4691e10b93dSalc
4701e10b93dSalc /* Calibrate the AGC and wait for completion. */
4711e10b93dSalc OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
4721e10b93dSalc OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
4731e10b93dSalc (void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0);
4741e10b93dSalc
4751e10b93dSalc /* Perform noise floor and set status */
4761e10b93dSalc if (!ar5211CalNoiseFloor(ah, ichan)) {
4771e10b93dSalc if (!IS_CHAN_CCK(chan))
4781e10b93dSalc chan->channelFlags |= CHANNEL_CW_INT;
4791e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
4801e10b93dSalc "%s: noise floor calibration failed\n", __func__);
4811e10b93dSalc FAIL(HAL_EIO);
4821e10b93dSalc }
4831e10b93dSalc
4841e10b93dSalc /* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
4851e10b93dSalc if (ahp->ah_calibrationTime != 0) {
4861e10b93dSalc OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4,
4871e10b93dSalc AR_PHY_TIMING_CTRL4_DO_IQCAL | (INIT_IQCAL_LOG_COUNT_MAX << AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S));
4881e10b93dSalc ahp->ah_bIQCalibration = AH_TRUE;
4891e10b93dSalc }
4901e10b93dSalc
4911e10b93dSalc /* set 1:1 QCU to DCU mapping for all queues */
4921e10b93dSalc for (q = 0; q < AR_NUM_DCU; q++)
4931e10b93dSalc OS_REG_WRITE(ah, AR_DQCUMASK(q), 1<<q);
4941e10b93dSalc
4951e10b93dSalc for (q = 0; q < HAL_NUM_TX_QUEUES; q++)
4961e10b93dSalc ar5211ResetTxQueue(ah, q);
4971e10b93dSalc
4981e10b93dSalc /* Setup QCU0 transmit interrupt masks (TX_ERR, TX_OK, TX_DESC, TX_URN) */
4991e10b93dSalc OS_REG_WRITE(ah, AR_IMR_S0,
5001e10b93dSalc (AR_IMR_S0_QCU_TXOK & AR_QCU_0) |
5011e10b93dSalc (AR_IMR_S0_QCU_TXDESC & (AR_QCU_0<<AR_IMR_S0_QCU_TXDESC_S)));
5021e10b93dSalc OS_REG_WRITE(ah, AR_IMR_S1, (AR_IMR_S1_QCU_TXERR & AR_QCU_0));
5031e10b93dSalc OS_REG_WRITE(ah, AR_IMR_S2, (AR_IMR_S2_QCU_TXURN & AR_QCU_0));
5041e10b93dSalc
5051e10b93dSalc /*
5061e10b93dSalc * GBL_EIFS must always be written after writing
5071e10b93dSalc * to any QCUMASK register.
5081e10b93dSalc */
5091e10b93dSalc OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, OS_REG_READ(ah, AR_D_GBL_IFS_EIFS));
5101e10b93dSalc
5111e10b93dSalc /* Now set up the Interrupt Mask Register and save it for future use */
5121e10b93dSalc OS_REG_WRITE(ah, AR_IMR, INIT_INTERRUPT_MASK);
5131e10b93dSalc ahp->ah_maskReg = INIT_INTERRUPT_MASK;
5141e10b93dSalc
5151e10b93dSalc /* Enable bus error interrupts */
5161e10b93dSalc OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) |
5171e10b93dSalc AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR);
5181e10b93dSalc
5191e10b93dSalc /* Enable interrupts specific to AP */
5201e10b93dSalc if (opmode == HAL_M_HOSTAP) {
5211e10b93dSalc OS_REG_WRITE(ah, AR_IMR, OS_REG_READ(ah, AR_IMR) | AR_IMR_MIB);
5221e10b93dSalc ahp->ah_maskReg |= AR_IMR_MIB;
5231e10b93dSalc }
5241e10b93dSalc
5251e10b93dSalc if (AH_PRIVATE(ah)->ah_rfkillEnabled)
5261e10b93dSalc ar5211EnableRfKill(ah);
5271e10b93dSalc
5281e10b93dSalc /*
5291e10b93dSalc * Writing to AR_BEACON will start timers. Hence it should
5301e10b93dSalc * be the last register to be written. Do not reset tsf, do
5311e10b93dSalc * not enable beacons at this point, but preserve other values
5321e10b93dSalc * like beaconInterval.
5331e10b93dSalc */
5341e10b93dSalc OS_REG_WRITE(ah, AR_BEACON,
5351e10b93dSalc (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
5361e10b93dSalc
5371e10b93dSalc /* Restore user-specified slot time and timeouts */
5381e10b93dSalc if (ahp->ah_sifstime != (u_int) -1)
5391e10b93dSalc ar5211SetSifsTime(ah, ahp->ah_sifstime);
5401e10b93dSalc if (ahp->ah_slottime != (u_int) -1)
5411e10b93dSalc ar5211SetSlotTime(ah, ahp->ah_slottime);
5421e10b93dSalc if (ahp->ah_acktimeout != (u_int) -1)
5431e10b93dSalc ar5211SetAckTimeout(ah, ahp->ah_acktimeout);
5441e10b93dSalc if (ahp->ah_ctstimeout != (u_int) -1)
5451e10b93dSalc ar5211SetCTSTimeout(ah, ahp->ah_ctstimeout);
5461e10b93dSalc if (AH_PRIVATE(ah)->ah_diagreg != 0)
5471e10b93dSalc OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
5481e10b93dSalc
5491e10b93dSalc AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
5501e10b93dSalc
5511e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
5521e10b93dSalc
5531e10b93dSalc return AH_TRUE;
5541e10b93dSalc bad:
555*f24695abScegger if (status != AH_NULL)
5561e10b93dSalc *status = ecode;
5571e10b93dSalc return AH_FALSE;
5581e10b93dSalc #undef FAIL
5591e10b93dSalc #undef N
5601e10b93dSalc }
5611e10b93dSalc
5621e10b93dSalc /*
5631e10b93dSalc * Places the PHY and Radio chips into reset. A full reset
5641e10b93dSalc * must be called to leave this state. The PCI/MAC/PCU are
5651e10b93dSalc * not placed into reset as we must receive interrupt to
5661e10b93dSalc * re-enable the hardware.
5671e10b93dSalc */
5681e10b93dSalc HAL_BOOL
ar5211PhyDisable(struct ath_hal * ah)5691e10b93dSalc ar5211PhyDisable(struct ath_hal *ah)
5701e10b93dSalc {
5711e10b93dSalc return ar5211SetResetReg(ah, AR_RC_BB);
5721e10b93dSalc }
5731e10b93dSalc
5741e10b93dSalc /*
5751e10b93dSalc * Places all of hardware into reset
5761e10b93dSalc */
5771e10b93dSalc HAL_BOOL
ar5211Disable(struct ath_hal * ah)5781e10b93dSalc ar5211Disable(struct ath_hal *ah)
5791e10b93dSalc {
5801e10b93dSalc if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
5811e10b93dSalc return AH_FALSE;
5821e10b93dSalc /*
5831e10b93dSalc * Reset the HW - PCI must be reset after the rest of the
5841e10b93dSalc * device has been reset.
5851e10b93dSalc */
5861e10b93dSalc if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))
5871e10b93dSalc return AH_FALSE;
5881e10b93dSalc OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */
5891e10b93dSalc
5901e10b93dSalc return AH_TRUE;
5911e10b93dSalc }
5921e10b93dSalc
5931e10b93dSalc /*
5941e10b93dSalc * Places the hardware into reset and then pulls it out of reset
5951e10b93dSalc *
5961e10b93dSalc * Only write the PLL if we're changing to or from CCK mode
5971e10b93dSalc *
5981e10b93dSalc * Attach calls with channelFlags = 0, as the coldreset should have
5991e10b93dSalc * us in the correct mode and we cannot check the hwchannel flags.
6001e10b93dSalc */
6011e10b93dSalc HAL_BOOL
ar5211ChipReset(struct ath_hal * ah,uint16_t channelFlags)6021e10b93dSalc ar5211ChipReset(struct ath_hal *ah, uint16_t channelFlags)
6031e10b93dSalc {
6041e10b93dSalc if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
6051e10b93dSalc return AH_FALSE;
6061e10b93dSalc
6071e10b93dSalc /* Set CCK and Turbo modes correctly */
6081e10b93dSalc switch (channelFlags & CHANNEL_ALL) {
6091e10b93dSalc case CHANNEL_2GHZ|CHANNEL_CCK:
6101e10b93dSalc case CHANNEL_2GHZ|CHANNEL_CCK|CHANNEL_TURBO:
6111e10b93dSalc OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
6121e10b93dSalc OS_REG_WRITE(ah, AR5211_PHY_MODE,
6131e10b93dSalc AR5211_PHY_MODE_CCK | AR5211_PHY_MODE_RF2GHZ);
6141e10b93dSalc OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
6151e10b93dSalc /* Wait for the PLL to settle */
6161e10b93dSalc OS_DELAY(DELAY_PLL_SETTLE);
6171e10b93dSalc break;
6181e10b93dSalc case CHANNEL_2GHZ|CHANNEL_OFDM:
6191e10b93dSalc case CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO:
6201e10b93dSalc OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
6211e10b93dSalc if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {
6221e10b93dSalc OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
6231e10b93dSalc OS_DELAY(DELAY_PLL_SETTLE);
6241e10b93dSalc OS_REG_WRITE(ah, AR5211_PHY_MODE,
6251e10b93dSalc AR5211_PHY_MODE_OFDM | AR5211_PHY_MODE_RF2GHZ);
6261e10b93dSalc }
6271e10b93dSalc break;
6281e10b93dSalc case CHANNEL_A:
6291e10b93dSalc case CHANNEL_T:
6301e10b93dSalc if (channelFlags & CHANNEL_TURBO) {
6311e10b93dSalc OS_REG_WRITE(ah, AR_PHY_TURBO,
6321e10b93dSalc AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT);
6331e10b93dSalc } else { /* 5 GHZ OFDM Mode */
6341e10b93dSalc OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
6351e10b93dSalc }
6361e10b93dSalc if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {
6371e10b93dSalc OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
6381e10b93dSalc OS_DELAY(DELAY_PLL_SETTLE);
6391e10b93dSalc OS_REG_WRITE(ah, AR5211_PHY_MODE,
6401e10b93dSalc AR5211_PHY_MODE_OFDM | AR5211_PHY_MODE_RF5GHZ);
6411e10b93dSalc }
6421e10b93dSalc break;
6431e10b93dSalc }
6441e10b93dSalc /* NB: else no flags set - must be attach calling - do nothing */
6451e10b93dSalc
6461e10b93dSalc /*
6471e10b93dSalc * Reset the HW - PCI must be reset after the rest of the
6481e10b93dSalc * device has been reset
6491e10b93dSalc */
6501e10b93dSalc if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))
6511e10b93dSalc return AH_FALSE;
6521e10b93dSalc OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */
6531e10b93dSalc
6541e10b93dSalc /* Bring out of sleep mode (AGAIN) */
6551e10b93dSalc if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
6561e10b93dSalc return AH_FALSE;
6571e10b93dSalc
6581e10b93dSalc /* Clear warm reset register */
6591e10b93dSalc return ar5211SetResetReg(ah, 0);
6601e10b93dSalc }
6611e10b93dSalc
6621e10b93dSalc /*
6631e10b93dSalc * Recalibrate the lower PHY chips to account for temperature/environment
6641e10b93dSalc * changes.
6651e10b93dSalc */
6661e10b93dSalc HAL_BOOL
ar5211PerCalibrationN(struct ath_hal * ah,HAL_CHANNEL * chan,u_int chainMask,HAL_BOOL longCal,HAL_BOOL * isCalDone)6671e10b93dSalc ar5211PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, u_int chainMask,
6681e10b93dSalc HAL_BOOL longCal, HAL_BOOL *isCalDone)
6691e10b93dSalc {
6701e10b93dSalc struct ath_hal_5211 *ahp = AH5211(ah);
6711e10b93dSalc HAL_CHANNEL_INTERNAL *ichan;
6721e10b93dSalc int32_t qCoff, qCoffDenom;
6731e10b93dSalc uint32_t data;
6741e10b93dSalc int32_t iqCorrMeas;
6751e10b93dSalc int32_t iCoff, iCoffDenom;
6761e10b93dSalc uint32_t powerMeasQ, powerMeasI;
6771e10b93dSalc
6781e10b93dSalc ichan = ath_hal_checkchannel(ah, chan);
6791e10b93dSalc if (ichan == AH_NULL) {
6801e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
6811e10b93dSalc "%s: invalid channel %u/0x%x; no mapping\n",
6821e10b93dSalc __func__, chan->channel, chan->channelFlags);
6831e10b93dSalc return AH_FALSE;
6841e10b93dSalc }
6851e10b93dSalc /* IQ calibration in progress. Check to see if it has finished. */
6861e10b93dSalc if (ahp->ah_bIQCalibration &&
6871e10b93dSalc !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {
6881e10b93dSalc /* IQ Calibration has finished. */
6891e10b93dSalc ahp->ah_bIQCalibration = AH_FALSE;
6901e10b93dSalc
6911e10b93dSalc /* Read calibration results. */
6921e10b93dSalc powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I);
6931e10b93dSalc powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q);
6941e10b93dSalc iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS);
6951e10b93dSalc
6961e10b93dSalc /*
6971e10b93dSalc * Prescale these values to remove 64-bit operation requirement at the loss
6981e10b93dSalc * of a little precision.
6991e10b93dSalc */
7001e10b93dSalc iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
7011e10b93dSalc qCoffDenom = powerMeasQ / 64;
7021e10b93dSalc
7031e10b93dSalc /* Protect against divide-by-0. */
7041e10b93dSalc if (iCoffDenom != 0 && qCoffDenom != 0) {
7051e10b93dSalc iCoff = (-iqCorrMeas) / iCoffDenom;
7061e10b93dSalc /* IQCORR_Q_I_COFF is a signed 6 bit number */
7071e10b93dSalc iCoff = iCoff & 0x3f;
7081e10b93dSalc
7091e10b93dSalc qCoff = ((int32_t)powerMeasI / qCoffDenom) - 64;
7101e10b93dSalc /* IQCORR_Q_Q_COFF is a signed 5 bit number */
7111e10b93dSalc qCoff = qCoff & 0x1f;
7121e10b93dSalc
7131e10b93dSalc HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasI = 0x%08x\n",
7141e10b93dSalc powerMeasI);
7151e10b93dSalc HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasQ = 0x%08x\n",
7161e10b93dSalc powerMeasQ);
7171e10b93dSalc HALDEBUG(ah, HAL_DEBUG_PERCAL, "iqCorrMeas = 0x%08x\n",
7181e10b93dSalc iqCorrMeas);
7191e10b93dSalc HALDEBUG(ah, HAL_DEBUG_PERCAL, "iCoff = %d\n",
7201e10b93dSalc iCoff);
7211e10b93dSalc HALDEBUG(ah, HAL_DEBUG_PERCAL, "qCoff = %d\n",
7221e10b93dSalc qCoff);
7231e10b93dSalc
7241e10b93dSalc /* Write IQ */
7251e10b93dSalc data = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) |
7261e10b93dSalc AR_PHY_TIMING_CTRL4_IQCORR_ENABLE |
7271e10b93dSalc (((uint32_t)iCoff) << AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S) |
7281e10b93dSalc ((uint32_t)qCoff);
7291e10b93dSalc OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data);
7301e10b93dSalc }
7311e10b93dSalc }
7321e10b93dSalc *isCalDone = !ahp->ah_bIQCalibration;
7331e10b93dSalc
7341e10b93dSalc if (longCal) {
7351e10b93dSalc /* Perform noise floor and set status */
7361e10b93dSalc if (!ar5211IsNfGood(ah, ichan)) {
7371e10b93dSalc /* report up and clear internal state */
7381e10b93dSalc chan->channelFlags |= CHANNEL_CW_INT;
7391e10b93dSalc ichan->channelFlags &= ~CHANNEL_CW_INT;
7401e10b93dSalc return AH_FALSE;
7411e10b93dSalc }
7421e10b93dSalc if (!ar5211CalNoiseFloor(ah, ichan)) {
7431e10b93dSalc /*
7441e10b93dSalc * Delay 5ms before retrying the noise floor
7451e10b93dSalc * just to make sure, as we are in an error
7461e10b93dSalc * condition here.
7471e10b93dSalc */
7481e10b93dSalc OS_DELAY(5000);
7491e10b93dSalc if (!ar5211CalNoiseFloor(ah, ichan)) {
7501e10b93dSalc if (!IS_CHAN_CCK(chan))
7511e10b93dSalc chan->channelFlags |= CHANNEL_CW_INT;
7521e10b93dSalc return AH_FALSE;
7531e10b93dSalc }
7541e10b93dSalc }
7551e10b93dSalc ar5211RequestRfgain(ah);
7561e10b93dSalc }
7571e10b93dSalc return AH_TRUE;
7581e10b93dSalc }
7591e10b93dSalc
7601e10b93dSalc HAL_BOOL
ar5211PerCalibration(struct ath_hal * ah,HAL_CHANNEL * chan,HAL_BOOL * isIQdone)7611e10b93dSalc ar5211PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone)
7621e10b93dSalc {
7631e10b93dSalc return ar5211PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);
7641e10b93dSalc }
7651e10b93dSalc
7661e10b93dSalc HAL_BOOL
ar5211ResetCalValid(struct ath_hal * ah,HAL_CHANNEL * chan)7671e10b93dSalc ar5211ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
7681e10b93dSalc {
7691e10b93dSalc /* XXX */
7701e10b93dSalc return AH_TRUE;
7711e10b93dSalc }
7721e10b93dSalc
7731e10b93dSalc /*
7741e10b93dSalc * Writes the given reset bit mask into the reset register
7751e10b93dSalc */
7761e10b93dSalc static HAL_BOOL
ar5211SetResetReg(struct ath_hal * ah,uint32_t resetMask)7771e10b93dSalc ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask)
7781e10b93dSalc {
7791e10b93dSalc uint32_t mask = resetMask ? resetMask : ~0;
7801e10b93dSalc HAL_BOOL rt;
7811e10b93dSalc
7821e10b93dSalc (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */
7831e10b93dSalc OS_REG_WRITE(ah, AR_RC, resetMask);
7841e10b93dSalc
7851e10b93dSalc /* need to wait at least 128 clocks when reseting PCI before read */
7861e10b93dSalc OS_DELAY(15);
7871e10b93dSalc
7881e10b93dSalc resetMask &= AR_RC_MAC | AR_RC_BB;
7891e10b93dSalc mask &= AR_RC_MAC | AR_RC_BB;
7901e10b93dSalc rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
7911e10b93dSalc if ((resetMask & AR_RC_MAC) == 0) {
7921e10b93dSalc if (isBigEndian()) {
7931e10b93dSalc /*
7941e10b93dSalc * Set CFG, little-endian for register
7951e10b93dSalc * and descriptor accesses.
7961e10b93dSalc */
7971e10b93dSalc mask = INIT_CONFIG_STATUS |
7981e10b93dSalc AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG;
7991e10b93dSalc OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
8001e10b93dSalc } else
8011e10b93dSalc OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
8021e10b93dSalc }
8031e10b93dSalc return rt;
8041e10b93dSalc }
8051e10b93dSalc
8061e10b93dSalc /*
8071e10b93dSalc * Takes the MHz channel value and sets the Channel value
8081e10b93dSalc *
8091e10b93dSalc * ASSUMES: Writes enabled to analog bus before AGC is active
8101e10b93dSalc * or by disabling the AGC.
8111e10b93dSalc */
8121e10b93dSalc static HAL_BOOL
ar5211SetChannel(struct ath_hal * ah,HAL_CHANNEL_INTERNAL * chan)8131e10b93dSalc ar5211SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
8141e10b93dSalc {
8151e10b93dSalc uint32_t refClk, reg32, data2111;
8161e10b93dSalc int16_t chan5111, chanIEEE;
8171e10b93dSalc
8181e10b93dSalc chanIEEE = ath_hal_mhz2ieee(ah, chan->channel, chan->channelFlags);
8191e10b93dSalc if (IS_CHAN_2GHZ(chan)) {
8201e10b93dSalc const CHAN_INFO_2GHZ* ci =
8211e10b93dSalc &chan2GHzData[chanIEEE + CI_2GHZ_INDEX_CORRECTION];
8221e10b93dSalc
8231e10b93dSalc data2111 = ((ath_hal_reverseBits(ci->channelSelect, 8) & 0xff)
8241e10b93dSalc << 5)
8251e10b93dSalc | (ci->refClkSel << 4);
8261e10b93dSalc chan5111 = ci->channel5111;
8271e10b93dSalc } else {
8281e10b93dSalc data2111 = 0;
8291e10b93dSalc chan5111 = chanIEEE;
8301e10b93dSalc }
8311e10b93dSalc
8321e10b93dSalc /* Rest of the code is common for 5 GHz and 2.4 GHz. */
8331e10b93dSalc if (chan5111 >= 145 || (chan5111 & 0x1)) {
8341e10b93dSalc reg32 = ath_hal_reverseBits(chan5111 - 24, 8) & 0xFF;
8351e10b93dSalc refClk = 1;
8361e10b93dSalc } else {
8371e10b93dSalc reg32 = ath_hal_reverseBits(((chan5111 - 24) / 2), 8) & 0xFF;
8381e10b93dSalc refClk = 0;
8391e10b93dSalc }
8401e10b93dSalc
8411e10b93dSalc reg32 = (reg32 << 2) | (refClk << 1) | (1 << 10) | 0x1;
8421e10b93dSalc OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff));
8431e10b93dSalc reg32 >>= 8;
8441e10b93dSalc OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff));
8451e10b93dSalc
8461e10b93dSalc AH_PRIVATE(ah)->ah_curchan = chan;
8471e10b93dSalc return AH_TRUE;
8481e10b93dSalc }
8491e10b93dSalc
8501e10b93dSalc static int16_t
ar5211GetNoiseFloor(struct ath_hal * ah)8511e10b93dSalc ar5211GetNoiseFloor(struct ath_hal *ah)
8521e10b93dSalc {
8531e10b93dSalc int16_t nf;
8541e10b93dSalc
8551e10b93dSalc nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
8561e10b93dSalc if (nf & 0x100)
8571e10b93dSalc nf = 0 - ((nf ^ 0x1ff) + 1);
8581e10b93dSalc return nf;
8591e10b93dSalc }
8601e10b93dSalc
8611e10b93dSalc /*
8621e10b93dSalc * Peform the noisefloor calibration for the length of time set
8631e10b93dSalc * in runTime (valid values 1 to 7)
8641e10b93dSalc *
8651e10b93dSalc * Returns: The NF value at the end of the given time (or 0 for failure)
8661e10b93dSalc */
8671e10b93dSalc int16_t
ar5211RunNoiseFloor(struct ath_hal * ah,uint8_t runTime,int16_t startingNF)8681e10b93dSalc ar5211RunNoiseFloor(struct ath_hal *ah, uint8_t runTime, int16_t startingNF)
8691e10b93dSalc {
8701e10b93dSalc int i, searchTime;
8711e10b93dSalc
8721e10b93dSalc HALASSERT(runTime <= 7);
8731e10b93dSalc
8741e10b93dSalc /* Setup noise floor run time and starting value */
8751e10b93dSalc OS_REG_WRITE(ah, AR_PHY(25),
8761e10b93dSalc (OS_REG_READ(ah, AR_PHY(25)) & ~0xFFF) |
8771e10b93dSalc ((runTime << 9) & 0xE00) | (startingNF & 0x1FF));
8781e10b93dSalc /* Calibrate the noise floor */
8791e10b93dSalc OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
8801e10b93dSalc OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
8811e10b93dSalc
8821e10b93dSalc /* Compute the required amount of searchTime needed to finish NF */
8831e10b93dSalc if (runTime == 0) {
8841e10b93dSalc /* 8 search windows * 6.4us each */
8851e10b93dSalc searchTime = 8 * 7;
8861e10b93dSalc } else {
8871e10b93dSalc /* 512 * runtime search windows * 6.4us each */
8881e10b93dSalc searchTime = (runTime * 512) * 7;
8891e10b93dSalc }
8901e10b93dSalc
8911e10b93dSalc /*
8921e10b93dSalc * Do not read noise floor until it has been updated
8931e10b93dSalc *
8941e10b93dSalc * As a guesstimate - we may only get 1/60th the time on
8951e10b93dSalc * the air to see search windows in a heavily congested
8961e10b93dSalc * network (40 us every 2400 us of time)
8971e10b93dSalc */
8981e10b93dSalc for (i = 0; i < 60; i++) {
8991e10b93dSalc if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0)
9001e10b93dSalc break;
9011e10b93dSalc OS_DELAY(searchTime);
9021e10b93dSalc }
9031e10b93dSalc if (i >= 60) {
9041e10b93dSalc HALDEBUG(ah, HAL_DEBUG_NFCAL,
9051e10b93dSalc "NF with runTime %d failed to end on channel %d\n",
9061e10b93dSalc runTime, AH_PRIVATE(ah)->ah_curchan->channel);
9071e10b93dSalc HALDEBUG(ah, HAL_DEBUG_NFCAL,
9081e10b93dSalc " PHY NF Reg state: 0x%x\n",
9091e10b93dSalc OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
9101e10b93dSalc HALDEBUG(ah, HAL_DEBUG_NFCAL,
9111e10b93dSalc " PHY Active Reg state: 0x%x\n",
9121e10b93dSalc OS_REG_READ(ah, AR_PHY_ACTIVE));
9131e10b93dSalc return 0;
9141e10b93dSalc }
9151e10b93dSalc
9161e10b93dSalc return ar5211GetNoiseFloor(ah);
9171e10b93dSalc }
9181e10b93dSalc
9191e10b93dSalc static HAL_BOOL
getNoiseFloorThresh(struct ath_hal * ah,HAL_CHANNEL_INTERNAL * chan,int16_t * nft)9201e10b93dSalc getNoiseFloorThresh(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, int16_t *nft)
9211e10b93dSalc {
9221e10b93dSalc HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
9231e10b93dSalc
9241e10b93dSalc switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
9251e10b93dSalc case CHANNEL_A:
9261e10b93dSalc *nft = ee->ee_noiseFloorThresh[0];
9271e10b93dSalc break;
9281e10b93dSalc case CHANNEL_CCK|CHANNEL_2GHZ:
9291e10b93dSalc *nft = ee->ee_noiseFloorThresh[1];
9301e10b93dSalc break;
9311e10b93dSalc case CHANNEL_OFDM|CHANNEL_2GHZ:
9321e10b93dSalc *nft = ee->ee_noiseFloorThresh[2];
9331e10b93dSalc break;
9341e10b93dSalc default:
9351e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
9361e10b93dSalc __func__, chan->channelFlags);
9371e10b93dSalc return AH_FALSE;
9381e10b93dSalc }
9391e10b93dSalc return AH_TRUE;
9401e10b93dSalc }
9411e10b93dSalc
9421e10b93dSalc /*
9431e10b93dSalc * Read the NF and check it against the noise floor threshhold
9441e10b93dSalc *
9451e10b93dSalc * Returns: TRUE if the NF is good
9461e10b93dSalc */
9471e10b93dSalc static HAL_BOOL
ar5211IsNfGood(struct ath_hal * ah,HAL_CHANNEL_INTERNAL * chan)9481e10b93dSalc ar5211IsNfGood(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
9491e10b93dSalc {
9501e10b93dSalc int16_t nf, nfThresh;
9511e10b93dSalc
9521e10b93dSalc if (!getNoiseFloorThresh(ah, chan, &nfThresh))
9531e10b93dSalc return AH_FALSE;
954a9d4fb0bSalc #ifdef AH_DEBUG
9551e10b93dSalc if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
9561e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
9571e10b93dSalc "%s: NF did not complete in calibration window\n", __func__);
958a9d4fb0bSalc #endif
9591e10b93dSalc nf = ar5211GetNoiseFloor(ah);
9601e10b93dSalc if (nf > nfThresh) {
9611e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
9621e10b93dSalc "%s: noise floor failed; detected %u, threshold %u\n",
9631e10b93dSalc __func__, nf, nfThresh);
9641e10b93dSalc /*
9651e10b93dSalc * NB: Don't discriminate 2.4 vs 5Ghz, if this
9661e10b93dSalc * happens it indicates a problem regardless
9671e10b93dSalc * of the band.
9681e10b93dSalc */
9691e10b93dSalc chan->channelFlags |= CHANNEL_CW_INT;
9701e10b93dSalc }
9711e10b93dSalc chan->rawNoiseFloor = nf;
9721e10b93dSalc return (nf <= nfThresh);
9731e10b93dSalc }
9741e10b93dSalc
9751e10b93dSalc /*
9761e10b93dSalc * Peform the noisefloor calibration and check for any constant channel
9771e10b93dSalc * interference.
9781e10b93dSalc *
9791e10b93dSalc * NOTE: preAR5211 have a lengthy carrier wave detection process - hence
9801e10b93dSalc * it is if'ed for MKK regulatory domain only.
9811e10b93dSalc *
9821e10b93dSalc * Returns: TRUE for a successful noise floor calibration; else FALSE
9831e10b93dSalc */
9841e10b93dSalc HAL_BOOL
ar5211CalNoiseFloor(struct ath_hal * ah,HAL_CHANNEL_INTERNAL * chan)9851e10b93dSalc ar5211CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
9861e10b93dSalc {
9871e10b93dSalc #define N(a) (sizeof (a) / sizeof (a[0]))
9881e10b93dSalc /* Check for Carrier Wave interference in MKK regulatory zone */
9891e10b93dSalc if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU &&
9901e10b93dSalc ath_hal_getnfcheckrequired(ah, (HAL_CHANNEL *) chan)) {
9911e10b93dSalc static const uint8_t runtime[3] = { 0, 2, 7 };
9921e10b93dSalc int16_t nf, nfThresh;
9931e10b93dSalc int i;
9941e10b93dSalc
9951e10b93dSalc if (!getNoiseFloorThresh(ah, chan, &nfThresh))
9961e10b93dSalc return AH_FALSE;
9971e10b93dSalc /*
9981e10b93dSalc * Run a quick noise floor that will hopefully
9991e10b93dSalc * complete (decrease delay time).
10001e10b93dSalc */
10011e10b93dSalc for (i = 0; i < N(runtime); i++) {
10021e10b93dSalc nf = ar5211RunNoiseFloor(ah, runtime[i], 0);
10031e10b93dSalc if (nf > nfThresh) {
10041e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
10051e10b93dSalc "%s: run failed with %u > threshold %u "
10061e10b93dSalc "(runtime %u)\n", __func__,
10071e10b93dSalc nf, nfThresh, runtime[i]);
10081e10b93dSalc chan->rawNoiseFloor = 0;
10091e10b93dSalc } else
10101e10b93dSalc chan->rawNoiseFloor = nf;
10111e10b93dSalc }
10121e10b93dSalc return (i <= N(runtime));
10131e10b93dSalc } else {
10141e10b93dSalc /* Calibrate the noise floor */
10151e10b93dSalc OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
10161e10b93dSalc OS_REG_READ(ah, AR_PHY_AGC_CONTROL) |
10171e10b93dSalc AR_PHY_AGC_CONTROL_NF);
10181e10b93dSalc }
10191e10b93dSalc return AH_TRUE;
10201e10b93dSalc #undef N
10211e10b93dSalc }
10221e10b93dSalc
10231e10b93dSalc /*
10241e10b93dSalc * Adjust NF based on statistical values for 5GHz frequencies.
10251e10b93dSalc */
10261e10b93dSalc int16_t
ar5211GetNfAdjust(struct ath_hal * ah,const HAL_CHANNEL_INTERNAL * c)10271e10b93dSalc ar5211GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
10281e10b93dSalc {
10291e10b93dSalc static const struct {
10301e10b93dSalc uint16_t freqLow;
10311e10b93dSalc int16_t adjust;
10321e10b93dSalc } adjust5111[] = {
10331e10b93dSalc { 5790, 11 }, /* NB: ordered high -> low */
10341e10b93dSalc { 5730, 10 },
10351e10b93dSalc { 5690, 9 },
10361e10b93dSalc { 5660, 8 },
10371e10b93dSalc { 5610, 7 },
10381e10b93dSalc { 5530, 5 },
10391e10b93dSalc { 5450, 4 },
10401e10b93dSalc { 5379, 2 },
10411e10b93dSalc { 5209, 0 }, /* XXX? bogus but doesn't matter */
10421e10b93dSalc { 0, 1 },
10431e10b93dSalc };
10441e10b93dSalc int i;
10451e10b93dSalc
10461e10b93dSalc for (i = 0; c->channel <= adjust5111[i].freqLow; i++)
10471e10b93dSalc ;
10481e10b93dSalc /* NB: placeholder for 5111's less severe requirement */
10491e10b93dSalc return adjust5111[i].adjust / 3;
10501e10b93dSalc }
10511e10b93dSalc
10521e10b93dSalc /*
10531e10b93dSalc * Reads EEPROM header info from device structure and programs
10541e10b93dSalc * analog registers 6 and 7
10551e10b93dSalc *
10561e10b93dSalc * REQUIRES: Access to the analog device
10571e10b93dSalc */
10581e10b93dSalc static HAL_BOOL
ar5211SetRf6and7(struct ath_hal * ah,HAL_CHANNEL * chan)10591e10b93dSalc ar5211SetRf6and7(struct ath_hal *ah, HAL_CHANNEL *chan)
10601e10b93dSalc {
10611e10b93dSalc #define N(a) (sizeof (a) / sizeof (a[0]))
10621e10b93dSalc HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
10631e10b93dSalc struct ath_hal_5211 *ahp = AH5211(ah);
10641e10b93dSalc uint16_t rfXpdGain, rfPloSel, rfPwdXpd;
10651e10b93dSalc uint16_t tempOB, tempDB;
10661e10b93dSalc uint16_t freqIndex;
10671e10b93dSalc int i;
10681e10b93dSalc
10691e10b93dSalc freqIndex = (chan->channelFlags & CHANNEL_2GHZ) ? 2 : 1;
10701e10b93dSalc
10711e10b93dSalc /*
10721e10b93dSalc * TODO: This array mode correspondes with the index used
10731e10b93dSalc * during the read.
10741e10b93dSalc * For readability, this should be changed to an enum or #define
10751e10b93dSalc */
10761e10b93dSalc switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
10771e10b93dSalc case CHANNEL_A:
10781e10b93dSalc if (chan->channel > 4000 && chan->channel < 5260) {
10791e10b93dSalc tempOB = ee->ee_ob1;
10801e10b93dSalc tempDB = ee->ee_db1;
10811e10b93dSalc } else if (chan->channel >= 5260 && chan->channel < 5500) {
10821e10b93dSalc tempOB = ee->ee_ob2;
10831e10b93dSalc tempDB = ee->ee_db2;
10841e10b93dSalc } else if (chan->channel >= 5500 && chan->channel < 5725) {
10851e10b93dSalc tempOB = ee->ee_ob3;
10861e10b93dSalc tempDB = ee->ee_db3;
10871e10b93dSalc } else if (chan->channel >= 5725) {
10881e10b93dSalc tempOB = ee->ee_ob4;
10891e10b93dSalc tempDB = ee->ee_db4;
10901e10b93dSalc } else {
10911e10b93dSalc /* XXX panic?? */
10921e10b93dSalc tempOB = tempDB = 0;
10931e10b93dSalc }
10941e10b93dSalc
10951e10b93dSalc rfXpdGain = ee->ee_xgain[0];
10961e10b93dSalc rfPloSel = ee->ee_xpd[0];
10971e10b93dSalc rfPwdXpd = !ee->ee_xpd[0];
10981e10b93dSalc
10991e10b93dSalc ar5211Rf6n7[5][freqIndex] =
11001e10b93dSalc (ar5211Rf6n7[5][freqIndex] & ~0x10000000) |
11011e10b93dSalc (ee->ee_cornerCal.pd84<< 28);
11021e10b93dSalc ar5211Rf6n7[6][freqIndex] =
11031e10b93dSalc (ar5211Rf6n7[6][freqIndex] & ~0x04000000) |
11041e10b93dSalc (ee->ee_cornerCal.pd90 << 26);
11051e10b93dSalc ar5211Rf6n7[21][freqIndex] =
11061e10b93dSalc (ar5211Rf6n7[21][freqIndex] & ~0x08) |
11071e10b93dSalc (ee->ee_cornerCal.gSel << 3);
11081e10b93dSalc break;
11091e10b93dSalc case CHANNEL_CCK|CHANNEL_2GHZ:
11101e10b93dSalc tempOB = ee->ee_obFor24;
11111e10b93dSalc tempDB = ee->ee_dbFor24;
11121e10b93dSalc rfXpdGain = ee->ee_xgain[1];
11131e10b93dSalc rfPloSel = ee->ee_xpd[1];
11141e10b93dSalc rfPwdXpd = !ee->ee_xpd[1];
11151e10b93dSalc break;
11161e10b93dSalc case CHANNEL_OFDM|CHANNEL_2GHZ:
11171e10b93dSalc tempOB = ee->ee_obFor24g;
11181e10b93dSalc tempDB = ee->ee_dbFor24g;
11191e10b93dSalc rfXpdGain = ee->ee_xgain[2];
11201e10b93dSalc rfPloSel = ee->ee_xpd[2];
11211e10b93dSalc rfPwdXpd = !ee->ee_xpd[2];
11221e10b93dSalc break;
11231e10b93dSalc default:
11241e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
11251e10b93dSalc __func__, chan->channelFlags);
11261e10b93dSalc return AH_FALSE;
11271e10b93dSalc }
11281e10b93dSalc
11291e10b93dSalc HALASSERT(1 <= tempOB && tempOB <= 5);
11301e10b93dSalc HALASSERT(1 <= tempDB && tempDB <= 5);
11311e10b93dSalc
11321e10b93dSalc /* Set rfXpdGain and rfPwdXpd */
11331e10b93dSalc ar5211Rf6n7[11][freqIndex] = (ar5211Rf6n7[11][freqIndex] & ~0xC0) |
11341e10b93dSalc (((ath_hal_reverseBits(rfXpdGain, 4) << 7) | (rfPwdXpd << 6)) & 0xC0);
11351e10b93dSalc ar5211Rf6n7[12][freqIndex] = (ar5211Rf6n7[12][freqIndex] & ~0x07) |
11361e10b93dSalc ((ath_hal_reverseBits(rfXpdGain, 4) >> 1) & 0x07);
11371e10b93dSalc
11381e10b93dSalc /* Set OB */
11391e10b93dSalc ar5211Rf6n7[12][freqIndex] = (ar5211Rf6n7[12][freqIndex] & ~0x80) |
11401e10b93dSalc ((ath_hal_reverseBits(tempOB, 3) << 7) & 0x80);
11411e10b93dSalc ar5211Rf6n7[13][freqIndex] = (ar5211Rf6n7[13][freqIndex] & ~0x03) |
11421e10b93dSalc ((ath_hal_reverseBits(tempOB, 3) >> 1) & 0x03);
11431e10b93dSalc
11441e10b93dSalc /* Set DB */
11451e10b93dSalc ar5211Rf6n7[13][freqIndex] = (ar5211Rf6n7[13][freqIndex] & ~0x1C) |
11461e10b93dSalc ((ath_hal_reverseBits(tempDB, 3) << 2) & 0x1C);
11471e10b93dSalc
11481e10b93dSalc /* Set rfPloSel */
11491e10b93dSalc ar5211Rf6n7[17][freqIndex] = (ar5211Rf6n7[17][freqIndex] & ~0x08) |
11501e10b93dSalc ((rfPloSel << 3) & 0x08);
11511e10b93dSalc
11521e10b93dSalc /* Write the Rf registers 6 & 7 */
11531e10b93dSalc for (i = 0; i < N(ar5211Rf6n7); i++)
11541e10b93dSalc OS_REG_WRITE(ah, ar5211Rf6n7[i][0], ar5211Rf6n7[i][freqIndex]);
11551e10b93dSalc
11561e10b93dSalc /* Now that we have reprogrammed rfgain value, clear the flag. */
11571e10b93dSalc ahp->ah_rfgainState = RFGAIN_INACTIVE;
11581e10b93dSalc
11591e10b93dSalc return AH_TRUE;
11601e10b93dSalc #undef N
11611e10b93dSalc }
11621e10b93dSalc
11631e10b93dSalc HAL_BOOL
ar5211SetAntennaSwitchInternal(struct ath_hal * ah,HAL_ANT_SETTING settings,const HAL_CHANNEL * chan)11641e10b93dSalc ar5211SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
11651e10b93dSalc const HAL_CHANNEL *chan)
11661e10b93dSalc {
11671e10b93dSalc #define ANT_SWITCH_TABLE1 0x9960
11681e10b93dSalc #define ANT_SWITCH_TABLE2 0x9964
11691e10b93dSalc HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
11701e10b93dSalc struct ath_hal_5211 *ahp = AH5211(ah);
11711e10b93dSalc uint32_t antSwitchA, antSwitchB;
11721e10b93dSalc int ix;
11731e10b93dSalc
11741e10b93dSalc switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
11751e10b93dSalc case CHANNEL_A: ix = 0; break;
11761e10b93dSalc case CHANNEL_B: ix = 1; break;
11771e10b93dSalc case CHANNEL_PUREG: ix = 2; break;
11781e10b93dSalc default:
11791e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
11801e10b93dSalc __func__, chan->channelFlags);
11811e10b93dSalc return AH_FALSE;
11821e10b93dSalc }
11831e10b93dSalc
11841e10b93dSalc antSwitchA = ee->ee_antennaControl[1][ix]
11851e10b93dSalc | (ee->ee_antennaControl[2][ix] << 6)
11861e10b93dSalc | (ee->ee_antennaControl[3][ix] << 12)
11871e10b93dSalc | (ee->ee_antennaControl[4][ix] << 18)
11881e10b93dSalc | (ee->ee_antennaControl[5][ix] << 24)
11891e10b93dSalc ;
11901e10b93dSalc antSwitchB = ee->ee_antennaControl[6][ix]
11911e10b93dSalc | (ee->ee_antennaControl[7][ix] << 6)
11921e10b93dSalc | (ee->ee_antennaControl[8][ix] << 12)
11931e10b93dSalc | (ee->ee_antennaControl[9][ix] << 18)
11941e10b93dSalc | (ee->ee_antennaControl[10][ix] << 24)
11951e10b93dSalc ;
11961e10b93dSalc /*
11971e10b93dSalc * For fixed antenna, give the same setting for both switch banks
11981e10b93dSalc */
11991e10b93dSalc switch (settings) {
12001e10b93dSalc case HAL_ANT_FIXED_A:
12011e10b93dSalc antSwitchB = antSwitchA;
12021e10b93dSalc break;
12031e10b93dSalc case HAL_ANT_FIXED_B:
12041e10b93dSalc antSwitchA = antSwitchB;
12051e10b93dSalc break;
12061e10b93dSalc case HAL_ANT_VARIABLE:
12071e10b93dSalc break;
12081e10b93dSalc default:
12091e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n",
12101e10b93dSalc __func__, settings);
12111e10b93dSalc return AH_FALSE;
12121e10b93dSalc }
12131e10b93dSalc ahp->ah_diversityControl = settings;
12141e10b93dSalc
12151e10b93dSalc OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA);
12161e10b93dSalc OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB);
12171e10b93dSalc
12181e10b93dSalc return AH_TRUE;
12191e10b93dSalc #undef ANT_SWITCH_TABLE1
12201e10b93dSalc #undef ANT_SWITCH_TABLE2
12211e10b93dSalc }
12221e10b93dSalc
12231e10b93dSalc /*
12241e10b93dSalc * Reads EEPROM header info and programs the device for correct operation
12251e10b93dSalc * given the channel value
12261e10b93dSalc */
12271e10b93dSalc static HAL_BOOL
ar5211SetBoardValues(struct ath_hal * ah,HAL_CHANNEL * chan)12281e10b93dSalc ar5211SetBoardValues(struct ath_hal *ah, HAL_CHANNEL *chan)
12291e10b93dSalc {
12301e10b93dSalc HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
12311e10b93dSalc struct ath_hal_5211 *ahp = AH5211(ah);
12321e10b93dSalc int arrayMode, falseDectectBackoff;
12331e10b93dSalc
12341e10b93dSalc switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
12351e10b93dSalc case CHANNEL_A:
12361e10b93dSalc arrayMode = 0;
12371e10b93dSalc OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
12381e10b93dSalc AR_PHY_FRAME_CTL_TX_CLIP, ee->ee_cornerCal.clip);
12391e10b93dSalc break;
12401e10b93dSalc case CHANNEL_CCK|CHANNEL_2GHZ:
12411e10b93dSalc arrayMode = 1;
12421e10b93dSalc break;
12431e10b93dSalc case CHANNEL_OFDM|CHANNEL_2GHZ:
12441e10b93dSalc arrayMode = 2;
12451e10b93dSalc break;
12461e10b93dSalc default:
12471e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
12481e10b93dSalc __func__, chan->channelFlags);
12491e10b93dSalc return AH_FALSE;
12501e10b93dSalc }
12511e10b93dSalc
12521e10b93dSalc /* Set the antenna register(s) correctly for the chip revision */
12531e10b93dSalc if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
12541e10b93dSalc OS_REG_WRITE(ah, AR_PHY(68),
12551e10b93dSalc (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) | 0x3);
12561e10b93dSalc } else {
12571e10b93dSalc OS_REG_WRITE(ah, AR_PHY(68),
12581e10b93dSalc (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFC06) |
12591e10b93dSalc (ee->ee_antennaControl[0][arrayMode] << 4) | 0x1);
12601e10b93dSalc
12611e10b93dSalc ar5211SetAntennaSwitchInternal(ah,
12621e10b93dSalc ahp->ah_diversityControl, chan);
12631e10b93dSalc
12641e10b93dSalc /* Set the Noise Floor Thresh on ar5211 devices */
12651e10b93dSalc OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2),
12661e10b93dSalc (ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) | (1<<9));
12671e10b93dSalc }
12681e10b93dSalc OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2),
12691e10b93dSalc (OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) |
12701e10b93dSalc ((ee->ee_switchSettling[arrayMode] << 7) & 0x3F80));
12711e10b93dSalc OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2),
12721e10b93dSalc (OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) |
12731e10b93dSalc ((ee->ee_txrxAtten[arrayMode] << 12) & 0x3F000));
12741e10b93dSalc OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2),
12751e10b93dSalc (OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) |
12761e10b93dSalc ((ee->ee_pgaDesiredSize[arrayMode] << 8) & 0xFF00) |
12771e10b93dSalc (ee->ee_adcDesiredSize[arrayMode] & 0x00FF));
12781e10b93dSalc OS_REG_WRITE(ah, AR_PHY_BASE + (13 << 2),
12791e10b93dSalc (ee->ee_txEndToXPAOff[arrayMode] << 24) |
12801e10b93dSalc (ee->ee_txEndToXPAOff[arrayMode] << 16) |
12811e10b93dSalc (ee->ee_txFrameToXPAOn[arrayMode] << 8) |
12821e10b93dSalc ee->ee_txFrameToXPAOn[arrayMode]);
12831e10b93dSalc OS_REG_WRITE(ah, AR_PHY_BASE + (10 << 2),
12841e10b93dSalc (OS_REG_READ(ah, AR_PHY_BASE + (10 << 2)) & 0xFFFF00FF) |
12851e10b93dSalc (ee->ee_txEndToXLNAOn[arrayMode] << 8));
12861e10b93dSalc OS_REG_WRITE(ah, AR_PHY_BASE + (25 << 2),
12871e10b93dSalc (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) & 0xFFF80FFF) |
12881e10b93dSalc ((ee->ee_thresh62[arrayMode] << 12) & 0x7F000));
12891e10b93dSalc
12901e10b93dSalc #define NO_FALSE_DETECT_BACKOFF 2
12911e10b93dSalc #define CB22_FALSE_DETECT_BACKOFF 6
12921e10b93dSalc /*
12931e10b93dSalc * False detect backoff - suspected 32 MHz spur causes
12941e10b93dSalc * false detects in OFDM, causing Tx Hangs. Decrease
12951e10b93dSalc * weak signal sensitivity for this card.
12961e10b93dSalc */
12971e10b93dSalc falseDectectBackoff = NO_FALSE_DETECT_BACKOFF;
12981e10b93dSalc if (AH_PRIVATE(ah)->ah_eeversion < AR_EEPROM_VER3_3) {
12991e10b93dSalc if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 &&
13001e10b93dSalc IS_CHAN_OFDM(chan))
13011e10b93dSalc falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF;
13021e10b93dSalc } else {
13031e10b93dSalc uint32_t remainder = chan->channel % 32;
13041e10b93dSalc
13051e10b93dSalc if (remainder && (remainder < 10 || remainder > 22))
13061e10b93dSalc falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode];
13071e10b93dSalc }
13081e10b93dSalc OS_REG_WRITE(ah, 0x9924,
13091e10b93dSalc (OS_REG_READ(ah, 0x9924) & 0xFFFFFF01)
13101e10b93dSalc | ((falseDectectBackoff << 1) & 0xF7));
13111e10b93dSalc
13121e10b93dSalc return AH_TRUE;
13131e10b93dSalc #undef NO_FALSE_DETECT_BACKOFF
13141e10b93dSalc #undef CB22_FALSE_DETECT_BACKOFF
13151e10b93dSalc }
13161e10b93dSalc
13171e10b93dSalc /*
13181e10b93dSalc * Set the limit on the overall output power. Used for dynamic
13191e10b93dSalc * transmit power control and the like.
13201e10b93dSalc *
13211e10b93dSalc * NOTE: The power is passed in is in units of 0.5 dBm.
13221e10b93dSalc */
13231e10b93dSalc HAL_BOOL
ar5211SetTxPowerLimit(struct ath_hal * ah,uint32_t limit)13241e10b93dSalc ar5211SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
13251e10b93dSalc {
13261e10b93dSalc
13271e10b93dSalc AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
13281e10b93dSalc OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, limit);
13291e10b93dSalc return AH_TRUE;
13301e10b93dSalc }
13311e10b93dSalc
13321e10b93dSalc /*
13331e10b93dSalc * Sets the transmit power in the baseband for the given
13341e10b93dSalc * operating channel and mode.
13351e10b93dSalc */
13361e10b93dSalc HAL_BOOL
ar5211SetTransmitPower(struct ath_hal * ah,HAL_CHANNEL * chan)13371e10b93dSalc ar5211SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
13381e10b93dSalc {
13391e10b93dSalc HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
13401e10b93dSalc TRGT_POWER_INFO *pi;
13411e10b93dSalc RD_EDGES_POWER *rep;
13421e10b93dSalc PCDACS_EEPROM eepromPcdacs;
13431e10b93dSalc u_int nchan, cfgCtl;
13441e10b93dSalc int i;
13451e10b93dSalc
13461e10b93dSalc /* setup the pcdac struct to point to the correct info, based on mode */
13471e10b93dSalc switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
13481e10b93dSalc case CHANNEL_A:
13491e10b93dSalc eepromPcdacs.numChannels = ee->ee_numChannels11a;
13501e10b93dSalc eepromPcdacs.pChannelList= ee->ee_channels11a;
13511e10b93dSalc eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a;
13521e10b93dSalc nchan = ee->ee_numTargetPwr_11a;
13531e10b93dSalc pi = ee->ee_trgtPwr_11a;
13541e10b93dSalc break;
13551e10b93dSalc case CHANNEL_OFDM|CHANNEL_2GHZ:
13561e10b93dSalc eepromPcdacs.numChannels = ee->ee_numChannels2_4;
13571e10b93dSalc eepromPcdacs.pChannelList= ee->ee_channels11g;
13581e10b93dSalc eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g;
13591e10b93dSalc nchan = ee->ee_numTargetPwr_11g;
13601e10b93dSalc pi = ee->ee_trgtPwr_11g;
13611e10b93dSalc break;
13621e10b93dSalc case CHANNEL_CCK|CHANNEL_2GHZ:
13631e10b93dSalc eepromPcdacs.numChannels = ee->ee_numChannels2_4;
13641e10b93dSalc eepromPcdacs.pChannelList= ee->ee_channels11b;
13651e10b93dSalc eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b;
13661e10b93dSalc nchan = ee->ee_numTargetPwr_11b;
13671e10b93dSalc pi = ee->ee_trgtPwr_11b;
13681e10b93dSalc break;
13691e10b93dSalc default:
13701e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
13711e10b93dSalc __func__, chan->channelFlags);
13721e10b93dSalc return AH_FALSE;
13731e10b93dSalc }
13741e10b93dSalc
13751e10b93dSalc ar5211SetPowerTable(ah, &eepromPcdacs, chan->channel);
13761e10b93dSalc
13771e10b93dSalc rep = AH_NULL;
13781e10b93dSalc /* Match CTL to EEPROM value */
13791e10b93dSalc cfgCtl = ath_hal_getctl(ah, chan);
13801e10b93dSalc for (i = 0; i < ee->ee_numCtls; i++)
13811e10b93dSalc if (ee->ee_ctl[i] != 0 && ee->ee_ctl[i] == cfgCtl) {
13821e10b93dSalc rep = &ee->ee_rdEdgesPower[i * NUM_EDGES];
13831e10b93dSalc break;
13841e10b93dSalc }
13851e10b93dSalc ar5211SetRateTable(ah, rep, pi, nchan, chan);
13861e10b93dSalc
13871e10b93dSalc return AH_TRUE;
13881e10b93dSalc }
13891e10b93dSalc
13901e10b93dSalc /*
13911e10b93dSalc * Read the transmit power levels from the structures taken
13921e10b93dSalc * from EEPROM. Interpolate read transmit power values for
13931e10b93dSalc * this channel. Organize the transmit power values into a
13941e10b93dSalc * table for writing into the hardware.
13951e10b93dSalc */
13961e10b93dSalc void
ar5211SetPowerTable(struct ath_hal * ah,PCDACS_EEPROM * pSrcStruct,uint16_t channel)13971e10b93dSalc ar5211SetPowerTable(struct ath_hal *ah, PCDACS_EEPROM *pSrcStruct, uint16_t channel)
13981e10b93dSalc {
13991e10b93dSalc static FULL_PCDAC_STRUCT pcdacStruct;
14001e10b93dSalc static uint16_t pcdacTable[PWR_TABLE_SIZE];
14011e10b93dSalc
14021e10b93dSalc uint16_t i, j;
14031e10b93dSalc uint16_t *pPcdacValues;
14041e10b93dSalc int16_t *pScaledUpDbm;
14051e10b93dSalc int16_t minScaledPwr;
14061e10b93dSalc int16_t maxScaledPwr;
14071e10b93dSalc int16_t pwr;
14081e10b93dSalc uint16_t pcdacMin = 0;
14091e10b93dSalc uint16_t pcdacMax = 63;
14101e10b93dSalc uint16_t pcdacTableIndex;
14111e10b93dSalc uint16_t scaledPcdac;
14121e10b93dSalc uint32_t addr;
14131e10b93dSalc uint32_t temp32;
14141e10b93dSalc
14151e10b93dSalc OS_MEMZERO(&pcdacStruct, sizeof(FULL_PCDAC_STRUCT));
14161e10b93dSalc OS_MEMZERO(pcdacTable, sizeof(uint16_t) * PWR_TABLE_SIZE);
14171e10b93dSalc pPcdacValues = pcdacStruct.PcdacValues;
14181e10b93dSalc pScaledUpDbm = pcdacStruct.PwrValues;
14191e10b93dSalc
14201e10b93dSalc /* Initialize the pcdacs to dBM structs pcdacs to be 1 to 63 */
14211e10b93dSalc for (i = PCDAC_START, j = 0; i <= PCDAC_STOP; i+= PCDAC_STEP, j++)
14221e10b93dSalc pPcdacValues[j] = i;
14231e10b93dSalc
14241e10b93dSalc pcdacStruct.numPcdacValues = j;
14251e10b93dSalc pcdacStruct.pcdacMin = PCDAC_START;
14261e10b93dSalc pcdacStruct.pcdacMax = PCDAC_STOP;
14271e10b93dSalc
14281e10b93dSalc /* Fill out the power values for this channel */
14291e10b93dSalc for (j = 0; j < pcdacStruct.numPcdacValues; j++ )
14301e10b93dSalc pScaledUpDbm[j] = ar5211GetScaledPower(channel, pPcdacValues[j], pSrcStruct);
14311e10b93dSalc
14321e10b93dSalc /* Now scale the pcdac values to fit in the 64 entry power table */
14331e10b93dSalc minScaledPwr = pScaledUpDbm[0];
14341e10b93dSalc maxScaledPwr = pScaledUpDbm[pcdacStruct.numPcdacValues - 1];
14351e10b93dSalc
14361e10b93dSalc /* find minimum and make monotonic */
14371e10b93dSalc for (j = 0; j < pcdacStruct.numPcdacValues; j++) {
14381e10b93dSalc if (minScaledPwr >= pScaledUpDbm[j]) {
14391e10b93dSalc minScaledPwr = pScaledUpDbm[j];
14401e10b93dSalc pcdacMin = j;
14411e10b93dSalc }
14421e10b93dSalc /*
14431e10b93dSalc * Make the full_hsh monotonically increasing otherwise
14441e10b93dSalc * interpolation algorithm will get fooled gotta start
14451e10b93dSalc * working from the top, hence i = 63 - j.
14461e10b93dSalc */
14471e10b93dSalc i = (uint16_t)(pcdacStruct.numPcdacValues - 1 - j);
14481e10b93dSalc if (i == 0)
14491e10b93dSalc break;
14501e10b93dSalc if (pScaledUpDbm[i-1] > pScaledUpDbm[i]) {
14511e10b93dSalc /*
14521e10b93dSalc * It could be a glitch, so make the power for
14531e10b93dSalc * this pcdac the same as the power from the
14541e10b93dSalc * next highest pcdac.
14551e10b93dSalc */
14561e10b93dSalc pScaledUpDbm[i - 1] = pScaledUpDbm[i];
14571e10b93dSalc }
14581e10b93dSalc }
14591e10b93dSalc
14601e10b93dSalc for (j = 0; j < pcdacStruct.numPcdacValues; j++)
14611e10b93dSalc if (maxScaledPwr < pScaledUpDbm[j]) {
14621e10b93dSalc maxScaledPwr = pScaledUpDbm[j];
14631e10b93dSalc pcdacMax = j;
14641e10b93dSalc }
14651e10b93dSalc
14661e10b93dSalc /* Find the first power level with a pcdac */
14671e10b93dSalc pwr = (uint16_t)(PWR_STEP * ((minScaledPwr - PWR_MIN + PWR_STEP / 2) / PWR_STEP) + PWR_MIN);
14681e10b93dSalc
14691e10b93dSalc /* Write all the first pcdac entries based off the pcdacMin */
14701e10b93dSalc pcdacTableIndex = 0;
14711e10b93dSalc for (i = 0; i < (2 * (pwr - PWR_MIN) / EEP_SCALE + 1); i++)
14721e10b93dSalc pcdacTable[pcdacTableIndex++] = pcdacMin;
14731e10b93dSalc
14741e10b93dSalc i = 0;
14751e10b93dSalc while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1]) {
14761e10b93dSalc pwr += PWR_STEP;
14771e10b93dSalc /* stop if dbM > max_power_possible */
14781e10b93dSalc while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
14791e10b93dSalc (pwr - pScaledUpDbm[i])*(pwr - pScaledUpDbm[i+1]) > 0)
14801e10b93dSalc i++;
14811e10b93dSalc /* scale by 2 and add 1 to enable round up or down as needed */
14821e10b93dSalc scaledPcdac = (uint16_t)(ar5211GetInterpolatedValue(pwr,
14831e10b93dSalc pScaledUpDbm[i], pScaledUpDbm[i+1],
14841e10b93dSalc (uint16_t)(pPcdacValues[i] * 2),
14851e10b93dSalc (uint16_t)(pPcdacValues[i+1] * 2), 0) + 1);
14861e10b93dSalc
14871e10b93dSalc pcdacTable[pcdacTableIndex] = scaledPcdac / 2;
14881e10b93dSalc if (pcdacTable[pcdacTableIndex] > pcdacMax)
14891e10b93dSalc pcdacTable[pcdacTableIndex] = pcdacMax;
14901e10b93dSalc pcdacTableIndex++;
14911e10b93dSalc }
14921e10b93dSalc
14931e10b93dSalc /* Write all the last pcdac entries based off the last valid pcdac */
14941e10b93dSalc while (pcdacTableIndex < PWR_TABLE_SIZE) {
14951e10b93dSalc pcdacTable[pcdacTableIndex] = pcdacTable[pcdacTableIndex - 1];
14961e10b93dSalc pcdacTableIndex++;
14971e10b93dSalc }
14981e10b93dSalc
14991e10b93dSalc /* Finally, write the power values into the baseband power table */
15001e10b93dSalc addr = AR_PHY_BASE + (608 << 2);
15011e10b93dSalc for (i = 0; i < 32; i++) {
15021e10b93dSalc temp32 = 0xffff & ((pcdacTable[2 * i + 1] << 8) | 0xff);
15031e10b93dSalc temp32 = (temp32 << 16) | (0xffff & ((pcdacTable[2 * i] << 8) | 0xff));
15041e10b93dSalc OS_REG_WRITE(ah, addr, temp32);
15051e10b93dSalc addr += 4;
15061e10b93dSalc }
15071e10b93dSalc
15081e10b93dSalc }
15091e10b93dSalc
15101e10b93dSalc /*
15111e10b93dSalc * Set the transmit power in the baseband for the given
15121e10b93dSalc * operating channel and mode.
15131e10b93dSalc */
15141e10b93dSalc void
ar5211SetRateTable(struct ath_hal * ah,RD_EDGES_POWER * pRdEdgesPower,TRGT_POWER_INFO * pPowerInfo,uint16_t numChannels,HAL_CHANNEL * chan)15151e10b93dSalc ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
15161e10b93dSalc TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels,
15171e10b93dSalc HAL_CHANNEL *chan)
15181e10b93dSalc {
15191e10b93dSalc HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
15201e10b93dSalc struct ath_hal_5211 *ahp = AH5211(ah);
15211e10b93dSalc static uint16_t ratesArray[NUM_RATES];
15221e10b93dSalc static const uint16_t tpcScaleReductionTable[5] =
15231e10b93dSalc { 0, 3, 6, 9, MAX_RATE_POWER };
15241e10b93dSalc
15251e10b93dSalc uint16_t *pRatesPower;
15267c9a97abSmrg uint16_t lowerChannel = 0, lowerIndex=0, lowerPower=0;
15277c9a97abSmrg uint16_t upperChannel = 0, upperIndex=0, upperPower=0;
15281e10b93dSalc uint16_t twiceMaxEdgePower=63;
15291e10b93dSalc uint16_t twicePower = 0;
15301e10b93dSalc uint16_t i, numEdges;
15311e10b93dSalc uint16_t tempChannelList[NUM_EDGES]; /* temp array for holding edge channels */
15321e10b93dSalc uint16_t twiceMaxRDPower;
15331e10b93dSalc int16_t scaledPower = 0; /* for gcc -O2 */
15341e10b93dSalc uint16_t mask = 0x3f;
15351e10b93dSalc HAL_BOOL paPreDEnable = 0;
15361e10b93dSalc int8_t twiceAntennaGain, twiceAntennaReduction = 0;
15371e10b93dSalc
15381e10b93dSalc pRatesPower = ratesArray;
15391e10b93dSalc twiceMaxRDPower = chan->maxRegTxPower * 2;
15401e10b93dSalc
15411e10b93dSalc if (IS_CHAN_5GHZ(chan)) {
15421e10b93dSalc twiceAntennaGain = ee->ee_antennaGainMax[0];
15431e10b93dSalc } else {
15441e10b93dSalc twiceAntennaGain = ee->ee_antennaGainMax[1];
15451e10b93dSalc }
15461e10b93dSalc
15471e10b93dSalc twiceAntennaReduction = ath_hal_getantennareduction(ah, chan, twiceAntennaGain);
15481e10b93dSalc
15491e10b93dSalc if (pRdEdgesPower) {
15501e10b93dSalc /* Get the edge power */
15511e10b93dSalc for (i = 0; i < NUM_EDGES; i++) {
15521e10b93dSalc if (pRdEdgesPower[i].rdEdge == 0)
15531e10b93dSalc break;
15541e10b93dSalc tempChannelList[i] = pRdEdgesPower[i].rdEdge;
15551e10b93dSalc }
15561e10b93dSalc numEdges = i;
15571e10b93dSalc
15581e10b93dSalc ar5211GetLowerUpperValues(chan->channel, tempChannelList,
15591e10b93dSalc numEdges, &lowerChannel, &upperChannel);
15601e10b93dSalc /* Get the index for this channel */
15611e10b93dSalc for (i = 0; i < numEdges; i++)
15621e10b93dSalc if (lowerChannel == tempChannelList[i])
15631e10b93dSalc break;
15641e10b93dSalc HALASSERT(i != numEdges);
15651e10b93dSalc
15661e10b93dSalc if ((lowerChannel == upperChannel &&
15671e10b93dSalc lowerChannel == chan->channel) ||
15681e10b93dSalc pRdEdgesPower[i].flag) {
15691e10b93dSalc twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower;
15701e10b93dSalc HALASSERT(twiceMaxEdgePower > 0);
15711e10b93dSalc }
15721e10b93dSalc }
15731e10b93dSalc
15741e10b93dSalc /* extrapolate the power values for the test Groups */
15751e10b93dSalc for (i = 0; i < numChannels; i++)
15761e10b93dSalc tempChannelList[i] = pPowerInfo[i].testChannel;
15771e10b93dSalc
15781e10b93dSalc ar5211GetLowerUpperValues(chan->channel, tempChannelList,
15791e10b93dSalc numChannels, &lowerChannel, &upperChannel);
15801e10b93dSalc
15811e10b93dSalc /* get the index for the channel */
15821e10b93dSalc for (i = 0; i < numChannels; i++) {
15831e10b93dSalc if (lowerChannel == tempChannelList[i])
15841e10b93dSalc lowerIndex = i;
15851e10b93dSalc if (upperChannel == tempChannelList[i]) {
15861e10b93dSalc upperIndex = i;
15871e10b93dSalc break;
15881e10b93dSalc }
15891e10b93dSalc }
15901e10b93dSalc
15911e10b93dSalc for (i = 0; i < NUM_RATES; i++) {
15921e10b93dSalc if (IS_CHAN_OFDM(chan)) {
15931e10b93dSalc /* power for rates 6,9,12,18,24 is all the same */
15941e10b93dSalc if (i < 5) {
15951e10b93dSalc lowerPower = pPowerInfo[lowerIndex].twicePwr6_24;
15961e10b93dSalc upperPower = pPowerInfo[upperIndex].twicePwr6_24;
15971e10b93dSalc } else if (i == 5) {
15981e10b93dSalc lowerPower = pPowerInfo[lowerIndex].twicePwr36;
15991e10b93dSalc upperPower = pPowerInfo[upperIndex].twicePwr36;
16001e10b93dSalc } else if (i == 6) {
16011e10b93dSalc lowerPower = pPowerInfo[lowerIndex].twicePwr48;
16021e10b93dSalc upperPower = pPowerInfo[upperIndex].twicePwr48;
16031e10b93dSalc } else if (i == 7) {
16041e10b93dSalc lowerPower = pPowerInfo[lowerIndex].twicePwr54;
16051e10b93dSalc upperPower = pPowerInfo[upperIndex].twicePwr54;
16061e10b93dSalc }
16071e10b93dSalc } else {
16081e10b93dSalc switch (i) {
16091e10b93dSalc case 0:
16101e10b93dSalc case 1:
16111e10b93dSalc lowerPower = pPowerInfo[lowerIndex].twicePwr6_24;
16121e10b93dSalc upperPower = pPowerInfo[upperIndex].twicePwr6_24;
16131e10b93dSalc break;
16141e10b93dSalc case 2:
16151e10b93dSalc case 3:
16161e10b93dSalc lowerPower = pPowerInfo[lowerIndex].twicePwr36;
16171e10b93dSalc upperPower = pPowerInfo[upperIndex].twicePwr36;
16181e10b93dSalc break;
16191e10b93dSalc case 4:
16201e10b93dSalc case 5:
16211e10b93dSalc lowerPower = pPowerInfo[lowerIndex].twicePwr48;
16221e10b93dSalc upperPower = pPowerInfo[upperIndex].twicePwr48;
16231e10b93dSalc break;
16241e10b93dSalc case 6:
16251e10b93dSalc case 7:
16261e10b93dSalc lowerPower = pPowerInfo[lowerIndex].twicePwr54;
16271e10b93dSalc upperPower = pPowerInfo[upperIndex].twicePwr54;
16281e10b93dSalc break;
16291e10b93dSalc }
16301e10b93dSalc }
16311e10b93dSalc
16321e10b93dSalc twicePower = ar5211GetInterpolatedValue(chan->channel,
16331e10b93dSalc lowerChannel, upperChannel, lowerPower, upperPower, 0);
16341e10b93dSalc
16351e10b93dSalc /* Reduce power by band edge restrictions */
16361e10b93dSalc twicePower = AH_MIN(twicePower, twiceMaxEdgePower);
16371e10b93dSalc
16381e10b93dSalc /*
16391e10b93dSalc * If turbo is set, reduce power to keep power
16401e10b93dSalc * consumption under 2 Watts. Note that we always do
16411e10b93dSalc * this unless specially configured. Then we limit
16421e10b93dSalc * power only for non-AP operation.
16431e10b93dSalc */
16441e10b93dSalc if (IS_CHAN_TURBO(chan) &&
16451e10b93dSalc AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1
16461e10b93dSalc #ifdef AH_ENABLE_AP_SUPPORT
16471e10b93dSalc && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP
16481e10b93dSalc #endif
16491e10b93dSalc ) {
16501e10b93dSalc twicePower = AH_MIN(twicePower, ee->ee_turbo2WMaxPower5);
16511e10b93dSalc }
16521e10b93dSalc
16531e10b93dSalc /* Reduce power by max regulatory domain allowed restrictions */
16541e10b93dSalc pRatesPower[i] = AH_MIN(twicePower, twiceMaxRDPower - twiceAntennaReduction);
16551e10b93dSalc
16561e10b93dSalc /* Use 6 Mb power level for transmit power scaling reduction */
16571e10b93dSalc /* We don't want to reduce higher rates if its not needed */
16581e10b93dSalc if (i == 0) {
16591e10b93dSalc scaledPower = pRatesPower[0] -
16601e10b93dSalc (tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2);
16611e10b93dSalc if (scaledPower < 1)
16621e10b93dSalc scaledPower = 1;
16631e10b93dSalc }
16641e10b93dSalc
16651e10b93dSalc pRatesPower[i] = AH_MIN(pRatesPower[i], scaledPower);
16661e10b93dSalc }
16671e10b93dSalc
16681e10b93dSalc /* Record txPower at Rate 6 for info gathering */
16691e10b93dSalc ahp->ah_tx6PowerInHalfDbm = pRatesPower[0];
16701e10b93dSalc
16711e10b93dSalc #ifdef AH_DEBUG
16721e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RESET,
16731e10b93dSalc "%s: final output power setting %d MHz:\n",
16741e10b93dSalc __func__, chan->channel);
16751e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RESET,
16761e10b93dSalc "6 Mb %d dBm, MaxRD: %d dBm, MaxEdge %d dBm\n",
16771e10b93dSalc scaledPower / 2, twiceMaxRDPower / 2, twiceMaxEdgePower / 2);
16781e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RESET, "TPC Scale %d dBm - Ant Red %d dBm\n",
16791e10b93dSalc tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2,
16801e10b93dSalc twiceAntennaReduction / 2);
16811e10b93dSalc if (IS_CHAN_TURBO(chan) &&
16821e10b93dSalc AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1)
16831e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RESET, "Max Turbo %d dBm\n",
16841e10b93dSalc ee->ee_turbo2WMaxPower5);
16851e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RESET,
16861e10b93dSalc " %2d | %2d | %2d | %2d | %2d | %2d | %2d | %2d dBm\n",
16871e10b93dSalc pRatesPower[0] / 2, pRatesPower[1] / 2, pRatesPower[2] / 2,
16881e10b93dSalc pRatesPower[3] / 2, pRatesPower[4] / 2, pRatesPower[5] / 2,
16891e10b93dSalc pRatesPower[6] / 2, pRatesPower[7] / 2);
16901e10b93dSalc #endif /* AH_DEBUG */
16911e10b93dSalc
16921e10b93dSalc /* Write the power table into the hardware */
16931e10b93dSalc OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
16941e10b93dSalc ((paPreDEnable & 1)<< 30) | ((pRatesPower[3] & mask) << 24) |
16951e10b93dSalc ((paPreDEnable & 1)<< 22) | ((pRatesPower[2] & mask) << 16) |
16961e10b93dSalc ((paPreDEnable & 1)<< 14) | ((pRatesPower[1] & mask) << 8) |
16971e10b93dSalc ((paPreDEnable & 1)<< 6 ) | (pRatesPower[0] & mask));
16981e10b93dSalc OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
16991e10b93dSalc ((paPreDEnable & 1)<< 30) | ((pRatesPower[7] & mask) << 24) |
17001e10b93dSalc ((paPreDEnable & 1)<< 22) | ((pRatesPower[6] & mask) << 16) |
17011e10b93dSalc ((paPreDEnable & 1)<< 14) | ((pRatesPower[5] & mask) << 8) |
17021e10b93dSalc ((paPreDEnable & 1)<< 6 ) | (pRatesPower[4] & mask));
17031e10b93dSalc
17041e10b93dSalc /* set max power to the power value at rate 6 */
17051e10b93dSalc ar5211SetTxPowerLimit(ah, pRatesPower[0]);
17061e10b93dSalc
17071e10b93dSalc AH_PRIVATE(ah)->ah_maxPowerLevel = pRatesPower[0];
17081e10b93dSalc }
17091e10b93dSalc
17101e10b93dSalc /*
17111e10b93dSalc * Get or interpolate the pcdac value from the calibrated data
17121e10b93dSalc */
17131e10b93dSalc uint16_t
ar5211GetScaledPower(uint16_t channel,uint16_t pcdacValue,const PCDACS_EEPROM * pSrcStruct)17141e10b93dSalc ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue, const PCDACS_EEPROM *pSrcStruct)
17151e10b93dSalc {
17161e10b93dSalc uint16_t powerValue;
17177c9a97abSmrg uint16_t lFreq = 0, rFreq = 0; /* left and right frequency values */
17187c9a97abSmrg uint16_t llPcdac = 0, ulPcdac = 0; /* lower and upper left pcdac values */
17197c9a97abSmrg uint16_t lrPcdac = 0, urPcdac = 0; /* lower and upper right pcdac values */
17207c9a97abSmrg uint16_t lPwr = 0, uPwr = 0; /* lower and upper temp pwr values */
17211e10b93dSalc uint16_t lScaledPwr, rScaledPwr; /* left and right scaled power */
17221e10b93dSalc
17231e10b93dSalc if (ar5211FindValueInList(channel, pcdacValue, pSrcStruct, &powerValue))
17241e10b93dSalc /* value was copied from srcStruct */
17251e10b93dSalc return powerValue;
17261e10b93dSalc
17271e10b93dSalc ar5211GetLowerUpperValues(channel, pSrcStruct->pChannelList,
17281e10b93dSalc pSrcStruct->numChannels, &lFreq, &rFreq);
17291e10b93dSalc ar5211GetLowerUpperPcdacs(pcdacValue, lFreq, pSrcStruct,
17301e10b93dSalc &llPcdac, &ulPcdac);
17311e10b93dSalc ar5211GetLowerUpperPcdacs(pcdacValue, rFreq, pSrcStruct,
17321e10b93dSalc &lrPcdac, &urPcdac);
17331e10b93dSalc
17341e10b93dSalc /* get the power index for the pcdac value */
17351e10b93dSalc ar5211FindValueInList(lFreq, llPcdac, pSrcStruct, &lPwr);
17361e10b93dSalc ar5211FindValueInList(lFreq, ulPcdac, pSrcStruct, &uPwr);
17371e10b93dSalc lScaledPwr = ar5211GetInterpolatedValue(pcdacValue,
17381e10b93dSalc llPcdac, ulPcdac, lPwr, uPwr, 0);
17391e10b93dSalc
17401e10b93dSalc ar5211FindValueInList(rFreq, lrPcdac, pSrcStruct, &lPwr);
17411e10b93dSalc ar5211FindValueInList(rFreq, urPcdac, pSrcStruct, &uPwr);
17421e10b93dSalc rScaledPwr = ar5211GetInterpolatedValue(pcdacValue,
17431e10b93dSalc lrPcdac, urPcdac, lPwr, uPwr, 0);
17441e10b93dSalc
17451e10b93dSalc return ar5211GetInterpolatedValue(channel, lFreq, rFreq,
17461e10b93dSalc lScaledPwr, rScaledPwr, 0);
17471e10b93dSalc }
17481e10b93dSalc
17491e10b93dSalc /*
17501e10b93dSalc * Find the value from the calibrated source data struct
17511e10b93dSalc */
17521e10b93dSalc HAL_BOOL
ar5211FindValueInList(uint16_t channel,uint16_t pcdacValue,const PCDACS_EEPROM * pSrcStruct,uint16_t * powerValue)17531e10b93dSalc ar5211FindValueInList(uint16_t channel, uint16_t pcdacValue,
17541e10b93dSalc const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue)
17551e10b93dSalc {
17561e10b93dSalc const DATA_PER_CHANNEL *pChannelData;
17571e10b93dSalc const uint16_t *pPcdac;
17581e10b93dSalc uint16_t i, j;
17591e10b93dSalc
17601e10b93dSalc pChannelData = pSrcStruct->pDataPerChannel;
17611e10b93dSalc for (i = 0; i < pSrcStruct->numChannels; i++ ) {
17621e10b93dSalc if (pChannelData->channelValue == channel) {
17631e10b93dSalc pPcdac = pChannelData->PcdacValues;
17641e10b93dSalc for (j = 0; j < pChannelData->numPcdacValues; j++ ) {
17651e10b93dSalc if (*pPcdac == pcdacValue) {
17661e10b93dSalc *powerValue = pChannelData->PwrValues[j];
17671e10b93dSalc return AH_TRUE;
17681e10b93dSalc }
17691e10b93dSalc pPcdac++;
17701e10b93dSalc }
17711e10b93dSalc }
17721e10b93dSalc pChannelData++;
17731e10b93dSalc }
17741e10b93dSalc return AH_FALSE;
17751e10b93dSalc }
17761e10b93dSalc
17771e10b93dSalc /*
17781e10b93dSalc * Returns interpolated or the scaled up interpolated value
17791e10b93dSalc */
17801e10b93dSalc uint16_t
ar5211GetInterpolatedValue(uint16_t target,uint16_t srcLeft,uint16_t srcRight,uint16_t targetLeft,uint16_t targetRight,HAL_BOOL scaleUp)17811e10b93dSalc ar5211GetInterpolatedValue(uint16_t target,
17821e10b93dSalc uint16_t srcLeft, uint16_t srcRight,
17831e10b93dSalc uint16_t targetLeft, uint16_t targetRight,
17841e10b93dSalc HAL_BOOL scaleUp)
17851e10b93dSalc {
17861e10b93dSalc uint16_t rv;
17871e10b93dSalc int16_t lRatio;
17881e10b93dSalc uint16_t scaleValue = EEP_SCALE;
17891e10b93dSalc
17901e10b93dSalc /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */
17911e10b93dSalc if ((targetLeft * targetRight) == 0)
17921e10b93dSalc return 0;
17931e10b93dSalc if (scaleUp)
17941e10b93dSalc scaleValue = 1;
17951e10b93dSalc
17961e10b93dSalc if (srcRight != srcLeft) {
17971e10b93dSalc /*
17981e10b93dSalc * Note the ratio always need to be scaled,
17991e10b93dSalc * since it will be a fraction.
18001e10b93dSalc */
18011e10b93dSalc lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft);
18021e10b93dSalc if (lRatio < 0) {
18031e10b93dSalc /* Return as Left target if value would be negative */
18041e10b93dSalc rv = targetLeft * (scaleUp ? EEP_SCALE : 1);
18051e10b93dSalc } else if (lRatio > EEP_SCALE) {
18061e10b93dSalc /* Return as Right target if Ratio is greater than 100% (SCALE) */
18071e10b93dSalc rv = targetRight * (scaleUp ? EEP_SCALE : 1);
18081e10b93dSalc } else {
18091e10b93dSalc rv = (lRatio * targetRight + (EEP_SCALE - lRatio) *
18101e10b93dSalc targetLeft) / scaleValue;
18111e10b93dSalc }
18121e10b93dSalc } else {
18131e10b93dSalc rv = targetLeft;
18141e10b93dSalc if (scaleUp)
18151e10b93dSalc rv *= EEP_SCALE;
18161e10b93dSalc }
18171e10b93dSalc return rv;
18181e10b93dSalc }
18191e10b93dSalc
18201e10b93dSalc /*
18211e10b93dSalc * Look for value being within 0.1 of the search values
18221e10b93dSalc * however, NDIS can't do float calculations, so multiply everything
18231e10b93dSalc * up by EEP_SCALE so can do integer arithmatic
18241e10b93dSalc *
18251e10b93dSalc * INPUT value -value to search for
18261e10b93dSalc * INPUT pList -ptr to the list to search
18271e10b93dSalc * INPUT listSize -number of entries in list
18281e10b93dSalc * OUTPUT pLowerValue -return the lower value
18291e10b93dSalc * OUTPUT pUpperValue -return the upper value
18301e10b93dSalc */
18311e10b93dSalc void
ar5211GetLowerUpperValues(uint16_t value,const uint16_t * pList,uint16_t listSize,uint16_t * pLowerValue,uint16_t * pUpperValue)18321e10b93dSalc ar5211GetLowerUpperValues(uint16_t value,
18331e10b93dSalc const uint16_t *pList, uint16_t listSize,
18341e10b93dSalc uint16_t *pLowerValue, uint16_t *pUpperValue)
18351e10b93dSalc {
18361e10b93dSalc const uint16_t listEndValue = *(pList + listSize - 1);
18371e10b93dSalc uint32_t target = value * EEP_SCALE;
18381e10b93dSalc int i;
18391e10b93dSalc
18401e10b93dSalc /*
18411e10b93dSalc * See if value is lower than the first value in the list
18421e10b93dSalc * if so return first value
18431e10b93dSalc */
18441e10b93dSalc if (target < (uint32_t)(*pList * EEP_SCALE - EEP_DELTA)) {
18451e10b93dSalc *pLowerValue = *pList;
18461e10b93dSalc *pUpperValue = *pList;
18471e10b93dSalc return;
18481e10b93dSalc }
18491e10b93dSalc
18501e10b93dSalc /*
18511e10b93dSalc * See if value is greater than last value in list
18521e10b93dSalc * if so return last value
18531e10b93dSalc */
18541e10b93dSalc if (target > (uint32_t)(listEndValue * EEP_SCALE + EEP_DELTA)) {
18551e10b93dSalc *pLowerValue = listEndValue;
18561e10b93dSalc *pUpperValue = listEndValue;
18571e10b93dSalc return;
18581e10b93dSalc }
18591e10b93dSalc
18601e10b93dSalc /* look for value being near or between 2 values in list */
18611e10b93dSalc for (i = 0; i < listSize; i++) {
18621e10b93dSalc /*
18631e10b93dSalc * If value is close to the current value of the list
18641e10b93dSalc * then target is not between values, it is one of the values
18651e10b93dSalc */
18661e10b93dSalc if (abs(pList[i] * EEP_SCALE - (int32_t) target) < EEP_DELTA) {
18671e10b93dSalc *pLowerValue = pList[i];
18681e10b93dSalc *pUpperValue = pList[i];
18691e10b93dSalc return;
18701e10b93dSalc }
18711e10b93dSalc
18721e10b93dSalc /*
18731e10b93dSalc * Look for value being between current value and next value
18741e10b93dSalc * if so return these 2 values
18751e10b93dSalc */
18761e10b93dSalc if (target < (uint32_t)(pList[i + 1] * EEP_SCALE - EEP_DELTA)) {
18771e10b93dSalc *pLowerValue = pList[i];
18781e10b93dSalc *pUpperValue = pList[i + 1];
18791e10b93dSalc return;
18801e10b93dSalc }
18811e10b93dSalc }
18821e10b93dSalc }
18831e10b93dSalc
18841e10b93dSalc /*
18851e10b93dSalc * Get the upper and lower pcdac given the channel and the pcdac
18861e10b93dSalc * used in the search
18871e10b93dSalc */
18881e10b93dSalc void
ar5211GetLowerUpperPcdacs(uint16_t pcdac,uint16_t channel,const PCDACS_EEPROM * pSrcStruct,uint16_t * pLowerPcdac,uint16_t * pUpperPcdac)18891e10b93dSalc ar5211GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel,
18901e10b93dSalc const PCDACS_EEPROM *pSrcStruct,
18911e10b93dSalc uint16_t *pLowerPcdac, uint16_t *pUpperPcdac)
18921e10b93dSalc {
18931e10b93dSalc const DATA_PER_CHANNEL *pChannelData;
18941e10b93dSalc int i;
18951e10b93dSalc
18961e10b93dSalc /* Find the channel information */
18971e10b93dSalc pChannelData = pSrcStruct->pDataPerChannel;
18981e10b93dSalc for (i = 0; i < pSrcStruct->numChannels; i++) {
18991e10b93dSalc if (pChannelData->channelValue == channel)
19001e10b93dSalc break;
19011e10b93dSalc pChannelData++;
19021e10b93dSalc }
19031e10b93dSalc ar5211GetLowerUpperValues(pcdac, pChannelData->PcdacValues,
19041e10b93dSalc pChannelData->numPcdacValues, pLowerPcdac, pUpperPcdac);
19051e10b93dSalc }
19061e10b93dSalc
19071e10b93dSalc #define DYN_ADJ_UP_MARGIN 15
19081e10b93dSalc #define DYN_ADJ_LO_MARGIN 20
19091e10b93dSalc
19101e10b93dSalc static const GAIN_OPTIMIZATION_LADDER gainLadder = {
19111e10b93dSalc 9, /* numStepsInLadder */
19121e10b93dSalc 4, /* defaultStepNum */
19131e10b93dSalc { { {4, 1, 1, 1}, 6, "FG8"},
19141e10b93dSalc { {4, 0, 1, 1}, 4, "FG7"},
19151e10b93dSalc { {3, 1, 1, 1}, 3, "FG6"},
19161e10b93dSalc { {4, 0, 0, 1}, 1, "FG5"},
19171e10b93dSalc { {4, 1, 1, 0}, 0, "FG4"}, /* noJack */
19181e10b93dSalc { {4, 0, 1, 0}, -2, "FG3"}, /* halfJack */
19191e10b93dSalc { {3, 1, 1, 0}, -3, "FG2"}, /* clip3 */
19201e10b93dSalc { {4, 0, 0, 0}, -4, "FG1"}, /* noJack */
19211e10b93dSalc { {2, 1, 1, 0}, -6, "FG0"} /* clip2 */
19221e10b93dSalc }
19231e10b93dSalc };
19241e10b93dSalc
19251e10b93dSalc /*
19261e10b93dSalc * Initialize the gain structure to good values
19271e10b93dSalc */
19281e10b93dSalc void
ar5211InitializeGainValues(struct ath_hal * ah)19291e10b93dSalc ar5211InitializeGainValues(struct ath_hal *ah)
19301e10b93dSalc {
19311e10b93dSalc struct ath_hal_5211 *ahp = AH5211(ah);
19321e10b93dSalc GAIN_VALUES *gv = &ahp->ah_gainValues;
19331e10b93dSalc
19341e10b93dSalc /* initialize gain optimization values */
19351e10b93dSalc gv->currStepNum = gainLadder.defaultStepNum;
19361e10b93dSalc gv->currStep = &gainLadder.optStep[gainLadder.defaultStepNum];
19371e10b93dSalc gv->active = AH_TRUE;
19381e10b93dSalc gv->loTrig = 20;
19391e10b93dSalc gv->hiTrig = 35;
19401e10b93dSalc }
19411e10b93dSalc
19421e10b93dSalc static HAL_BOOL
ar5211InvalidGainReadback(struct ath_hal * ah,GAIN_VALUES * gv)19431e10b93dSalc ar5211InvalidGainReadback(struct ath_hal *ah, GAIN_VALUES *gv)
19441e10b93dSalc {
19451e10b93dSalc HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
19461e10b93dSalc uint32_t gStep, g;
19471e10b93dSalc uint32_t L1, L2, L3, L4;
19481e10b93dSalc
19491e10b93dSalc if (IS_CHAN_CCK(chan)) {
19501e10b93dSalc gStep = 0x18;
19511e10b93dSalc L1 = 0;
19521e10b93dSalc L2 = gStep + 4;
19531e10b93dSalc L3 = 0x40;
19541e10b93dSalc L4 = L3 + 50;
19551e10b93dSalc
19561e10b93dSalc gv->loTrig = L1;
19571e10b93dSalc gv->hiTrig = L4+5;
19581e10b93dSalc } else {
19591e10b93dSalc gStep = 0x3f;
19601e10b93dSalc L1 = 0;
19611e10b93dSalc L2 = 50;
19621e10b93dSalc L3 = L1;
19631e10b93dSalc L4 = L3 + 50;
19641e10b93dSalc
19651e10b93dSalc gv->loTrig = L1 + DYN_ADJ_LO_MARGIN;
19661e10b93dSalc gv->hiTrig = L4 - DYN_ADJ_UP_MARGIN;
19671e10b93dSalc }
19681e10b93dSalc g = gv->currGain;
19691e10b93dSalc
19701e10b93dSalc return !((g >= L1 && g<= L2) || (g >= L3 && g <= L4));
19711e10b93dSalc }
19721e10b93dSalc
19731e10b93dSalc /*
19741e10b93dSalc * Enable the probe gain check on the next packet
19751e10b93dSalc */
19761e10b93dSalc static void
ar5211RequestRfgain(struct ath_hal * ah)19771e10b93dSalc ar5211RequestRfgain(struct ath_hal *ah)
19781e10b93dSalc {
19791e10b93dSalc struct ath_hal_5211 *ahp = AH5211(ah);
19801e10b93dSalc
19811e10b93dSalc /* Enable the gain readback probe */
19821e10b93dSalc OS_REG_WRITE(ah, AR_PHY_PAPD_PROBE,
19831e10b93dSalc SM(ahp->ah_tx6PowerInHalfDbm, AR_PHY_PAPD_PROBE_POWERTX)
19841e10b93dSalc | AR_PHY_PAPD_PROBE_NEXT_TX);
19851e10b93dSalc
19861e10b93dSalc ahp->ah_rfgainState = HAL_RFGAIN_READ_REQUESTED;
19871e10b93dSalc }
19881e10b93dSalc
19891e10b93dSalc /*
19901e10b93dSalc * Exported call to check for a recent gain reading and return
19911e10b93dSalc * the current state of the thermal calibration gain engine.
19921e10b93dSalc */
19931e10b93dSalc HAL_RFGAIN
ar5211GetRfgain(struct ath_hal * ah)19941e10b93dSalc ar5211GetRfgain(struct ath_hal *ah)
19951e10b93dSalc {
19961e10b93dSalc struct ath_hal_5211 *ahp = AH5211(ah);
19971e10b93dSalc GAIN_VALUES *gv = &ahp->ah_gainValues;
19981e10b93dSalc uint32_t rddata;
19991e10b93dSalc
20001e10b93dSalc if (!gv->active)
20011e10b93dSalc return HAL_RFGAIN_INACTIVE;
20021e10b93dSalc
20031e10b93dSalc if (ahp->ah_rfgainState == HAL_RFGAIN_READ_REQUESTED) {
20041e10b93dSalc /* Caller had asked to setup a new reading. Check it. */
20051e10b93dSalc rddata = OS_REG_READ(ah, AR_PHY_PAPD_PROBE);
20061e10b93dSalc
20071e10b93dSalc if ((rddata & AR_PHY_PAPD_PROBE_NEXT_TX) == 0) {
20081e10b93dSalc /* bit got cleared, we have a new reading. */
20091e10b93dSalc gv->currGain = rddata >> AR_PHY_PAPD_PROBE_GAINF_S;
20101e10b93dSalc /* inactive by default */
20111e10b93dSalc ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
20121e10b93dSalc
20131e10b93dSalc if (!ar5211InvalidGainReadback(ah, gv) &&
20141e10b93dSalc ar5211IsGainAdjustNeeded(ah, gv) &&
20151e10b93dSalc ar5211AdjustGain(ah, gv) > 0) {
20161e10b93dSalc /*
20171e10b93dSalc * Change needed. Copy ladder info
20181e10b93dSalc * into eeprom info.
20191e10b93dSalc */
20201e10b93dSalc ar5211SetRfgain(ah, gv);
20211e10b93dSalc ahp->ah_rfgainState = HAL_RFGAIN_NEED_CHANGE;
20221e10b93dSalc }
20231e10b93dSalc }
20241e10b93dSalc }
20251e10b93dSalc return ahp->ah_rfgainState;
20261e10b93dSalc }
20271e10b93dSalc
20281e10b93dSalc /*
20291e10b93dSalc * Check to see if our readback gain level sits within the linear
20301e10b93dSalc * region of our current variable attenuation window
20311e10b93dSalc */
20321e10b93dSalc static HAL_BOOL
ar5211IsGainAdjustNeeded(struct ath_hal * ah,const GAIN_VALUES * gv)20331e10b93dSalc ar5211IsGainAdjustNeeded(struct ath_hal *ah, const GAIN_VALUES *gv)
20341e10b93dSalc {
20351e10b93dSalc return (gv->currGain <= gv->loTrig || gv->currGain >= gv->hiTrig);
20361e10b93dSalc }
20371e10b93dSalc
20381e10b93dSalc /*
20391e10b93dSalc * Move the rabbit ears in the correct direction.
20401e10b93dSalc */
20411e10b93dSalc static int32_t
ar5211AdjustGain(struct ath_hal * ah,GAIN_VALUES * gv)20421e10b93dSalc ar5211AdjustGain(struct ath_hal *ah, GAIN_VALUES *gv)
20431e10b93dSalc {
20441e10b93dSalc /* return > 0 for valid adjustments. */
20451e10b93dSalc if (!gv->active)
20461e10b93dSalc return -1;
20471e10b93dSalc
20481e10b93dSalc gv->currStep = &gainLadder.optStep[gv->currStepNum];
20491e10b93dSalc if (gv->currGain >= gv->hiTrig) {
20501e10b93dSalc if (gv->currStepNum == 0) {
20511e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RFPARAM,
20521e10b93dSalc "%s: Max gain limit.\n", __func__);
20531e10b93dSalc return -1;
20541e10b93dSalc }
20551e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RFPARAM,
20561e10b93dSalc "%s: Adding gain: currG=%d [%s] --> ",
20571e10b93dSalc __func__, gv->currGain, gv->currStep->stepName);
20581e10b93dSalc gv->targetGain = gv->currGain;
20591e10b93dSalc while (gv->targetGain >= gv->hiTrig && gv->currStepNum > 0) {
20601e10b93dSalc gv->targetGain -= 2 * (gainLadder.optStep[--(gv->currStepNum)].stepGain -
20611e10b93dSalc gv->currStep->stepGain);
20621e10b93dSalc gv->currStep = &gainLadder.optStep[gv->currStepNum];
20631e10b93dSalc }
20641e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",
20651e10b93dSalc gv->targetGain, gv->currStep->stepName);
20661e10b93dSalc return 1;
20671e10b93dSalc }
20681e10b93dSalc if (gv->currGain <= gv->loTrig) {
20691e10b93dSalc if (gv->currStepNum == gainLadder.numStepsInLadder-1) {
20701e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RFPARAM,
20711e10b93dSalc "%s: Min gain limit.\n", __func__);
20721e10b93dSalc return -2;
20731e10b93dSalc }
20741e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RFPARAM,
20751e10b93dSalc "%s: Deducting gain: currG=%d [%s] --> ",
20761e10b93dSalc __func__, gv->currGain, gv->currStep->stepName);
20771e10b93dSalc gv->targetGain = gv->currGain;
20781e10b93dSalc while (gv->targetGain <= gv->loTrig &&
20791e10b93dSalc gv->currStepNum < (gainLadder.numStepsInLadder - 1)) {
20801e10b93dSalc gv->targetGain -= 2 *
20811e10b93dSalc (gainLadder.optStep[++(gv->currStepNum)].stepGain - gv->currStep->stepGain);
20821e10b93dSalc gv->currStep = &gainLadder.optStep[gv->currStepNum];
20831e10b93dSalc }
20841e10b93dSalc HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",
20851e10b93dSalc gv->targetGain, gv->currStep->stepName);
20861e10b93dSalc return 2;
20871e10b93dSalc }
20881e10b93dSalc return 0; /* caller didn't call needAdjGain first */
20891e10b93dSalc }
20901e10b93dSalc
20911e10b93dSalc /*
20921e10b93dSalc * Adjust the 5GHz EEPROM information with the desired calibration values.
20931e10b93dSalc */
20941e10b93dSalc static void
ar5211SetRfgain(struct ath_hal * ah,const GAIN_VALUES * gv)20951e10b93dSalc ar5211SetRfgain(struct ath_hal *ah, const GAIN_VALUES *gv)
20961e10b93dSalc {
20971e10b93dSalc HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
20981e10b93dSalc
20991e10b93dSalc if (!gv->active)
21001e10b93dSalc return;
21011e10b93dSalc ee->ee_cornerCal.clip = gv->currStep->paramVal[0]; /* bb_tx_clip */
21021e10b93dSalc ee->ee_cornerCal.pd90 = gv->currStep->paramVal[1]; /* rf_pwd_90 */
21031e10b93dSalc ee->ee_cornerCal.pd84 = gv->currStep->paramVal[2]; /* rf_pwd_84 */
21041e10b93dSalc ee->ee_cornerCal.gSel = gv->currStep->paramVal[3]; /* rf_rfgainsel */
21051e10b93dSalc }
21061e10b93dSalc
21071e10b93dSalc static void
ar5211SetOperatingMode(struct ath_hal * ah,int opmode)21081e10b93dSalc ar5211SetOperatingMode(struct ath_hal *ah, int opmode)
21091e10b93dSalc {
21101e10b93dSalc struct ath_hal_5211 *ahp = AH5211(ah);
21111e10b93dSalc uint32_t val;
21121e10b93dSalc
21131e10b93dSalc val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;
21141e10b93dSalc switch (opmode) {
21151e10b93dSalc case HAL_M_HOSTAP:
21161e10b93dSalc OS_REG_WRITE(ah, AR_STA_ID1, val
21171e10b93dSalc | AR_STA_ID1_STA_AP
21181e10b93dSalc | AR_STA_ID1_RTS_USE_DEF
21191e10b93dSalc | ahp->ah_staId1Defaults);
21201e10b93dSalc break;
21211e10b93dSalc case HAL_M_IBSS:
21221e10b93dSalc OS_REG_WRITE(ah, AR_STA_ID1, val
21231e10b93dSalc | AR_STA_ID1_ADHOC
21241e10b93dSalc | AR_STA_ID1_DESC_ANTENNA
21251e10b93dSalc | ahp->ah_staId1Defaults);
21261e10b93dSalc break;
21271e10b93dSalc case HAL_M_STA:
21281e10b93dSalc case HAL_M_MONITOR:
21291e10b93dSalc OS_REG_WRITE(ah, AR_STA_ID1, val
21301e10b93dSalc | AR_STA_ID1_DEFAULT_ANTENNA
21311e10b93dSalc | ahp->ah_staId1Defaults);
21321e10b93dSalc break;
21331e10b93dSalc }
21341e10b93dSalc }
21351e10b93dSalc
21361e10b93dSalc void
ar5211SetPCUConfig(struct ath_hal * ah)21371e10b93dSalc ar5211SetPCUConfig(struct ath_hal *ah)
21381e10b93dSalc {
21391e10b93dSalc ar5211SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
21401e10b93dSalc }
2141