11e10b93dSalc /*
21e10b93dSalc * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
31e10b93dSalc * Copyright (c) 2002-2008 Atheros Communications, Inc.
41e10b93dSalc *
51e10b93dSalc * Permission to use, copy, modify, and/or distribute this software for any
61e10b93dSalc * purpose with or without fee is hereby granted, provided that the above
71e10b93dSalc * copyright notice and this permission notice appear in all copies.
81e10b93dSalc *
91e10b93dSalc * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
101e10b93dSalc * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
111e10b93dSalc * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
121e10b93dSalc * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
131e10b93dSalc * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
141e10b93dSalc * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
151e10b93dSalc * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
161e10b93dSalc *
17*7c9a97abSmrg * $Id: ar5111.c,v 1.3 2009/01/06 06:03:57 mrg Exp $
181e10b93dSalc */
191e10b93dSalc #include "opt_ah.h"
201e10b93dSalc
211e10b93dSalc #include "ah.h"
221e10b93dSalc #include "ah_internal.h"
231e10b93dSalc
241e10b93dSalc #include "ah_eeprom_v3.h"
251e10b93dSalc
261e10b93dSalc #include "ar5212/ar5212.h"
271e10b93dSalc #include "ar5212/ar5212reg.h"
281e10b93dSalc #include "ar5212/ar5212phy.h"
291e10b93dSalc
301e10b93dSalc #define AH_5212_5111
311e10b93dSalc #include "ar5212/ar5212.ini"
321e10b93dSalc
331e10b93dSalc #define N(a) (sizeof(a)/sizeof(a[0]))
341e10b93dSalc
351e10b93dSalc struct ar5111State {
361e10b93dSalc RF_HAL_FUNCS base; /* public state, must be first */
371e10b93dSalc uint16_t pcdacTable[PWR_TABLE_SIZE];
381e10b93dSalc
391e10b93dSalc uint32_t Bank0Data[N(ar5212Bank0_5111)];
401e10b93dSalc uint32_t Bank1Data[N(ar5212Bank1_5111)];
411e10b93dSalc uint32_t Bank2Data[N(ar5212Bank2_5111)];
421e10b93dSalc uint32_t Bank3Data[N(ar5212Bank3_5111)];
431e10b93dSalc uint32_t Bank6Data[N(ar5212Bank6_5111)];
441e10b93dSalc uint32_t Bank7Data[N(ar5212Bank7_5111)];
451e10b93dSalc };
461e10b93dSalc #define AR5111(ah) ((struct ar5111State *) AH5212(ah)->ah_rfHal)
471e10b93dSalc
481e10b93dSalc static uint16_t ar5212GetScaledPower(uint16_t channel, uint16_t pcdacValue,
491e10b93dSalc const PCDACS_EEPROM *pSrcStruct);
501e10b93dSalc static HAL_BOOL ar5212FindValueInList(uint16_t channel, uint16_t pcdacValue,
511e10b93dSalc const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue);
521e10b93dSalc static void ar5212GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel,
531e10b93dSalc const PCDACS_EEPROM *pSrcStruct,
541e10b93dSalc uint16_t *pLowerPcdac, uint16_t *pUpperPcdac);
551e10b93dSalc
561e10b93dSalc extern void ar5212GetLowerUpperValues(uint16_t value,
571e10b93dSalc const uint16_t *pList, uint16_t listSize,
581e10b93dSalc uint16_t *pLowerValue, uint16_t *pUpperValue);
591e10b93dSalc extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
601e10b93dSalc uint32_t numBits, uint32_t firstBit, uint32_t column);
611e10b93dSalc
621e10b93dSalc static void
ar5111WriteRegs(struct ath_hal * ah,u_int modesIndex,u_int freqIndex,int writes)631e10b93dSalc ar5111WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
641e10b93dSalc int writes)
651e10b93dSalc {
661e10b93dSalc HAL_INI_WRITE_ARRAY(ah, ar5212Modes_5111, modesIndex, writes);
671e10b93dSalc HAL_INI_WRITE_ARRAY(ah, ar5212Common_5111, 1, writes);
681e10b93dSalc HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_5111, freqIndex, writes);
691e10b93dSalc }
701e10b93dSalc
711e10b93dSalc /*
721e10b93dSalc * Take the MHz channel value and set the Channel value
731e10b93dSalc *
741e10b93dSalc * ASSUMES: Writes enabled to analog bus
751e10b93dSalc */
761e10b93dSalc static HAL_BOOL
ar5111SetChannel(struct ath_hal * ah,HAL_CHANNEL_INTERNAL * chan)771e10b93dSalc ar5111SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
781e10b93dSalc {
791e10b93dSalc #define CI_2GHZ_INDEX_CORRECTION 19
801e10b93dSalc uint32_t refClk, reg32, data2111;
811e10b93dSalc int16_t chan5111, chanIEEE;
821e10b93dSalc
831e10b93dSalc /*
841e10b93dSalc * Structure to hold 11b tuning information for 5111/2111
851e10b93dSalc * 16 MHz mode, divider ratio = 198 = NP+S. N=16, S=4 or 6, P=12
861e10b93dSalc */
871e10b93dSalc typedef struct {
881e10b93dSalc uint32_t refClkSel; /* reference clock, 1 for 16 MHz */
891e10b93dSalc uint32_t channelSelect; /* P[7:4]S[3:0] bits */
901e10b93dSalc uint16_t channel5111; /* 11a channel for 5111 */
911e10b93dSalc } CHAN_INFO_2GHZ;
921e10b93dSalc
93a9d4fb0bSalc static const CHAN_INFO_2GHZ chan2GHzData[] = {
941e10b93dSalc { 1, 0x46, 96 }, /* 2312 -19 */
951e10b93dSalc { 1, 0x46, 97 }, /* 2317 -18 */
961e10b93dSalc { 1, 0x46, 98 }, /* 2322 -17 */
971e10b93dSalc { 1, 0x46, 99 }, /* 2327 -16 */
981e10b93dSalc { 1, 0x46, 100 }, /* 2332 -15 */
991e10b93dSalc { 1, 0x46, 101 }, /* 2337 -14 */
1001e10b93dSalc { 1, 0x46, 102 }, /* 2342 -13 */
1011e10b93dSalc { 1, 0x46, 103 }, /* 2347 -12 */
1021e10b93dSalc { 1, 0x46, 104 }, /* 2352 -11 */
1031e10b93dSalc { 1, 0x46, 105 }, /* 2357 -10 */
1041e10b93dSalc { 1, 0x46, 106 }, /* 2362 -9 */
1051e10b93dSalc { 1, 0x46, 107 }, /* 2367 -8 */
1061e10b93dSalc { 1, 0x46, 108 }, /* 2372 -7 */
1071e10b93dSalc /* index -6 to 0 are pad to make this a nolookup table */
1081e10b93dSalc { 1, 0x46, 116 }, /* -6 */
1091e10b93dSalc { 1, 0x46, 116 }, /* -5 */
1101e10b93dSalc { 1, 0x46, 116 }, /* -4 */
1111e10b93dSalc { 1, 0x46, 116 }, /* -3 */
1121e10b93dSalc { 1, 0x46, 116 }, /* -2 */
1131e10b93dSalc { 1, 0x46, 116 }, /* -1 */
1141e10b93dSalc { 1, 0x46, 116 }, /* 0 */
1151e10b93dSalc { 1, 0x46, 116 }, /* 2412 1 */
1161e10b93dSalc { 1, 0x46, 117 }, /* 2417 2 */
1171e10b93dSalc { 1, 0x46, 118 }, /* 2422 3 */
1181e10b93dSalc { 1, 0x46, 119 }, /* 2427 4 */
1191e10b93dSalc { 1, 0x46, 120 }, /* 2432 5 */
1201e10b93dSalc { 1, 0x46, 121 }, /* 2437 6 */
1211e10b93dSalc { 1, 0x46, 122 }, /* 2442 7 */
1221e10b93dSalc { 1, 0x46, 123 }, /* 2447 8 */
1231e10b93dSalc { 1, 0x46, 124 }, /* 2452 9 */
1241e10b93dSalc { 1, 0x46, 125 }, /* 2457 10 */
1251e10b93dSalc { 1, 0x46, 126 }, /* 2462 11 */
1261e10b93dSalc { 1, 0x46, 127 }, /* 2467 12 */
1271e10b93dSalc { 1, 0x46, 128 }, /* 2472 13 */
1281e10b93dSalc { 1, 0x44, 124 }, /* 2484 14 */
1291e10b93dSalc { 1, 0x46, 136 }, /* 2512 15 */
1301e10b93dSalc { 1, 0x46, 140 }, /* 2532 16 */
1311e10b93dSalc { 1, 0x46, 144 }, /* 2552 17 */
1321e10b93dSalc { 1, 0x46, 148 }, /* 2572 18 */
1331e10b93dSalc { 1, 0x46, 152 }, /* 2592 19 */
1341e10b93dSalc { 1, 0x46, 156 }, /* 2612 20 */
1351e10b93dSalc { 1, 0x46, 160 }, /* 2632 21 */
1361e10b93dSalc { 1, 0x46, 164 }, /* 2652 22 */
1371e10b93dSalc { 1, 0x46, 168 }, /* 2672 23 */
1381e10b93dSalc { 1, 0x46, 172 }, /* 2692 24 */
1391e10b93dSalc { 1, 0x46, 176 }, /* 2712 25 */
1401e10b93dSalc { 1, 0x46, 180 } /* 2732 26 */
1411e10b93dSalc };
1421e10b93dSalc
1431e10b93dSalc OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
1441e10b93dSalc
1451e10b93dSalc chanIEEE = ath_hal_mhz2ieee(ah, chan->channel, chan->channelFlags);
1461e10b93dSalc if (IS_CHAN_2GHZ(chan)) {
1471e10b93dSalc const CHAN_INFO_2GHZ* ci =
1481e10b93dSalc &chan2GHzData[chanIEEE + CI_2GHZ_INDEX_CORRECTION];
1491e10b93dSalc uint32_t txctl;
1501e10b93dSalc
1511e10b93dSalc data2111 = ((ath_hal_reverseBits(ci->channelSelect, 8) & 0xff)
1521e10b93dSalc << 5)
1531e10b93dSalc | (ci->refClkSel << 4);
1541e10b93dSalc chan5111 = ci->channel5111;
1551e10b93dSalc txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
1561e10b93dSalc if (chan->channel == 2484) {
1571e10b93dSalc /* Enable channel spreading for channel 14 */
1581e10b93dSalc OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1591e10b93dSalc txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
1601e10b93dSalc } else {
1611e10b93dSalc OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1621e10b93dSalc txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
1631e10b93dSalc }
1641e10b93dSalc } else {
1651e10b93dSalc chan5111 = chanIEEE; /* no conversion needed */
1661e10b93dSalc data2111 = 0;
1671e10b93dSalc }
1681e10b93dSalc
1691e10b93dSalc /* Rest of the code is common for 5 GHz and 2.4 GHz. */
1701e10b93dSalc if (chan5111 >= 145 || (chan5111 & 0x1)) {
1711e10b93dSalc reg32 = ath_hal_reverseBits(chan5111 - 24, 8) & 0xff;
1721e10b93dSalc refClk = 1;
1731e10b93dSalc } else {
1741e10b93dSalc reg32 = ath_hal_reverseBits(((chan5111 - 24)/2), 8) & 0xff;
1751e10b93dSalc refClk = 0;
1761e10b93dSalc }
1771e10b93dSalc
1781e10b93dSalc reg32 = (reg32 << 2) | (refClk << 1) | (1 << 10) | 0x1;
1791e10b93dSalc OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff));
1801e10b93dSalc reg32 >>= 8;
1811e10b93dSalc OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff));
1821e10b93dSalc
1831e10b93dSalc AH_PRIVATE(ah)->ah_curchan = chan;
1841e10b93dSalc return AH_TRUE;
1851e10b93dSalc #undef CI_2GHZ_INDEX_CORRECTION
1861e10b93dSalc }
1871e10b93dSalc
1881e10b93dSalc /*
1891e10b93dSalc * Return a reference to the requested RF Bank.
1901e10b93dSalc */
1911e10b93dSalc static uint32_t *
ar5111GetRfBank(struct ath_hal * ah,int bank)1921e10b93dSalc ar5111GetRfBank(struct ath_hal *ah, int bank)
1931e10b93dSalc {
1941e10b93dSalc struct ar5111State *priv = AR5111(ah);
1951e10b93dSalc
1961e10b93dSalc HALASSERT(priv != AH_NULL);
1971e10b93dSalc switch (bank) {
1981e10b93dSalc case 0: return priv->Bank0Data;
1991e10b93dSalc case 1: return priv->Bank1Data;
2001e10b93dSalc case 2: return priv->Bank2Data;
2011e10b93dSalc case 3: return priv->Bank3Data;
2021e10b93dSalc case 6: return priv->Bank6Data;
2031e10b93dSalc case 7: return priv->Bank7Data;
2041e10b93dSalc }
2051e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
2061e10b93dSalc __func__, bank);
2071e10b93dSalc return AH_NULL;
2081e10b93dSalc }
2091e10b93dSalc
2101e10b93dSalc /*
2111e10b93dSalc * Reads EEPROM header info from device structure and programs
2121e10b93dSalc * all rf registers
2131e10b93dSalc *
2141e10b93dSalc * REQUIRES: Access to the analog rf device
2151e10b93dSalc */
2161e10b93dSalc static HAL_BOOL
ar5111SetRfRegs(struct ath_hal * ah,HAL_CHANNEL_INTERNAL * chan,uint16_t modesIndex,uint16_t * rfXpdGain)2171e10b93dSalc ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
2181e10b93dSalc uint16_t modesIndex, uint16_t *rfXpdGain)
2191e10b93dSalc {
2201e10b93dSalc struct ath_hal_5212 *ahp = AH5212(ah);
2211e10b93dSalc const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
2221e10b93dSalc uint16_t rfXpdGainFixed, rfPloSel, rfPwdXpd, gainI;
2231e10b93dSalc uint16_t tempOB, tempDB;
2241e10b93dSalc uint32_t ob2GHz, db2GHz, rfReg[N(ar5212Bank6_5111)];
2251e10b93dSalc int i, regWrites = 0;
2261e10b93dSalc
2271e10b93dSalc /* Setup rf parameters */
2281e10b93dSalc switch (chan->channelFlags & CHANNEL_ALL) {
2291e10b93dSalc case CHANNEL_A:
2301e10b93dSalc case CHANNEL_T:
2311e10b93dSalc if (4000 < chan->channel && chan->channel < 5260) {
2321e10b93dSalc tempOB = ee->ee_ob1;
2331e10b93dSalc tempDB = ee->ee_db1;
2341e10b93dSalc } else if (5260 <= chan->channel && chan->channel < 5500) {
2351e10b93dSalc tempOB = ee->ee_ob2;
2361e10b93dSalc tempDB = ee->ee_db2;
2371e10b93dSalc } else if (5500 <= chan->channel && chan->channel < 5725) {
2381e10b93dSalc tempOB = ee->ee_ob3;
2391e10b93dSalc tempDB = ee->ee_db3;
2401e10b93dSalc } else if (chan->channel >= 5725) {
2411e10b93dSalc tempOB = ee->ee_ob4;
2421e10b93dSalc tempDB = ee->ee_db4;
2431e10b93dSalc } else {
2441e10b93dSalc /* XXX when does this happen??? */
2451e10b93dSalc tempOB = tempDB = 0;
2461e10b93dSalc }
2471e10b93dSalc ob2GHz = db2GHz = 0;
2481e10b93dSalc
2491e10b93dSalc rfXpdGainFixed = ee->ee_xgain[headerInfo11A];
2501e10b93dSalc rfPloSel = ee->ee_xpd[headerInfo11A];
2511e10b93dSalc rfPwdXpd = !ee->ee_xpd[headerInfo11A];
2521e10b93dSalc gainI = ee->ee_gainI[headerInfo11A];
2531e10b93dSalc break;
2541e10b93dSalc case CHANNEL_B:
2551e10b93dSalc tempOB = ee->ee_obFor24;
2561e10b93dSalc tempDB = ee->ee_dbFor24;
2571e10b93dSalc ob2GHz = ee->ee_ob2GHz[0];
2581e10b93dSalc db2GHz = ee->ee_db2GHz[0];
2591e10b93dSalc
2601e10b93dSalc rfXpdGainFixed = ee->ee_xgain[headerInfo11B];
2611e10b93dSalc rfPloSel = ee->ee_xpd[headerInfo11B];
2621e10b93dSalc rfPwdXpd = !ee->ee_xpd[headerInfo11B];
2631e10b93dSalc gainI = ee->ee_gainI[headerInfo11B];
2641e10b93dSalc break;
2651e10b93dSalc case CHANNEL_G:
2661e10b93dSalc tempOB = ee->ee_obFor24g;
2671e10b93dSalc tempDB = ee->ee_dbFor24g;
2681e10b93dSalc ob2GHz = ee->ee_ob2GHz[1];
2691e10b93dSalc db2GHz = ee->ee_db2GHz[1];
2701e10b93dSalc
2711e10b93dSalc rfXpdGainFixed = ee->ee_xgain[headerInfo11G];
2721e10b93dSalc rfPloSel = ee->ee_xpd[headerInfo11G];
2731e10b93dSalc rfPwdXpd = !ee->ee_xpd[headerInfo11G];
2741e10b93dSalc gainI = ee->ee_gainI[headerInfo11G];
2751e10b93dSalc break;
2761e10b93dSalc default:
2771e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
2781e10b93dSalc __func__, chan->channelFlags);
2791e10b93dSalc return AH_FALSE;
2801e10b93dSalc }
2811e10b93dSalc
2821e10b93dSalc HALASSERT(1 <= tempOB && tempOB <= 5);
2831e10b93dSalc HALASSERT(1 <= tempDB && tempDB <= 5);
2841e10b93dSalc
2851e10b93dSalc /* Bank 0 Write */
2861e10b93dSalc for (i = 0; i < N(ar5212Bank0_5111); i++)
2871e10b93dSalc rfReg[i] = ar5212Bank0_5111[i][modesIndex];
2881e10b93dSalc if (IS_CHAN_2GHZ(chan)) {
2891e10b93dSalc ar5212ModifyRfBuffer(rfReg, ob2GHz, 3, 119, 0);
2901e10b93dSalc ar5212ModifyRfBuffer(rfReg, db2GHz, 3, 122, 0);
2911e10b93dSalc }
2921e10b93dSalc HAL_INI_WRITE_BANK(ah, ar5212Bank0_5111, rfReg, regWrites);
2931e10b93dSalc
2941e10b93dSalc /* Bank 1 Write */
2951e10b93dSalc HAL_INI_WRITE_ARRAY(ah, ar5212Bank1_5111, 1, regWrites);
2961e10b93dSalc
2971e10b93dSalc /* Bank 2 Write */
2981e10b93dSalc HAL_INI_WRITE_ARRAY(ah, ar5212Bank2_5111, modesIndex, regWrites);
2991e10b93dSalc
3001e10b93dSalc /* Bank 3 Write */
3011e10b93dSalc HAL_INI_WRITE_ARRAY(ah, ar5212Bank3_5111, modesIndex, regWrites);
3021e10b93dSalc
3031e10b93dSalc /* Bank 6 Write */
3041e10b93dSalc for (i = 0; i < N(ar5212Bank6_5111); i++)
3051e10b93dSalc rfReg[i] = ar5212Bank6_5111[i][modesIndex];
3061e10b93dSalc if (IS_CHAN_A(chan)) { /* NB: CHANNEL_A | CHANNEL_T */
3071e10b93dSalc ar5212ModifyRfBuffer(rfReg, ee->ee_cornerCal.pd84, 1, 51, 3);
3081e10b93dSalc ar5212ModifyRfBuffer(rfReg, ee->ee_cornerCal.pd90, 1, 45, 3);
3091e10b93dSalc }
3101e10b93dSalc ar5212ModifyRfBuffer(rfReg, rfPwdXpd, 1, 95, 0);
3111e10b93dSalc ar5212ModifyRfBuffer(rfReg, rfXpdGainFixed, 4, 96, 0);
3121e10b93dSalc /* Set 5212 OB & DB */
3131e10b93dSalc ar5212ModifyRfBuffer(rfReg, tempOB, 3, 104, 0);
3141e10b93dSalc ar5212ModifyRfBuffer(rfReg, tempDB, 3, 107, 0);
3151e10b93dSalc HAL_INI_WRITE_BANK(ah, ar5212Bank6_5111, rfReg, regWrites);
3161e10b93dSalc
3171e10b93dSalc /* Bank 7 Write */
3181e10b93dSalc for (i = 0; i < N(ar5212Bank7_5111); i++)
3191e10b93dSalc rfReg[i] = ar5212Bank7_5111[i][modesIndex];
3201e10b93dSalc ar5212ModifyRfBuffer(rfReg, gainI, 6, 29, 0);
3211e10b93dSalc ar5212ModifyRfBuffer(rfReg, rfPloSel, 1, 4, 0);
3221e10b93dSalc
3231e10b93dSalc if (IS_CHAN_QUARTER_RATE(chan) || IS_CHAN_HALF_RATE(chan)) {
3241e10b93dSalc uint32_t rfWaitI, rfWaitS, rfMaxTime;
3251e10b93dSalc
3261e10b93dSalc rfWaitS = 0x1f;
3271e10b93dSalc rfWaitI = (IS_CHAN_HALF_RATE(chan)) ? 0x10 : 0x1f;
3281e10b93dSalc rfMaxTime = 3;
3291e10b93dSalc ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0);
3301e10b93dSalc ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0);
3311e10b93dSalc ar5212ModifyRfBuffer(rfReg, rfMaxTime, 2, 49, 0);
3321e10b93dSalc
3331e10b93dSalc }
3341e10b93dSalc
3351e10b93dSalc HAL_INI_WRITE_BANK(ah, ar5212Bank7_5111, rfReg, regWrites);
3361e10b93dSalc
3371e10b93dSalc /* Now that we have reprogrammed rfgain value, clear the flag. */
3381e10b93dSalc ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
3391e10b93dSalc
3401e10b93dSalc return AH_TRUE;
3411e10b93dSalc }
3421e10b93dSalc
3431e10b93dSalc /*
3441e10b93dSalc * Returns interpolated or the scaled up interpolated value
3451e10b93dSalc */
3461e10b93dSalc static uint16_t
interpolate(uint16_t target,uint16_t srcLeft,uint16_t srcRight,uint16_t targetLeft,uint16_t targetRight)3471e10b93dSalc interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
3481e10b93dSalc uint16_t targetLeft, uint16_t targetRight)
3491e10b93dSalc {
3501e10b93dSalc uint16_t rv;
3511e10b93dSalc int16_t lRatio;
3521e10b93dSalc
3531e10b93dSalc /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */
3541e10b93dSalc if ((targetLeft * targetRight) == 0)
3551e10b93dSalc return 0;
3561e10b93dSalc
3571e10b93dSalc if (srcRight != srcLeft) {
3581e10b93dSalc /*
3591e10b93dSalc * Note the ratio always need to be scaled,
3601e10b93dSalc * since it will be a fraction.
3611e10b93dSalc */
3621e10b93dSalc lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft);
3631e10b93dSalc if (lRatio < 0) {
3641e10b93dSalc /* Return as Left target if value would be negative */
3651e10b93dSalc rv = targetLeft;
3661e10b93dSalc } else if (lRatio > EEP_SCALE) {
3671e10b93dSalc /* Return as Right target if Ratio is greater than 100% (SCALE) */
3681e10b93dSalc rv = targetRight;
3691e10b93dSalc } else {
3701e10b93dSalc rv = (lRatio * targetRight + (EEP_SCALE - lRatio) *
3711e10b93dSalc targetLeft) / EEP_SCALE;
3721e10b93dSalc }
3731e10b93dSalc } else {
3741e10b93dSalc rv = targetLeft;
3751e10b93dSalc }
3761e10b93dSalc return rv;
3771e10b93dSalc }
3781e10b93dSalc
3791e10b93dSalc /*
3801e10b93dSalc * Read the transmit power levels from the structures taken from EEPROM
3811e10b93dSalc * Interpolate read transmit power values for this channel
3821e10b93dSalc * Organize the transmit power values into a table for writing into the hardware
3831e10b93dSalc */
3841e10b93dSalc static HAL_BOOL
ar5111SetPowerTable(struct ath_hal * ah,int16_t * pMinPower,int16_t * pMaxPower,HAL_CHANNEL_INTERNAL * chan,uint16_t * rfXpdGain)3851e10b93dSalc ar5111SetPowerTable(struct ath_hal *ah,
3861e10b93dSalc int16_t *pMinPower, int16_t *pMaxPower, HAL_CHANNEL_INTERNAL *chan,
3871e10b93dSalc uint16_t *rfXpdGain)
3881e10b93dSalc {
3891e10b93dSalc struct ath_hal_5212 *ahp = AH5212(ah);
3901e10b93dSalc const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
3911e10b93dSalc FULL_PCDAC_STRUCT pcdacStruct;
3921e10b93dSalc int i, j;
3931e10b93dSalc
3941e10b93dSalc uint16_t *pPcdacValues;
3951e10b93dSalc int16_t *pScaledUpDbm;
3961e10b93dSalc int16_t minScaledPwr;
3971e10b93dSalc int16_t maxScaledPwr;
3981e10b93dSalc int16_t pwr;
3991e10b93dSalc uint16_t pcdacMin = 0;
4001e10b93dSalc uint16_t pcdacMax = PCDAC_STOP;
4011e10b93dSalc uint16_t pcdacTableIndex;
4021e10b93dSalc uint16_t scaledPcdac;
4031e10b93dSalc PCDACS_EEPROM *pSrcStruct;
4041e10b93dSalc PCDACS_EEPROM eepromPcdacs;
4051e10b93dSalc
4061e10b93dSalc /* setup the pcdac struct to point to the correct info, based on mode */
4071e10b93dSalc switch (chan->channelFlags & CHANNEL_ALL) {
4081e10b93dSalc case CHANNEL_A:
4091e10b93dSalc case CHANNEL_T:
4101e10b93dSalc eepromPcdacs.numChannels = ee->ee_numChannels11a;
4111e10b93dSalc eepromPcdacs.pChannelList = ee->ee_channels11a;
4121e10b93dSalc eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a;
4131e10b93dSalc break;
4141e10b93dSalc case CHANNEL_B:
4151e10b93dSalc eepromPcdacs.numChannels = ee->ee_numChannels2_4;
4161e10b93dSalc eepromPcdacs.pChannelList = ee->ee_channels11b;
4171e10b93dSalc eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b;
4181e10b93dSalc break;
4191e10b93dSalc case CHANNEL_G:
4201e10b93dSalc case CHANNEL_108G:
4211e10b93dSalc eepromPcdacs.numChannels = ee->ee_numChannels2_4;
4221e10b93dSalc eepromPcdacs.pChannelList = ee->ee_channels11g;
4231e10b93dSalc eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g;
4241e10b93dSalc break;
4251e10b93dSalc default:
4261e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
4271e10b93dSalc __func__, chan->channelFlags);
4281e10b93dSalc return AH_FALSE;
4291e10b93dSalc }
4301e10b93dSalc
4311e10b93dSalc pSrcStruct = &eepromPcdacs;
4321e10b93dSalc
4331e10b93dSalc OS_MEMZERO(&pcdacStruct, sizeof(pcdacStruct));
4341e10b93dSalc pPcdacValues = pcdacStruct.PcdacValues;
4351e10b93dSalc pScaledUpDbm = pcdacStruct.PwrValues;
4361e10b93dSalc
4371e10b93dSalc /* Initialize the pcdacs to dBM structs pcdacs to be 1 to 63 */
4381e10b93dSalc for (i = PCDAC_START, j = 0; i <= PCDAC_STOP; i+= PCDAC_STEP, j++)
4391e10b93dSalc pPcdacValues[j] = i;
4401e10b93dSalc
4411e10b93dSalc pcdacStruct.numPcdacValues = j;
4421e10b93dSalc pcdacStruct.pcdacMin = PCDAC_START;
4431e10b93dSalc pcdacStruct.pcdacMax = PCDAC_STOP;
4441e10b93dSalc
4451e10b93dSalc /* Fill out the power values for this channel */
4461e10b93dSalc for (j = 0; j < pcdacStruct.numPcdacValues; j++ )
4471e10b93dSalc pScaledUpDbm[j] = ar5212GetScaledPower(chan->channel,
4481e10b93dSalc pPcdacValues[j], pSrcStruct);
4491e10b93dSalc
4501e10b93dSalc /* Now scale the pcdac values to fit in the 64 entry power table */
4511e10b93dSalc minScaledPwr = pScaledUpDbm[0];
4521e10b93dSalc maxScaledPwr = pScaledUpDbm[pcdacStruct.numPcdacValues - 1];
4531e10b93dSalc
4541e10b93dSalc /* find minimum and make monotonic */
4551e10b93dSalc for (j = 0; j < pcdacStruct.numPcdacValues; j++) {
4561e10b93dSalc if (minScaledPwr >= pScaledUpDbm[j]) {
4571e10b93dSalc minScaledPwr = pScaledUpDbm[j];
4581e10b93dSalc pcdacMin = j;
4591e10b93dSalc }
4601e10b93dSalc /*
4611e10b93dSalc * Make the full_hsh monotonically increasing otherwise
4621e10b93dSalc * interpolation algorithm will get fooled gotta start
4631e10b93dSalc * working from the top, hence i = 63 - j.
4641e10b93dSalc */
4651e10b93dSalc i = (uint16_t)(pcdacStruct.numPcdacValues - 1 - j);
4661e10b93dSalc if (i == 0)
4671e10b93dSalc break;
4681e10b93dSalc if (pScaledUpDbm[i-1] > pScaledUpDbm[i]) {
4691e10b93dSalc /*
4701e10b93dSalc * It could be a glitch, so make the power for
4711e10b93dSalc * this pcdac the same as the power from the
4721e10b93dSalc * next highest pcdac.
4731e10b93dSalc */
4741e10b93dSalc pScaledUpDbm[i - 1] = pScaledUpDbm[i];
4751e10b93dSalc }
4761e10b93dSalc }
4771e10b93dSalc
4781e10b93dSalc for (j = 0; j < pcdacStruct.numPcdacValues; j++)
4791e10b93dSalc if (maxScaledPwr < pScaledUpDbm[j]) {
4801e10b93dSalc maxScaledPwr = pScaledUpDbm[j];
4811e10b93dSalc pcdacMax = j;
4821e10b93dSalc }
4831e10b93dSalc
4841e10b93dSalc /* Find the first power level with a pcdac */
4851e10b93dSalc pwr = (uint16_t)(PWR_STEP *
4861e10b93dSalc ((minScaledPwr - PWR_MIN + PWR_STEP / 2) / PWR_STEP) + PWR_MIN);
4871e10b93dSalc
4881e10b93dSalc /* Write all the first pcdac entries based off the pcdacMin */
4891e10b93dSalc pcdacTableIndex = 0;
4901e10b93dSalc for (i = 0; i < (2 * (pwr - PWR_MIN) / EEP_SCALE + 1); i++) {
4911e10b93dSalc HALASSERT(pcdacTableIndex < PWR_TABLE_SIZE);
4921e10b93dSalc ahp->ah_pcdacTable[pcdacTableIndex++] = pcdacMin;
4931e10b93dSalc }
4941e10b93dSalc
4951e10b93dSalc i = 0;
4961e10b93dSalc while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
4971e10b93dSalc pcdacTableIndex < PWR_TABLE_SIZE) {
4981e10b93dSalc pwr += PWR_STEP;
4991e10b93dSalc /* stop if dbM > max_power_possible */
5001e10b93dSalc while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
5011e10b93dSalc (pwr - pScaledUpDbm[i])*(pwr - pScaledUpDbm[i+1]) > 0)
5021e10b93dSalc i++;
5031e10b93dSalc /* scale by 2 and add 1 to enable round up or down as needed */
5041e10b93dSalc scaledPcdac = (uint16_t)(interpolate(pwr,
5051e10b93dSalc pScaledUpDbm[i], pScaledUpDbm[i + 1],
5061e10b93dSalc (uint16_t)(pPcdacValues[i] * 2),
5071e10b93dSalc (uint16_t)(pPcdacValues[i + 1] * 2)) + 1);
5081e10b93dSalc
5091e10b93dSalc HALASSERT(pcdacTableIndex < PWR_TABLE_SIZE);
5101e10b93dSalc ahp->ah_pcdacTable[pcdacTableIndex] = scaledPcdac / 2;
5111e10b93dSalc if (ahp->ah_pcdacTable[pcdacTableIndex] > pcdacMax)
5121e10b93dSalc ahp->ah_pcdacTable[pcdacTableIndex] = pcdacMax;
5131e10b93dSalc pcdacTableIndex++;
5141e10b93dSalc }
5151e10b93dSalc
5161e10b93dSalc /* Write all the last pcdac entries based off the last valid pcdac */
5171e10b93dSalc while (pcdacTableIndex < PWR_TABLE_SIZE) {
5181e10b93dSalc ahp->ah_pcdacTable[pcdacTableIndex] =
5191e10b93dSalc ahp->ah_pcdacTable[pcdacTableIndex - 1];
5201e10b93dSalc pcdacTableIndex++;
5211e10b93dSalc }
5221e10b93dSalc
5231e10b93dSalc /* No power table adjustment for 5111 */
5241e10b93dSalc ahp->ah_txPowerIndexOffset = 0;
5251e10b93dSalc
5261e10b93dSalc return AH_TRUE;
5271e10b93dSalc }
5281e10b93dSalc
5291e10b93dSalc /*
5301e10b93dSalc * Get or interpolate the pcdac value from the calibrated data.
5311e10b93dSalc */
5321e10b93dSalc static uint16_t
ar5212GetScaledPower(uint16_t channel,uint16_t pcdacValue,const PCDACS_EEPROM * pSrcStruct)5331e10b93dSalc ar5212GetScaledPower(uint16_t channel, uint16_t pcdacValue,
5341e10b93dSalc const PCDACS_EEPROM *pSrcStruct)
5351e10b93dSalc {
5361e10b93dSalc uint16_t powerValue;
5371e10b93dSalc uint16_t lFreq, rFreq; /* left and right frequency values */
5381e10b93dSalc uint16_t llPcdac, ulPcdac; /* lower and upper left pcdac values */
5391e10b93dSalc uint16_t lrPcdac, urPcdac; /* lower and upper right pcdac values */
540*7c9a97abSmrg uint16_t lPwr = 0, uPwr = 0; /* lower and upper temp pwr values */
5411e10b93dSalc uint16_t lScaledPwr, rScaledPwr; /* left and right scaled power */
5421e10b93dSalc
5431e10b93dSalc if (ar5212FindValueInList(channel, pcdacValue, pSrcStruct, &powerValue)) {
5441e10b93dSalc /* value was copied from srcStruct */
5451e10b93dSalc return powerValue;
5461e10b93dSalc }
5471e10b93dSalc
5481e10b93dSalc ar5212GetLowerUpperValues(channel,
5491e10b93dSalc pSrcStruct->pChannelList, pSrcStruct->numChannels,
5501e10b93dSalc &lFreq, &rFreq);
5511e10b93dSalc ar5212GetLowerUpperPcdacs(pcdacValue,
5521e10b93dSalc lFreq, pSrcStruct, &llPcdac, &ulPcdac);
5531e10b93dSalc ar5212GetLowerUpperPcdacs(pcdacValue,
5541e10b93dSalc rFreq, pSrcStruct, &lrPcdac, &urPcdac);
5551e10b93dSalc
5561e10b93dSalc /* get the power index for the pcdac value */
5571e10b93dSalc ar5212FindValueInList(lFreq, llPcdac, pSrcStruct, &lPwr);
5581e10b93dSalc ar5212FindValueInList(lFreq, ulPcdac, pSrcStruct, &uPwr);
5591e10b93dSalc lScaledPwr = interpolate(pcdacValue, llPcdac, ulPcdac, lPwr, uPwr);
5601e10b93dSalc
5611e10b93dSalc ar5212FindValueInList(rFreq, lrPcdac, pSrcStruct, &lPwr);
5621e10b93dSalc ar5212FindValueInList(rFreq, urPcdac, pSrcStruct, &uPwr);
5631e10b93dSalc rScaledPwr = interpolate(pcdacValue, lrPcdac, urPcdac, lPwr, uPwr);
5641e10b93dSalc
5651e10b93dSalc return interpolate(channel, lFreq, rFreq, lScaledPwr, rScaledPwr);
5661e10b93dSalc }
5671e10b93dSalc
5681e10b93dSalc /*
5691e10b93dSalc * Find the value from the calibrated source data struct
5701e10b93dSalc */
5711e10b93dSalc static HAL_BOOL
ar5212FindValueInList(uint16_t channel,uint16_t pcdacValue,const PCDACS_EEPROM * pSrcStruct,uint16_t * powerValue)5721e10b93dSalc ar5212FindValueInList(uint16_t channel, uint16_t pcdacValue,
5731e10b93dSalc const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue)
5741e10b93dSalc {
5751e10b93dSalc const DATA_PER_CHANNEL *pChannelData = pSrcStruct->pDataPerChannel;
5761e10b93dSalc int i;
5771e10b93dSalc
5781e10b93dSalc for (i = 0; i < pSrcStruct->numChannels; i++ ) {
5791e10b93dSalc if (pChannelData->channelValue == channel) {
5801e10b93dSalc const uint16_t* pPcdac = pChannelData->PcdacValues;
5811e10b93dSalc int j;
5821e10b93dSalc
5831e10b93dSalc for (j = 0; j < pChannelData->numPcdacValues; j++ ) {
5841e10b93dSalc if (*pPcdac == pcdacValue) {
5851e10b93dSalc *powerValue = pChannelData->PwrValues[j];
5861e10b93dSalc return AH_TRUE;
5871e10b93dSalc }
5881e10b93dSalc pPcdac++;
5891e10b93dSalc }
5901e10b93dSalc }
5911e10b93dSalc pChannelData++;
5921e10b93dSalc }
5931e10b93dSalc return AH_FALSE;
5941e10b93dSalc }
5951e10b93dSalc
5961e10b93dSalc /*
5971e10b93dSalc * Get the upper and lower pcdac given the channel and the pcdac
5981e10b93dSalc * used in the search
5991e10b93dSalc */
6001e10b93dSalc static void
ar5212GetLowerUpperPcdacs(uint16_t pcdac,uint16_t channel,const PCDACS_EEPROM * pSrcStruct,uint16_t * pLowerPcdac,uint16_t * pUpperPcdac)6011e10b93dSalc ar5212GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel,
6021e10b93dSalc const PCDACS_EEPROM *pSrcStruct,
6031e10b93dSalc uint16_t *pLowerPcdac, uint16_t *pUpperPcdac)
6041e10b93dSalc {
6051e10b93dSalc const DATA_PER_CHANNEL *pChannelData = pSrcStruct->pDataPerChannel;
6061e10b93dSalc int i;
6071e10b93dSalc
6081e10b93dSalc /* Find the channel information */
6091e10b93dSalc for (i = 0; i < pSrcStruct->numChannels; i++) {
6101e10b93dSalc if (pChannelData->channelValue == channel)
6111e10b93dSalc break;
6121e10b93dSalc pChannelData++;
6131e10b93dSalc }
6141e10b93dSalc ar5212GetLowerUpperValues(pcdac, pChannelData->PcdacValues,
6151e10b93dSalc pChannelData->numPcdacValues,
6161e10b93dSalc pLowerPcdac, pUpperPcdac);
6171e10b93dSalc }
6181e10b93dSalc
6191e10b93dSalc static HAL_BOOL
ar5111GetChannelMaxMinPower(struct ath_hal * ah,HAL_CHANNEL * chan,int16_t * maxPow,int16_t * minPow)6201e10b93dSalc ar5111GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
6211e10b93dSalc int16_t *maxPow, int16_t *minPow)
6221e10b93dSalc {
6231e10b93dSalc /* XXX - Get 5111 power limits! */
6241e10b93dSalc /* NB: caller will cope */
6251e10b93dSalc return AH_FALSE;
6261e10b93dSalc }
6271e10b93dSalc
6281e10b93dSalc /*
6291e10b93dSalc * Adjust NF based on statistical values for 5GHz frequencies.
6301e10b93dSalc */
6311e10b93dSalc static int16_t
ar5111GetNfAdjust(struct ath_hal * ah,const HAL_CHANNEL_INTERNAL * c)6321e10b93dSalc ar5111GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
6331e10b93dSalc {
6341e10b93dSalc static const struct {
6351e10b93dSalc uint16_t freqLow;
6361e10b93dSalc int16_t adjust;
6371e10b93dSalc } adjust5111[] = {
6381e10b93dSalc { 5790, 6 }, /* NB: ordered high -> low */
6391e10b93dSalc { 5730, 4 },
6401e10b93dSalc { 5690, 3 },
6411e10b93dSalc { 5660, 2 },
6421e10b93dSalc { 5610, 1 },
6431e10b93dSalc { 5530, 0 },
6441e10b93dSalc { 5450, 0 },
6451e10b93dSalc { 5379, 1 },
6461e10b93dSalc { 5209, 3 },
6471e10b93dSalc { 3000, 5 },
6481e10b93dSalc { 0, 0 },
6491e10b93dSalc };
6501e10b93dSalc int i;
6511e10b93dSalc
6521e10b93dSalc for (i = 0; c->channel <= adjust5111[i].freqLow; i++)
6531e10b93dSalc ;
6541e10b93dSalc return adjust5111[i].adjust;
6551e10b93dSalc }
6561e10b93dSalc
6571e10b93dSalc /*
6581e10b93dSalc * Free memory for analog bank scratch buffers
6591e10b93dSalc */
6601e10b93dSalc static void
ar5111RfDetach(struct ath_hal * ah)6611e10b93dSalc ar5111RfDetach(struct ath_hal *ah)
6621e10b93dSalc {
6631e10b93dSalc struct ath_hal_5212 *ahp = AH5212(ah);
6641e10b93dSalc
6651e10b93dSalc HALASSERT(ahp->ah_rfHal != AH_NULL);
6661e10b93dSalc ath_hal_free(ahp->ah_rfHal);
6671e10b93dSalc ahp->ah_rfHal = AH_NULL;
6681e10b93dSalc }
6691e10b93dSalc
6701e10b93dSalc /*
6711e10b93dSalc * Allocate memory for analog bank scratch buffers
6721e10b93dSalc * Scratch Buffer will be reinitialized every reset so no need to zero now
6731e10b93dSalc */
6741e10b93dSalc static HAL_BOOL
ar5111RfAttach(struct ath_hal * ah,HAL_STATUS * status)6751e10b93dSalc ar5111RfAttach(struct ath_hal *ah, HAL_STATUS *status)
6761e10b93dSalc {
6771e10b93dSalc struct ath_hal_5212 *ahp = AH5212(ah);
6781e10b93dSalc struct ar5111State *priv;
6791e10b93dSalc
6801e10b93dSalc HALASSERT(ah->ah_magic == AR5212_MAGIC);
6811e10b93dSalc
6821e10b93dSalc HALASSERT(ahp->ah_rfHal == AH_NULL);
6831e10b93dSalc priv = ath_hal_malloc(sizeof(struct ar5111State));
6841e10b93dSalc if (priv == AH_NULL) {
6851e10b93dSalc HALDEBUG(ah, HAL_DEBUG_ANY,
6861e10b93dSalc "%s: cannot allocate private state\n", __func__);
6871e10b93dSalc *status = HAL_ENOMEM; /* XXX */
6881e10b93dSalc return AH_FALSE;
6891e10b93dSalc }
6901e10b93dSalc priv->base.rfDetach = ar5111RfDetach;
6911e10b93dSalc priv->base.writeRegs = ar5111WriteRegs;
6921e10b93dSalc priv->base.getRfBank = ar5111GetRfBank;
6931e10b93dSalc priv->base.setChannel = ar5111SetChannel;
6941e10b93dSalc priv->base.setRfRegs = ar5111SetRfRegs;
6951e10b93dSalc priv->base.setPowerTable = ar5111SetPowerTable;
6961e10b93dSalc priv->base.getChannelMaxMinPower = ar5111GetChannelMaxMinPower;
6971e10b93dSalc priv->base.getNfAdjust = ar5111GetNfAdjust;
6981e10b93dSalc
6991e10b93dSalc ahp->ah_pcdacTable = priv->pcdacTable;
7001e10b93dSalc ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
7011e10b93dSalc ahp->ah_rfHal = &priv->base;
7021e10b93dSalc
7031e10b93dSalc return AH_TRUE;
7041e10b93dSalc }
7051e10b93dSalc
7061e10b93dSalc static HAL_BOOL
ar5111Probe(struct ath_hal * ah)7071e10b93dSalc ar5111Probe(struct ath_hal *ah)
7081e10b93dSalc {
7091e10b93dSalc return IS_RAD5111(ah);
7101e10b93dSalc }
7111e10b93dSalc AH_RF(RF5111, ar5111Probe, ar5111RfAttach);
712