1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $Id: ar5416reg.h,v 1.1.1.1 2008/12/11 04:46:51 alc Exp $ 18 */ 19 #ifndef _DEV_ATH_AR5416REG_H 20 #define _DEV_ATH_AR5416REG_H 21 22 #include "ar5212/ar5212reg.h" 23 24 /* 25 * Register added starting with the AR5416 26 */ 27 #define AR_MIRT 0x0020 /* interrupt rate threshold */ 28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30 #define AR_GTXTO 0x0064 /* global transmit timeout */ 31 #define AR_GTTM 0x0068 /* global transmit timeout mode */ 32 #define AR_CST 0x006C /* carrier sense timeout */ 33 #define AR_MAC_LED 0x1f04 /* LED control */ 34 #define AR5416_PCIE_PM_CTRL 0x4014 35 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 36 #define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 37 #define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 38 #define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 39 #define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 40 #define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 41 #define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 42 #define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 43 #define AR5416_PCIE_SERDES 0x4040 44 #define AR5416_PCIE_SERDES2 0x4044 45 #define AR_GPIO_IN 0x4048 /* GPIO input register */ 46 #define AR_GPIO_INTR_OUT 0x404c /* GPIO output register */ 47 #define AR_EEPROM_STATUS_DATA 0x407c 48 #define AR_OBS 0x4080 49 #define AR_RTC_RC 0x7000 /* reset control */ 50 #define AR_RTC_PLL_CONTROL 0x7014 51 #define AR_RTC_RESET 0x7040 /* RTC reset register */ 52 #define AR_RTC_STATUS 0x7044 /* system sleep status */ 53 #define AR_RTC_SLEEP_CLK 0x7048 54 #define AR_RTC_FORCE_WAKE 0x704c /* control MAC force wake */ 55 #define AR_RTC_INTR_CAUSE 0x7050 /* RTC interrupt cause/clear */ 56 #define AR_RTC_INTR_ENABLE 0x7054 /* RTC interrupt enable */ 57 #define AR_RTC_INTR_MASK 0x7058 /* RTC interrupt mask */ 58 /* AR9280: rf long shift registers */ 59 #define AR_AN_RF2G1_CH0 0x7810 60 #define AR_AN_RF5G1_CH0 0x7818 61 #define AR_AN_RF2G1_CH1 0x7834 62 #define AR_AN_RF5G1_CH1 0x783C 63 #define AR_AN_TOP2 0x7894 64 #define AR_AN_SYNTH9 0x7868 65 #define AR9285_AN_RF2G3 0x7828 66 #define AR9285_AN_TOP3 0x786c 67 #define AR_RESET_TSF 0x8020 68 #define AR_RXFIFO_CFG 0x8114 69 #define AR_PHY_ERR_1 0x812c 70 #define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 71 #define AR_PHY_ERR_2 0x8134 72 #define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 73 #define AR_TSFOOR_THRESHOLD 0x813c 74 #define AR_PHY_ERR_3 0x8168 75 #define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 76 #define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 77 #define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 78 #define AR_TXOP_4_7 0x81f4 79 #define AR_TXOP_8_11 0x81f8 80 #define AR_TXOP_12_15 0x81fc 81 /* generic timers based on tsf - all uS */ 82 #define AR_NEXT_TBTT 0x8200 83 #define AR_NEXT_DBA 0x8204 84 #define AR_NEXT_SWBA 0x8208 85 #define AR_NEXT_CFP 0x8208 86 #define AR_NEXT_HCF 0x820C 87 #define AR_NEXT_TIM 0x8210 88 #define AR_NEXT_DTIM 0x8214 89 #define AR_NEXT_QUIET 0x8218 90 #define AR_NEXT_NDP 0x821C 91 #define AR5416_BEACON_PERIOD 0x8220 92 #define AR_DBA_PERIOD 0x8224 93 #define AR_SWBA_PERIOD 0x8228 94 #define AR_HCF_PERIOD 0x822C 95 #define AR_TIM_PERIOD 0x8230 96 #define AR_DTIM_PERIOD 0x8234 97 #define AR_QUIET_PERIOD 0x8238 98 #define AR_NDP_PERIOD 0x823C 99 #define AR_TIMER_MODE 0x8240 100 #define AR_SLP32_MODE 0x8244 101 #define AR_SLP32_WAKE 0x8248 102 #define AR_SLP32_INC 0x824c 103 #define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 104 #define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 105 #define AR_SLP_MIB_CTRL 0x8258 106 #define AR_2040_MODE 0x8318 107 #define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 108 #define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 109 #define AR_PCU_TXBUF_CTRL 0x8340 110 111 /* DMA & PCI Registers in PCI space (usable during sleep)*/ 112 #define AR_RC_AHB 0x00000001 /* AHB reset */ 113 #define AR_RC_APB 0x00000002 /* APB reset */ 114 #define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 115 116 #define AR_MIRT_VAL 0x0000ffff /* in uS */ 117 #define AR_MIRT_VAL_S 16 118 119 #define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 120 #define AR_TIMT_LAST_S 0 121 #define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 122 #define AR_TIMT_FIRST_S 16 123 124 #define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 125 #define AR_RIMT_LAST_S 0 126 #define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 127 #define AR_RIMT_FIRST_S 16 128 129 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 130 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 131 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 132 133 #define AR_GTTM_USEC 0x00000001 // usec strobe 134 #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 135 #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 136 #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 137 138 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 139 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 140 #define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 141 142 /* MAC tx DMA size config */ 143 #define AR_TXCFG_DMASZ_MASK 0x00000003 144 #define AR_TXCFG_DMASZ_4B 0 145 #define AR_TXCFG_DMASZ_8B 1 146 #define AR_TXCFG_DMASZ_16B 2 147 #define AR_TXCFG_DMASZ_32B 3 148 #define AR_TXCFG_DMASZ_64B 4 149 #define AR_TXCFG_DMASZ_128B 5 150 #define AR_TXCFG_DMASZ_256B 6 151 #define AR_TXCFG_DMASZ_512B 7 152 #define AR_TXCFG_ATIM_TXPOLICY 0x00000800 153 154 /* MAC rx DMA size config */ 155 #define AR_RXCFG_DMASZ_MASK 0x00000007 156 #define AR_RXCFG_DMASZ_4B 0 157 #define AR_RXCFG_DMASZ_8B 1 158 #define AR_RXCFG_DMASZ_16B 2 159 #define AR_RXCFG_DMASZ_32B 3 160 #define AR_RXCFG_DMASZ_64B 4 161 #define AR_RXCFG_DMASZ_128B 5 162 #define AR_RXCFG_DMASZ_256B 6 163 #define AR_RXCFG_DMASZ_512B 7 164 165 /* MAC Led registers */ 166 #define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 167 #define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 168 #define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 169 #define AR_MAC_LED_MODE_S 7 170 #define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 171 #define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 172 #define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 173 #define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 174 #define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 175 #define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 176 #define AR_MAC_LED_ASSOC 0x00000c00 177 #define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ 178 #define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ 179 #define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ 180 #define AR_MAC_LED_ASSOC_S 10 181 182 #define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 183 #define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 184 #define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 185 #define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 186 #define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 187 #define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 188 #define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 189 #define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 190 191 /* MAC PCU Registers */ 192 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 193 194 /* Extended PCU DIAG_SW control fields */ 195 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 196 #define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 197 #define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 198 #define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 199 #define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 200 #define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 201 202 #define AR_TXOP_X_VAL 0x000000FF 203 204 #define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 205 206 /* Interrupts */ 207 #define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 208 #define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 209 #define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 210 #define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 211 212 #define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 213 #define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 214 #define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 215 216 #define AR_INTR_SPURIOUS 0xffffffff 217 #define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 218 #define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 219 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 220 #define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 221 #define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 222 223 /* Interrupt Mask Registers */ 224 #define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 225 #define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 226 #define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 227 #define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 228 229 #define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 230 #define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 231 232 /* synchronous interrupt signals */ 233 #define AR_INTR_SYNC_RTC_IRQ 0x00000001 234 #define AR_INTR_SYNC_MAC_IRQ 0x00000002 235 #define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 236 #define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 237 #define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 238 #define AR_INTR_SYNC_HOST1_FATAL 0x00000020 239 #define AR_INTR_SYNC_HOST1_PERR 0x00000040 240 #define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 241 #define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 242 #define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 243 #define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 244 #define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 245 #define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 246 #define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 247 #define AR_INTR_SYNC_PM_ACCESS 0x00004000 248 #define AR_INTR_SYNC_MAC_AWAKE 0x00008000 249 #define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 250 #define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 251 #define AR_INTR_SYNC_ALL 0x0003FFFF 252 253 /* default synchronous interrupt signals enabled */ 254 #define AR_INTR_SYNC_DEFAULT \ 255 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 256 AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 257 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 258 AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 259 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 260 261 /* RTC registers */ 262 #define AR_RTC_RC_M 0x00000003 263 #define AR_RTC_RC_MAC_WARM 0x00000001 264 #define AR_RTC_RC_MAC_COLD 0x00000002 265 #define AR_RTC_PLL_DIV 0x0000001f 266 #define AR_RTC_PLL_DIV_S 0 267 #define AR_RTC_PLL_DIV2 0x00000020 268 #define AR_RTC_PLL_REFDIV_5 0x000000c0 269 270 #define AR_RTC_SOWL_PLL_DIV 0x000003ff 271 #define AR_RTC_SOWL_PLL_DIV_S 0 272 #define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 273 #define AR_RTC_SOWL_PLL_REFDIV_S 10 274 #define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 275 #define AR_RTC_SOWL_PLL_CLKSEL_S 14 276 277 #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 278 279 #define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 280 #define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 281 #define AR_RTC_STATUS_SHUTDOWN 0x00000001 282 #define AR_RTC_STATUS_ON 0x00000002 283 #define AR_RTC_STATUS_SLEEP 0x00000004 284 #define AR_RTC_STATUS_WAKEUP 0x00000008 285 #define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 286 #define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 287 288 #define AR_RTC_SLEEP_DERIVED_CLK 0x2 289 290 #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 291 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 292 293 #define AR_RTC_PLL_CLKSEL 0x00000300 294 #define AR_RTC_PLL_CLKSEL_S 8 295 296 /* AR9280: rf long shift registers */ 297 #define AR_AN_RF2G1_CH0_OB 0x03800000 298 #define AR_AN_RF2G1_CH0_OB_S 23 299 #define AR_AN_RF2G1_CH0_DB 0x1C000000 300 #define AR_AN_RF2G1_CH0_DB_S 26 301 302 #define AR_AN_RF5G1_CH0_OB5 0x00070000 303 #define AR_AN_RF5G1_CH0_OB5_S 16 304 #define AR_AN_RF5G1_CH0_DB5 0x00380000 305 #define AR_AN_RF5G1_CH0_DB5_S 19 306 307 #define AR_AN_RF2G1_CH1_OB 0x03800000 308 #define AR_AN_RF2G1_CH1_OB_S 23 309 #define AR_AN_RF2G1_CH1_DB 0x1C000000 310 #define AR_AN_RF2G1_CH1_DB_S 26 311 312 #define AR_AN_RF5G1_CH1_OB5 0x00070000 313 #define AR_AN_RF5G1_CH1_OB5_S 16 314 #define AR_AN_RF5G1_CH1_DB5 0x00380000 315 #define AR_AN_RF5G1_CH1_DB5_S 19 316 317 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 318 #define AR_AN_TOP2_XPABIAS_LVL_S 30 319 #define AR_AN_TOP2_LOCALBIAS 0x00200000 320 #define AR_AN_TOP2_LOCALBIAS_S 21 321 #define AR_AN_TOP2_PWDCLKIND 0x00400000 322 #define AR_AN_TOP2_PWDCLKIND_S 22 323 324 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 325 #define AR_AN_SYNTH9_REFDIVA_S 27 326 327 /* AR9285 Analog registers */ 328 #define AR9285_AN_RF2G3_OB_0 0x00E00000 329 #define AR9285_AN_RF2G3_OB_0_S 21 330 #define AR9285_AN_RF2G3_OB_1 0x001C0000 331 #define AR9285_AN_RF2G3_OB_1_S 18 332 #define AR9285_AN_RF2G3_OB_2 0x00038000 333 #define AR9285_AN_RF2G3_OB_2_S 15 334 #define AR9285_AN_RF2G3_OB_3 0x00007000 335 #define AR9285_AN_RF2G3_OB_3_S 12 336 #define AR9285_AN_RF2G3_OB_4 0x00000E00 337 #define AR9285_AN_RF2G3_OB_4_S 9 338 339 #define AR9285_AN_RF2G3_DB1_0 0x000001C0 340 #define AR9285_AN_RF2G3_DB1_0_S 6 341 #define AR9285_AN_RF2G3_DB1_1 0x00000038 342 #define AR9285_AN_RF2G3_DB1_1_S 3 343 #define AR9285_AN_RF2G3_DB1_2 0x00000007 344 #define AR9285_AN_RF2G3_DB1_2_S 0 345 #define AR9285_AN_RF2G4 0x782C 346 #define AR9285_AN_RF2G4_DB1_3 0xE0000000 347 #define AR9285_AN_RF2G4_DB1_3_S 29 348 #define AR9285_AN_RF2G4_DB1_4 0x1C000000 349 #define AR9285_AN_RF2G4_DB1_4_S 26 350 351 #define AR9285_AN_RF2G4_DB2_0 0x03800000 352 #define AR9285_AN_RF2G4_DB2_0_S 23 353 #define AR9285_AN_RF2G4_DB2_1 0x00700000 354 #define AR9285_AN_RF2G4_DB2_1_S 20 355 #define AR9285_AN_RF2G4_DB2_2 0x000E0000 356 #define AR9285_AN_RF2G4_DB2_2_S 17 357 #define AR9285_AN_RF2G4_DB2_3 0x0001C000 358 #define AR9285_AN_RF2G4_DB2_3_S 14 359 #define AR9285_AN_RF2G4_DB2_4 0x00003800 360 #define AR9285_AN_RF2G4_DB2_4_S 11 361 362 #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 363 #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 364 365 /* Sleep control */ 366 #define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 367 #define AR5416_SLEEP1_CAB_TIMEOUT_S 22 368 369 #define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 370 #define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 371 372 /* Sleep Registers */ 373 #define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 374 #define AR_SLP32_ENA 0x00100000 375 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 376 377 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 378 379 #define AR_SLP32_TST_INC 0x000FFFFF 380 381 #define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 382 #define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 383 384 #define AR_TIMER_MODE_TBTT 0x00000001 385 #define AR_TIMER_MODE_DBA 0x00000002 386 #define AR_TIMER_MODE_SWBA 0x00000004 387 #define AR_TIMER_MODE_HCF 0x00000008 388 #define AR_TIMER_MODE_TIM 0x00000010 389 #define AR_TIMER_MODE_DTIM 0x00000020 390 #define AR_TIMER_MODE_QUIET 0x00000040 391 #define AR_TIMER_MODE_NDP 0x00000080 392 #define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 393 #define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 394 #define AR_TIMER_MODE_THRESH 0xFFFFF000 395 #define AR_TIMER_MODE_THRESH_S 12 396 397 /* PCU Misc modes */ 398 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 399 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 400 #define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 401 #define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 402 #define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 403 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 404 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 405 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 406 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 407 #define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 408 #define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 409 #define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 410 411 /* GPIO Interrupt */ 412 #define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 413 #define AR_INTR_GPIO_S 20 414 415 #define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 416 #define AR_GPIO_OUT_VAL 0x000FFC00 417 #define AR_GPIO_OUT_VAL_S 10 418 #define AR_GPIO_INTR_CTRL 0x3FF00000 419 #define AR_GPIO_INTR_CTRL_S 20 420 421 #define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 422 423 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 424 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 425 426 /* Eeprom defines */ 427 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 428 #define AR_EEPROM_STATUS_DATA_VAL_S 0 429 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 430 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 431 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 432 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 433 434 #define AR_SREV_REVISION_OWL_10 0x08 435 #define AR_SREV_REVISION_OWL_20 0x09 436 #define AR_SREV_REVISION_OWL_22 0x0a 437 438 #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 439 #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 440 #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 441 #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 442 443 /* Test macro for owl 1.0 */ 444 #define IS_5416V1(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_10) 445 #define IS_5416V2(_ah) ((_ah)->ah_macRev >= AR_SREV_REVISION_OWL_20) 446 #define IS_5416V2_2(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_22) 447 448 /* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 449 #define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 450 #define AR_XSREV_ID_S 0 451 #define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 452 #define AR_XSREV_VERSION_S 18 453 #define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 454 #define AR_XSREV_TYPE_S 12 455 #define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 456 * 0:2 chains) */ 457 #define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 458 #define AR_XSREV_REVISION 0x00000F00 459 #define AR_XSREV_REVISION_S 8 460 461 #define AR_XSREV_VERSION_OWL_PCI 0x0D 462 #define AR_XSREV_VERSION_OWL_PCIE 0x0C 463 #define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 464 #define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 465 #define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 466 #define AR_XSREV_VERSION_SOWL 0x40 467 #define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 468 #define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 469 #define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 470 #define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 471 #define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 472 #define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 473 #define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 474 #define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 475 476 #define AR_SREV_OWL_20_OR_LATER(_ah) \ 477 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \ 478 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_20) 479 #define AR_SREV_OWL_22_OR_LATER(_ah) \ 480 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \ 481 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22) 482 483 #define AR_SREV_SOWL(_ah) \ 484 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 485 #define AR_SREV_SOWL_10_OR_LATER(_ah) \ 486 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 487 #define AR_SREV_SOWL_11(_ah) \ 488 (AR_SREV_SOWL(_ah) && \ 489 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 490 491 #define AR_SREV_MERLIN(_ah) \ 492 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 493 #define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 494 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 495 #define AR_SREV_MERLIN_20(_ah) \ 496 (AR_SREV_MERLIN(_ah) && \ 497 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) 498 #define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 499 (AR_SREV_MERLIN_20(_ah) || \ 500 AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) 501 502 #define AR_SREV_KITE(_ah) \ 503 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 504 #define AR_SREV_KITE_10_OR_LATER(_ah) \ 505 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 506 #endif /* _DEV_ATH_AR5416REG_H */ 507