1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 // 25 // This file provides common types for both UVM driver and RM's UVM interface. 26 // 27 28 #ifndef _NV_UVM_TYPES_H_ 29 #define _NV_UVM_TYPES_H_ 30 31 #include "nvtypes.h" 32 #include "nvstatus.h" 33 #include "nvgputypes.h" 34 #include "nvCpuUuid.h" 35 36 37 // 38 // Default Page Size if left "0" because in RM BIG page size is default & there 39 // are multiple BIG page sizes in RM. These defines are used as flags to "0" 40 // should be OK when user is not sure which pagesize allocation it wants 41 // 42 #define UVM_PAGE_SIZE_DEFAULT 0x0 43 #define UVM_PAGE_SIZE_4K 0x1000 44 #define UVM_PAGE_SIZE_64K 0x10000 45 #define UVM_PAGE_SIZE_128K 0x20000 46 #define UVM_PAGE_SIZE_2M 0x200000 47 #define UVM_PAGE_SIZE_512M 0x20000000 48 49 // 50 // When modifying flags, make sure they are compatible with the mirrored 51 // PMA_* flags in phys_mem_allocator.h. 52 // 53 // Input flags 54 #define UVM_PMA_ALLOCATE_DONT_EVICT NVBIT(0) 55 #define UVM_PMA_ALLOCATE_PINNED NVBIT(1) 56 #define UVM_PMA_ALLOCATE_SPECIFY_MINIMUM_SPEED NVBIT(2) 57 #define UVM_PMA_ALLOCATE_SPECIFY_ADDRESS_RANGE NVBIT(3) 58 #define UVM_PMA_ALLOCATE_SPECIFY_REGION_ID NVBIT(4) 59 #define UVM_PMA_ALLOCATE_PREFER_SLOWEST NVBIT(5) 60 #define UVM_PMA_ALLOCATE_CONTIGUOUS NVBIT(6) 61 #define UVM_PMA_ALLOCATE_PERSISTENT NVBIT(7) 62 #define UVM_PMA_ALLOCATE_PROTECTED_REGION NVBIT(8) 63 #define UVM_PMA_ALLOCATE_FORCE_ALIGNMENT NVBIT(9) 64 #define UVM_PMA_ALLOCATE_NO_ZERO NVBIT(10) 65 #define UVM_PMA_ALLOCATE_TURN_BLACKLIST_OFF NVBIT(11) 66 #define UVM_PMA_ALLOCATE_ALLOW_PARTIAL NVBIT(12) 67 68 // Output flags 69 #define UVM_PMA_ALLOCATE_RESULT_IS_ZERO NVBIT(0) 70 71 // Input flags to pmaFree 72 #define UVM_PMA_FREE_IS_ZERO NVBIT(0) 73 74 // 75 // Indicate that the PMA operation is being done from one of the PMA eviction 76 // callbacks. 77 // 78 // Notably this flag is currently used only by the UVM/RM interface and not 79 // mirrored in PMA. 80 // 81 #define UVM_PMA_CALLED_FROM_PMA_EVICTION 16384 82 83 #define UVM_UUID_LEN 16 84 #define UVM_SW_OBJ_SUBCHANNEL 5 85 86 typedef unsigned long long UvmGpuPointer; 87 88 // 89 // The following typedefs serve to explain the resources they point to. 90 // The actual resources remain RM internal and not exposed. 91 // 92 typedef struct uvmGpuSession_tag *uvmGpuSessionHandle; // gpuSessionHandle 93 typedef struct uvmGpuDevice_tag *uvmGpuDeviceHandle; // gpuDeviceHandle 94 typedef struct uvmGpuAddressSpace_tag *uvmGpuAddressSpaceHandle; // gpuAddressSpaceHandle 95 typedef struct uvmGpuChannel_tag *uvmGpuChannelHandle; // gpuChannelHandle 96 typedef struct uvmGpuCopyEngine_tag *uvmGpuCopyEngineHandle; // gpuObjectHandle 97 98 typedef struct UvmGpuMemoryInfo_tag 99 { 100 // Out: Memory layout. 101 NvU32 kind; 102 103 // Out: Set to TRUE, if the allocation is in sysmem. 104 NvBool sysmem; 105 106 // Out: Set to TRUE, if the allocation is a constructed 107 // under a Device or Subdevice. 108 // All permutations of sysmem and deviceDescendant are valid. 109 // !sysmem && !deviceDescendant implies a fabric allocation. 110 NvBool deviceDescendant; 111 112 // Out: Page size associated with the phys alloc. 113 NvU64 pageSize; 114 115 // Out: Set to TRUE, if the allocation is contiguous. 116 NvBool contig; 117 118 // Out: Starting Addr if the allocation is contiguous. 119 // This is only valid if contig is NV_TRUE. 120 NvU64 physAddr; 121 122 // Out: Total size of the allocation. 123 NvU64 size; 124 125 // Out: Uuid of the GPU to which the allocation belongs. 126 // This is only valid if deviceDescendant is NV_TRUE. 127 // Note: If the allocation is owned by a device in 128 // an SLI group and the allocation is broadcast 129 // across the SLI group, this UUID will be any one 130 // of the subdevices in the SLI group. 131 NvProcessorUuid uuid; 132 } UvmGpuMemoryInfo; 133 134 // Some resources must share the same virtual mappings across channels. A mapped 135 // resource must be shared by a channel iff: 136 // 137 // 1) The channel belongs to a TSG (UvmGpuChannelInstanceInfo::bTsgChannel is 138 // NV_TRUE). 139 // 140 // 2) The channel is in the same TSG as all other channels sharing that mapping 141 // (UvmGpuChannelInstanceInfo::tsgId matches among channels). 142 // 143 // 3) The channel is in the same GPU address space as the other channels 144 // sharing that mapping. 145 // 146 // 4) The resource handle(s) match those of the shared mapping 147 // (UvmGpuChannelResourceInfo::resourceDescriptor and 148 // UvmGpuChannelResourceInfo::resourceId). 149 typedef struct UvmGpuChannelResourceInfo_tag 150 { 151 // Out: Ptr to the RM memDesc of the channel resource. 152 NvP64 resourceDescriptor; 153 154 // Out: RM ID of the channel resource. 155 NvU32 resourceId; 156 157 // Out: Alignment needed for the resource allocation. 158 NvU64 alignment; 159 160 // Out: Info about the resource allocation. 161 UvmGpuMemoryInfo resourceInfo; 162 } UvmGpuChannelResourceInfo; 163 164 typedef struct UvmGpuPagingChannelInfo_tag 165 { 166 // Pointer to a shadown buffer mirroring the contents of the error notifier 167 // for the paging channel 168 NvNotification *shadowErrorNotifier; 169 } UvmGpuPagingChannelInfo; 170 171 typedef enum 172 { 173 UVM_GPU_CHANNEL_ENGINE_TYPE_GR = 1, 174 UVM_GPU_CHANNEL_ENGINE_TYPE_CE = 2, 175 UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2 = 3, 176 } UVM_GPU_CHANNEL_ENGINE_TYPE; 177 178 #define UVM_GPU_CHANNEL_MAX_RESOURCES 13 179 180 typedef struct UvmGpuChannelInstanceInfo_tag 181 { 182 // Out: Starting address of the channel instance. 183 NvU64 base; 184 185 // Out: Set to NV_TRUE, if the instance is in sysmem. 186 // Set to NV_FALSE, if the instance is in vidmem. 187 NvBool sysmem; 188 189 // Out: Hardware runlist ID. 190 NvU32 runlistId; 191 192 // Out: Hardware channel ID. 193 NvU32 chId; 194 195 // Out: NV_TRUE if the channel belongs to a subcontext or NV_FALSE if it 196 // belongs to a regular context. 197 NvBool bInSubctx; 198 199 // Out: ID of the subcontext to which the channel belongs. 200 NvU32 subctxId; 201 202 // Out: Whether the channel belongs to a TSG or not 203 NvBool bTsgChannel; 204 205 // Out: ID of the TSG to which the channel belongs 206 NvU32 tsgId; 207 208 // Out: Maximum number of subcontexts in the TSG to which the channel belongs 209 NvU32 tsgMaxSubctxCount; 210 211 // Out: Info of channel resources associated with the channel. 212 UvmGpuChannelResourceInfo resourceInfo[UVM_GPU_CHANNEL_MAX_RESOURCES]; 213 214 // Out: Number of valid entries in resourceInfo array. 215 NvU32 resourceCount; 216 217 // Out: Type of the engine the channel is bound to 218 NvU32 channelEngineType; 219 220 // Out: Channel handle to be used in the CLEAR_FAULTED method 221 NvU32 clearFaultedToken; 222 223 // Out: Address of the NV_CHRAM_CHANNEL register required to clear the 224 // ENG_FAULTED/PBDMA_FAULTED bits after servicing non-replayable faults on 225 // Ampere+ GPUs 226 volatile NvU32 *pChramChannelRegister; 227 228 // Out: Address of the Runlist PRI Base Register required to ring the 229 // doorbell after clearing the faulted bit. 230 volatile NvU32 *pRunlistPRIBaseRegister; 231 232 // Out: SMC engine id to which the GR channel is bound, or zero if the GPU 233 // does not support SMC or it is a CE channel 234 NvU32 smcEngineId; 235 236 // Out: Start of the VEID range assigned to the SMC engine the GR channel 237 // is bound to, or zero if the GPU does not support SMC or it is a CE 238 // channel 239 NvU32 smcEngineVeIdOffset; 240 } UvmGpuChannelInstanceInfo; 241 242 typedef struct UvmGpuChannelResourceBindParams_tag 243 { 244 // In: RM ID of the channel resource. 245 NvU32 resourceId; 246 247 // In: Starting VA at which the channel resource is mapped. 248 NvU64 resourceVa; 249 } UvmGpuChannelResourceBindParams; 250 251 typedef struct UvmGpuChannelInfo_tag 252 { 253 volatile unsigned *gpGet; 254 volatile unsigned *gpPut; 255 UvmGpuPointer *gpFifoEntries; 256 unsigned numGpFifoEntries; 257 unsigned channelClassNum; 258 259 // The errorNotifier is filled out when the channel hits an RC error. 260 NvNotification *errorNotifier; 261 262 NvU32 hwRunlistId; 263 NvU32 hwChannelId; 264 265 volatile unsigned *dummyBar1Mapping; 266 267 // These values are filled by nvUvmInterfaceCopyEngineAlloc. The work 268 // submission token requires the channel to be bound to a runlist and that 269 // happens after CE allocation. 270 volatile NvU32 *workSubmissionOffset; 271 272 // To be deprecated. See pWorkSubmissionToken below. 273 NvU32 workSubmissionToken; 274 275 // 276 // This is the memory location where the most recently updated work 277 // submission token for this channel will be written to. After submitting 278 // new work and updating GP_PUT with the appropriate fence, the token must 279 // be read from this location before writing it to the workSubmissionOffset 280 // to kick off the new work. 281 // 282 volatile NvU32 *pWorkSubmissionToken; 283 } UvmGpuChannelInfo; 284 285 typedef enum 286 { 287 // This value must be passed by Pascal and pre-Pascal GPUs for those 288 // allocations for which a specific location cannot be enforced. 289 UVM_BUFFER_LOCATION_DEFAULT = 0, 290 291 UVM_BUFFER_LOCATION_SYS = 1, 292 UVM_BUFFER_LOCATION_VID = 2, 293 } UVM_BUFFER_LOCATION; 294 295 typedef struct UvmGpuChannelAllocParams_tag 296 { 297 NvU32 numGpFifoEntries; 298 299 // The next two fields store UVM_BUFFER_LOCATION values 300 NvU32 gpFifoLoc; 301 NvU32 gpPutLoc; 302 303 // Index of the engine the channel will be bound to 304 // ignored if engineType is anything other than UVM_GPU_CHANNEL_ENGINE_TYPE_CE 305 NvU32 engineIndex; 306 307 // interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE 308 NvU32 engineType; 309 310 } UvmGpuChannelAllocParams; 311 312 typedef struct UvmGpuPagingChannelAllocParams_tag 313 { 314 // Index of the LCE engine the channel will be bound to, a zero-based offset 315 // from NV2080_ENGINE_TYPE_COPY0. 316 NvU32 engineIndex; 317 } UvmGpuPagingChannelAllocParams; 318 319 // The max number of Copy Engines supported by a GPU. 320 // The gpu ops build has a static assert that this is the correct number. 321 #define UVM_COPY_ENGINE_COUNT_MAX 10 322 323 typedef struct 324 { 325 // True if the CE is supported at all 326 NvBool supported:1; 327 328 // True if the CE is synchronous with GR 329 NvBool grce:1; 330 331 // True if the CE shares physical CEs with any other CE 332 // 333 // The value returned by RM for this field may change when a GPU is 334 // registered with RM for the first time, so UVM needs to query it 335 // again each time a GPU is registered. 336 NvBool shared:1; 337 338 // True if the CE can give enhanced performance for SYSMEM reads over other CEs 339 NvBool sysmemRead:1; 340 341 // True if the CE can give enhanced performance for SYSMEM writes over other CEs 342 NvBool sysmemWrite:1; 343 344 // True if the CE can be used for SYSMEM transactions 345 NvBool sysmem:1; 346 347 // True if the CE can be used for P2P transactions using NVLINK 348 NvBool nvlinkP2p:1; 349 350 // True if the CE can be used for P2P transactions 351 NvBool p2p:1; 352 353 // Mask of physical CEs assigned to this LCE 354 // 355 // The value returned by RM for this field may change when a GPU is 356 // registered with RM for the first time, so UVM needs to query it 357 // again each time a GPU is registered. 358 NvU32 cePceMask; 359 } UvmGpuCopyEngineCaps; 360 361 typedef struct UvmGpuCopyEnginesCaps_tag 362 { 363 // Supported CEs may not be contiguous 364 UvmGpuCopyEngineCaps copyEngineCaps[UVM_COPY_ENGINE_COUNT_MAX]; 365 } UvmGpuCopyEnginesCaps; 366 367 typedef enum 368 { 369 UVM_LINK_TYPE_NONE, 370 UVM_LINK_TYPE_PCIE, 371 UVM_LINK_TYPE_NVLINK_1, 372 UVM_LINK_TYPE_NVLINK_2, 373 UVM_LINK_TYPE_NVLINK_3, 374 UVM_LINK_TYPE_NVLINK_4, 375 } UVM_LINK_TYPE; 376 377 typedef struct UvmGpuCaps_tag 378 { 379 NvU32 sysmemLink; // UVM_LINK_TYPE 380 NvU32 sysmemLinkRateMBps; // See UvmGpuP2PCapsParams::totalLinkLineRateMBps 381 NvBool numaEnabled; 382 NvU32 numaNodeId; 383 384 // On ATS systems, GPUs connected to different CPU sockets can have peer 385 // traffic. They are called indirect peers. However, indirect peers are 386 // mapped using sysmem aperture. In order to disambiguate the location of a 387 // specific memory address, each GPU maps its memory to a different window 388 // in the System Physical Address (SPA) space. The following fields contain 389 // the base + size of such window for the GPU. systemMemoryWindowSize 390 // different than 0 indicates that the window is valid. 391 // 392 // - If the window is valid, then we can map GPU memory to the CPU as 393 // cache-coherent by adding the GPU address to the window start. 394 // - If numaEnabled is NV_TRUE, then we can also convert the system 395 // addresses of allocated GPU memory to struct pages. 396 // 397 // TODO: Bug 1986868: fix window start computation for SIMICS 398 NvU64 systemMemoryWindowStart; 399 NvU64 systemMemoryWindowSize; 400 401 // This tells if the GPU is connected to NVSwitch. On systems with NVSwitch 402 // all GPUs are connected to it. If connectedToSwitch is NV_TRUE, 403 // nvswitchMemoryWindowStart tells the base address for the GPU in the 404 // NVSwitch address space. It is used when creating PTEs of memory mappings 405 // to NVSwitch peers. 406 NvBool connectedToSwitch; 407 NvU64 nvswitchMemoryWindowStart; 408 } UvmGpuCaps; 409 410 typedef struct UvmGpuAddressSpaceInfo_tag 411 { 412 NvU64 bigPageSize; 413 414 NvBool atsEnabled; 415 416 // Mapped registers that contain the current GPU time 417 volatile NvU32 *time0Offset; 418 volatile NvU32 *time1Offset; 419 420 // Maximum number of subcontexts supported under this GPU address space 421 NvU32 maxSubctxCount; 422 423 NvBool smcEnabled; 424 425 NvU32 smcSwizzId; 426 427 NvU32 smcGpcCount; 428 } UvmGpuAddressSpaceInfo; 429 430 typedef struct UvmGpuAllocInfo_tag 431 { 432 NvU64 gpuPhysOffset; // Returns gpuPhysOffset if contiguous requested 433 NvU64 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M 434 NvU64 alignment; // Virtual alignment 435 NvBool bContiguousPhysAlloc; // Flag to request contiguous physical allocation 436 NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB 437 NvBool bPersistentVidmem; // Causes RM to allocate persistent video memory 438 NvHandle hPhysHandle; // Handle for phys allocation either provided or retrieved 439 } UvmGpuAllocInfo; 440 441 typedef enum 442 { 443 UVM_VIRT_MODE_NONE = 0, // Baremetal or passthrough virtualization 444 UVM_VIRT_MODE_LEGACY = 1, // Virtualization without SRIOV support 445 UVM_VIRT_MODE_SRIOV_HEAVY = 2, // Virtualization with SRIOV Heavy configured 446 UVM_VIRT_MODE_SRIOV_STANDARD = 3, // Virtualization with SRIOV Standard configured 447 UVM_VIRT_MODE_COUNT = 4, 448 } UVM_VIRT_MODE; 449 450 // !!! The following enums (with UvmRm prefix) are defined and documented in 451 // mm/uvm/interface/uvm_types.h and must be mirrored. Please refer to that file 452 // for more details. 453 454 // UVM GPU mapping types 455 typedef enum 456 { 457 UvmRmGpuMappingTypeDefault = 0, 458 UvmRmGpuMappingTypeReadWriteAtomic = 1, 459 UvmRmGpuMappingTypeReadWrite = 2, 460 UvmRmGpuMappingTypeReadOnly = 3, 461 UvmRmGpuMappingTypeCount = 4 462 } UvmRmGpuMappingType; 463 464 // UVM GPU caching types 465 typedef enum 466 { 467 UvmRmGpuCachingTypeDefault = 0, 468 UvmRmGpuCachingTypeForceUncached = 1, 469 UvmRmGpuCachingTypeForceCached = 2, 470 UvmRmGpuCachingTypeCount = 3 471 } UvmRmGpuCachingType; 472 473 // UVM GPU format types 474 typedef enum { 475 UvmRmGpuFormatTypeDefault = 0, 476 UvmRmGpuFormatTypeBlockLinear = 1, 477 UvmRmGpuFormatTypeCount = 2 478 } UvmRmGpuFormatType; 479 480 // UVM GPU Element bits types 481 typedef enum { 482 UvmRmGpuFormatElementBitsDefault = 0, 483 UvmRmGpuFormatElementBits8 = 1, 484 UvmRmGpuFormatElementBits16 = 2, 485 // Cuda does not support 24-bit width 486 UvmRmGpuFormatElementBits32 = 4, 487 UvmRmGpuFormatElementBits64 = 5, 488 UvmRmGpuFormatElementBits128 = 6, 489 UvmRmGpuFormatElementBitsCount = 7 490 } UvmRmGpuFormatElementBits; 491 492 // UVM GPU Compression types 493 typedef enum { 494 UvmRmGpuCompressionTypeDefault = 0, 495 UvmRmGpuCompressionTypeEnabledNoPlc = 1, 496 UvmRmGpuCompressionTypeCount = 2 497 } UvmRmGpuCompressionType; 498 499 typedef struct UvmGpuExternalMappingInfo_tag 500 { 501 // In: GPU caching ability. 502 UvmRmGpuCachingType cachingType; 503 504 // In: Virtual permissions. 505 UvmRmGpuMappingType mappingType; 506 507 // In: RM virtual mapping memory format 508 UvmRmGpuFormatType formatType; 509 510 // In: RM virtual mapping element bits 511 UvmRmGpuFormatElementBits elementBits; 512 513 // In: RM virtual compression type 514 UvmRmGpuCompressionType compressionType; 515 516 // In: Size of the buffer to store PTEs (in bytes). 517 NvU64 pteBufferSize; 518 519 // In: Page size for mapping 520 // If this field is passed as 0, the page size 521 // of the allocation is used for mapping. 522 // nvUvmInterfaceGetExternalAllocPtes must pass 523 // this field as zero. 524 NvU64 mappingPageSize; 525 526 // In: Pointer to a buffer to store PTEs. 527 // Out: The interface will fill the buffer with PTEs 528 NvU64 *pteBuffer; 529 530 // Out: Number of PTEs filled in to the buffer. 531 NvU64 numWrittenPtes; 532 533 // Out: Number of PTEs remaining to be filled 534 // if the buffer is not sufficient to accommodate 535 // requested PTEs. 536 NvU64 numRemainingPtes; 537 538 // Out: PTE size (in bytes) 539 NvU32 pteSize; 540 } UvmGpuExternalMappingInfo; 541 542 typedef struct UvmGpuP2PCapsParams_tag 543 { 544 // Out: peerId[i] contains gpu[i]'s peer id of gpu[1 - i]. Only defined if 545 // the GPUs are direct peers. 546 NvU32 peerIds[2]; 547 548 // Out: UVM_LINK_TYPE 549 NvU32 p2pLink; 550 551 // Out: optimalNvlinkWriteCEs[i] contains gpu[i]'s optimal CE for writing to 552 // gpu[1 - i]. The CE indexes are valid only if the GPUs are NVLink peers. 553 // 554 // The value returned by RM for this field may change when a GPU is 555 // registered with RM for the first time, so UVM needs to query it again 556 // each time a GPU is registered. 557 NvU32 optimalNvlinkWriteCEs[2]; 558 559 // Out: Maximum unidirectional bandwidth between the peers in megabytes per 560 // second, not taking into account the protocols overhead. The reported 561 // bandwidth for indirect peers is zero. 562 NvU32 totalLinkLineRateMBps; 563 564 // Out: True if the peers have a indirect link to communicate. On P9 565 // systems, this is true if peers are connected to different NPUs that 566 // forward the requests between them. 567 NvU32 indirectAccess : 1; 568 } UvmGpuP2PCapsParams; 569 570 // Platform-wide information 571 typedef struct UvmPlatformInfo_tag 572 { 573 // Out: ATS (Address Translation Services) is supported 574 NvBool atsSupported; 575 576 // Out: AMD SEV (Secure Encrypted Virtualization) is enabled 577 NvBool sevEnabled; 578 } UvmPlatformInfo; 579 580 typedef struct UvmGpuClientInfo_tag 581 { 582 NvHandle hClient; 583 584 NvHandle hSmcPartRef; 585 } UvmGpuClientInfo; 586 587 #define UVM_GPU_NAME_LENGTH 0x40 588 589 typedef struct UvmGpuInfo_tag 590 { 591 // Printable gpu name 592 char name[UVM_GPU_NAME_LENGTH]; 593 594 // Uuid of this gpu 595 NvProcessorUuid uuid; 596 597 // Gpu architecture; NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_* 598 NvU32 gpuArch; 599 600 // Gpu implementation; NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_* 601 NvU32 gpuImplementation; 602 603 // Host (gpfifo) class; *_CHANNEL_GPFIFO_*, e.g. KEPLER_CHANNEL_GPFIFO_A 604 NvU32 hostClass; 605 606 // Copy engine (dma) class; *_DMA_COPY_*, e.g. KEPLER_DMA_COPY_A 607 NvU32 ceClass; 608 609 // Compute class; *_COMPUTE_*, e.g. KEPLER_COMPUTE_A 610 NvU32 computeClass; 611 612 // Set if GPU supports TCC Mode & is in TCC mode. 613 NvBool gpuInTcc; 614 615 // Number of subdevices in SLI group. 616 NvU32 subdeviceCount; 617 618 // Virtualization mode of this gpu. 619 NvU32 virtMode; // UVM_VIRT_MODE 620 621 // NV_TRUE if this is a simulated/emulated GPU. NV_FALSE, otherwise. 622 NvBool isSimulated; 623 624 // Number of GPCs 625 // If SMC is enabled, this is the currently configured number of GPCs for 626 // the given partition (also see the smcSwizzId field below). 627 NvU32 gpcCount; 628 629 // Maximum number of GPCs; NV_SCAL_LITTER_NUM_GPCS 630 // This number is independent of the partition configuration, and can be 631 // used to conservatively size GPU-global constructs. 632 NvU32 maxGpcCount; 633 634 // Number of TPCs 635 NvU32 tpcCount; 636 637 // Maximum number of TPCs per GPC 638 NvU32 maxTpcPerGpcCount; 639 640 // NV_TRUE if SMC is enabled on this GPU. 641 NvBool smcEnabled; 642 643 // SMC partition ID (unique per GPU); note: valid when first looked up in 644 // nvUvmInterfaceGetGpuInfo(), but not guaranteed to remain valid. 645 // nvUvmInterfaceDeviceCreate() re-verifies the swizzId and fails if it is 646 // no longer valid. 647 NvU32 smcSwizzId; 648 649 UvmGpuClientInfo smcUserClientInfo; 650 651 } UvmGpuInfo; 652 653 typedef struct UvmGpuFbInfo_tag 654 { 655 // Max physical address that can be allocated by UVM. This excludes internal 656 // RM regions that are not registered with PMA either. 657 NvU64 maxAllocatableAddress; 658 659 NvU32 heapSize; // RAM in KB available for user allocations 660 NvU32 reservedHeapSize; // RAM in KB reserved for internal RM allocation 661 NvBool bZeroFb; // Zero FB mode enabled. 662 } UvmGpuFbInfo; 663 664 typedef struct UvmGpuEccInfo_tag 665 { 666 unsigned eccMask; 667 unsigned eccOffset; 668 void *eccReadLocation; 669 NvBool *eccErrorNotifier; 670 NvBool bEccEnabled; 671 } UvmGpuEccInfo; 672 673 typedef struct UvmPmaAllocationOptions_tag 674 { 675 NvU32 flags; 676 NvU32 minimumSpeed; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_MININUM_SPEED 677 NvU64 physBegin, physEnd; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_ADDRESS_RANGE 678 NvU32 regionId; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_REGION_ID 679 NvU64 alignment; // valid if flags & UVM_PMA_ALLOCATE_FORCE_ALIGNMENT 680 NvLength numPagesAllocated; // valid if flags & UVM_PMA_ALLOCATE_ALLOW_PARTIAL 681 682 NvU32 resultFlags; // valid if the allocation function returns NV_OK 683 } UvmPmaAllocationOptions; 684 685 // 686 // Mirrored in PMA (PMA_STATS) 687 // 688 typedef struct UvmPmaStatistics_tag 689 { 690 volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions 691 volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions 692 volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions 693 } UvmPmaStatistics; 694 695 /******************************************************************************* 696 uvmEventSuspend 697 This function will be called by the GPU driver to signal to UVM that the 698 system is about to enter a sleep state. When it is called, the 699 following assumptions/guarantees are valid/made: 700 701 * User channels have been preempted and disabled 702 * UVM channels are still running normally and will continue to do 703 so until after this function returns control 704 * User threads are still running, but can no longer issue system 705 system calls to the GPU driver 706 * Until exit from this function, UVM is allowed to make full use of 707 the GPUs under its control, as well as of the GPU driver 708 709 Upon return from this function, UVM may not access GPUs under its control 710 until the GPU driver calls uvmEventResume(). It may still receive 711 calls to uvmEventIsrTopHalf() during this time, which it should return 712 NV_ERR_NO_INTR_PENDING from. It will not receive any other calls. 713 */ 714 typedef NV_STATUS (*uvmEventSuspend_t) (void); 715 716 /******************************************************************************* 717 uvmEventResume 718 This function will be called by the GPU driver to signal to UVM that the 719 system has exited a previously entered sleep state. When it is called, 720 the following assumptions/guarantees are valid/made: 721 722 * UVM is again allowed to make full use of the GPUs under its 723 control, as well as of the GPU driver 724 * UVM channels are running normally 725 * User channels are still preempted and disabled 726 * User threads are again running, but still cannot issue system 727 calls to the GPU driver, nor submit new work 728 729 Upon return from this function, UVM is expected to be fully functional. 730 */ 731 typedef NV_STATUS (*uvmEventResume_t) (void); 732 733 /******************************************************************************* 734 uvmEventStartDevice 735 This function will be called by the GPU driver once it has finished its 736 initialization to tell the UVM driver that this GPU has come up. 737 */ 738 typedef NV_STATUS (*uvmEventStartDevice_t) (const NvProcessorUuid *pGpuUuidStruct); 739 740 /******************************************************************************* 741 uvmEventStopDevice 742 This function will be called by the GPU driver to let UVM know that a GPU 743 is going down. 744 */ 745 typedef NV_STATUS (*uvmEventStopDevice_t) (const NvProcessorUuid *pGpuUuidStruct); 746 747 #if defined (_WIN32) 748 /******************************************************************************* 749 uvmEventWddmResetDuringTimeout 750 This function will be called by KMD in a TDR servicing path to unmap channel 751 resources and to destroy channels. This is a Windows specific event. 752 */ 753 typedef NV_STATUS (*uvmEventWddmResetDuringTimeout_t) (const NvProcessorUuid *pGpuUuidStruct); 754 755 /******************************************************************************* 756 uvmEventWddmRestartAfterTimeout 757 This function will be called by KMD in a TDR servicing path to map channel 758 resources and to create channels. This is a Windows specific event. 759 */ 760 typedef NV_STATUS (*uvmEventWddmRestartAfterTimeout_t) (const NvProcessorUuid *pGpuUuidStruct); 761 762 /******************************************************************************* 763 uvmEventServiceInterrupt 764 This function gets called from RM's intr service routine when an interrupt 765 to service a page fault is triggered. 766 */ 767 typedef NV_STATUS (*uvmEventServiceInterrupt_t) (void *pDeviceObject, 768 NvU32 deviceId, NvU32 subdeviceId); 769 #endif 770 771 /******************************************************************************* 772 uvmEventIsrTopHalf_t 773 This function will be called by the GPU driver to let UVM know 774 that an interrupt has occurred. 775 776 Returns: 777 NV_OK if the UVM driver handled the interrupt 778 NV_ERR_NO_INTR_PENDING if the interrupt is not for the UVM driver 779 */ 780 #if defined (__linux__) 781 typedef NV_STATUS (*uvmEventIsrTopHalf_t) (const NvProcessorUuid *pGpuUuidStruct); 782 #else 783 typedef void (*uvmEventIsrTopHalf_t) (void); 784 #endif 785 786 struct UvmOpsUvmEvents 787 { 788 uvmEventSuspend_t suspend; 789 uvmEventResume_t resume; 790 uvmEventStartDevice_t startDevice; 791 uvmEventStopDevice_t stopDevice; 792 uvmEventIsrTopHalf_t isrTopHalf; 793 #if defined (_WIN32) 794 uvmEventWddmResetDuringTimeout_t wddmResetDuringTimeout; 795 uvmEventWddmRestartAfterTimeout_t wddmRestartAfterTimeout; 796 uvmEventServiceInterrupt_t serviceInterrupt; 797 #endif 798 }; 799 800 typedef struct UvmGpuFaultInfo_tag 801 { 802 struct 803 { 804 // Register mappings obtained from RM 805 volatile NvU32* pFaultBufferGet; 806 volatile NvU32* pFaultBufferPut; 807 // Note: this variable is deprecated since buffer overflow is not a separate 808 // register from future chips. 809 volatile NvU32* pFaultBufferInfo; 810 volatile NvU32* pPmcIntr; 811 volatile NvU32* pPmcIntrEnSet; 812 volatile NvU32* pPmcIntrEnClear; 813 volatile NvU32* pPrefetchCtrl; 814 NvU32 replayableFaultMask; 815 // fault buffer cpu mapping and size 816 void* bufferAddress; 817 NvU32 bufferSize; 818 } replayable; 819 struct 820 { 821 // Shadow buffer for non-replayable faults on cpu memory. Resman copies 822 // here the non-replayable faults that need to be handled by UVM 823 void* shadowBufferAddress; 824 825 // Execution context for the queue associated with the fault buffer 826 void* shadowBufferContext; 827 828 // Fault buffer size 829 NvU32 bufferSize; 830 831 // Preallocated stack for functions called from the UVM isr top half 832 void *isr_sp; 833 834 // Preallocated stack for functions called from the UVM isr bottom half 835 void *isr_bh_sp; 836 837 } nonReplayable; 838 NvHandle faultBufferHandle; 839 } UvmGpuFaultInfo; 840 841 struct Device; 842 843 typedef struct UvmGpuPagingChannel_tag 844 { 845 struct gpuDevice *device; 846 NvNotification *errorNotifier; 847 NvHandle channelHandle; 848 NvHandle errorNotifierHandle; 849 void *pushStreamSp; 850 struct Device *pDevice; 851 } UvmGpuPagingChannel, *UvmGpuPagingChannelHandle; 852 853 typedef struct UvmGpuAccessCntrInfo_tag 854 { 855 // Register mappings obtained from RM 856 // pointer to the Get register for the access counter buffer 857 volatile NvU32* pAccessCntrBufferGet; 858 // pointer to the Put register for the access counter buffer 859 volatile NvU32* pAccessCntrBufferPut; 860 // pointer to the Full register for the access counter buffer 861 volatile NvU32* pAccessCntrBufferFull; 862 // pointer to the hub interrupt 863 volatile NvU32* pHubIntr; 864 // pointer to interrupt enable register 865 volatile NvU32* pHubIntrEnSet; 866 // pointer to interrupt disable register 867 volatile NvU32* pHubIntrEnClear; 868 // mask for the access counter buffer 869 NvU32 accessCounterMask; 870 // access counter buffer cpu mapping and size 871 void* bufferAddress; 872 NvU32 bufferSize; 873 NvHandle accessCntrBufferHandle; 874 875 // The Notification address in the access counter notification msg does not 876 // contain the correct upper bits 63-47 for GPA-based notifications. RM 877 // provides us with the correct offset to be added. 878 // See Bug 1803015 879 NvU64 baseDmaSysmemAddr; 880 } UvmGpuAccessCntrInfo; 881 882 typedef enum 883 { 884 UVM_ACCESS_COUNTER_GRANULARITY_64K = 1, 885 UVM_ACCESS_COUNTER_GRANULARITY_2M = 2, 886 UVM_ACCESS_COUNTER_GRANULARITY_16M = 3, 887 UVM_ACCESS_COUNTER_GRANULARITY_16G = 4, 888 } UVM_ACCESS_COUNTER_GRANULARITY; 889 890 typedef enum 891 { 892 UVM_ACCESS_COUNTER_USE_LIMIT_NONE = 1, 893 UVM_ACCESS_COUNTER_USE_LIMIT_QTR = 2, 894 UVM_ACCESS_COUNTER_USE_LIMIT_HALF = 3, 895 UVM_ACCESS_COUNTER_USE_LIMIT_FULL = 4, 896 } UVM_ACCESS_COUNTER_USE_LIMIT; 897 898 typedef struct UvmGpuAccessCntrConfig_tag 899 { 900 NvU32 mimcGranularity; 901 902 NvU32 momcGranularity; 903 904 NvU32 mimcUseLimit; 905 906 NvU32 momcUseLimit; 907 908 NvU32 threshold; 909 } UvmGpuAccessCntrConfig; 910 911 // 912 // When modifying this enum, make sure they are compatible with the mirrored 913 // MEMORY_PROTECTION enum in phys_mem_allocator.h. 914 // 915 typedef enum UvmPmaGpuMemoryType_tag 916 { 917 UVM_PMA_GPU_MEMORY_TYPE_UNPROTECTED = 0, 918 UVM_PMA_GPU_MEMORY_TYPE_PROTECTED = 1 919 } UVM_PMA_GPU_MEMORY_TYPE; 920 921 typedef UvmGpuChannelInfo gpuChannelInfo; 922 typedef UvmGpuChannelAllocParams gpuChannelAllocParams; 923 typedef UvmGpuCaps gpuCaps; 924 typedef UvmGpuCopyEngineCaps gpuCeCaps; 925 typedef UvmGpuCopyEnginesCaps gpuCesCaps; 926 typedef UvmGpuP2PCapsParams getP2PCapsParams; 927 typedef UvmGpuAddressSpaceInfo gpuAddressSpaceInfo; 928 typedef UvmGpuAllocInfo gpuAllocInfo; 929 typedef UvmGpuInfo gpuInfo; 930 typedef UvmGpuClientInfo gpuClientInfo; 931 typedef UvmGpuAccessCntrInfo gpuAccessCntrInfo; 932 typedef UvmGpuAccessCntrConfig gpuAccessCntrConfig; 933 typedef UvmGpuFaultInfo gpuFaultInfo; 934 typedef UvmGpuMemoryInfo gpuMemoryInfo; 935 typedef UvmGpuExternalMappingInfo gpuExternalMappingInfo; 936 typedef UvmGpuChannelResourceInfo gpuChannelResourceInfo; 937 typedef UvmGpuChannelInstanceInfo gpuChannelInstanceInfo; 938 typedef UvmGpuChannelResourceBindParams gpuChannelResourceBindParams; 939 typedef UvmGpuFbInfo gpuFbInfo; 940 typedef UvmGpuEccInfo gpuEccInfo; 941 typedef UvmGpuPagingChannel *gpuPagingChannelHandle; 942 typedef UvmGpuPagingChannelInfo gpuPagingChannelInfo; 943 typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams; 944 typedef UvmPmaAllocationOptions gpuPmaAllocationOptions; 945 946 #endif // _NV_UVM_TYPES_H_ 947