1 /******************************************************************************* 2 Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included in 12 all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 24 #include "nvtypes.h" 25 26 #ifndef _clc0b5_h_ 27 #define _clc0b5_h_ 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define PASCAL_DMA_COPY_A (0x0000C0B5) 34 35 #define NVC0B5_NOP (0x00000100) 36 #define NVC0B5_NOP_PARAMETER 31:0 37 #define NVC0B5_PM_TRIGGER (0x00000140) 38 #define NVC0B5_PM_TRIGGER_V 31:0 39 #define NVC0B5_SET_SEMAPHORE_A (0x00000240) 40 #define NVC0B5_SET_SEMAPHORE_A_UPPER 16:0 41 #define NVC0B5_SET_SEMAPHORE_B (0x00000244) 42 #define NVC0B5_SET_SEMAPHORE_B_LOWER 31:0 43 #define NVC0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) 44 #define NVC0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 45 #define NVC0B5_SET_RENDER_ENABLE_A (0x00000254) 46 #define NVC0B5_SET_RENDER_ENABLE_A_UPPER 7:0 47 #define NVC0B5_SET_RENDER_ENABLE_B (0x00000258) 48 #define NVC0B5_SET_RENDER_ENABLE_B_LOWER 31:0 49 #define NVC0B5_SET_RENDER_ENABLE_C (0x0000025C) 50 #define NVC0B5_SET_RENDER_ENABLE_C_MODE 2:0 51 #define NVC0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) 52 #define NVC0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) 53 #define NVC0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) 54 #define NVC0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) 55 #define NVC0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) 56 #define NVC0B5_SET_SRC_PHYS_MODE (0x00000260) 57 #define NVC0B5_SET_SRC_PHYS_MODE_TARGET 1:0 58 #define NVC0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) 59 #define NVC0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) 60 #define NVC0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) 61 #define NVC0B5_SET_DST_PHYS_MODE (0x00000264) 62 #define NVC0B5_SET_DST_PHYS_MODE_TARGET 1:0 63 #define NVC0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) 64 #define NVC0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) 65 #define NVC0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) 66 #define NVC0B5_LAUNCH_DMA (0x00000300) 67 #define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 68 #define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) 69 #define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) 70 #define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) 71 #define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 72 #define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) 73 #define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) 74 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 75 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) 76 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) 77 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) 78 #define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 79 #define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) 80 #define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) 81 #define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) 82 #define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 83 #define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) 84 #define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) 85 #define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 86 #define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) 87 #define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) 88 #define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 89 #define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) 90 #define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) 91 #define NVC0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 92 #define NVC0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) 93 #define NVC0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) 94 #define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 95 #define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) 96 #define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) 97 #define NVC0B5_LAUNCH_DMA_SRC_TYPE 12:12 98 #define NVC0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) 99 #define NVC0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) 100 #define NVC0B5_LAUNCH_DMA_DST_TYPE 13:13 101 #define NVC0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) 102 #define NVC0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) 103 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 104 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) 105 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) 106 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) 107 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) 108 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) 109 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) 110 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) 111 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) 112 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) 113 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 114 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) 115 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) 116 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 117 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) 118 #define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) 119 #define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 120 #define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) 121 #define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) 122 #define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 123 #define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) 124 #define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) 125 #define NVC0B5_LAUNCH_DMA_RESERVED 31:28 126 #define NVC0B5_OFFSET_IN_UPPER (0x00000400) 127 #define NVC0B5_OFFSET_IN_UPPER_UPPER 16:0 128 #define NVC0B5_OFFSET_IN_LOWER (0x00000404) 129 #define NVC0B5_OFFSET_IN_LOWER_VALUE 31:0 130 #define NVC0B5_OFFSET_OUT_UPPER (0x00000408) 131 #define NVC0B5_OFFSET_OUT_UPPER_UPPER 16:0 132 #define NVC0B5_OFFSET_OUT_LOWER (0x0000040C) 133 #define NVC0B5_OFFSET_OUT_LOWER_VALUE 31:0 134 #define NVC0B5_PITCH_IN (0x00000410) 135 #define NVC0B5_PITCH_IN_VALUE 31:0 136 #define NVC0B5_PITCH_OUT (0x00000414) 137 #define NVC0B5_PITCH_OUT_VALUE 31:0 138 #define NVC0B5_LINE_LENGTH_IN (0x00000418) 139 #define NVC0B5_LINE_LENGTH_IN_VALUE 31:0 140 #define NVC0B5_LINE_COUNT (0x0000041C) 141 #define NVC0B5_LINE_COUNT_VALUE 31:0 142 #define NVC0B5_SET_REMAP_CONST_A (0x00000700) 143 #define NVC0B5_SET_REMAP_CONST_A_V 31:0 144 #define NVC0B5_SET_REMAP_CONST_B (0x00000704) 145 #define NVC0B5_SET_REMAP_CONST_B_V 31:0 146 #define NVC0B5_SET_REMAP_COMPONENTS (0x00000708) 147 #define NVC0B5_SET_REMAP_COMPONENTS_DST_X 2:0 148 #define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) 149 #define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) 150 #define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) 151 #define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) 152 #define NVC0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) 153 #define NVC0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) 154 #define NVC0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) 155 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 156 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) 157 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) 158 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) 159 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) 160 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) 161 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) 162 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) 163 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 164 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) 165 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) 166 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) 167 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) 168 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) 169 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) 170 #define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) 171 #define NVC0B5_SET_REMAP_COMPONENTS_DST_W 14:12 172 #define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) 173 #define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) 174 #define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) 175 #define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) 176 #define NVC0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) 177 #define NVC0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) 178 #define NVC0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) 179 #define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 180 #define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) 181 #define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) 182 #define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) 183 #define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) 184 #define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 185 #define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) 186 #define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) 187 #define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) 188 #define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) 189 #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 190 #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) 191 #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) 192 #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) 193 #define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) 194 #define NVC0B5_SET_DST_BLOCK_SIZE (0x0000070C) 195 #define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 196 #define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) 197 #define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 198 #define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) 199 #define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) 200 #define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) 201 #define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) 202 #define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) 203 #define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) 204 #define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 205 #define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) 206 #define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) 207 #define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) 208 #define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) 209 #define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) 210 #define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) 211 #define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 212 #define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) 213 #define NVC0B5_SET_DST_WIDTH (0x00000710) 214 #define NVC0B5_SET_DST_WIDTH_V 31:0 215 #define NVC0B5_SET_DST_HEIGHT (0x00000714) 216 #define NVC0B5_SET_DST_HEIGHT_V 31:0 217 #define NVC0B5_SET_DST_DEPTH (0x00000718) 218 #define NVC0B5_SET_DST_DEPTH_V 31:0 219 #define NVC0B5_SET_DST_LAYER (0x0000071C) 220 #define NVC0B5_SET_DST_LAYER_V 31:0 221 #define NVC0B5_SET_DST_ORIGIN (0x00000720) 222 #define NVC0B5_SET_DST_ORIGIN_X 15:0 223 #define NVC0B5_SET_DST_ORIGIN_Y 31:16 224 #define NVC0B5_SET_SRC_BLOCK_SIZE (0x00000728) 225 #define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 226 #define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) 227 #define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 228 #define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) 229 #define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) 230 #define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) 231 #define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) 232 #define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) 233 #define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) 234 #define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 235 #define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) 236 #define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) 237 #define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) 238 #define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) 239 #define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) 240 #define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) 241 #define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 242 #define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) 243 #define NVC0B5_SET_SRC_WIDTH (0x0000072C) 244 #define NVC0B5_SET_SRC_WIDTH_V 31:0 245 #define NVC0B5_SET_SRC_HEIGHT (0x00000730) 246 #define NVC0B5_SET_SRC_HEIGHT_V 31:0 247 #define NVC0B5_SET_SRC_DEPTH (0x00000734) 248 #define NVC0B5_SET_SRC_DEPTH_V 31:0 249 #define NVC0B5_SET_SRC_LAYER (0x00000738) 250 #define NVC0B5_SET_SRC_LAYER_V 31:0 251 #define NVC0B5_SET_SRC_ORIGIN (0x0000073C) 252 #define NVC0B5_SET_SRC_ORIGIN_X 15:0 253 #define NVC0B5_SET_SRC_ORIGIN_Y 31:16 254 #define NVC0B5_PM_TRIGGER_END (0x00001114) 255 #define NVC0B5_PM_TRIGGER_END_V 31:0 256 257 #ifdef __cplusplus 258 }; /* extern "C" */ 259 #endif 260 #endif // _clc0b5_h 261 262