1 /*******************************************************************************
2 Copyright (c) 2016-2023 NVIDIA Corporation
3
4 Permission is hereby granted, free of charge, to any person obtaining a copy
5 of this software and associated documentation files (the "Software"), to
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8 sell copies of the Software, and to permit persons to whom the Software is
9 furnished to do so, subject to the following conditions:
10
11 The above copyright notice and this permission notice shall be
12 included in all copies or substantial portions of the Software.
13
14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 *******************************************************************************/
23
24 #include "uvm_hal.h"
25 #include "uvm_gpu.h"
26 #include "uvm_mem.h"
27 #include "uvm_volta_fault_buffer.h"
28
uvm_hal_volta_arch_init_properties(uvm_parent_gpu_t * parent_gpu)29 void uvm_hal_volta_arch_init_properties(uvm_parent_gpu_t *parent_gpu)
30 {
31 parent_gpu->tlb_batch.va_invalidate_supported = true;
32
33 parent_gpu->tlb_batch.va_range_invalidate_supported = true;
34
35 // TODO: Bug 1767241: Run benchmarks to figure out a good number
36 parent_gpu->tlb_batch.max_ranges = 8;
37
38 parent_gpu->utlb_per_gpc_count = uvm_volta_get_utlbs_per_gpc(parent_gpu);
39
40 parent_gpu->fault_buffer_info.replayable.utlb_count = parent_gpu->rm_info.gpcCount * parent_gpu->utlb_per_gpc_count;
41 {
42 uvm_fault_buffer_entry_t *dummy;
43 UVM_ASSERT(parent_gpu->fault_buffer_info.replayable.utlb_count <= (1 << (sizeof(dummy->fault_source.utlb_id) * 8)));
44 }
45
46 // A single top level PDE on Volta covers 128 TB and that's the minimum
47 // size that can be used.
48 parent_gpu->rm_va_base = 0;
49 parent_gpu->rm_va_size = 128 * UVM_SIZE_1TB;
50
51 parent_gpu->uvm_mem_va_base = 384 * UVM_SIZE_1TB;
52 parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE;
53
54 parent_gpu->ce_phys_vidmem_write_supported = true;
55
56 parent_gpu->peer_copy_mode = UVM_GPU_PEER_COPY_MODE_VIRTUAL;
57
58 // Not all units on Volta support 49-bit addressing, including those which
59 // access channel buffers.
60 parent_gpu->max_channel_va = 1ULL << 40;
61
62 parent_gpu->max_host_va = 1ULL << 40;
63
64 // Volta can map sysmem with any page size
65 parent_gpu->can_map_sysmem_with_large_pages = true;
66
67 // Prefetch instructions will generate faults
68 parent_gpu->prefetch_fault_supported = true;
69
70 // Pascal and Volta require post-invalidate membars to flush out HSHUB. See
71 // bug 1975028. All GV100-class chips supported by UVM have HSHUB.
72 UVM_ASSERT(parent_gpu->rm_info.gpuArch == NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GV100);
73 parent_gpu->num_hshub_tlb_invalidate_membars = 2;
74
75 // Volta can place GPFIFO in vidmem
76 parent_gpu->gpfifo_in_vidmem_supported = true;
77
78 parent_gpu->replayable_faults_supported = true;
79
80 parent_gpu->non_replayable_faults_supported = true;
81
82 parent_gpu->access_counters_supported = true;
83
84 parent_gpu->access_counters_can_use_physical_addresses = true;
85
86 parent_gpu->fault_cancel_va_supported = true;
87
88 parent_gpu->scoped_atomics_supported = true;
89
90 // SW method is not currently supported on Volta.
91 // See Bug 3254782: [RM] Support clear_faulted SW method on Volta and Turing
92 parent_gpu->has_clear_faulted_channel_sw_method = false;
93
94 parent_gpu->has_clear_faulted_channel_method = true;
95
96 parent_gpu->sparse_mappings_supported = true;
97
98 parent_gpu->map_remap_larger_page_promotion = false;
99
100 parent_gpu->smc.supported = false;
101
102 parent_gpu->plc_supported = false;
103
104 parent_gpu->no_ats_range_required = false;
105 }
106