1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __gh100_dev_fsp_pri_h__ 24 #define __gh100_dev_fsp_pri_h__ 25 26 #define NV_PFSP_EMEMC(i) (0x008F2ac0+(i)*8) /* RW-4A */ 27 #define NV_PFSP_EMEMC__SIZE_1 8 /* */ 28 #define NV_PFSP_EMEMC_OFFS 7:2 /* RWIVF */ 29 #define NV_PFSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */ 30 #define NV_PFSP_EMEMC_BLK 15:8 /* RWIVF */ 31 #define NV_PFSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */ 32 #define NV_PFSP_EMEMC_AINCW 24:24 /* RWIVF */ 33 #define NV_PFSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */ 34 #define NV_PFSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */ 35 #define NV_PFSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */ 36 #define NV_PFSP_EMEMC_AINCR 25:25 /* RWIVF */ 37 #define NV_PFSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */ 38 #define NV_PFSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */ 39 #define NV_PFSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */ 40 #define NV_PFSP_EMEMD(i) (0x008F2ac4+(i)*8) /* RW-4A */ 41 #define NV_PFSP_EMEMD__SIZE_1 8 /* */ 42 #define NV_PFSP_EMEMD_DATA 31:0 /* RWXVF */ 43 44 #define NV_PFSP_MSGQ_HEAD(i) (0x008F2c80+(i)*8) /* RW-4A */ 45 #define NV_PFSP_MSGQ_HEAD__SIZE_1 8 /* */ 46 #define NV_PFSP_MSGQ_HEAD_VAL 31:0 /* RWIUF */ 47 #define NV_PFSP_MSGQ_HEAD_VAL_INIT 0x00000000 /* RWI-V */ 48 #define NV_PFSP_MSGQ_TAIL(i) (0x008F2c84+(i)*8) /* RW-4A */ 49 #define NV_PFSP_MSGQ_TAIL__SIZE_1 8 /* */ 50 #define NV_PFSP_MSGQ_TAIL_VAL 31:0 /* RWIUF */ 51 #define NV_PFSP_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */ 52 53 #define NV_PFSP_QUEUE_HEAD(i) (0x008F2c00+(i)*8) /* RW-4A */ 54 #define NV_PFSP_QUEUE_HEAD__SIZE_1 8 /* */ 55 #define NV_PFSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */ 56 #define NV_PFSP_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */ 57 #define NV_PFSP_QUEUE_TAIL(i) (0x008F2c04+(i)*8) /* RW-4A */ 58 #define NV_PFSP_QUEUE_TAIL__SIZE_1 8 /* */ 59 #define NV_PFSP_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */ 60 #define NV_PFSP_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */ 61 62 #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x008f0320+(i)*4) /* RW-4A */ 63 #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ 64 #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */ 65 #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ 66 #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ 67 #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x008f0330+(i)*4) /* RW-4A */ 68 #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ 69 #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ 70 #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ 71 72 #endif // __gh100_dev_fsp_pri_h__ 73