1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __gh100_dev_xtl_ep_pcfg_gpu_h__ 25 #define __gh100_dev_xtl_ep_pcfg_gpu_h__ 26 #define NV_EP_PCFG_GPU_ID 0x00000000 /* R--4R */ 27 #define NV_EP_PCFG_GPU_ID_VENDOR 15:0 /* R-EVF */ 28 #define NV_EP_PCFG_GPU_ID_VENDOR_NVIDIA 0x000010DE /* R-E-V */ 29 #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */ 30 #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE 0:0 /* RWIVF */ 31 #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE 0x00000001 /* RW--V */ 32 #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE 1:1 /* RWIVF */ 33 #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE_DEFAULT 0x00000000 /* RWI-V */ 34 #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE_ENABLE 0x00000001 /* RW--V */ 35 #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER 2:2 /* RWIVF */ 36 #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER_DISABLE 0x00000000 /* RWI-V */ 37 #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER_ENABLE 0x00000001 /* RW--V */ 38 #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE 0x00000008 /* R--4R */ 39 #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_PGM_INTERFACE 15:8 /* R-IVF */ 40 #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_SUB_CLASSCODE 23:16 /* R-IVF */ 41 #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE 31:24 /* R-IVF */ 42 #define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE_3D 0x00000003 /* R-I-V */ 43 #define NV_EP_PCFG_GPU_BARREG0 0x00000010 /* RW-4R */ 44 #define NV_EP_PCFG_GPU_BARREG0_REG_ADDR_TYPE 2:1 /* R-IVF */ 45 #define NV_EP_PCFG_GPU_BARREG0_REG_ADDR_TYPE_32BIT 0x00000000 /* R-I-V */ 46 #define NV_EP_PCFG_GPU_BARREG0_REG_ADDR_TYPE_64BIT 0x00000002 /* R---V */ 47 #define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS 31:18 /* RWIVF */ 48 #define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ 49 #define NV_EP_PCFG_GPU_BARREG5 0x00000024 /* RW-4R */ 50 #define NV_EP_PCFG_GPU_SUBSYSTEM_ID 0x0000002C /* R--4R */ 51 #define NV_EP_PCFG_GPU_MSI_64_HEADER 0x00000048 /* RW-4R */ 52 #define NV_EP_PCFG_GPU_MSI_64_HEADER_MSI_ENABLE 16:16 /* RWIVF */ 53 #define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES 0x00000064 /* R--4R */ 54 #define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED 5:5 /* R-IVF */ 55 #define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY 28:28 /* R-IVF */ 56 #define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY_NOT_SUPPORTED 0x00000000 /* R-I-V */ 57 #define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY_SUPPORTED 0x00000001 /* R---V */ 58 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS 0x00000068 /* RW-4R */ 59 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */ 60 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT 0x00000001 /* RWI-V */ 61 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */ 62 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000001 /* RWI-V */ 63 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */ 64 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST 15:15 /* RWIVF */ 65 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED 16:16 /* RWIVF */ 66 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */ 67 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */ 68 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED 19:19 /* RWIVF */ 69 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */ 70 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2 0x00000088 /* RW-4R */ 71 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE 6:6 /* RWIVF */ 72 #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE_DEFAULT 0x00000000 /* RWI-V */ 73 #define NV_EP_PCFG_GPU_LINK_CAPABILITIES 0x0000006C /* R--4R */ 74 #define NV_EP_PCFG_GPU_LINK_CONTROL_STATUS 0x00000070 /* RW-4R */ 75 #define NV_EP_PCFG_GPU_LINK_CONTROL_STATUS_CURRENT_LINK_SPEED 19:16 /* R-EVF */ 76 #define NV_EP_PCFG_GPU_MSIX_CAP_HEADER 0x000000B0 /* RW-4R */ 77 #define NV_EP_PCFG_GPU_MSIX_CAP_HEADER_ENABLE 31:31 /* RWIVF */ 78 #define NV_EP_PCFG_GPU_MSIX_CAP_HEADER_ENABLE_ENABLED 0x00000001 /* RW--V */ 79 #define NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL 0x0000013C /* RW-4R */ 80 #define NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL_BAR_SIZE 13:8 /* RWIVF */ 81 #define NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL_BAR_SIZE_MIN 0x00000006 /* RW--V */ 82 #define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS 0x000001BC /* RW-4R */ 83 #define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_DL_PROTOCOL_ERROR 4:4 /* RWCVF */ 84 #define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_RCVD 12:12 /* RWCVF */ 85 #define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT 14:14 /* RWCVF */ 86 #define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION 16:16 /* RWCVF */ 87 #define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP 18:18 /* RWCVF */ 88 #define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR 20:20 /* RWCVF */ 89 #define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS 0x000001C8 /* RW-4R */ 90 #define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR 0:0 /* RWCVF */ 91 #define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_BAD_TLP 6:6 /* RWCVF */ 92 #define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_BAD_DLLP 7:7 /* RWCVF */ 93 #define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER 8:8 /* RWCVF */ 94 #define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT 12:12 /* RWCVF */ 95 #define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR 13:13 /* RWCVF */ 96 #define NV_EP_PCFG_GPU_SRIOV_INIT_TOT_VF 0x0000025C /* R--4R */ 97 #define NV_EP_PCFG_GPU_SRIOV_INIT_TOT_VF_TOTAL_VFS 31:16 /* R-EVF */ 98 #define NV_EP_PCFG_GPU_SRIOV_FIRST_VF_STRIDE 0x00000264 /* R--4R */ 99 #define NV_EP_PCFG_GPU_SRIOV_FIRST_VF_STRIDE_FIRST_VF_OFFSET 15:0 /* R-IVF */ 100 #define NV_EP_PCFG_GPU_VF_BAR0 0x00000274 /* RW-4R */ 101 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC 0x000002B4 /* R--4R */ 102 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FUSE_POD 0:0 /* R-CVF */ 103 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FUSE_SCPM 1:1 /* R-CVF */ 104 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FSP_SCPM 2:2 /* R-CVF */ 105 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_SEC2_SCPM 3:3 /* R-CVF */ 106 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FSP_DCLS 4:4 /* R-CVF */ 107 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_SEC2_DCLS 5:5 /* R-CVF */ 108 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_GSP_DCLS 6:6 /* R-CVF */ 109 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_PMU_DCLS 7:7 /* R-CVF */ 110 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_SEQ_TOO_BIG 8:8 /* R-CVF */ 111 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_PRE_IFF_CRC 9:9 /* R-CVF */ 112 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_POST_IFF_CRC 10:10 /* R-CVF */ 113 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ECC 11:11 /* R-CVF */ 114 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_CMD 12:12 /* R-CVF */ 115 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_PRI 13:13 /* R-CVF */ 116 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_WDG 14:14 /* R-CVF */ 117 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_BOOTFSM 15:15 /* R-CVF */ 118 #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */ 119 #define NV_EP_PCFG_GPU_L1_PM_SS_CONTROL_1_REGISTER 0x00000298 /* RW-4R */ 120 #endif // __gh100_dev_xtl_ep_pcfg_gpu_h__ 121