1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __dev_nv_pcfg_xve_addendum_h__ 25 #define __dev_nv_pcfg_xve_addendum_h__ 26 27 #define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000 28 29 /* 30 * <prefix>_MAP has 1 bit set for each dword register. 31 * <prefix>_COUNT has total number of set bits in <prefix>_MAP. 32 */ 33 #define NV_PCFG_XVE_REGISTER_VALID_COUNT 242 34 #define NV_PCFG_XVE_REGISTER_VALID_MAP { \ 35 /* 0x00088000 */ 0xFFF1FFFF, 0x1003FF9F, \ 36 /* 0x00088100 */ 0x1FBA3C7F, 0x00000000, \ 37 /* 0x00088200 */ 0x03F00000, 0x00000000, \ 38 /* 0x00088300 */ 0x00000000, 0x00000000, \ 39 /* 0x00088400 */ 0x8007FFC0, 0x3F1F5807, \ 40 /* 0x00088500 */ 0x000000BF, 0x00000000, \ 41 /* 0x00088600 */ 0x0140AA1F, 0x00000000, \ 42 /* 0x00088700 */ 0x00000FFF, 0x00000000, \ 43 /* 0x00088800 */ 0xFFEFDF97, 0x02DAEDFF, \ 44 /* 0x00088900 */ 0xFFFFFFFF, 0x0000000F, \ 45 /* 0x00088A00 */ 0x077FFFFB } 46 47 #define NV_PCFG_XVE_REGISTER_WR_COUNT 166 48 #define NV_PCFG_XVE_REGISTER_WR_MAP { \ 49 /* 0x00088000 */ 0x3EF193FA, 0x1003C515, \ 50 /* 0x00088100 */ 0x1FBA0828, 0x00000000, \ 51 /* 0x00088200 */ 0x03200000, 0x00000000, \ 52 /* 0x00088300 */ 0x00000000, 0x00000000, \ 53 /* 0x00088400 */ 0x80007EC0, 0x3F075007, \ 54 /* 0x00088500 */ 0x000000BF, 0x00000000, \ 55 /* 0x00088600 */ 0x0140AA10, 0x00000000, \ 56 /* 0x00088700 */ 0x00000FFF, 0x00000000, \ 57 /* 0x00088800 */ 0x00445F83, 0x005AEDC0, \ 58 /* 0x00088900 */ 0xFFFC7806, 0x0000000F, \ 59 /* 0x00088A00 */ 0x077FFDFB } 60 61 #endif // {__dev_nv_pcfg_xve_addendum_h__} 62