1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _SOECORE_H_ 25 #define _SOECORE_H_ 26 27 /*! 28 * @file soeifutil.h 29 * @brief SOE CORE Command Queue 30 * 31 * The CORE unit ID will be used for sending and recieving 32 * Command Messages between driver and CORE unit of SOE 33 */ 34 35 /*! 36 * Commands offered by the SOE utility Interface. 37 */ 38 enum 39 { 40 /*! 41 * Read the BIOS Size 42 */ 43 RM_SOE_CORE_CMD_READ_BIOS_SIZE, 44 45 /*! 46 * Read the BIOS 47 */ 48 RM_SOE_CORE_CMD_READ_BIOS, 49 50 /*! 51 * Run DMA self-test 52 */ 53 RM_SOE_CORE_CMD_DMA_SELFTEST, 54 55 /*! 56 * Perform I2C transaction 57 */ 58 RM_SOE_CORE_CMD_I2C_ACCESS, 59 60 /*! 61 * Issue NPORT Reset 62 */ 63 RM_SOE_CORE_CMD_ISSUE_NPORT_RESET, 64 65 /*! 66 * Restore NPORT state 67 */ 68 RM_SOE_CORE_CMD_RESTORE_NPORT_STATE, 69 70 /*! 71 * Set NPORT TPROD state 72 */ 73 RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE, 74 75 /*! 76 * Read VRs 77 * Needed to be in sync with chips_a defines 78 */ 79 RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES, 80 81 /*! 82 * Init PLM2 protected registers 83 */ 84 RM_SOE_CORE_CMD_INIT_L2_STATE 85 }; 86 87 // Timeout for SOE reset callback function 88 #define SOE_UNLOAD_CALLBACK_TIMEOUT_US 10000 // 10ms 89 90 #define SOE_DMA_TEST_BUF_SIZE 512 91 92 #define SOE_DMA_TEST_INIT_PATTERN 0xab 93 #define SOE_DMA_TEST_XFER_PATTERN 0xcd 94 95 #define RM_SOE_DMA_READ_TEST_SUBCMD 0x00 96 #define RM_SOE_DMA_WRITE_TEST_SUBCMD 0x01 97 98 #define SOE_I2C_DMA_BUF_SIZE 512 99 #define SOE_I2C_STATUS_INDEX (SOE_I2C_DMA_BUF_SIZE - 1) 100 101 /*! 102 * CORE queue command payload 103 */ 104 typedef struct 105 { 106 NvU8 cmdType; 107 RM_FLCN_U64 dmaHandle; 108 NvU32 offset; 109 NvU32 sizeInBytes; 110 } RM_SOE_CORE_CMD_BIOS; 111 112 typedef struct 113 { 114 NvU8 cmdType; 115 NvU8 subCmdType; 116 RM_FLCN_U64 dmaHandle; 117 NvU8 dataPattern; 118 NvU16 xferSize; 119 } RM_SOE_CORE_CMD_DMA_TEST; 120 121 typedef struct 122 { 123 NvU8 cmdType; 124 RM_FLCN_U64 dmaHandle; 125 NvU16 xferSize; 126 } RM_SOE_CORE_CMD_I2C; 127 128 typedef struct 129 { 130 NvU8 cmdType; 131 NvU32 nport; 132 } RM_SOE_CORE_CMD_NPORT_RESET; 133 134 typedef struct 135 { 136 NvU8 cmdType; 137 NvU32 nport; 138 } RM_SOE_CORE_CMD_NPORT_STATE; 139 140 typedef struct 141 { 142 NvU8 cmdType; 143 NvU32 nport; 144 } RM_SOE_CORE_CMD_NPORT_TPROD_STATE; 145 146 typedef struct 147 { 148 NvU8 cmdType; 149 } RM_SOE_CORE_CMD_L2_STATE; 150 151 typedef union 152 { 153 NvU8 cmdType; 154 RM_SOE_CORE_CMD_BIOS bios; 155 RM_SOE_CORE_CMD_DMA_TEST dma_test; 156 RM_SOE_CORE_CMD_I2C i2c; 157 RM_SOE_CORE_CMD_NPORT_RESET nportReset; 158 RM_SOE_CORE_CMD_NPORT_STATE nportState; 159 RM_SOE_CORE_CMD_NPORT_TPROD_STATE nportTprodState; 160 RM_SOE_CORE_CMD_L2_STATE l2State; 161 } RM_SOE_CORE_CMD; 162 #endif // _SOECORE_H_ 163