1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /* 25 * This file defines CTRL calls that are device specifics. 26 * 27 * This is a platform agnostic file and lists the CTRL calls used by all the 28 * clients, Fabric Manager, MODS or NVSwitch GTEST etc. 29 * 30 * As Fabric Manager relies on driver ABI compatibility the CTRL calls listed in 31 * this file contribute to the driver ABI version. 32 * 33 * Note: ctrl_dev_nvswitch.h and ctrl_dev_internal_nvswitch.h do not share any 34 * data. This helps to keep the driver ABI stable. 35 */ 36 37 #ifndef _CTRL_DEVICE_NVSWITCH_H_ 38 #define _CTRL_DEVICE_NVSWITCH_H_ 39 40 #ifdef __cplusplus 41 extern "C" 42 { 43 #endif 44 45 46 #include "nvtypes.h" 47 #include "nvfixedtypes.h" 48 #include "nvmisc.h" 49 #include "ioctl_common_nvswitch.h" 50 51 /* 52 * CTRL_NVSWITCH_GET_INFO 53 * 54 * Control for querying miscellaneous device information. 55 * 56 * This provides a single API to query for multiple pieces of miscellaneous 57 * information via a single call. 58 * 59 * Parameters: 60 * count [IN] 61 * Count of queries. Max supported queries per-call are 62 * NVSWITCH_GET_INFO_COUNT_MAX 63 * index [IN] 64 * One of the NVSWITCH_GET_INFO_INDEX type value. 65 * 66 * info [OUT] 67 * Data pertaining to the provided NVSWITCH_GET_INFO_INDEX type value. 68 */ 69 70 #define NVSWITCH_GET_INFO_COUNT_MAX 32 71 72 typedef enum nvswitch_get_info_index 73 { 74 NVSWITCH_GET_INFO_INDEX_ARCH = 0x0, 75 NVSWITCH_GET_INFO_INDEX_IMPL, 76 NVSWITCH_GET_INFO_INDEX_CHIPID, 77 NVSWITCH_GET_INFO_INDEX_REVISION_MAJOR, 78 NVSWITCH_GET_INFO_INDEX_REVISION_MINOR, 79 NVSWITCH_GET_INFO_INDEX_REVISION_MINOR_EXT, 80 NVSWITCH_GET_INFO_INDEX_PLATFORM, 81 NVSWITCH_GET_INFO_INDEX_DEVICE_ID, 82 83 NVSWITCH_GET_INFO_INDEX_NUM_PORTS = 0x100, 84 NVSWITCH_GET_INFO_INDEX_ENABLED_PORTS_MASK_31_0, 85 NVSWITCH_GET_INFO_INDEX_ENABLED_PORTS_MASK_63_32, 86 NVSWITCH_GET_INFO_INDEX_NUM_VCS, 87 NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_TABLE_SIZE, 88 NVSWITCH_GET_INFO_INDEX_ROUTING_ID_TABLE_SIZE, 89 NVSWITCH_GET_INFO_INDEX_ROUTING_LAN_TABLE_SIZE, 90 NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTA_TABLE_SIZE, 91 NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTB_TABLE_SIZE, 92 NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_MULTICAST_TABLE_SIZE, 93 94 NVSWITCH_GET_INFO_INDEX_FREQ_KHZ = 0x200, 95 NVSWITCH_GET_INFO_INDEX_VCOFREQ_KHZ, 96 NVSWITCH_GET_INFO_INDEX_VOLTAGE_MVOLT, 97 NVSWITCH_GET_INFO_INDEX_PHYSICAL_ID, 98 99 NVSWITCH_GET_INFO_INDEX_PCI_DOMAIN = 0x300, 100 NVSWITCH_GET_INFO_INDEX_PCI_BUS, 101 NVSWITCH_GET_INFO_INDEX_PCI_DEVICE, 102 NVSWITCH_GET_INFO_INDEX_PCI_FUNCTION, 103 /* See enum modification guidelines at the top of this file */ 104 } NVSWITCH_GET_INFO_INDEX; 105 106 #define NVSWITCH_GET_INFO_INDEX_ARCH_LR10 0x02 107 #define NVSWITCH_GET_INFO_INDEX_IMPL_LR10 0x01 108 109 #define NVSWITCH_GET_INFO_INDEX_ARCH_LS10 0x03 110 #define NVSWITCH_GET_INFO_INDEX_IMPL_LS10 0x01 111 112 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_UNKNOWN 0x00 113 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_RTLSIM 0x01 114 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_FMODEL 0x02 115 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_EMULATION 0x03 116 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_SILICON 0x04 117 118 typedef struct nvswitch_get_info 119 { 120 NvU32 count; 121 NvU32 index[NVSWITCH_GET_INFO_COUNT_MAX]; 122 NvU32 info[NVSWITCH_GET_INFO_COUNT_MAX]; 123 124 } NVSWITCH_GET_INFO; 125 126 /* 127 * CTRL_NVSWITCH_SET_INGRESS_REQUEST_TABLE 128 * 129 * Control for programming ingress request tables. 130 * This interface is only supported on SV10 architecture. All others will 131 * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 132 * 133 * Parameters: 134 * portNum [IN] 135 * A valid port number present in the port masks returned by 136 * NVSWITCH_GET_INFO 137 * firstIndex [IN] 138 * A starting index of the ingress request table from which table entries 139 * should be programmed. 140 * numEntries [IN] 141 * Number of entries to be programmed. Currently, the call supports 142 * programming NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX at a time. 143 * entries [IN] 144 * The entries (entry format is architecture dependent). 145 */ 146 147 #define NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX 256 148 149 /* TODO: document the entry format in detail */ 150 typedef struct nvswitch_ingress_request_entry 151 { 152 NvU32 vcModeValid7_0; 153 NvU32 vcModeValid15_8; 154 NvU32 vcModeValid17_16; 155 NvU32 mappedAddress; 156 NvU32 routePolicy; 157 NvBool entryValid; 158 159 } NVSWITCH_INGRESS_REQUEST_ENTRY; 160 161 typedef struct nvswitch_set_ingress_request_table 162 { 163 NvU32 portNum; 164 NvU32 firstIndex; 165 NvU32 numEntries; 166 NVSWITCH_INGRESS_REQUEST_ENTRY entries[NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX]; 167 168 } NVSWITCH_SET_INGRESS_REQUEST_TABLE; 169 170 /* 171 * CTRL_NVSWITCH_GET_INGRESS_REQUEST_TABLE 172 * 173 * Control for reading ingress request tables. A sparse list of nonzero entries 174 * and their table indices is returned. 175 * 176 * Parameters: 177 * portNum [IN] 178 * A valid port number present in the port masks returned by 179 * NVSWITCH_GET_INFO 180 * firstIndex [IN] 181 * A starting index of the ingress request table from which table entries 182 * should be read. 183 * nextIndex [OUT] 184 * The table index of the next entry to read. Set to INGRESS_MAP_TABLE_SIZE 185 * when the end of the table has been reached. 186 * numEntries [OUT] 187 * Number of entries returned. Currently, the call supports returning up to 188 * NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX entries at a time. 189 * entries [OUT] 190 * Ingress request entries along with their table indices. 191 * Entry format is architecture dependent. 192 */ 193 194 typedef struct nvswitch_ingress_request_idx_entry 195 { 196 NvU32 idx; 197 NVSWITCH_INGRESS_REQUEST_ENTRY entry; 198 199 } NVSWITCH_INGRESS_REQUEST_IDX_ENTRY; 200 201 typedef struct nvswitch_get_ingress_request_table_params 202 { 203 NvU32 portNum; 204 NvU32 firstIndex; 205 NvU32 nextIndex; 206 NvU32 numEntries; 207 NVSWITCH_INGRESS_REQUEST_IDX_ENTRY entries[NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX]; 208 209 } NVSWITCH_GET_INGRESS_REQUEST_TABLE_PARAMS; 210 211 /* 212 * CTRL_NVSWITCH_SET_INGRESS_REQUEST_VALID 213 * 214 * Control for toggling the existing ingress request table entries' validity. 215 * This interface is only supported on SV10 architecture. All others will 216 * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 217 * 218 * Parameters: 219 * portNum [IN] 220 * A valid port number present in the port masks returned by 221 * NVSWITCH_GET_INFO 222 * firstIndex [IN] 223 * A starting index of the ingress request table from which table entries 224 * should be programmed. 225 * numEntries [IN] 226 * Number of entries to be programmed. Currently, the call supports 227 * programming NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX at a time. 228 * entryValid [IN] 229 * If true, an existing entry is marked valid, else will be marked invalid. 230 */ 231 232 typedef struct nvswitch_set_ingress_request_valid 233 { 234 NvU32 portNum; 235 NvU32 firstIndex; 236 NvU32 numEntries; 237 NvBool entryValid[NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX]; 238 239 } NVSWITCH_SET_INGRESS_REQUEST_VALID; 240 241 /* 242 * CTRL_NVSWITCH_SET_INGRESS_RESPONSE_TABLE 243 * 244 * Control for programming ingress response tables. 245 * This interface is only supported on SV10 architecture. All others will 246 * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 247 * 248 * Parameters: 249 * portNum [IN] 250 * A valid port number present in the port masks returned by 251 * NVSWITCH_GET_INFO 252 * firstIndex [IN] 253 * A starting index of the ingress request table from which table entries 254 * should be programmed. 255 * numEntries [IN] 256 * Number of entries to be programmed. Currently, the call supports 257 * programming NVSWITCH_INGRESS_REQUEST_ENTRIES_MAX at a time. 258 * entries [IN] 259 * The entries (entry format is architecture dependent). 260 */ 261 262 #define NVSWITCH_INGRESS_RESPONSE_ENTRIES_MAX 256 263 264 /* TODO: document the entry format in detail */ 265 typedef struct nvswitch_ingress_response_entry 266 { 267 NvU32 vcModeValid7_0; 268 NvU32 vcModeValid15_8; 269 NvU32 vcModeValid17_16; 270 NvU32 routePolicy; 271 NvBool entryValid; 272 273 } NVSWITCH_INGRESS_RESPONSE_ENTRY; 274 275 typedef struct nvswitch_set_ingress_response_table 276 { 277 NvU32 portNum; 278 NvU32 firstIndex; 279 NvU32 numEntries; 280 NVSWITCH_INGRESS_RESPONSE_ENTRY entries[NVSWITCH_INGRESS_RESPONSE_ENTRIES_MAX]; 281 282 } NVSWITCH_SET_INGRESS_RESPONSE_TABLE; 283 284 /* 285 * CTRL_NVSWITCH_SET_REMAP_POLICY 286 * 287 * Control to load remap policy table 288 * This interface is not supported on SV10 architecture. SV10 will return an 289 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 290 * 291 * Parameters: 292 * portNum [IN] 293 * A valid port number present in the port masks returned by 294 * NVSWITCH_GET_INFO 295 * tableSelect [IN] 296 * Remap table selector 297 * firstIndex [IN] 298 * A starting index of the remap table from which table entries 299 * should be programmed. Valid range should be queried using 300 * NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_TABLE_SIZE. 301 * numEntries [IN] 302 * Number of entries to be programmed. Currently, the call supports 303 * programming NVSWITCH_REMAP_POLICY_ENTRIES_MAX at a time. 304 * remapPolicy [IN] 305 * The entries (see NVSWITCH_REMAP_POLICY_ENTRY). 306 */ 307 308 #define NVSWITCH_REMAP_POLICY_ENTRIES_MAX 64 309 310 #define NVSWITCH_REMAP_POLICY_FLAGS_REMAP_ADDR NVBIT(0) 311 #define NVSWITCH_REMAP_POLICY_FLAGS_REQCTXT_CHECK NVBIT(1) 312 #define NVSWITCH_REMAP_POLICY_FLAGS_REQCTXT_REPLACE NVBIT(2) 313 #define NVSWITCH_REMAP_POLICY_FLAGS_ADR_BASE NVBIT(4) 314 #define NVSWITCH_REMAP_POLICY_FLAGS_ADR_OFFSET NVBIT(5) /* Apply address offset */ 315 #define NVSWITCH_REMAP_POLICY_FLAGS_REFLECTIVE NVBIT(30) /* Reflective mapping */ 316 #define NVSWITCH_REMAP_POLICY_FLAGS_ADDR_TYPE NVBIT(31) /* Enforce address type checking */ 317 318 typedef struct nvswitch_remap_policy_entry 319 { 320 NvBool entryValid; 321 NvU32 targetId; /* Unique endpoint ID */ 322 323 NvU32 irlSelect; /* Injection rate limiter (0=none/1=IRL1/2=IRL2) */ 324 325 NvU32 flags; /* See NVSWITCH_REMAP_POLICY_FLAGS_* */ 326 327 NV_DECLARE_ALIGNED(NvU64 address, 8); /* 47-bit remap address. Bits 46:36 are used. */ 328 329 /* reqContext fields are used when */ 330 /* routing function _REQCTXT_CHECK or _REPLACE */ 331 /* is set. */ 332 NvU32 reqCtxMask; /* Used to mask packet request ctxt before */ 333 /* checking. */ 334 335 NvU32 reqCtxChk; /* Post-mask packet request ctxt check value. */ 336 /* Packets that fail compare are converted to */ 337 /* UR response and looped back. */ 338 339 NvU32 reqCtxRep; /* Replaces packet request context when */ 340 /* _REQCTXT_REPLACE is set. */ 341 342 NV_DECLARE_ALIGNED(NvU64 addressOffset, 8); /* offset - base is added to packet address if */ 343 /* routing function _ADR_OFFSET & _ADR_BASE are */ 344 /* set. 64GB offset 1MB aligned on LR10. */ 345 346 NV_DECLARE_ALIGNED(NvU64 addressBase, 8); /* If routing function _ADR_BASE is set, limits */ 347 NV_DECLARE_ALIGNED(NvU64 addressLimit, 8); /* application of _ADR_OFFSET to packet */ 348 /* addresses that pass base/limit bounds check. */ 349 /* Maximum 64GB size 1MB aligned on LR10. */ 350 351 352 } NVSWITCH_REMAP_POLICY_ENTRY; 353 354 typedef enum nvswitch_table_select_remap 355 { 356 NVSWITCH_TABLE_SELECT_REMAP_PRIMARY = 0, 357 NVSWITCH_TABLE_SELECT_REMAP_EXTA, 358 NVSWITCH_TABLE_SELECT_REMAP_EXTB, 359 NVSWITCH_TABLE_SELECT_REMAP_MULTICAST, 360 NVSWITCH_TABLE_SELECT_REMAP_MAX 361 } NVSWITCH_TABLE_SELECT_REMAP; 362 363 typedef struct nvswitch_set_remap_policy 364 { 365 NvU32 portNum; 366 NVSWITCH_TABLE_SELECT_REMAP tableSelect; 367 NvU32 firstIndex; 368 NvU32 numEntries; 369 NVSWITCH_REMAP_POLICY_ENTRY remapPolicy[NVSWITCH_REMAP_POLICY_ENTRIES_MAX]; 370 371 } NVSWITCH_SET_REMAP_POLICY; 372 373 /* 374 * CTRL_NVSWITCH_GET_REMAP_POLICY 375 * 376 * Control to get remap policy table 377 * This interface is not supported on SV10 architecture. SV10 will return unsupported 378 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 379 * 380 * Parameters: 381 * portNum [IN] 382 * A valid port number present in the port masks returned by 383 * NVSWITCH_GET_INFO 384 * tableSelect [IN] 385 * Remap table selector 386 * firstIndex [IN] 387 * A starting index of the remap policy table from which table entries 388 * should be read. 389 * numEntries [OUT] 390 * Number of entries returned. This call returns 391 * NVSWITCH_REMAP_POLICY_ENTRIES_MAX entries at a time. 392 * nextIndex [OUT] 393 * The table index of the next entry to read. Set to INGRESS_REMAPTAB_SIZE 394 * when the end of the table has been reached. 395 * entries [OUT] 396 * The entries (see NVSWITCH_REMAP_POLICY_ENTRY). 397 */ 398 399 400 typedef struct nvswitch_get_remap_policy_params 401 { 402 NvU32 portNum; 403 NVSWITCH_TABLE_SELECT_REMAP tableSelect; 404 NvU32 firstIndex; 405 NvU32 numEntries; 406 NvU32 nextIndex; 407 NVSWITCH_REMAP_POLICY_ENTRY entry[NVSWITCH_REMAP_POLICY_ENTRIES_MAX]; 408 409 } NVSWITCH_GET_REMAP_POLICY_PARAMS; 410 411 /* 412 * CTRL_NVSWITCH_SET_REMAP_POLICY_VALID 413 * 414 * Control to set remap policy tables valid/invalid 415 * This interface is not supported on SV10 architecture. SV10 will return unsupported 416 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 417 * 418 * Parameters: 419 * portNum [IN] 420 * A valid port number present in the port masks returned by 421 * NVSWITCH_GET_INFO 422 * tableSelect [IN] 423 * Remap table selector 424 * firstIndex [IN] 425 * A starting index of the remap policy table from which table entries 426 * should be programmed. 427 * numEntries [IN] 428 * Number of entries to be programmed. The call supports 429 * programming of maximum NVSWITCH_REMAP_POLICY_ENTRIES_MAX at a time. 430 * entryValid [IN] 431 * If true, an existing entry is marked valid, else will be marked invalid. 432 */ 433 434 typedef struct nvswitch_set_remap_policy_valid 435 { 436 NvU32 portNum; 437 NVSWITCH_TABLE_SELECT_REMAP tableSelect; 438 NvU32 firstIndex; 439 NvU32 numEntries; 440 NvBool entryValid[NVSWITCH_REMAP_POLICY_ENTRIES_MAX]; 441 442 } NVSWITCH_SET_REMAP_POLICY_VALID; 443 444 /* 445 * CTRL_NVSWITCH_SET_ROUTING_ID 446 * 447 * Control to load Routing ID table 448 * The routing ID table configures the VC and routing policy as well as the 449 * valid set if ganged link routes. 450 * This interface is not supported on SV10 architecture. SV10 will return an 451 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 452 * 453 * Parameters: 454 * portNum [IN] 455 * A valid port number present in the port masks returned by 456 * NVSWITCH_GET_INFO 457 * firstIndex [IN] 458 * A starting index of the routing ID table from which table entries 459 * should be programmed. Valid range should be queried using 460 * NVSWITCH_GET_INFO_INDEX_ROUTING_ID_TABLE_SIZE. 461 * numEntries [IN] 462 * Number of entries to be programmed. Currently, the call supports programming 463 * maximum of NVSWITCH_ROUTING_ID_ENTRIES_MAX entries at a time. 464 * routingId [IN] 465 * The entries (see NVSWITCH_ROUTING_ID_ENTRY). 466 */ 467 468 #define NVSWITCH_ROUTING_ID_DEST_PORT_LIST_MAX 16 469 #define NVSWITCH_ROUTING_ID_VC_MODE_MAX 4 470 #define NVSWITCH_ROUTING_ID_ENTRIES_MAX 64 471 472 typedef enum nvswitch_routing_id_vcmap 473 { 474 NVSWITCH_ROUTING_ID_VCMAP_SAME = 0x0, 475 NVSWITCH_ROUTING_ID_VCMAP_INVERT, 476 NVSWITCH_ROUTING_ID_VCMAP_ZERO, 477 NVSWITCH_ROUTING_ID_VCMAP_ONE 478 /* See enum modification guidelines at the top of this file */ 479 } NVSWITCH_ROUTING_ID_VCMAP; 480 481 typedef struct nvswitch_routing_id_dest_port_list 482 { 483 NvU32 vcMap; /* NVSWITCH_ROUTING_ID_VCMAP_* */ 484 NvU32 destPortNum; 485 486 } NVSWITCH_ROUTING_ID_DEST_PORT_LIST; 487 488 typedef struct nvswitch_routing_id_entry 489 { 490 NvBool entryValid; 491 NvBool useRoutingLan; 492 NvBool enableIrlErrResponse; 493 NvU32 numEntries; 494 NVSWITCH_ROUTING_ID_DEST_PORT_LIST portList[NVSWITCH_ROUTING_ID_DEST_PORT_LIST_MAX]; 495 496 } NVSWITCH_ROUTING_ID_ENTRY; 497 498 typedef struct nvswitch_set_routing_id 499 { 500 NvU32 portNum; 501 NvU32 firstIndex; 502 NvU32 numEntries; 503 NVSWITCH_ROUTING_ID_ENTRY routingId[NVSWITCH_ROUTING_ID_ENTRIES_MAX]; 504 505 } NVSWITCH_SET_ROUTING_ID; 506 507 /* 508 * CTRL_NVSWITCH_GET_ROUTING_ID 509 * 510 * Control to get routing ID table 511 * This interface is not supported on SV10 architecture. SV10 will return unsupported 512 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 513 * 514 * Parameters: 515 * portNum [IN] 516 * A valid port number present in the port masks returned by 517 * NVSWITCH_GET_INFO 518 * firstIndex [IN] 519 * A starting index of the routing id table from which table entries 520 * should be read. 521 * numEntries [OUT] 522 * Number of entries returned. The call returns only 523 * NVSWITCH_ROUTING_ID_ENTRIES_MAX entries at a time. 524 * nextIndex [OUT] 525 * The table index of the next entry to read. Set to INGRESS_RIDTAB_SIZE 526 * when the end of the table has been reached. 527 * entries [OUT] 528 * The entries (see NVSWITCH_ROUTING_ID_IDX_ENTRY). 529 */ 530 531 typedef struct nvswitch_routing_id_idx_entry 532 { 533 NvU32 idx; 534 NVSWITCH_ROUTING_ID_ENTRY entry; 535 536 } NVSWITCH_ROUTING_ID_IDX_ENTRY; 537 538 typedef struct nvswitch_get_routing_id_params 539 { 540 NvU32 portNum; 541 NvU32 firstIndex; 542 NvU32 numEntries; 543 NvU32 nextIndex; 544 NVSWITCH_ROUTING_ID_IDX_ENTRY entries[NVSWITCH_ROUTING_ID_ENTRIES_MAX]; 545 546 } NVSWITCH_GET_ROUTING_ID_PARAMS; 547 548 /* 549 * CTRL_NVSWITCH_SET_ROUTING_ID_VALID 550 * 551 * Control to set routing ID tables valid/invalid 552 * This interface is not supported on SV10 architecture. SV10 will return unsupported 553 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 554 * 555 * Parameters: 556 * portNum [IN] 557 * A valid port number present in the port masks returned by 558 * NVSWITCH_GET_INFO 559 * firstIndex [IN] 560 * A starting index of the routing lan table from which table entries 561 * should be programmed. 562 * numEntries [IN] 563 * Number of entries to be programmed. This call supports programming 564 * maximum entries of NVSWITCH_ROUTING_ID_ENTRIES_MAX at a time. 565 * entryValid [IN] 566 * If true, an existing entry is marked valid, else will be marked invalid. 567 */ 568 569 typedef struct nvswitch_set_routing_id_valid 570 { 571 NvU32 portNum; 572 NvU32 firstIndex; 573 NvU32 numEntries; 574 NvBool entryValid[NVSWITCH_ROUTING_ID_ENTRIES_MAX]; 575 576 } NVSWITCH_SET_ROUTING_ID_VALID; 577 578 /* 579 * CTRL_NVSWITCH_SET_ROUTING_LAN 580 * 581 * Control to load routing LAN table 582 * This interface is not supported on SV10 architecture. SV10 will return an 583 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 584 * 585 * Parameters: 586 * portNum [IN] 587 * A valid port number present in the port masks returned by 588 * NVSWITCH_GET_INFO 589 * firstIndex [IN] 590 * A starting index of the ingress request table from which table entries 591 * should be programmed. Valid range should be queried using 592 * NVSWITCH_GET_INFO_INDEX_ROUTING_LAN_TABLE_SIZE. 593 * numEntries [IN] 594 * Number of entries to be programmed. Currently, the call supports 595 * programming NVSWITCH_ROUTING_LAN_ENTRIES_MAX at a time. 596 * routingLan [IN] 597 * The entries (see NVSWITCH_ROUTING_LAN_ENTRY). 598 */ 599 600 #define NVSWITCH_ROUTING_LAN_GROUP_SEL_MAX 16 601 #define NVSWITCH_ROUTING_LAN_GROUP_SIZE_MAX 16 602 #define NVSWITCH_ROUTING_LAN_ENTRIES_MAX 64 603 604 typedef struct nvswitch_routing_lan_port_select 605 { 606 NvU32 groupSelect; /* Port list group selector */ 607 NvU32 groupSize; /* Valid range: 1..16 */ 608 609 } NVSWITCH_ROUTING_LAN_PORT_SELECT; 610 611 typedef struct nvswitch_routing_lan_entry 612 { 613 NvBool entryValid; 614 NvU32 numEntries; 615 NVSWITCH_ROUTING_LAN_PORT_SELECT portList[NVSWITCH_ROUTING_LAN_GROUP_SEL_MAX]; 616 617 } NVSWITCH_ROUTING_LAN_ENTRY; 618 619 typedef struct nvswitch_set_routing_lan 620 { 621 NvU32 portNum; 622 NvU32 firstIndex; 623 NvU32 numEntries; 624 NVSWITCH_ROUTING_LAN_ENTRY routingLan[NVSWITCH_ROUTING_LAN_ENTRIES_MAX]; 625 626 } NVSWITCH_SET_ROUTING_LAN; 627 628 /* 629 * CTRL_NVSWITCH_GET_ROUTING_LAN 630 * 631 * Control to get routing LAN table 632 * This interface is not supported on SV10 architecture. SV10 will return unsupported 633 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 634 * 635 * Parameters: 636 * portNum [IN] 637 * A valid port number present in the port masks returned by 638 * NVSWITCH_GET_INFO 639 * firstIndex [IN] 640 * A starting index of the routing lan table from which table entries 641 * should be read. 642 * numEntries [OUT] 643 * Number of entries returned. Currently, the call supports 644 * NVSWITCH_ROUTING_LAN_ENTRIES_MAX at a time. 645 * nextIndex [OUT] 646 * The table index of the next entry to read. Set to INGRESS_RLANTAB_SIZE 647 * when the end of the table has been reached. 648 * entries [OUT] 649 * The entries (see NVSWITCH_ROUTING_LAN_IDX_ENTRY). 650 */ 651 652 typedef struct nvswitch_routing_lan_idx_entry 653 { 654 NvU32 idx; 655 NVSWITCH_ROUTING_LAN_ENTRY entry; 656 657 } NVSWITCH_ROUTING_LAN_IDX_ENTRY; 658 659 typedef struct nvswitch_get_routing_lan_params 660 { 661 NvU32 portNum; 662 NvU32 firstIndex; 663 NvU32 numEntries; 664 NvU32 nextIndex; 665 NVSWITCH_ROUTING_LAN_IDX_ENTRY entries[NVSWITCH_ROUTING_LAN_ENTRIES_MAX]; 666 667 } NVSWITCH_GET_ROUTING_LAN_PARAMS; 668 669 /* 670 * CTRL_NVSWITCH_SET_ROUTING_LAN_VALID 671 * 672 * Control to set routing LAN tables valid/invalid 673 * This interface is not supported on SV10 architecture. SV10 will return unsupported 674 * error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 675 * 676 * Parameters: 677 * portNum [IN] 678 * A valid port number present in the port masks returned by 679 * NVSWITCH_GET_INFO 680 * firstIndex [IN] 681 * A starting index of the routing lan table from which table entries 682 * should be programmed. 683 * numEntries [IN] 684 * Number of entries to be programmed. Currently, the call supports 685 * programming NVSWITCH_ROUTING_LAN_ENTRIES_MAX at a time. 686 * entryValid [IN] 687 * If true, an existing entry is marked valid, else will be marked invalid. 688 */ 689 690 typedef struct nvswitch_set_routing_lan_valid 691 { 692 NvU32 portNum; 693 NvU32 firstIndex; 694 NvU32 numEntries; 695 NvBool entryValid[NVSWITCH_ROUTING_LAN_ENTRIES_MAX]; 696 697 } NVSWITCH_SET_ROUTING_LAN_VALID; 698 699 /* 700 * CTRL_NVSWITCH_GET_INGRESS_RESPONSE_TABLE 701 * 702 * Control for reading ingress response tables. A sparse list of nonzero entries 703 * and their table indices is returned. 704 * 705 * Parameters: 706 * portNum [IN] 707 * A valid port number present in the port masks returned by 708 * NVSWITCH_GET_INFO 709 * firstIndex [IN] 710 * A starting index of the ingress response table from which table entries 711 * should be read. 712 * nextIndex [OUT] 713 * The table index of the next entry to read. Set to INGRESS_MAP_TABLE_SIZE 714 * when the end of the table has been reached. 715 * numEntries [OUT] 716 * Number of entries returned. Currently, the call supports returning up to 717 * NVSWITCH_INGRESS_RESPONSE_ENTRIES_MAX entries at a time. 718 * entries [OUT] 719 * Ingress response entries along with their table indices. 720 * Entry format is architecture dependent. 721 */ 722 723 typedef struct nvswitch_ingress_response_idx_entry 724 { 725 NvU32 idx; 726 NVSWITCH_INGRESS_RESPONSE_ENTRY entry; 727 728 } NVSWITCH_INGRESS_RESPONSE_IDX_ENTRY; 729 730 typedef struct nvswitch_get_ingress_response_table_params 731 { 732 NvU32 portNum; 733 NvU32 firstIndex; 734 NvU32 nextIndex; 735 NvU32 numEntries; 736 NVSWITCH_INGRESS_RESPONSE_IDX_ENTRY entries[NVSWITCH_INGRESS_RESPONSE_ENTRIES_MAX]; 737 738 } NVSWITCH_GET_INGRESS_RESPONSE_TABLE_PARAMS; 739 740 /* 741 * CTRL_NVSWITCH_GET_VOLTAGE 742 * 743 * Zero(0) indicates that a measurement is not available on the current platform. 744 * 745 */ 746 747 typedef struct 748 { 749 NvU32 vdd_mv; 750 NvU32 dvdd_mv; 751 NvU32 hvdd_mv; 752 } NVSWITCH_CTRL_GET_VOLTAGE_PARAMS; 753 754 /* 755 * CTRL_NVSWITCH_GET_ERRORS 756 * 757 * Control to query error information. 758 * 759 * Parameters: 760 * errorType [IN] 761 * Allows to query specific class of errors. See NVSWITCH_ERROR_SEVERITY_xxx. 762 * 763 * errorIndex [IN/OUT] 764 * On input: The index of the first error of the specified 'errorType' at which to start 765 * reading out of the driver. 766 * 767 * On output: The index of the first error that wasn't reported through the 'error' array 768 * in this call to CTRL_NVSWITCH_GET_ERRORS. Specific to the specified 'errorType'. 769 * 770 * nextErrorIndex[OUT] 771 * The index that will be assigned to the next error to occur for the specified 'errorType'. 772 * Users of the GET_ERRORS control call may set 'errorIndex' to this field on initialization 773 * to bypass errors that have already occurred without making multiple control calls. 774 * 775 * errorCount [OUT] 776 * Number of errors returned by the call. Currently, errorCount is limited 777 * by NVSWITCH_ERROR_COUNT_SIZE. In order to query all the errors, a 778 * client needs to keep calling the control till errorCount is zero. 779 * error [OUT] 780 * The error entires. 781 */ 782 783 typedef enum nvswitch_error_severity_type 784 { 785 NVSWITCH_ERROR_SEVERITY_NONFATAL = 0, 786 NVSWITCH_ERROR_SEVERITY_FATAL, 787 NVSWITCH_ERROR_SEVERITY_MAX 788 /* See enum modification guidelines at the top of this file */ 789 } NVSWITCH_ERROR_SEVERITY_TYPE; 790 791 typedef enum nvswitch_error_src_type 792 { 793 NVSWITCH_ERROR_SRC_NONE = 0, 794 NVSWITCH_ERROR_SRC_HW 795 /* See enum modification guidelines at the top of this file */ 796 } NVSWITCH_ERROR_SRC_TYPE; 797 798 typedef enum nvswitch_err_type 799 { 800 NVSWITCH_ERR_NO_ERROR = 0x0, 801 802 /* 803 * These error enumerations are derived from the error bits defined in each 804 * hardware manual. 805 * 806 * NVSwitch errors values should start from 10000 (decimal) to be 807 * distinguishable from GPU errors. 808 */ 809 810 /* HOST */ 811 NVSWITCH_ERR_HW_HOST = 10000, 812 NVSWITCH_ERR_HW_HOST_PRIV_ERROR = 10001, 813 NVSWITCH_ERR_HW_HOST_PRIV_TIMEOUT = 10002, 814 NVSWITCH_ERR_HW_HOST_UNHANDLED_INTERRUPT = 10003, 815 NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START = 10004, 816 NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_END = 10005, 817 NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN = 10006, 818 NVSWITCH_ERR_HW_HOST_IO_FAILURE = 10007, 819 NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE = 10008, 820 NVSWITCH_ERR_HW_HOST_LAST, 821 822 823 /* NPORT: Ingress errors */ 824 NVSWITCH_ERR_HW_NPORT_INGRESS = 11000, 825 NVSWITCH_ERR_HW_NPORT_INGRESS_CMDDECODEERR = 11001, 826 NVSWITCH_ERR_HW_NPORT_INGRESS_BDFMISMATCHERR = 11002, 827 NVSWITCH_ERR_HW_NPORT_INGRESS_BUBBLEDETECT = 11003, 828 NVSWITCH_ERR_HW_NPORT_INGRESS_ACLFAIL = 11004, 829 NVSWITCH_ERR_HW_NPORT_INGRESS_PKTPOISONSET = 11005, 830 NVSWITCH_ERR_HW_NPORT_INGRESS_ECCSOFTLIMITERR = 11006, 831 NVSWITCH_ERR_HW_NPORT_INGRESS_ECCHDRDOUBLEBITERR = 11007, 832 NVSWITCH_ERR_HW_NPORT_INGRESS_INVALIDCMD = 11008, 833 NVSWITCH_ERR_HW_NPORT_INGRESS_INVALIDVCSET = 11009, 834 NVSWITCH_ERR_HW_NPORT_INGRESS_ERRORINFO = 11010, 835 NVSWITCH_ERR_HW_NPORT_INGRESS_REQCONTEXTMISMATCHERR = 11011, 836 NVSWITCH_ERR_HW_NPORT_INGRESS_NCISOC_HDR_ECC_LIMIT_ERR = 11012, 837 NVSWITCH_ERR_HW_NPORT_INGRESS_NCISOC_HDR_ECC_DBE_ERR = 11013, 838 NVSWITCH_ERR_HW_NPORT_INGRESS_ADDRBOUNDSERR = 11014, 839 NVSWITCH_ERR_HW_NPORT_INGRESS_RIDTABCFGERR = 11015, 840 NVSWITCH_ERR_HW_NPORT_INGRESS_RLANTABCFGERR = 11016, 841 NVSWITCH_ERR_HW_NPORT_INGRESS_REMAPTAB_ECC_DBE_ERR = 11017, 842 NVSWITCH_ERR_HW_NPORT_INGRESS_RIDTAB_ECC_DBE_ERR = 11018, 843 NVSWITCH_ERR_HW_NPORT_INGRESS_RLANTAB_ECC_DBE_ERR = 11019, 844 NVSWITCH_ERR_HW_NPORT_INGRESS_NCISOC_PARITY_ERR = 11020, 845 NVSWITCH_ERR_HW_NPORT_INGRESS_REMAPTAB_ECC_LIMIT_ERR = 11021, 846 NVSWITCH_ERR_HW_NPORT_INGRESS_RIDTAB_ECC_LIMIT_ERR = 11022, 847 NVSWITCH_ERR_HW_NPORT_INGRESS_RLANTAB_ECC_LIMIT_ERR = 11023, 848 NVSWITCH_ERR_HW_NPORT_INGRESS_ADDRTYPEERR = 11024, 849 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_INDEX_ERR = 11025, 850 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_INDEX_ERR = 11026, 851 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_INDEX_ERR = 11027, 852 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_DBE_ERR = 11028, 853 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_DBE_ERR = 11029, 854 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ECC_DBE_ERR = 11030, 855 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_REQCONTEXTMISMATCHERR = 11031, 856 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_REQCONTEXTMISMATCHERR = 11032, 857 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_REQCONTEXTMISMATCHERR = 11033, 858 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ACLFAIL = 11034, 859 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ACLFAIL = 11035, 860 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ACLFAIL = 11036, 861 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRBOUNDSERR = 11037, 862 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRBOUNDSERR = 11038, 863 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ADDRBOUNDSERR = 11039, 864 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_LIMIT_ERR = 11040, 865 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_LIMIT_ERR = 11041, 866 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ECC_LIMIT_ERR = 11042, 867 NVSWITCH_ERR_HW_NPORT_INGRESS_MCCMDTOUCADDRERR = 11043, 868 NVSWITCH_ERR_HW_NPORT_INGRESS_READMCREFLECTMEMERR = 11044, 869 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRTYPEERR = 11045, 870 NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRTYPEERR = 11046, 871 NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ADDRTYPEERR = 11047, 872 NVSWITCH_ERR_HW_NPORT_INGRESS_LAST, /* NOTE: Must be last */ 873 874 /* NPORT: Egress errors */ 875 NVSWITCH_ERR_HW_NPORT_EGRESS = 12000, 876 NVSWITCH_ERR_HW_NPORT_EGRESS_EGRESSBUFERR = 12001, 877 NVSWITCH_ERR_HW_NPORT_EGRESS_PKTROUTEERR = 12002, 878 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCSINGLEBITLIMITERR0 = 12003, 879 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCHDRDOUBLEBITERR0 = 12004, 880 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCDATADOUBLEBITERR0 = 12005, 881 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCSINGLEBITLIMITERR1 = 12006, 882 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCHDRDOUBLEBITERR1 = 12007, 883 NVSWITCH_ERR_HW_NPORT_EGRESS_ECCDATADOUBLEBITERR1 = 12008, 884 NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOCHDRCREDITOVFL = 12009, 885 NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOCDATACREDITOVFL = 12010, 886 NVSWITCH_ERR_HW_NPORT_EGRESS_ADDRMATCHERR = 12011, 887 NVSWITCH_ERR_HW_NPORT_EGRESS_TAGCOUNTERR = 12012, 888 NVSWITCH_ERR_HW_NPORT_EGRESS_FLUSHRSPERR = 12013, 889 NVSWITCH_ERR_HW_NPORT_EGRESS_DROPNPURRSPERR = 12014, 890 NVSWITCH_ERR_HW_NPORT_EGRESS_POISONERR = 12015, 891 NVSWITCH_ERR_HW_NPORT_EGRESS_PACKET_HEADER = 12016, 892 NVSWITCH_ERR_HW_NPORT_EGRESS_BUFFER_DATA = 12017, 893 NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOC_CREDITS = 12018, 894 NVSWITCH_ERR_HW_NPORT_EGRESS_TAG_DATA = 12019, 895 NVSWITCH_ERR_HW_NPORT_EGRESS_SEQIDERR = 12020, 896 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_HDR_ECC_LIMIT_ERR = 12021, 897 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_HDR_ECC_DBE_ERR = 12022, 898 NVSWITCH_ERR_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_LIMIT_ERR = 12023, 899 NVSWITCH_ERR_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_DBE_ERR = 12024, 900 NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOCCREDITOVFL = 12025, 901 NVSWITCH_ERR_HW_NPORT_EGRESS_REQTGTIDMISMATCHERR = 12026, 902 NVSWITCH_ERR_HW_NPORT_EGRESS_RSPREQIDMISMATCHERR = 12027, 903 NVSWITCH_ERR_HW_NPORT_EGRESS_PRIVRSPERR = 12028, 904 NVSWITCH_ERR_HW_NPORT_EGRESS_HWRSPERR = 12029, 905 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_HDR_PARITY_ERR = 12030, 906 NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOC_CREDIT_PARITY_ERR = 12031, 907 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_FLITTYPE_MISMATCH_ERR = 12032, 908 NVSWITCH_ERR_HW_NPORT_EGRESS_CREDIT_TIME_OUT_ERR = 12033, 909 NVSWITCH_ERR_HW_NPORT_EGRESS_INVALIDVCSET_ERR = 12034, 910 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_SIDEBAND_PD_PARITY_ERR = 12035, 911 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR = 12036, 912 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_DBE_ERR = 12037, 913 NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_LIMIT_ERR = 12038, 914 NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_DBE_ERR = 12039, 915 NVSWITCH_ERR_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_LIMIT_ERR = 12040, 916 NVSWITCH_ERR_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_DBE_ERR = 12041, 917 NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDSGT_ECC_LIMIT_ERR = 12042, 918 NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDSGT_ECC_DBE_ERR = 12043, 919 NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDBUF_ECC_LIMIT_ERR = 12044, 920 NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDBUF_ECC_DBE_ERR = 12045, 921 NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_LIMIT_ERR = 12046, 922 NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_DBE_ERR = 12047, 923 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_PARITY_ERR = 12048, 924 NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR = 12049, 925 NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_CNT_ERR = 12050, 926 NVSWITCH_ERR_HW_NPORT_EGRESS_RBRSP_CNT_ERR = 12051, 927 NVSWITCH_ERR_HW_NPORT_EGRESS_LAST, /* NOTE: Must be last */ 928 929 /* NPORT: Fstate errors */ 930 NVSWITCH_ERR_HW_NPORT_FSTATE = 13000, 931 NVSWITCH_ERR_HW_NPORT_FSTATE_TAGPOOLBUFERR = 13001, 932 NVSWITCH_ERR_HW_NPORT_FSTATE_CRUMBSTOREBUFERR = 13002, 933 NVSWITCH_ERR_HW_NPORT_FSTATE_SINGLEBITECCLIMITERR_CRUMBSTORE = 13003, 934 NVSWITCH_ERR_HW_NPORT_FSTATE_UNCORRECTABLEECCERR_CRUMBSTORE = 13004, 935 NVSWITCH_ERR_HW_NPORT_FSTATE_SINGLEBITECCLIMITERR_TAGSTORE = 13005, 936 NVSWITCH_ERR_HW_NPORT_FSTATE_UNCORRECTABLEECCERR_TAGSTORE = 13006, 937 NVSWITCH_ERR_HW_NPORT_FSTATE_SINGLEBITECCLIMITERR_FLUSHREQSTORE = 13007, 938 NVSWITCH_ERR_HW_NPORT_FSTATE_UNCORRECTABLEECCERR_FLUSHREQSTORE = 13008, 939 NVSWITCH_ERR_HW_NPORT_FSTATE_LAST, /* NOTE: Must be last */ 940 941 /* NPORT: Tstate errors */ 942 NVSWITCH_ERR_HW_NPORT_TSTATE = 14000, 943 NVSWITCH_ERR_HW_NPORT_TSTATE_TAGPOOLBUFERR = 14001, 944 NVSWITCH_ERR_HW_NPORT_TSTATE_CRUMBSTOREBUFERR = 14002, 945 NVSWITCH_ERR_HW_NPORT_TSTATE_SINGLEBITECCLIMITERR_CRUMBSTORE = 14003, 946 NVSWITCH_ERR_HW_NPORT_TSTATE_UNCORRECTABLEECCERR_CRUMBSTORE = 14004, 947 NVSWITCH_ERR_HW_NPORT_TSTATE_SINGLEBITECCLIMITERR_TAGSTORE = 14005, 948 NVSWITCH_ERR_HW_NPORT_TSTATE_UNCORRECTABLEECCERR_TAGSTORE = 14006, 949 NVSWITCH_ERR_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR = 14007, 950 NVSWITCH_ERR_HW_NPORT_TSTATE_TAGPOOL_ECC_DBE_ERR = 14008, 951 NVSWITCH_ERR_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 14009, 952 NVSWITCH_ERR_HW_NPORT_TSTATE_CRUMBSTORE_ECC_DBE_ERR = 14010, 953 NVSWITCH_ERR_HW_NPORT_TSTATE_COL_CRUMBSTOREBUFERR = 14011, 954 NVSWITCH_ERR_HW_NPORT_TSTATE_COL_CRUMBSTORE_ECC_LIMIT_ERR = 14012, 955 NVSWITCH_ERR_HW_NPORT_TSTATE_COL_CRUMBSTORE_ECC_DBE_ERR = 14013, 956 NVSWITCH_ERR_HW_NPORT_TSTATE_TD_TID_RAMBUFERR = 14014, 957 NVSWITCH_ERR_HW_NPORT_TSTATE_TD_TID_RAM_ECC_LIMIT_ERR = 14015, 958 NVSWITCH_ERR_HW_NPORT_TSTATE_TD_TID_RAM_ECC_DBE_ERR = 14016, 959 NVSWITCH_ERR_HW_NPORT_TSTATE_ATO_ERR = 14017, 960 NVSWITCH_ERR_HW_NPORT_TSTATE_CAMRSP_ERR = 14018, 961 NVSWITCH_ERR_HW_NPORT_TSTATE_LAST, /* NOTE: Must be last */ 962 963 /* NPORT: Route errors */ 964 NVSWITCH_ERR_HW_NPORT_ROUTE = 15000, 965 NVSWITCH_ERR_HW_NPORT_ROUTE_ROUTEBUFERR = 15001, 966 NVSWITCH_ERR_HW_NPORT_ROUTE_NOPORTDEFINEDERR = 15002, 967 NVSWITCH_ERR_HW_NPORT_ROUTE_INVALIDROUTEPOLICYERR = 15003, 968 NVSWITCH_ERR_HW_NPORT_ROUTE_ECCLIMITERR = 15004, 969 NVSWITCH_ERR_HW_NPORT_ROUTE_UNCORRECTABLEECCERR = 15005, 970 NVSWITCH_ERR_HW_NPORT_ROUTE_TRANSDONERESVERR = 15006, 971 NVSWITCH_ERR_HW_NPORT_ROUTE_PACKET_HEADER = 15007, 972 NVSWITCH_ERR_HW_NPORT_ROUTE_GLT_ECC_LIMIT_ERR = 15008, 973 NVSWITCH_ERR_HW_NPORT_ROUTE_GLT_ECC_DBE_ERR = 15009, 974 NVSWITCH_ERR_HW_NPORT_ROUTE_PDCTRLPARERR = 15010, 975 NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR = 15011, 976 NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_DBE_ERR = 15012, 977 NVSWITCH_ERR_HW_NPORT_ROUTE_CDTPARERR = 15013, 978 NVSWITCH_ERR_HW_NPORT_ROUTE_MCRID_ECC_LIMIT_ERR = 15014, 979 NVSWITCH_ERR_HW_NPORT_ROUTE_MCRID_ECC_DBE_ERR = 15015, 980 NVSWITCH_ERR_HW_NPORT_ROUTE_EXTMCRID_ECC_LIMIT_ERR = 15016, 981 NVSWITCH_ERR_HW_NPORT_ROUTE_EXTMCRID_ECC_DBE_ERR = 15017, 982 NVSWITCH_ERR_HW_NPORT_ROUTE_RAM_ECC_LIMIT_ERR = 15018, 983 NVSWITCH_ERR_HW_NPORT_ROUTE_RAM_ECC_DBE_ERR = 15019, 984 NVSWITCH_ERR_HW_NPORT_ROUTE_INVALID_MCRID_ERR = 15020, 985 NVSWITCH_ERR_HW_NPORT_ROUTE_LAST, /* NOTE: Must be last */ 986 987 /* NPORT: Nport errors */ 988 NVSWITCH_ERR_HW_NPORT = 16000, 989 NVSWITCH_ERR_HW_NPORT_DATAPOISONED = 16001, 990 NVSWITCH_ERR_HW_NPORT_UCINTERNAL = 16002, 991 NVSWITCH_ERR_HW_NPORT_CINTERNAL = 16003, 992 NVSWITCH_ERR_HW_NPORT_LAST, /* NOTE: Must be last */ 993 994 /* NVLCTRL: NVCTRL errors */ 995 NVSWITCH_ERR_HW_NVLCTRL = 17000, 996 NVSWITCH_ERR_HW_NVLCTRL_INGRESSECCSOFTLIMITERR = 17001, 997 NVSWITCH_ERR_HW_NVLCTRL_INGRESSECCHDRDOUBLEBITERR = 17002, 998 NVSWITCH_ERR_HW_NVLCTRL_INGRESSECCDATADOUBLEBITERR = 17003, 999 NVSWITCH_ERR_HW_NVLCTRL_INGRESSBUFFERERR = 17004, 1000 NVSWITCH_ERR_HW_NVLCTRL_EGRESSECCSOFTLIMITERR = 17005, 1001 NVSWITCH_ERR_HW_NVLCTRL_EGRESSECCHDRDOUBLEBITERR = 17006, 1002 NVSWITCH_ERR_HW_NVLCTRL_EGRESSECCDATADOUBLEBITERR = 17007, 1003 NVSWITCH_ERR_HW_NVLCTRL_EGRESSBUFFERERR = 17008, 1004 NVSWITCH_ERR_HW_NVLCTRL_LAST, /* NOTE: Must be last */ 1005 1006 /* Nport: Nvlipt errors */ 1007 NVSWITCH_ERR_HW_NVLIPT = 18000, 1008 NVSWITCH_ERR_HW_NVLIPT_DLPROTOCOL = 18001, 1009 NVSWITCH_ERR_HW_NVLIPT_DATAPOISONED = 18002, 1010 NVSWITCH_ERR_HW_NVLIPT_FLOWCONTROL = 18003, 1011 NVSWITCH_ERR_HW_NVLIPT_RESPONSETIMEOUT = 18004, 1012 NVSWITCH_ERR_HW_NVLIPT_TARGETERROR = 18005, 1013 NVSWITCH_ERR_HW_NVLIPT_UNEXPECTEDRESPONSE = 18006, 1014 NVSWITCH_ERR_HW_NVLIPT_RECEIVEROVERFLOW = 18007, 1015 NVSWITCH_ERR_HW_NVLIPT_MALFORMEDPACKET = 18008, 1016 NVSWITCH_ERR_HW_NVLIPT_STOMPEDPACKETRECEIVED = 18009, 1017 NVSWITCH_ERR_HW_NVLIPT_UNSUPPORTEDREQUEST = 18010, 1018 NVSWITCH_ERR_HW_NVLIPT_UCINTERNAL = 18011, 1019 NVSWITCH_ERR_HW_NVLIPT_PHYRECEIVER = 18012, 1020 NVSWITCH_ERR_HW_NVLIPT_BADAN0PKT = 18013, 1021 NVSWITCH_ERR_HW_NVLIPT_REPLAYTIMEOUT = 18014, 1022 NVSWITCH_ERR_HW_NVLIPT_ADVISORYERROR = 18015, 1023 NVSWITCH_ERR_HW_NVLIPT_CINTERNAL = 18016, 1024 NVSWITCH_ERR_HW_NVLIPT_HEADEROVERFLOW = 18017, 1025 NVSWITCH_ERR_HW_NVLIPT_RSTSEQ_PHYARB_TIMEOUT = 18018, 1026 NVSWITCH_ERR_HW_NVLIPT_RSTSEQ_PLL_TIMEOUT = 18019, 1027 NVSWITCH_ERR_HW_NVLIPT_CLKCTL_ILLEGAL_REQUEST = 18020, 1028 NVSWITCH_ERR_HW_NVLIPT_LAST, /* NOTE: Must be last */ 1029 1030 /* Nport: Nvltlc TX/RX errors */ 1031 NVSWITCH_ERR_HW_NVLTLC = 19000, 1032 NVSWITCH_ERR_HW_NVLTLC_TXHDRCREDITOVFERR = 19001, 1033 NVSWITCH_ERR_HW_NVLTLC_TXDATACREDITOVFERR = 19002, 1034 NVSWITCH_ERR_HW_NVLTLC_TXDLCREDITOVFERR = 19003, 1035 NVSWITCH_ERR_HW_NVLTLC_TXDLCREDITPARITYERR = 19004, 1036 NVSWITCH_ERR_HW_NVLTLC_TXRAMHDRPARITYERR = 19005, 1037 NVSWITCH_ERR_HW_NVLTLC_TXRAMDATAPARITYERR = 19006, 1038 NVSWITCH_ERR_HW_NVLTLC_TXUNSUPVCOVFERR = 19007, 1039 NVSWITCH_ERR_HW_NVLTLC_TXSTOMPDET = 19008, 1040 NVSWITCH_ERR_HW_NVLTLC_TXPOISONDET = 19009, 1041 NVSWITCH_ERR_HW_NVLTLC_TARGETERR = 19010, 1042 NVSWITCH_ERR_HW_NVLTLC_TX_PACKET_HEADER = 19011, 1043 NVSWITCH_ERR_HW_NVLTLC_UNSUPPORTEDREQUESTERR = 19012, 1044 NVSWITCH_ERR_HW_NVLTLC_RXDLHDRPARITYERR = 19013, 1045 NVSWITCH_ERR_HW_NVLTLC_RXDLDATAPARITYERR = 19014, 1046 NVSWITCH_ERR_HW_NVLTLC_RXDLCTRLPARITYERR = 19015, 1047 NVSWITCH_ERR_HW_NVLTLC_RXRAMDATAPARITYERR = 19016, 1048 NVSWITCH_ERR_HW_NVLTLC_RXRAMHDRPARITYERR = 19017, 1049 NVSWITCH_ERR_HW_NVLTLC_RXINVALIDAEERR = 19018, 1050 NVSWITCH_ERR_HW_NVLTLC_RXINVALIDBEERR = 19019, 1051 NVSWITCH_ERR_HW_NVLTLC_RXINVALIDADDRALIGNERR = 19020, 1052 NVSWITCH_ERR_HW_NVLTLC_RXPKTLENERR = 19021, 1053 NVSWITCH_ERR_HW_NVLTLC_RSVCMDENCERR = 19022, 1054 NVSWITCH_ERR_HW_NVLTLC_RSVDATLENENCERR = 19023, 1055 NVSWITCH_ERR_HW_NVLTLC_RSVADDRTYPEERR = 19024, 1056 NVSWITCH_ERR_HW_NVLTLC_RSVRSPSTATUSERR = 19025, 1057 NVSWITCH_ERR_HW_NVLTLC_RSVPKTSTATUSERR = 19026, 1058 NVSWITCH_ERR_HW_NVLTLC_RSVCACHEATTRPROBEREQERR = 19027, 1059 NVSWITCH_ERR_HW_NVLTLC_RSVCACHEATTRPROBERSPERR = 19028, 1060 NVSWITCH_ERR_HW_NVLTLC_DATLENGTATOMICREQMAXERR = 19029, 1061 NVSWITCH_ERR_HW_NVLTLC_DATLENGTRMWREQMAXERR = 19030, 1062 NVSWITCH_ERR_HW_NVLTLC_DATLENLTATRRSPMINERR = 19031, 1063 NVSWITCH_ERR_HW_NVLTLC_INVALIDCACHEATTRPOERR = 19032, 1064 NVSWITCH_ERR_HW_NVLTLC_INVALIDCRERR = 19033, 1065 NVSWITCH_ERR_HW_NVLTLC_RXRESPSTATUSTARGETERR = 19034, 1066 NVSWITCH_ERR_HW_NVLTLC_RXRESPSTATUSUNSUPPORTEDREQUESTERR = 19035, 1067 NVSWITCH_ERR_HW_NVLTLC_RXHDROVFERR = 19036, 1068 NVSWITCH_ERR_HW_NVLTLC_RXDATAOVFERR = 19037, 1069 NVSWITCH_ERR_HW_NVLTLC_STOMPDETERR = 19038, 1070 NVSWITCH_ERR_HW_NVLTLC_RXPOISONERR = 19039, 1071 NVSWITCH_ERR_HW_NVLTLC_CORRECTABLEINTERNALERR = 19040, 1072 NVSWITCH_ERR_HW_NVLTLC_RXUNSUPVCOVFERR = 19041, 1073 NVSWITCH_ERR_HW_NVLTLC_RXUNSUPNVLINKCREDITRELERR = 19042, 1074 NVSWITCH_ERR_HW_NVLTLC_RXUNSUPNCISOCCREDITRELERR = 19043, 1075 NVSWITCH_ERR_HW_NVLTLC_RX_PACKET_HEADER = 19044, 1076 NVSWITCH_ERR_HW_NVLTLC_RX_ERR_HEADER = 19045, 1077 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_NCISOC_PARITY_ERR = 19046, 1078 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_NCISOC_HDR_ECC_DBE_ERR = 19047, 1079 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_NCISOC_DAT_ECC_DBE_ERR = 19048, 1080 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_NCISOC_ECC_LIMIT_ERR = 19049, 1081 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_TXRSPSTATUS_HW_ERR = 19050, 1082 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_TXRSPSTATUS_UR_ERR = 19051, 1083 NVSWITCH_ERR_HW_NVLTLC_TX_SYS_TXRSPSTATUS_PRIV_ERR = 19052, 1084 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_NCISOC_PARITY_ERR = 19053, 1085 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_HDR_RAM_ECC_DBE_ERR = 19054, 1086 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_HDR_RAM_ECC_LIMIT_ERR = 19055, 1087 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_DAT0_RAM_ECC_DBE_ERR = 19056, 1088 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_DAT0_RAM_ECC_LIMIT_ERR = 19057, 1089 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_DAT1_RAM_ECC_DBE_ERR = 19058, 1090 NVSWITCH_ERR_HW_NVLTLC_RX_SYS_DAT1_RAM_ECC_LIMIT_ERR = 19059, 1091 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_CREQ_RAM_HDR_ECC_DBE_ERR = 19060, 1092 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_CREQ_RAM_DAT_ECC_DBE_ERR = 19061, 1093 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_CREQ_RAM_ECC_LIMIT_ERR = 19062, 1094 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP_RAM_HDR_ECC_DBE_ERR = 19063, 1095 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP_RAM_DAT_ECC_DBE_ERR = 19064, 1096 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP_RAM_ECC_LIMIT_ERR = 19065, 1097 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_COM_RAM_HDR_ECC_DBE_ERR = 19066, 1098 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_COM_RAM_DAT_ECC_DBE_ERR = 19067, 1099 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_COM_RAM_ECC_LIMIT_ERR = 19068, 1100 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP1_RAM_HDR_ECC_DBE_ERR = 19069, 1101 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP1_RAM_DAT_ECC_DBE_ERR = 19070, 1102 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_RSP1_RAM_ECC_LIMIT_ERR = 19071, 1103 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC0 = 19072, 1104 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC1 = 19073, 1105 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC2 = 19074, 1106 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC3 = 19075, 1107 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC4 = 19076, 1108 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC5 = 19077, 1109 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC6 = 19078, 1110 NVSWITCH_ERR_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC7 = 19079, 1111 NVSWITCH_ERR_HW_NVLTLC_RX_LNK_RXRSPSTATUS_HW_ERR = 19080, 1112 NVSWITCH_ERR_HW_NVLTLC_RX_LNK_RXRSPSTATUS_UR_ERR = 19081, 1113 NVSWITCH_ERR_HW_NVLTLC_RX_LNK_RXRSPSTATUS_PRIV_ERR = 19082, 1114 NVSWITCH_ERR_HW_NVLTLC_RX_LNK_INVALID_COLLAPSED_RESPONSE_ERR = 19083, 1115 NVSWITCH_ERR_HW_NVLTLC_RX_LNK_AN1_HEARTBEAT_TIMEOUT_ERR = 19084, 1116 NVSWITCH_ERR_HW_NVLTLC_LAST, /* NOTE: Must be last */ 1117 1118 /* DLPL: errors ( SL1 errors too) */ 1119 NVSWITCH_ERR_HW_DLPL = 20000, 1120 NVSWITCH_ERR_HW_DLPL_TX_REPLAY = 20001, 1121 NVSWITCH_ERR_HW_DLPL_TX_RECOVERY_SHORT = 20002, 1122 NVSWITCH_ERR_HW_DLPL_TX_RECOVERY_LONG = 20003, 1123 NVSWITCH_ERR_HW_DLPL_TX_FAULT_RAM = 20004, 1124 NVSWITCH_ERR_HW_DLPL_TX_FAULT_INTERFACE = 20005, 1125 NVSWITCH_ERR_HW_DLPL_TX_FAULT_SUBLINK_CHANGE = 20006, 1126 NVSWITCH_ERR_HW_DLPL_RX_FAULT_SUBLINK_CHANGE = 20007, 1127 NVSWITCH_ERR_HW_DLPL_RX_FAULT_DL_PROTOCOL = 20008, 1128 NVSWITCH_ERR_HW_DLPL_RX_SHORT_ERROR_RATE = 20009, 1129 NVSWITCH_ERR_HW_DLPL_RX_LONG_ERROR_RATE = 20010, 1130 NVSWITCH_ERR_HW_DLPL_RX_ILA_TRIGGER = 20011, 1131 NVSWITCH_ERR_HW_DLPL_RX_CRC_COUNTER = 20012, 1132 NVSWITCH_ERR_HW_DLPL_LTSSM_FAULT = 20013, 1133 NVSWITCH_ERR_HW_DLPL_LTSSM_PROTOCOL = 20014, 1134 NVSWITCH_ERR_HW_DLPL_MINION_REQUEST = 20015, 1135 NVSWITCH_ERR_HW_DLPL_FIFO_DRAIN_ERR = 20016, 1136 NVSWITCH_ERR_HW_DLPL_CONST_DET_ERR = 20017, 1137 NVSWITCH_ERR_HW_DLPL_OFF2SAFE_LINK_DET_ERR = 20018, 1138 NVSWITCH_ERR_HW_DLPL_SAFE2NO_LINK_DET_ERR = 20019, 1139 NVSWITCH_ERR_HW_DLPL_SCRAM_LOCK_ERR = 20020, 1140 NVSWITCH_ERR_HW_DLPL_SYM_LOCK_ERR = 20021, 1141 NVSWITCH_ERR_HW_DLPL_SYM_ALIGN_END_ERR = 20022, 1142 NVSWITCH_ERR_HW_DLPL_FIFO_SKEW_ERR = 20023, 1143 NVSWITCH_ERR_HW_DLPL_TRAIN2SAFE_LINK_DET_ERR = 20024, 1144 NVSWITCH_ERR_HW_DLPL_HS2SAFE_LINK_DET_ERR = 20025, 1145 NVSWITCH_ERR_HW_DLPL_FENCE_ERR = 20026, 1146 NVSWITCH_ERR_HW_DLPL_SAFE_NO_LD_ERR = 20027, 1147 NVSWITCH_ERR_HW_DLPL_E2SAFE_LD_ERR = 20028, 1148 NVSWITCH_ERR_HW_DLPL_RC_RXPWR_ERR = 20029, 1149 NVSWITCH_ERR_HW_DLPL_RC_TXPWR_ERR = 20030, 1150 NVSWITCH_ERR_HW_DLPL_RC_DEADLINE_ERR = 20031, 1151 NVSWITCH_ERR_HW_DLPL_TX_HS2LP_ERR = 20032, 1152 NVSWITCH_ERR_HW_DLPL_RX_HS2LP_ERR = 20033, 1153 NVSWITCH_ERR_HW_DLPL_LTSSM_FAULT_UP = 20034, 1154 NVSWITCH_ERR_HW_DLPL_LTSSM_FAULT_DOWN = 20035, 1155 NVSWITCH_ERR_HW_DLPL_PHY_A = 20036, 1156 NVSWITCH_ERR_HW_DLPL_TX_PL_ERROR = 20037, 1157 NVSWITCH_ERR_HW_DLPL_RX_PL_ERROR = 20038, 1158 NVSWITCH_ERR_HW_DLPL_LAST, /* NOTE: Must be last */ 1159 1160 /* AFS: errors */ 1161 NVSWITCH_ERR_HW_AFS = 21000, 1162 NVSWITCH_ERR_HW_AFS_UC_INGRESS_CREDIT_OVERFLOW = 21001, 1163 NVSWITCH_ERR_HW_AFS_UC_INGRESS_CREDIT_UNDERFLOW = 21002, 1164 NVSWITCH_ERR_HW_AFS_UC_EGRESS_CREDIT_OVERFLOW = 21003, 1165 NVSWITCH_ERR_HW_AFS_UC_EGRESS_CREDIT_UNDERFLOW = 21004, 1166 NVSWITCH_ERR_HW_AFS_UC_INGRESS_NON_BURSTY_PKT_DETECTED = 21005, 1167 NVSWITCH_ERR_HW_AFS_UC_INGRESS_NON_STICKY_PKT_DETECTED = 21006, 1168 NVSWITCH_ERR_HW_AFS_UC_INGRESS_BURST_GT_17_DATA_VC_DETECTED = 21007, 1169 NVSWITCH_ERR_HW_AFS_UC_INGRESS_BURST_GT_1_NONDATA_VC_DETECTED = 21008, 1170 NVSWITCH_ERR_HW_AFS_UC_INVALID_DST = 21009, 1171 NVSWITCH_ERR_HW_AFS_UC_PKT_MISROUTE = 21010, 1172 NVSWITCH_ERR_HW_AFS_LAST, /* NOTE: Must be last */ 1173 1174 /* MINION: errors */ 1175 NVSWITCH_ERR_HW_MINION = 22000, 1176 NVSWITCH_ERR_HW_MINION_UCODE_IMEM = 22001, 1177 NVSWITCH_ERR_HW_MINION_UCODE_DMEM = 22002, 1178 NVSWITCH_ERR_HW_MINION_HALT = 22003, 1179 NVSWITCH_ERR_HW_MINION_BOOT_ERROR = 22004, 1180 NVSWITCH_ERR_HW_MINION_TIMEOUT = 22005, 1181 NVSWITCH_ERR_HW_MINION_DLCMD_FAULT = 22006, 1182 NVSWITCH_ERR_HW_MINION_DLCMD_TIMEOUT = 22007, 1183 NVSWITCH_ERR_HW_MINION_DLCMD_FAIL = 22008, 1184 NVSWITCH_ERR_HW_MINION_FATAL_INTR = 22009, 1185 NVSWITCH_ERR_HW_MINION_WATCHDOG = 22010, 1186 NVSWITCH_ERR_HW_MINION_EXTERR = 22011, 1187 NVSWITCH_ERR_HW_MINION_FATAL_LINK_INTR = 22012, 1188 NVSWITCH_ERR_HW_MINION_NONFATAL = 22013, 1189 NVSWITCH_ERR_HW_MINION_LAST, /* NOTE: Must be last */ 1190 1191 /* NXBAR errors */ 1192 NVSWITCH_ERR_HW_NXBAR = 23000, 1193 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_BUFFER_OVERFLOW = 23001, 1194 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_BUFFER_UNDERFLOW = 23002, 1195 NVSWITCH_ERR_HW_NXBAR_TILE_EGRESS_CREDIT_OVERFLOW = 23003, 1196 NVSWITCH_ERR_HW_NXBAR_TILE_EGRESS_CREDIT_UNDERFLOW = 23004, 1197 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_NON_BURSTY_PKT = 23005, 1198 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_NON_STICKY_PKT = 23006, 1199 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_BURST_GT_9_DATA_VC = 23007, 1200 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_PKT_INVALID_DST = 23008, 1201 NVSWITCH_ERR_HW_NXBAR_TILE_INGRESS_PKT_PARITY_ERROR = 23009, 1202 NVSWITCH_ERR_HW_NXBAR_TILEOUT_INGRESS_BUFFER_OVERFLOW = 23010, 1203 NVSWITCH_ERR_HW_NXBAR_TILEOUT_INGRESS_BUFFER_UNDERFLOW = 23011, 1204 NVSWITCH_ERR_HW_NXBAR_TILEOUT_EGRESS_CREDIT_OVERFLOW = 23012, 1205 NVSWITCH_ERR_HW_NXBAR_TILEOUT_EGRESS_CREDIT_UNDERFLOW = 23013, 1206 NVSWITCH_ERR_HW_NXBAR_TILEOUT_INGRESS_NON_BURSTY_PKT = 23014, 1207 NVSWITCH_ERR_HW_NXBAR_TILEOUT_INGRESS_NON_STICKY_PKT = 23015, 1208 NVSWITCH_ERR_HW_NXBAR_TILEOUT_INGRESS_BURST_GT_9_DATA_VC = 23016, 1209 NVSWITCH_ERR_HW_NXBAR_TILEOUT_EGRESS_CDT_PARITY_ERROR = 23017, 1210 NVSWITCH_ERR_HW_NXBAR_LAST, /* NOTE: Must be last */ 1211 1212 /* NPORT: SOURCETRACK errors */ 1213 NVSWITCH_ERR_HW_NPORT_SOURCETRACK = 24000, 1214 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR = 24001, 1215 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR = 24002, 1216 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR = 24003, 1217 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR = 24004, 1218 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR = 24005, 1219 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR = 24006, 1220 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_SOURCETRACK_TIME_OUT_ERR = 24007, 1221 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_DUP_CREQ_TCEN0_TAG_ERR = 24008, 1222 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_INVALID_TCEN0_RSP_ERR = 24009, 1223 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_INVALID_TCEN1_RSP_ERR = 24010, 1224 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_LAST, /* NOTE: Must be last */ 1225 1226 /* NVLIPT_LNK errors */ 1227 NVSWITCH_ERR_HW_NVLIPT_LNK = 25000, 1228 NVSWITCH_ERR_HW_NVLIPT_LNK_ILLEGALLINKSTATEREQUEST = 25001, 1229 NVSWITCH_ERR_HW_NVLIPT_LNK_FAILEDMINIONREQUEST = 25002, 1230 NVSWITCH_ERR_HW_NVLIPT_LNK_RESERVEDREQUESTVALUE = 25003, 1231 NVSWITCH_ERR_HW_NVLIPT_LNK_LINKSTATEWRITEWHILEBUSY = 25004, 1232 NVSWITCH_ERR_HW_NVLIPT_LNK_LINK_STATE_REQUEST_TIMEOUT = 25005, 1233 NVSWITCH_ERR_HW_NVLIPT_LNK_WRITE_TO_LOCKED_SYSTEM_REG_ERR = 25006, 1234 NVSWITCH_ERR_HW_NVLIPT_LNK_SLEEPWHILEACTIVELINK = 25007, 1235 NVSWITCH_ERR_HW_NVLIPT_LNK_RSTSEQ_PHYCTL_TIMEOUT = 25008, 1236 NVSWITCH_ERR_HW_NVLIPT_LNK_RSTSEQ_CLKCTL_TIMEOUT = 25009, 1237 NVSWITCH_ERR_HW_NVLIPT_LNK_ALI_TRAINING_FAIL = 25010, 1238 NVSWITCH_ERR_HW_NVLIPT_LNK_LAST, /* Note: Must be last */ 1239 1240 /* SOE errors */ 1241 NVSWITCH_ERR_HW_SOE = 26000, 1242 NVSWITCH_ERR_HW_SOE_RESET = 26001, 1243 NVSWITCH_ERR_HW_SOE_BOOTSTRAP = 26002, 1244 NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE = 26003, 1245 NVSWITCH_ERR_HW_SOE_TIMEOUT = 26004, 1246 NVSWITCH_ERR_HW_SOE_SHUTDOWN = 26005, 1247 NVSWITCH_ERR_HW_SOE_HALT = 26006, 1248 NVSWITCH_ERR_HW_SOE_EXTERR = 26007, 1249 NVSWITCH_ERR_HW_SOE_WATCHDOG = 26008, 1250 NVSWITCH_ERR_HW_SOE_LAST, /* Note: Must be last */ 1251 1252 /* NPORT: Multicast Tstate errors */ 1253 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE = 28000, 1254 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR = 28001, 1255 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_DBE_ERR = 28002, 1256 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 28003, 1257 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_DBE_ERR = 28004, 1258 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR = 28005, 1259 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_MCTO_ERR = 28006, 1260 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_LAST, /* Note: Must be last */ 1261 1262 /* NPORT: Reduction Tstate errors */ 1263 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE = 29000, 1264 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR = 29001, 1265 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_DBE_ERR = 29002, 1266 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 29003, 1267 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_DBE_ERR = 29004, 1268 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR = 29005, 1269 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_RTO_ERR = 29006, 1270 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_LAST, /* Note: Must be last */ 1271 1272 /* Please update nvswitch_translate_hw_errors with a newly added error class. */ 1273 NVSWITCH_ERR_LAST 1274 /* See enum modification guidelines at the top of this file */ 1275 } NVSWITCH_ERR_TYPE; 1276 1277 typedef enum nvswitch_pri_error_instance 1278 { 1279 NVSWITCH_PBUS_PRI_SQUASH = 0, 1280 NVSWITCH_PBUS_PRI_FECSERR, 1281 NVSWITCH_PBUS_PRI_TIMEOUT, 1282 NVSWITCH_PPRIV_WRITE_SYS, 1283 NVSWITCH_PPRIV_WRITE_PRT 1284 } NVSWITCH_PRI_ERROR_INSTANCE; 1285 1286 typedef struct nvswitch_error 1287 { 1288 NvU32 error_value; /* NVSWITCH_ERR_* */ 1289 NvU32 error_src; /* NVSWITCH_ERROR_SRC_* */ 1290 NvU32 instance; /* Used for link# or subengine instance */ 1291 NvU32 subinstance; /* Used for lane# or similar */ 1292 NV_DECLARE_ALIGNED(NvU64 time, 8); /* Platform time (nsec) */ 1293 NvBool error_resolved; /* If an error is correctable, set to true. */ 1294 } NVSWITCH_ERROR; 1295 1296 #define NVSWITCH_ERROR_COUNT_SIZE 64 1297 1298 typedef struct nvswitch_get_errors 1299 { 1300 NvU32 errorType; 1301 NvU64 errorIndex; 1302 NvU64 nextErrorIndex; 1303 NvU32 errorCount; 1304 NVSWITCH_ERROR error[NVSWITCH_ERROR_COUNT_SIZE]; 1305 } NVSWITCH_GET_ERRORS_PARAMS; 1306 1307 /* 1308 * CTRL_NVSWITCH_GET_INTERNAL_LATENCY 1309 * 1310 * Control for querying latency bins. 1311 * 1312 * Parameters: 1313 * vc_selector [IN] 1314 * A valid VC number returned by NVSWITCH_GET_INFO. 1315 * 1316 * elapsed_time_msec [OUT] 1317 * Elapsed time since the latency bins were queried. 1318 * egressHistogram [OUT] 1319 * Latency bin data/histogram format. The data will be available for the 1320 * enabled/supported ports returned by NVSWITCH_GET_INFO. 1321 */ 1322 1323 #define NVSWITCH_MAX_PORTS 64 1324 1325 /* TODO: describe the format */ 1326 typedef struct nvswitch_internal_latency_bins 1327 { 1328 NV_DECLARE_ALIGNED(NvU64 low, 8); 1329 NV_DECLARE_ALIGNED(NvU64 medium, 8); 1330 NV_DECLARE_ALIGNED(NvU64 high, 8); 1331 NV_DECLARE_ALIGNED(NvU64 panic, 8); 1332 NV_DECLARE_ALIGNED(NvU64 count, 8); 1333 } NVSWITCH_INTERNAL_LATENCY_BINS; 1334 1335 typedef struct nvswitch_get_internal_latency 1336 { 1337 NvU32 vc_selector; 1338 NV_DECLARE_ALIGNED(NvU64 elapsed_time_msec, 8); 1339 NVSWITCH_INTERNAL_LATENCY_BINS egressHistogram[NVSWITCH_MAX_PORTS]; 1340 } NVSWITCH_GET_INTERNAL_LATENCY; 1341 1342 /* 1343 * CTRL_NVSWITCH_SET_LATENCY_BINS 1344 * 1345 * Control for setting latency bins. 1346 * 1347 * Parameters: 1348 * NVSWITCH_LATENCY_BIN [IN] 1349 * Latency bin thresholds. The thresholds would be only applied to the 1350 * enabled ports and the supported VCs by those ports. 1351 * NVSWITCH_GET_INFO can be used to query enabled ports and supported VCs. 1352 */ 1353 1354 #define NVSWITCH_MAX_VCS 8 1355 1356 /* TODO: describe the format */ 1357 typedef struct nvswitch_latency_bin 1358 { 1359 NvU32 lowThreshold; /* in nsec */ 1360 NvU32 medThreshold; /* in nsec */ 1361 NvU32 hiThreshold; /* in nsec */ 1362 1363 } NVSWITCH_LATENCY_BIN; 1364 1365 typedef struct nvswitch_set_latency_bins 1366 { 1367 NVSWITCH_LATENCY_BIN bin[NVSWITCH_MAX_VCS]; 1368 1369 } NVSWITCH_SET_LATENCY_BINS; 1370 1371 /* 1372 * CTRL_NVSWITCH_SET_SWITCH_PORT_CONFIG 1373 * 1374 * Control for setting device port configurations. 1375 * 1376 * Parameters: 1377 * portNum [IN] 1378 * A valid port number present in the port masks returned by 1379 * NVSWITCH_GET_INFO. 1380 * type [IN] 1381 * A connection type. See NVSWITCH_CONNECTION_TYPE. 1382 * requesterLinkID [IN] 1383 * An unique port ID in the fabric. 1384 * requesterLan [IN] 1385 * A Lan Id. 1386 * count [IN] 1387 * Endpoint Count 1388 * acCoupled [IN] 1389 * Set true, if the port is AC coupled. 1390 * enableVC1 [IN] 1391 * Set true, if VC1 should be enabled for the port. 1392 * trunkSrcMask [IN] 1393 * Mask of source trunk ports. 1394 */ 1395 1396 typedef enum nvswitch_connection_type 1397 { 1398 CONNECT_ACCESS_GPU = 0, 1399 CONNECT_ACCESS_CPU, 1400 CONNECT_TRUNK_SWITCH, 1401 CONNECT_ACCESS_SWITCH 1402 /* See enum modification guidelines at the top of this file */ 1403 } NVSWITCH_CONNECTION_TYPE; 1404 1405 typedef enum nvswitch_connection_count 1406 { 1407 CONNECT_COUNT_512 = 0, 1408 CONNECT_COUNT_1024, 1409 CONNECT_COUNT_2048 1410 /* See enum modification guidelines at the top of this file */ 1411 } NVSWITCH_CONNECTION_COUNT; 1412 1413 typedef struct nvswitch_set_switch_port_config 1414 { 1415 NvU32 portNum; 1416 NvU32 type; 1417 NvU32 requesterLinkID; 1418 NvU32 requesterLanID; 1419 NvU32 count; 1420 NvBool acCoupled; 1421 NvBool enableVC1; 1422 NvU64 trunkSrcMask; 1423 1424 } NVSWITCH_SET_SWITCH_PORT_CONFIG; 1425 1426 /* 1427 * CTRL_NVSWITCH_SET_GANGED_LINK_TABLE 1428 * 1429 * Control for setting ganged link tables. 1430 * This interface is only supported on architectures that report 1431 * _GET_INFO_INDEX_ARCH == SV10. All others will return an error. 1432 * 1433 * Parameters: 1434 * linkMask [IN] 1435 * A valid link/port mask returned by the port masks returned by 1436 * NVSWITCH_GET_INFO. 1437 * entries [IN] 1438 * The Ganged link entires. (TODO: Describe format) 1439 */ 1440 1441 #define NVSWITCH_GANGED_LINK_TABLE_ENTRIES_MAX 256 1442 1443 typedef struct nvswitch_set_ganged_link_table 1444 { 1445 NvU32 link_mask; 1446 NvU32 entries[NVSWITCH_GANGED_LINK_TABLE_ENTRIES_MAX]; 1447 1448 } NVSWITCH_SET_GANGED_LINK_TABLE; 1449 1450 /* 1451 * CTRL_NVSWITCH_GET_NVLIPT_COUNTER 1452 * 1453 * Control for querying NVLIPT counters. 1454 * 1455 * Parameters: 1456 * liptCounter [OUT] 1457 * Port's TX/RX traffic data. The data will be available for the 1458 * enabled/supported ports returned by NVSWITCH_GET_INFO. 1459 */ 1460 1461 typedef struct nvswitch_nvlipt_counter 1462 { 1463 NV_DECLARE_ALIGNED(NvU64 txCounter0, 8); 1464 NV_DECLARE_ALIGNED(NvU64 txCounter1, 8); 1465 NV_DECLARE_ALIGNED(NvU64 rxCounter0, 8); 1466 NV_DECLARE_ALIGNED(NvU64 rxCounter1, 8); 1467 1468 } NVSWITCH_NVLIPT_COUNTER; 1469 1470 typedef struct nvswitch_get_nvlipt_counters 1471 { 1472 NVSWITCH_NVLIPT_COUNTER liptCounter[NVSWITCH_MAX_PORTS]; 1473 1474 } NVSWITCH_GET_NVLIPT_COUNTERS; 1475 1476 /* 1477 * CTRL_NVSWITCH_SET_NVLIPT_COUNTER_CONFIG 1478 * 1479 * Control to set NVLIPT counter configuration. 1480 * 1481 * Parameters: 1482 * linkMask [IN] 1483 * A valid link/port mask returned by the port masks returned by 1484 * NVSWITCH_GET_INFO. 1485 * tx0/tx1/rx0/rx1 [IN] 1486 * TX/RX link configurations. 1487 */ 1488 1489 /* TODO: describe format */ 1490 typedef struct nvlipt_counter_config 1491 { 1492 NvU32 ctrl_0; 1493 NvU32 ctrl_1; 1494 NvU32 req_filter; 1495 NvU32 rsp_filter; 1496 NvU32 misc_filter; 1497 NV_DECLARE_ALIGNED(NvU64 addr_filter, 8); 1498 NV_DECLARE_ALIGNED(NvU64 addr_mask, 8); 1499 1500 } NVLIPT_COUNTER_CONFIG; 1501 1502 typedef struct nvswitch_set_nvlipt_counter_config 1503 { 1504 NV_DECLARE_ALIGNED(NvU64 link_mask, 8); 1505 NVLIPT_COUNTER_CONFIG tx0; 1506 NVLIPT_COUNTER_CONFIG tx1; 1507 NVLIPT_COUNTER_CONFIG rx0; 1508 NVLIPT_COUNTER_CONFIG rx1; 1509 1510 } NVSWITCH_SET_NVLIPT_COUNTER_CONFIG; 1511 1512 /* 1513 * CTRL_NVSWITCH_GET_NVLIPT_COUNTER_CONFIG 1514 * 1515 * Control to query NVLIPT counter configuration. 1516 * 1517 * Parameters: 1518 * link [IN] 1519 * A valid link/port returned by the port masks returned by 1520 * NVSWITCH_GET_INFO. 1521 * 1522 * tx0/tx1/rx0/rx1 [OUT] 1523 * TX/RX link configurations for the provide port. 1524 */ 1525 1526 typedef struct nvswitch_get_nvlipt_counter_config 1527 { 1528 NvU32 link; 1529 NVLIPT_COUNTER_CONFIG tx0; 1530 NVLIPT_COUNTER_CONFIG tx1; 1531 NVLIPT_COUNTER_CONFIG rx0; 1532 NVLIPT_COUNTER_CONFIG rx1; 1533 1534 } NVSWITCH_GET_NVLIPT_COUNTER_CONFIG; 1535 1536 /* 1537 * CTRL_NVSWITCH_GET_INGRESS_REQLINKID 1538 * 1539 * Control to query the ingress requestor link id. 1540 * 1541 * Parameters: 1542 * portNum [IN] 1543 * A valid port number present in the port masks returned by 1544 * NVSWITCH_GET_INFO 1545 * 1546 * requesterLinkID [OUT] 1547 * Ingress requestor link id for the provided port. 1548 */ 1549 1550 typedef struct nvswitch_get_ingress_reqlinkid_params 1551 { 1552 NvU32 portNum; 1553 NvU32 requesterLinkID; 1554 1555 } NVSWITCH_GET_INGRESS_REQLINKID_PARAMS; 1556 1557 /* 1558 * CTRL_NVSWITCH_UNREGISTER_LINK 1559 * 1560 * Control to unregister the request link (port). This ensures that the black- 1561 * listed link will not be initialized or trained by the driver. 1562 * 1563 * Parameters: 1564 * portNum [IN] 1565 * A valid port number present in the port masks returned by 1566 * NVSWITCH_GET_INFO 1567 */ 1568 1569 typedef struct nvswitch_unregister_link_params 1570 { 1571 NvU32 portNum; 1572 1573 } NVSWITCH_UNREGISTER_LINK_PARAMS; 1574 1575 /* 1576 * CTRL_RESET_AND_DRAIN_LINKS 1577 * 1578 * Control to reset and drain the links. Resets NVLinks and ensures to drain 1579 * backed up traffic. 1580 * 1581 * Parameters: 1582 * linkMask [IN] 1583 * A mask of link(s) to be reset. 1584 * For SV10, the linkMask must contain at least a link-pair (even-odd links). 1585 * 1586 * Returns: 1587 * NVL_SUCCESS if there were no errors 1588 * -NVL_BAD_PARAMS if input parameters are wrong. 1589 * -NVL_ERR_INVALID_STATE if other errors are present and a full-chip reset is required. 1590 * -NVL_INITIALIZATION_TOTAL_FAILURE if NPORT initialization failed and a retry is required. 1591 */ 1592 1593 typedef struct nvswitch_reset_and_drain_links_params 1594 { 1595 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 1596 1597 } NVSWITCH_RESET_AND_DRAIN_LINKS_PARAMS; 1598 1599 /* 1600 * CTRL_NVSWITCH_GET_NVLINK_STATUS 1601 * 1602 * enabledLinkMask 1603 * This field specifies the mask of available links on this subdevice. 1604 * linkInfo 1605 * This structure stores the per-link status of different NVLink 1606 * parameters. The link is identified using an index. 1607 * 1608 * Possible status values returned are: 1609 * NV_OK 1610 * NV_ERR_INVALID_PARAM_STRUCT 1611 * NV_ERR_INVALID_ARGUMENT 1612 */ 1613 1614 /* 1615 * NVSWITCH_NVLINK_DEVICE_INFO 1616 * 1617 * This structure stores information about the device to which this link is 1618 * associated 1619 * 1620 * deviceIdFlags 1621 * Bitmask that specifies which IDs are valid for the device 1622 * Refer NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_* for possible values 1623 * If NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI is set, PCI 1624 * information is valid 1625 * If NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID is set, UUID is 1626 * valid 1627 * domain, bus, device, function, pciDeviceId 1628 * PCI information for the device 1629 * deviceType 1630 * Type of the device 1631 * See NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_* for possible values 1632 * deviceUUID 1633 * This field specifies the device UUID of the device. Useful for 1634 * identifying the device (or version) 1635 */ 1636 1637 typedef struct 1638 { 1639 // ID Flags 1640 NvU32 deviceIdFlags; 1641 1642 // PCI Information 1643 NvU32 domain; 1644 NvU16 bus; 1645 NvU16 device; 1646 NvU16 function; 1647 NvU32 pciDeviceId; 1648 1649 // Device Type 1650 NV_DECLARE_ALIGNED(NvU64 deviceType, 8); 1651 1652 // Device UUID 1653 NvU8 deviceUUID[16]; 1654 } NVSWITCH_NVLINK_DEVICE_INFO; 1655 1656 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS 31:0 1657 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000) 1658 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001) 1659 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002) 1660 1661 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000) 1662 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001) 1663 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002) 1664 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003) 1665 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004) 1666 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FF) 1667 1668 #define NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFF) 1669 1670 /* 1671 * NVSWITCH_NVLINK_CAPS_* 1672 * 1673 * SUPPORTED 1674 * Set if NVLink is present and supported on this subdevice, NV_FALSE 1675 * otherwise. This field is used for *global* caps only and NOT for 1676 * per-link caps 1677 * P2P_SUPPORTED 1678 * Set if P2P over NVLink is supported on this subdevice, NV_FALSE 1679 * otherwise. 1680 * SYSMEM_ACCESS 1681 * Set if sysmem can be accessed over NVLink on this subdevice, NV_FALSE 1682 * otherwise. 1683 * PEER_ATOMICS 1684 * Set if P2P atomics are supported over NVLink on this subdevice, NV_FALSE 1685 * otherwise. 1686 * SYSMEM_ATOMICS 1687 * Set if sysmem atomic transcations are supported over NVLink on this 1688 * subdevice, NV_FALSE otherwise. 1689 * PEX_TUNNELING 1690 * Set if PEX tunneling over NVLink is supported on this subdevice, 1691 * NV_FALSE otherwise. 1692 * SLI_BRIDGE 1693 * GLOBAL: Set if SLI over NVLink is supported on this subdevice, NV_FALSE 1694 * otherwise. 1695 * LINK: Set if SLI over NVLink is supported on a link, NV_FALSE 1696 * otherwise. 1697 * SLI_BRIDGE_SENSABLE 1698 * GLOBAL: Set if the subdevice is capable of sensing SLI bridges, NV_FALSE 1699 * otherwise. 1700 * LINK: Set if the link is capable of sensing an SLI bridge, NV_FALSE 1701 * otherwise. 1702 * POWER_STATE_L0 1703 * Set if L0 is a supported power state on this subdevice/link, NV_FALSE 1704 * otherwise. 1705 * POWER_STATE_L1 1706 * Set if L1 is a supported power state on this subdevice/link, NV_FALSE 1707 * otherwise. 1708 * POWER_STATE_L2 1709 * Set if L2 is a supported power state on this subdevice/link, NV_FALSE 1710 * otherwise. 1711 * POWER_STATE_L3 1712 * Set if L3 is a supported power state on this subdevice/link, NV_FALSE 1713 * otherwise. 1714 * VALID 1715 * Set if this link is supported on this subdevice, NV_FALSE otherwise. 1716 * This field is used for *per-link* caps only and NOT for global caps. 1717 * 1718 */ 1719 1720 /* caps format is byte_index:bit_mask */ 1721 #define NVSWITCH_NVLINK_CAPS_SUPPORTED 0:0x01 1722 #define NVSWITCH_NVLINK_CAPS_P2P_SUPPORTED 0:0x02 1723 #define NVSWITCH_NVLINK_CAPS_SYSMEM_ACCESS 0:0x04 1724 #define NVSWITCH_NVLINK_CAPS_P2P_ATOMICS 0:0x08 1725 #define NVSWITCH_NVLINK_CAPS_SYSMEM_ATOMICS 0:0x10 1726 #define NVSWITCH_NVLINK_CAPS_PEX_TUNNELING 0:0x20 1727 #define NVSWITCH_NVLINK_CAPS_SLI_BRIDGE 0:0x40 1728 #define NVSWITCH_NVLINK_CAPS_SLI_BRIDGE_SENSABLE 0:0x80 1729 #define NVSWITCH_NVLINK_CAPS_POWER_STATE_L0 1:0x01 1730 #define NVSWITCH_NVLINK_CAPS_POWER_STATE_L1 1:0x02 1731 #define NVSWITCH_NVLINK_CAPS_POWER_STATE_L2 1:0x04 1732 #define NVSWITCH_NVLINK_CAPS_POWER_STATE_L3 1:0x08 1733 #define NVSWITCH_NVLINK_CAPS_VALID 1:0x10 1734 1735 /* 1736 * Size in bytes of nvlink caps table. This value should be one greater 1737 * than the largest byte_index value above. 1738 */ 1739 #define NVSWITCH_NVLINK_CAPS_TBL_SIZE 2 1740 1741 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000) 1742 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_1_0 (0x00000001) 1743 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_2_0 (0x00000002) 1744 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004) 1745 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005) 1746 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006) 1747 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007) 1748 1749 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000) 1750 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001) 1751 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002) 1752 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004) 1753 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_3_0 (0x00000005) 1754 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006) 1755 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007) 1756 1757 1758 /* 1759 * NVSWITCH_NVLINK_LINK_STATUS_INFO 1760 * 1761 * This structure stores the per-link status of different NVLink parameters. 1762 * 1763 * capsTbl 1764 * This is bit field for getting different global caps. The individual 1765 * bitfields are specified by NVSWITCH_NVLINK_CAPS_* 1766 * phyType 1767 * This field specifies the type of PHY (NVHS or GRS) being used for this 1768 * link. 1769 * subLinkWidth 1770 * This field specifies the no. of lanes per sublink. 1771 * linkState 1772 * This field specifies the current state of the link. See 1773 * NVSWITCH_GET_NVLINK_STATUS_LINK_STATE_* for possible values. 1774 * linkPowerState 1775 * This field specifies the current power state of the link. See 1776 * NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_* for possible values. 1777 * rxSublinkStatus 1778 * This field specifies the current state of RX sublink. See 1779 * NVSWITCH_GET_NVLINK_STATUS_SUBLINK_RX_STATE_* for possible values. 1780 * txSublinkStatus 1781 * This field specifies the current state of TX sublink. See 1782 * NVSWITCH_GET_NVLINK_STATUS_SUBLINK_TX_STATE_* for possible values. 1783 * nvlinkVersion 1784 * This field specifies the NVLink version supported by the link. 1785 * nciVersion 1786 * This field specifies the NCI version supported by the link. 1787 * phyVersion 1788 * This field specifies the version of PHY being used by the link. 1789 * nvlinkCommonClockSpeed 1790 * This field gives the value of nvlink common clock. 1791 * nvlinkRefClkSpeed 1792 * This field gives the value of nvlink refclk clock. 1793 * nvlinkRefClkType 1794 * This field specifies whether refclk is taken from NVHS reflck or PEX 1795 * refclk for the current GPU. See NVSWITCH_NVLINK_REFCLK_TYPE_INVALID* 1796 * for possible values. 1797 * nvlinkLinkClock 1798 * This field gives the actual clock/speed at which links is running. 1799 * connected 1800 * This field specifies if any device is connected on the other end of the 1801 * link 1802 * loopProperty 1803 * This field specifies if the link is a loopback/loopout link. See 1804 * NVSWITCH_NVLINK_STATUS_LOOP_PROPERTY_* for possible values. 1805 * laneRxdetStatusMask 1806 * This field reports the per-lane RX Detect status provided by MINION. 1807 * remoteDeviceLinkNumber 1808 * This field specifies the link number on the remote end of the link 1809 * remoteDeviceInfo 1810 * This field stores the device information for the remote end of the link 1811 * 1812 */ 1813 1814 typedef struct 1815 { 1816 // Top level capablilites 1817 NvU32 capsTbl; 1818 1819 NvU8 phyType; 1820 NvU8 subLinkWidth; 1821 1822 // Link and sublink states 1823 NvU32 linkState; 1824 NvU32 linkPowerState; 1825 NvU8 rxSublinkStatus; 1826 NvU8 txSublinkStatus; 1827 1828 // Indicates that lane reveral is in effect on this link. 1829 NvBool bLaneReversal; 1830 1831 NvU8 nvlinkVersion; 1832 NvU8 nciVersion; 1833 NvU8 phyVersion; 1834 1835 // Clock information 1836 1837 // These are being deprecated, please use HW Consistent terminology below 1838 NvU32 nvlinkLinkClockKHz; 1839 NvU32 nvlinkCommonClockSpeedKHz; 1840 NvU32 nvlinkRefClkSpeedKHz; 1841 NvU32 nvlinkCommonClockSpeedMhz; 1842 1843 // HW consistent terminology 1844 NvU32 nvlinkLineRateMbps; 1845 NvU32 nvlinkLinkDataRateKiBps; 1846 NvU32 nvlinkLinkClockMhz; 1847 NvU32 nvlinkRefClkSpeedMhz; 1848 NvU8 nvlinkRefClkType; 1849 1850 // Connection information 1851 NvBool connected; 1852 NvU8 loopProperty; 1853 NvU8 remoteDeviceLinkNumber; 1854 NvU8 localDeviceLinkNumber; 1855 1856 // 1857 // Added as part of NvLink 3.0 1858 // Note: SID has link info appended to it when provided by minion 1859 // 1860 NV_DECLARE_ALIGNED(NvU64 remoteLinkSid, 8); 1861 NV_DECLARE_ALIGNED(NvU64 localLinkSid, 8); 1862 1863 // LR10+ only 1864 NvU32 laneRxdetStatusMask; 1865 1866 // LS10+ only 1867 NvBool bIsRepeaterMode; 1868 1869 NVSWITCH_NVLINK_DEVICE_INFO remoteDeviceInfo; 1870 NVSWITCH_NVLINK_DEVICE_INFO localDeviceInfo; 1871 } NVSWITCH_NVLINK_LINK_STATUS_INFO; 1872 1873 /* NVLink link states */ 1874 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_INIT (0x00000000) 1875 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_HWPCFG (0x0000000c) 1876 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_HWCFG (0x00000001) 1877 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002) 1878 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003) 1879 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004) 1880 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_SLEEP (0x00000005) 1881 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006) 1882 #define NVSWITCH_NVLINK_STATUS_LINK_STATE_INVALID (0xFFFFFFFF) 1883 1884 /* NVLink link power states */ 1885 #define NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_L0 (0x00000000) 1886 #define NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_L1 (0x00000001) 1887 #define NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_INVALID (0xFFFFFFFF) 1888 1889 /* NVLink Tx sublink states */ 1890 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000) 1891 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004) 1892 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING (0x00000005) 1893 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE (0x00000006) 1894 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_OFF (0x00000007) 1895 #define NVSWITCH_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID (0x000000FF) 1896 1897 /* NVLink Rx sublink states */ 1898 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000) 1899 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004) 1900 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING (0x00000005) 1901 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE (0x00000006) 1902 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_OFF (0x00000007) 1903 #define NVSWITCH_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID (0x000000FF) 1904 1905 #define NVSWITCH_NVLINK_STATUS_PHY_NVHS (0x00000001) 1906 #define NVSWITCH_NVLINK_STATUS_PHY_GRS (0x00000002) 1907 #define NVSWITCH_NVLINK_STATUS_PHY_INVALID (0x000000FF) 1908 1909 /* Version information */ 1910 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_1_0 (0x00000001) 1911 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_2_0 (0x00000002) 1912 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_2_2 (0x00000004) 1913 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_3_0 (0x00000005) 1914 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_3_1 (0x00000006) 1915 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_4_0 (0x00000007) 1916 #define NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FF) 1917 1918 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001) 1919 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_2_0 (0x00000002) 1920 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_2_2 (0x00000004) 1921 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_3_0 (0x00000005) 1922 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_3_1 (0x00000006) 1923 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_4_0 (0x00000007) 1924 #define NVSWITCH_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FF) 1925 1926 #define NVSWITCH_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001) 1927 #define NVSWITCH_NVLINK_STATUS_NVHS_VERSION_INVALID (0x000000FF) 1928 1929 #define NVSWITCH_NVLINK_STATUS_GRS_VERSION_1_0 (0x00000001) 1930 #define NVSWITCH_NVLINK_STATUS_GRS_VERSION_INVALID (0x000000FF) 1931 1932 /* Connection properties */ 1933 #define NVSWITCH_NVLINK_STATUS_CONNECTED_TRUE (0x00000001) 1934 #define NVSWITCH_NVLINK_STATUS_CONNECTED_FALSE (0x00000000) 1935 1936 #define NVSWITCH_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK (0x00000001) 1937 #define NVSWITCH_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT (0x00000002) 1938 #define NVSWITCH_NVLINK_STATUS_LOOP_PROPERTY_NONE (0x00000000) 1939 1940 #define NVSWITCH_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID (0x000000FF) 1941 1942 #define NVSWITCH_NVLINK_MAX_LINKS 64 1943 1944 /* NVLink REFCLK types */ 1945 #define NVSWITCH_NVLINK_REFCLK_TYPE_INVALID (0x00) 1946 #define NVSWITCH_NVLINK_REFCLK_TYPE_NVHS (0x01) 1947 #define NVSWITCH_NVLINK_REFCLK_TYPE_PEX (0x02) 1948 1949 typedef struct 1950 { 1951 NV_DECLARE_ALIGNED(NvU64 enabledLinkMask, 8); 1952 NVSWITCH_NVLINK_LINK_STATUS_INFO linkInfo[NVSWITCH_NVLINK_MAX_LINKS]; 1953 } NVSWITCH_GET_NVLINK_STATUS_PARAMS; 1954 1955 /* List of supported capability type */ 1956 #define NVSWITCH_CAP_FABRIC_MANAGEMENT 0 1957 1958 /* 1959 * Max supported capabilities count. 1960 */ 1961 #define NVSWITCH_CAP_COUNT 1 1962 1963 /* 1964 * CTRL_NVSWITCH_ACQUIRE_CAPABILITY 1965 * 1966 * Upon success, user mode would acquire the requested capability 1967 * to perform privilege operations. This IOCTL will acquire one 1968 * capability at a time. 1969 * 1970 * Parameters: 1971 * capDescriptor [IN] 1972 * The OS file descriptor or handle representing the capability. 1973 * cap [IN] 1974 * The requested capability. One of the NVSWITCH_CAP_*. 1975 */ 1976 typedef struct 1977 { 1978 /* input parameters */ 1979 NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); 1980 NvU32 cap; 1981 1982 1983 } NVSWITCH_ACQUIRE_CAPABILITY_PARAMS; 1984 1985 /* 1986 * CTRL_NVSWITCH_GET_TEMPERATURE 1987 * 1988 * Control to query temperature of Nvswitch sensors. 1989 * 1990 * The Temperatures are returned in FXP 24.8(NvTemp) format. 1991 * 1992 * Parameters: 1993 * channelMask [IN] 1994 * Mask of all the thermal channels queried. 1995 * temperature [OUT] 1996 * Temperature of the channel. 1997 * status [OUT] 1998 * Return status of the channel. 1999 */ 2000 2001 #define NVSWITCH_NUM_MAX_CHANNELS 16 2002 2003 typedef struct 2004 { 2005 NvU32 channelMask; 2006 NvTemp temperature[NVSWITCH_NUM_MAX_CHANNELS]; 2007 NvS32 status[NVSWITCH_NUM_MAX_CHANNELS]; 2008 } NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS; 2009 2010 #define NVSWITCH_CTRL_THERMAL_EVENT_ID_WARN 0 2011 #define NVSWITCH_CTRL_THERMAL_EVENT_ID_OVERT 1 2012 2013 typedef struct 2014 { 2015 NvU32 thermalEventId; 2016 NvTemp temperatureLimit; 2017 } NVSWITCH_CTRL_GET_TEMPERATURE_LIMIT_PARAMS; 2018 2019 /* 2020 * Limerock thermal channels 2021 */ 2022 #define NVSWITCH_THERM_CHANNEL_LR10_TSENSE_MAX 0x00 2023 #define NVSWITCH_THERM_CHANNEL_LR10_TSENSE_OFFSET_MAX 0x01 2024 #define NVSWITCH_THERM_CHANNEL_LR10_TDIODE 0x02 2025 #define NVSWITCH_THERM_CHANNEL_LR10_TDIODE_OFFSET 0x03 2026 #define NVSWITCH_NUM_CHANNELS_LR10 4 2027 2028 /* 2029 * Laguna Seca thermal channels 2030 */ 2031 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_MAX 0x00 2032 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_OFFSET_MAX 0x01 2033 #define NVSWITCH_THERM_CHANNEL_LS10_TDIODE 0x02 2034 #define NVSWITCH_THERM_CHANNEL_LS10_TDIODE_OFFSET 0x03 2035 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_0 0x04 2036 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_1 0x05 2037 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_2 0x06 2038 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_3 0x07 2039 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_4 0x08 2040 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_5 0x09 2041 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_6 0x0A 2042 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_7 0x0B 2043 #define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_8 0x0C 2044 #define NVSWITCH_NUM_CHANNELS_LS10 13 2045 2046 /* 2047 * CTRL_NVSWITCH_GET_THROUGHPUT_COUNTERS 2048 * 2049 * Control for querying NVLINK throughput counters. 2050 * 2051 * Parameters: 2052 * counterMask [IN] 2053 * A mask of counter types. 2054 * One of the NVSWITCH_THROUGHPUT_COUNTERS_TYPE_* macros 2055 * linkMask [IN] 2056 * A mask of desired link(s) 2057 * counters [OUT] 2058 * Fetched counter values 2059 */ 2060 2061 /* NVLink throughput counter types */ 2062 2063 /* Nvlink throughput counters reading data flits in TX */ 2064 #define NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_TX (0x00000001) 2065 2066 /* Nvlink throughput counters reading data flits in RX */ 2067 #define NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_RX (0x00000002) 2068 2069 /* Nvlink throughput counters reading all flits in TX */ 2070 #define NVSWITCH_THROUGHPUT_COUNTERS_TYPE_RAW_TX (0x00000004) 2071 2072 /* Nvlink throughput counters reading all flits in RX */ 2073 #define NVSWITCH_THROUGHPUT_COUNTERS_TYPE_RAW_RX (0x00000008) 2074 2075 #define NVSWITCH_THROUGHPUT_COUNTERS_TYPE_MAX 4 2076 2077 typedef struct nvswitch_throughput_values 2078 { 2079 NvU64 values[NVSWITCH_THROUGHPUT_COUNTERS_TYPE_MAX]; 2080 2081 } NVSWITCH_THROUGHPUT_COUNTER_VALUES; 2082 2083 typedef struct nvswitch_get_throughput_counters 2084 { 2085 NvU16 counterMask; 2086 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 2087 NVSWITCH_THROUGHPUT_COUNTER_VALUES counters[NVSWITCH_MAX_PORTS]; 2088 2089 } NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS; 2090 2091 /* 2092 * CTRL_NVSWITCH_GET_BIOS_INFO 2093 * 2094 * Control call to get VBIOS information. 2095 * 2096 * Parameters: 2097 * version [OUT] 2098 * Vbios version in hex value. 2099 */ 2100 typedef struct nvswitch_get_bios_info 2101 { 2102 NvU64 version; 2103 } NVSWITCH_GET_BIOS_INFO_PARAMS; 2104 2105 #define NVSWITCH_INFOROM_VERSION_LEN 16 2106 /* 2107 * CTRL_NVSWITCH_GET_INFOROM_VERSION 2108 * 2109 * Control call to get INFOROM information. 2110 * 2111 * Parameters: 2112 * version [OUT] 2113 * Inforom version in char value. 2114 */ 2115 typedef struct nvswitch_get_inforom_version 2116 { 2117 NvU8 version[NVSWITCH_INFOROM_VERSION_LEN]; 2118 } NVSWITCH_GET_INFOROM_VERSION_PARAMS; 2119 2120 /* 2121 * CTRL_NVSWITCH_BLACKLIST_DEVICE 2122 * 2123 * Control to Blacklist a device. A blacklisted device will have 2124 * interrupts disabled, and opens/ioctls will fail. If a device is 2125 * blacklisted OOB then the setting is persistent. If a device is 2126 * blacklisted by the OS (such as module parameter) then the setting 2127 * persists for the OS until the config file is changed and the driver 2128 * reloaded. If a device is blacklisted by ioctl then the setting does 2129 * not persist across driver unload/reload. 2130 * 2131 * See BLACKLIST_REASON enum definition in interface/ioctl_common_nvswitch.h 2132 * 2133 * Parameters: 2134 * deviceReason [IN] 2135 * The reason the device is blacklisted 2136 */ 2137 typedef struct nvswitch_blacklist_device 2138 { 2139 NVSWITCH_DEVICE_BLACKLIST_REASON deviceReason; 2140 } NVSWITCH_BLACKLIST_DEVICE_PARAMS; 2141 2142 /* 2143 * CTRL_NVSWITCH_SET_FM_DRIVER_STATE 2144 * 2145 * Control to set the FM driver state for a device (heartbeat). 2146 * 2147 * Driver Fabric State is intended to reflect the state of the driver and 2148 * fabric manager. Once FM sets the Driver State to CONFIGURED, it is 2149 * expected the FM will send heartbeat updates. If the heartbeat is not 2150 * received before the session timeout, then the driver reports status 2151 * as MANAGER_TIMEOUT. See also control device ioctl CTRL_NVSWITCH_GET_DEVICES_V2. 2152 * 2153 * See DRIVER_FABRIC_STATE enum definition in interface/ioctl_common_nvswitch.h 2154 * 2155 * Parameters: 2156 * driverState [IN] 2157 * The driver state for the device 2158 */ 2159 typedef struct nvswitch_set_fm_driver_state 2160 { 2161 NVSWITCH_DRIVER_FABRIC_STATE driverState; 2162 } NVSWITCH_SET_FM_DRIVER_STATE_PARAMS; 2163 2164 /* 2165 * CTRL_NVSWITCH_SET_DEVICE_FABRIC_STATE 2166 * 2167 * Control to set the device fabric state 2168 * 2169 * Device Fabric State reflects the fabric state of the nvswitch device. 2170 * FM sets the Device Fabric State to CONFIGURED once FM is managing the 2171 * device. 2172 * 2173 * See DEVICE_FABRIC_STATE enum definition in interface/ioctl_common_nvswitch.h 2174 * 2175 * Parameters: 2176 * deviceState [IN] 2177 * The device fabric state 2178 */ 2179 typedef struct nvswitch_set_device_fabric_state 2180 { 2181 NVSWITCH_DEVICE_FABRIC_STATE deviceState; 2182 } NVSWITCH_SET_DEVICE_FABRIC_STATE_PARAMS; 2183 2184 /* 2185 * CTRL_NVSWITCH_SET_FM_HEARTBEAT_TIMEOUT 2186 * 2187 * Control to set the FM session heartbeat timeout for a device 2188 * 2189 * If a device is managed by FM, and if a heartbeat is not received 2190 * by the FM_HEARTBEAT_TIMEOUT, then the driver reports Driver 2191 * Fabric State as MANAGER_TIMEOUT. 2192 * 2193 * NVSWITCH_DEFAULT_FM_HEARTBEAT_TIMEOUT_MSEC is the default timeout 2194 * 2195 * Parameters: 2196 * fmTimeout [IN] 2197 * The FM timeout value for the device, in milliseconds 2198 */ 2199 typedef struct nvswitch_set_fm_heartbeat_timeout 2200 { 2201 NvU32 fmTimeout; 2202 } NVSWITCH_SET_FM_HEARTBEAT_TIMEOUT_PARAMS; 2203 #define NVSWITCH_DEFAULT_FM_HEARTBEAT_TIMEOUT_MSEC (10*1000) 2204 2205 /* 2206 * CTRL_NVSWITCH_SET_LINK_ERROR_STATE_INFO 2207 * 2208 * Control to set bitmask info of the 2209 * link training error 2210 * 2211 * Parameters: 2212 * attemptedTrainingMask0 [IN] 2213 * Bitmask of links that have been 2214 * attempted to train. 2215 * trainingErrorMask0 [IN] 2216 * Bitmaks of links that have an error 2217 * during training. 2218 */ 2219 typedef struct nvswitch_set_training_error_info 2220 { 2221 NvU64 attemptedTrainingMask0; 2222 NvU64 trainingErrorMask0; 2223 } NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS; 2224 2225 #define NVSWITCH_DEVICE_EVENT_FATAL 0 2226 #define NVSWITCH_DEVICE_EVENT_NONFATAL 1 2227 #define NVSWITCH_DEVICE_EVENT_PORT_UP 2 2228 #define NVSWITCH_DEVICE_EVENT_PORT_DOWN 3 2229 #define NVSWITCH_DEVICE_EVENT_FABRIC_STATE 4 2230 #define NVSWITCH_DEVICE_EVENT_INBAND_DATA 5 2231 #define NVSWITCH_DEVICE_EVENT_COUNT 6 2232 #define NVSWITCH_REGISTER_EVENTS_MAX_EVENT_IDS (500) 2233 2234 /* 2235 * CTRL_NVSWITCH_REGISTER_EVENTS 2236 * 2237 * Control to register event IDs with an OS descriptor 2238 * 2239 * This control allows for clients to register one or more event IDs 2240 * with an OS descriptor. After registering event IDs, clients may poll 2241 * the OS descriptor for the registered event. 2242 * 2243 * Subsequent calls to register_event will overwrite currently registered 2244 * event IDs. This allows the client to switch event polling as and when required. 2245 * Explicit unregister_events control call isn't necessary when the 2246 * client wishes to change the event types currently being monitored. 2247 * 2248 * On Linux, only a single event ID can be registered to each 2249 * OS descriptor at a time. Calling this control with 2250 * numEvents > 1 on Linux will cause an error to be returned. 2251 * 2252 * On Windows, the osDescriptor field should be a valid 2253 * Windows EVENT handle. 2254 * 2255 * osDescriptor is unused on other operating systems. 2256 * 2257 * Parameters: 2258 * eventIds [IN] 2259 * A buffer of event IDs to register for 2260 * numEvents [IN] 2261 * Number of valid elements in eventIds 2262 * osDescriptor [IN] 2263 * OS event handle (Windows only) 2264 */ 2265 typedef struct nvswitch_register_events 2266 { 2267 NvU32 eventIds[NVSWITCH_REGISTER_EVENTS_MAX_EVENT_IDS]; 2268 NvU32 numEvents; 2269 void *osDescriptor; 2270 } NVSWITCH_REGISTER_EVENTS_PARAMS; 2271 2272 /* 2273 * CTRL_NVSWITCH_UNREGISTER_EVENTS 2274 * 2275 * Control to unregister all event IDs from an OS descriptor 2276 * 2277 * This control unregisters all registered event IDs associated 2278 * with an OS descriptor. 2279 * 2280 * On Windows, the osDescriptor field should be a valid 2281 * Windows EVENT handle. 2282 * 2283 * osDescriptor is unused on other operating systems. 2284 * 2285 * Parameters: 2286 * osDescriptor [IN] 2287 * OS event handle (Windows only) 2288 */ 2289 typedef struct nvswitch_unregister_events 2290 { 2291 void *osDescriptor; 2292 } NVSWITCH_UNREGISTER_EVENTS_PARAMS; 2293 2294 /* 2295 * CTRL_NVSWITCH_GET_FATAL_ERROR_SCOPE 2296 * 2297 * Control to query if a fatal error is occurred on a port or device 2298 * 2299 * Parameters: 2300 * device [OUT] 2301 * Set to NV_TRUE if the nvswitch device encountered a fatal error 2302 * port [OUT] 2303 * An array of booleans indicating which ports 2304 * encountered a fatal error 2305 */ 2306 typedef struct nvswitch_get_fatal_error_scope_params 2307 { 2308 NvBool device; 2309 NvBool port[NVSWITCH_MAX_PORTS]; 2310 } NVSWITCH_GET_FATAL_ERROR_SCOPE_PARAMS; 2311 2312 /* 2313 * CTRL_NVSWITCH_SET_MC_RID_TABLE 2314 * 2315 * Control for programming an ingress multicast RID table entry. 2316 * This interface is only supported on LS10 architecture. All others will 2317 * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 2318 * 2319 * Parameters: 2320 * portNum [IN] 2321 * A valid port number present in the port masks returned by 2322 * NVSWITCH_GET_INFO 2323 * index [IN] 2324 * Index within the multicast RID table to be programmed. This is 2325 * equivalent to MCID. 2326 * extendedTable [IN] 2327 * boolean: Set the requested entry in the extended table 2328 * else set the requested entry in the main table 2329 * ports [IN] 2330 * The list of ports. For each multicast request, the address hash 2331 * selects the multicast port string, and hardware multicasts to ports 2332 * in that string. 2333 * vcHop [IN] 2334 * Array of VC hop values for each port. 2335 * mcSize [IN] 2336 * Number of ports in the multicast group (must be a nonzero value). 2337 * Must be the number of ports in the main table, plus the extended table 2338 * if that is used. 2339 * Must be the same for all spray groups. 2340 * Caller is responsible for ensuring the above conditions, as the driver 2341 * provides only minimal range checking. 2342 * numSprayGroups [IN] 2343 * Number of groups to spray over. This must be a nonzero value. 2344 * portsPerSprayGroup [IN] 2345 * Array, number of ports contained in each spray group. 2346 * Note these must all be the same size unless an extended entry 2347 * is used, 2348 * _and_ numSprayGroups is the same for both the main entry and extended 2349 * entry, 2350 * _and_ the sum of ports in the main and extended groups equals 2351 * mcSize for each spray group. 2352 * FM is responsible for providing the correct value. Driver provides only 2353 * minimal range checking. 2354 * replicaOffset [IN] 2355 * Array, offsets within each spray group to the primary replica port for the group. 2356 * The caller should specify mcSize primaryReplicas. 2357 * replicaValid [IN] 2358 * boolean: Array, set the primary replica according to the replicaOffset array. 2359 * else let hardware choose a default primary replica port 2360 * extendedPtr [IN] 2361 * pointer to the extended table to append to the multicast table entry 2362 * can only be valid in the main table entries 2363 * extendedValid [IN] 2364 * boolean: Use the extended index to append to the main table string. 2365 * else the main string specifies the complete operation for its MCID 2366 * noDynRsp [IN] 2367 * boolean: no dynamic alt selection on MC responses. This field has no meaning in 2368 * the extended table 2369 * entryValid 2370 * boolean: flag this entry in the MC RID table as valid 2371 */ 2372 2373 #define NVSWITCH_MC_MAX_PORTS 64 2374 #define NVSWITCH_MC_MAX_SPRAYGROUPS 16 2375 2376 #define NVSWITCH_MC_VCHOP_PASS 0 2377 #define NVSWITCH_MC_VCHOP_INVERT 1 2378 #define NVSWITCH_MC_VCHOP_FORCE0 2 2379 #define NVSWITCH_MC_VCHOP_FORCE1 3 2380 2381 typedef struct nvswitch_set_mc_rid_table_params 2382 { 2383 NvU32 portNum; 2384 NvU32 index; 2385 NvBool extendedTable; 2386 NvU32 ports[NVSWITCH_MC_MAX_PORTS]; 2387 NvU8 vcHop[NVSWITCH_MC_MAX_PORTS]; 2388 NvU32 mcSize; 2389 NvU32 numSprayGroups; 2390 NvU32 portsPerSprayGroup[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2391 NvU32 replicaOffset[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2392 NvBool replicaValid[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2393 NvU32 extendedPtr; 2394 NvBool extendedValid; 2395 NvBool noDynRsp; 2396 NvBool entryValid; 2397 } NVSWITCH_SET_MC_RID_TABLE_PARAMS; 2398 2399 /* 2400 * CTRL_NVSWITCH_GET_MC_RID_TABLE 2401 * 2402 * Control for reading an ingress multicast RID table entry. 2403 * This interface is only supported on LS10 architecture. All others will 2404 * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. 2405 * 2406 * Parameters: 2407 * portNum [IN] 2408 * A valid port number present in the port masks returned by 2409 * NVSWITCH_GET_INFO 2410 * index [IN] 2411 * Index within the multicast RID table to be retrieved. This is 2412 * equivalent to MCID. 2413 * extendedTable [IN] 2414 * boolean: Get the requested entry from the extended table. 2415 * Else get the requested entry from the main table. 2416 * ports [OUT] 2417 * The list of ports. Port order within spray groups is not guaranteed 2418 * to be preserved. 2419 * vcHop [OUT] 2420 * Array containing VC hop values for each entry in the ports array. 2421 * mcSize [OUT] 2422 * Number of ports in the multicast group. 2423 * numSprayGroups [OUT] 2424 * Number of groups to spray over. 2425 * portsPerSprayGroup [OUT] 2426 * Array, each element contains the number of ports within each corresponding 2427 * spray group. 2428 * replicaOffset [OUT] 2429 * Array, offsets within each spray group to the primary replica port 2430 * for the group. 2431 * replicaValid [OUT] 2432 * boolean: Array, specifies whether each entry in the replicaOffset 2433 * array is valid. 2434 * extendedPtr [OUT] 2435 * Pointer to the extended table appended to the main table entry. 2436 * Only valid for main table entries. 2437 * extendedValid [OUT] 2438 * boolean: Whether the extendedPtr is valid. 2439 * noDynRsp [IN] 2440 * boolean: no dynamic alt selection on MC responses. 2441 * This field has no meaning in the extended table. 2442 * entryValid 2443 * boolean: Whether this entry in the MC RID table is valid 2444 */ 2445 2446 typedef struct nvswitch_get_mc_rid_table_params 2447 { 2448 NvU32 portNum; 2449 NvU32 index; 2450 NvBool extendedTable; 2451 NvU32 ports[NVSWITCH_MC_MAX_PORTS]; 2452 NvU8 vcHop[NVSWITCH_MC_MAX_PORTS]; 2453 NvU32 mcSize; 2454 NvU32 numSprayGroups; 2455 NvU32 portsPerSprayGroup[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2456 NvU32 replicaOffset[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2457 NvBool replicaValid[NVSWITCH_MC_MAX_SPRAYGROUPS]; 2458 NvU32 extendedPtr; 2459 NvBool extendedValid; 2460 NvBool noDynRsp; 2461 NvBool entryValid; 2462 } NVSWITCH_GET_MC_RID_TABLE_PARAMS; 2463 2464 #define NVSWITCH_I2C_SMBUS_CMD_QUICK 0 2465 #define NVSWITCH_I2C_SMBUS_CMD_BYTE 1 2466 #define NVSWITCH_I2C_SMBUS_CMD_BYTE_DATA 2 2467 #define NVSWITCH_I2C_SMBUS_CMD_WORD_DATA 3 2468 2469 /* 2470 * NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW 2471 * 2472 * This structure provides data for the SMBUS Byte command. 2473 * 2474 * message [IN/OUT] 2475 * 8 Bit data message to read or write. 2476 */ 2477 typedef struct 2478 { 2479 NvU8 message; 2480 } NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW; 2481 2482 /* 2483 * NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_DATA_RW 2484 * 2485 * This structure provides data for the SMBUS Byte Data command. 2486 * 2487 * cmd [IN] 2488 * SMBUS input command. 2489 * message [IN/OUT] 2490 * 8 Bit data message to read or write. 2491 */ 2492 typedef struct 2493 { 2494 NvU8 cmd; 2495 NvU8 message; 2496 } NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_DATA_RW; 2497 2498 /* 2499 * NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_WORD_DATA_RW 2500 * 2501 * This structure provides data for the SMBUS Word Data command. 2502 * 2503 * cmd [IN] 2504 * SMBUS input command. 2505 * message [IN/OUT] 2506 * 16 Bit data message to read or write. 2507 */ 2508 typedef struct 2509 { 2510 NvU8 cmd; 2511 NvU16 message; 2512 } NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_WORD_DATA_RW; 2513 2514 typedef union 2515 { 2516 NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW smbusByte; 2517 NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_BYTE_DATA_RW smbusByteData; 2518 NVSWITCH_I2C_TRANSACTION_DATA_SMBUS_WORD_DATA_RW smbusWordData; 2519 } NVSWITCH_I2C_TRANSACTION_DATA; 2520 2521 /* 2522 * CTRL_NVSWITCH_I2C_SMBUS_COMMAND 2523 * 2524 * Control to issue SMBUS I2C transaction to an I2C device 2525 * 2526 * Parameters: 2527 * deviceAddr [IN] 2528 * The I2C Slave address to issue a transaction to. This is the unshifted, 2529 * normal 7-bit address. For example, the input would be address 0x50 for 2530 * device 0xA0. 2531 * port [IN] 2532 * The logical port/bus in which the I2C transaction is requested. 2533 * cmdType [IN] 2534 * The desired SMBUS command type. See NVSWITCH_I2C_SMBUS_CMD_*. 2535 * bRead [IN] 2536 * This field must be specified to indicate whether the 2537 * command is a write (FALSE) or a read (TRUE). 2538 * transactionData [IN/OUT] 2539 * The NVSWITCH_I2C_TRANSACTION_DATA union to be filled out/read back 2540 * depending on the SMBUS command type. 2541 */ 2542 typedef struct nvswitch_i2c_smbus_command_params 2543 { 2544 NvU16 deviceAddr; 2545 NvU32 port; 2546 NvU8 cmdType; 2547 NvBool bRead; 2548 NVSWITCH_I2C_TRANSACTION_DATA transactionData; 2549 } NVSWITCH_I2C_SMBUS_COMMAND_PARAMS; 2550 2551 /* 2552 * APIs for getting NVLink counters 2553 */ 2554 2555 // These are the bitmask definitions for different counter types 2556 2557 #define NVSWITCH_NVLINK_COUNTER_INVALID 0x00000000 2558 2559 #define NVSWITCH_NVLINK_COUNTER_TL_TX0 0x00000001 2560 #define NVSWITCH_NVLINK_COUNTER_TL_TX1 0x00000002 2561 #define NVSWITCH_NVLINK_COUNTER_TL_RX0 0x00000004 2562 #define NVSWITCH_NVLINK_COUNTER_TL_RX1 0x00000008 2563 2564 #define NVSWITCH_NVLINK_LP_COUNTERS_DL 0x00000010 2565 2566 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT 0x00010000 2567 2568 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i) (1 << (i + 17)) 2569 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE 8 2570 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 0x00020000 2571 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 0x00040000 2572 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 0x00080000 2573 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 0x00100000 2574 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 0x00200000 2575 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 0x00400000 2576 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 0x00800000 2577 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 0x01000000 2578 2579 #define NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY 0x02000000 2580 #define NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY 0x04000000 2581 2582 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_REPLAY 0x08000000 2583 2584 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED 0x10000000 2585 2586 #define NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_ECC_COUNTS 0x20000000 2587 2588 #define NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_PASS 0x40000000 2589 #define NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_FAIL 0x80000000 2590 2591 /* 2592 * Note that COUNTER_MAX_TYPES will need to be updated each time adding 2593 * a new counter type exceeds the existing value. 2594 * 2595 */ 2596 #define NVSWITCH_NVLINK_COUNTER_MAX_TYPES 32 2597 2598 /* 2599 * CTRL_NVSWITCH_GET_COUNTERS 2600 * This command gets the counts for different counter types. 2601 * 2602 * [in] linkId 2603 * This parameter specifies the TL link id/no for which we want to get 2604 * counters for. 2605 * 2606 * [in] counterMask 2607 * This parameter specifies the input mask for desired counter types. 2608 * 2609 * [out] bTx0TlCounterOverflow 2610 * This boolean is set to NV_TRUE if TX Counter 0 has rolled over. 2611 * 2612 * [out] bTx1TlCounterOverflow 2613 * This boolean is set to NV_TRUE if TX Counter 1 has rolled over. 2614 * 2615 * [out] bRx0TlCounterOverflow 2616 * This boolean is set to NV_TRUE if RX Counter 0 has rolled over. 2617 * 2618 * [out] bRx1TlCounterOverflow 2619 * This boolean is set to NV_TRUE if RX Counter 1 has rolled over. 2620 * 2621 * [out] nvlinkCounters 2622 * This array contains the error counts for each error type as requested from 2623 * the counterMask. The array indexes correspond to the mask bits one-to-one. 2624 */ 2625 2626 typedef struct 2627 { 2628 NvU8 linkId; 2629 NvU32 counterMask; 2630 NvBool bTx0TlCounterOverflow; 2631 NvBool bTx1TlCounterOverflow; 2632 NvBool bRx0TlCounterOverflow; 2633 NvBool bRx1TlCounterOverflow; 2634 NV_DECLARE_ALIGNED(NvU64 nvlinkCounters[NVSWITCH_NVLINK_COUNTER_MAX_TYPES], 8); 2635 } NVSWITCH_NVLINK_GET_COUNTERS_PARAMS; 2636 2637 /* 2638 * Structure to store the ECC error data. 2639 * valid 2640 * Is the lane valid or not 2641 * eccErrorValue 2642 * Value of the Error. 2643 * overflowed 2644 * If the error overflowed or not 2645 */ 2646 typedef struct 2647 { 2648 NvBool valid; 2649 NvU32 eccErrorValue; 2650 NvBool overflowed; 2651 } NVSWITCH_LANE_ERROR; 2652 2653 /* 2654 * Structure to store ECC error data for Links 2655 * errorLane array index corresponds to the lane number. 2656 * 2657 * errorLane[] 2658 * Stores the ECC error data per lane. 2659 */ 2660 typedef struct 2661 { 2662 NVSWITCH_LANE_ERROR errorLane[NVSWITCH_NVLINK_MAX_LANES]; 2663 NvU32 eccDecFailed; 2664 NvBool eccDecFailedOverflowed; 2665 } NVSWITCH_LINK_ECC_ERROR; 2666 2667 /* 2668 * CTRL_GET_NVLINK_ECC_ERRORS 2669 * 2670 * Control to get the values of ECC ERRORS 2671 * 2672 * Parameters: 2673 * linkMask [IN] 2674 * Links on which the ECC error data requested 2675 * A valid link/port mask returned by the port masks returned by 2676 * NVSWITCH_GET_INFO 2677 * errorLink[] [OUT] 2678 * Stores the ECC error related information for each link. 2679 * errorLink array index corresponds to the link Number. 2680 */ 2681 2682 typedef struct nvswitch_get_nvlink_ecc_errors 2683 { 2684 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 2685 NVSWITCH_LINK_ECC_ERROR errorLink[NVSWITCH_NVLINK_MAX_LINKS]; 2686 } NVSWITCH_GET_NVLINK_ECC_ERRORS_PARAMS; 2687 2688 #define NVSWITCH_NVLINK_MAX_CORRECTABLE_ERROR_DAYS 5 2689 #define NVSWITCH_NVLINK_MAX_CORRECTABLE_ERROR_MONTHS 3 2690 2691 typedef struct 2692 { 2693 NvU32 lastUpdated; 2694 NvU32 flitCrcErrorsPerMinute; 2695 NvU32 laneCrcErrorsPerMinute[NVSWITCH_NVLINK_MAX_LANES]; 2696 } NVSWITCH_NVLINK_CORRECTABLE_ERROR_RATES; 2697 2698 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_NVHS 0 2699 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_RESERVED 1 2700 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_OTHER 2 2701 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_NUM_TX_LP_ENTER 3 2702 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_NUM_TX_LP_EXIT 4 2703 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_SLEEP 5 2704 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_MAX_COUNTERS 6 2705 /* 2706 * CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS 2707 * 2708 * Reads NVLINK low power counters for given linkId 2709 * 2710 * Parameters: 2711 * linkId [IN] 2712 * ID of the link to be queried 2713 * counterValidMask [IN,OUT] 2714 * Mask of valid counters 2715 * counterValues [OUT] 2716 * Low power counter values returned 2717 */ 2718 typedef struct nvswitch_get_nvlink_lp_counters_params 2719 { 2720 NvU32 linkId; 2721 NvU32 counterValidMask; 2722 NvU32 counterValues[CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_MAX_COUNTERS]; 2723 } NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS; 2724 2725 /* 2726 * CTRL_NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES 2727 * 2728 * This command queries recent correctable error rates for the given link. 2729 * 2730 * The error rates specify the maximum number of errors per minute recorded 2731 * for the given link within a 24-hour period for daily maximums or a 30-day 2732 * period for monthly maximums. 2733 * 2734 * Parameters: 2735 * linkId [in] 2736 * NVLink link ID 2737 * dailyMaxCorrectableErrorRates[] [OUT] 2738 * NVLink daily max correctable error rate array 2739 * monthlyMaxCorrectableErrorRates[] [OUT] 2740 * NVLink monthly max correctable error rate array 2741 */ 2742 2743 typedef struct 2744 { 2745 NvU8 linkId; 2746 NVSWITCH_NVLINK_CORRECTABLE_ERROR_RATES dailyMaxCorrectableErrorRates[NVSWITCH_NVLINK_MAX_CORRECTABLE_ERROR_DAYS]; 2747 NVSWITCH_NVLINK_CORRECTABLE_ERROR_RATES monthlyMaxCorrectableErrorRates[NVSWITCH_NVLINK_MAX_CORRECTABLE_ERROR_MONTHS]; 2748 } NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS; 2749 2750 #define NVSWITCH_NVLINK_ERROR_READ_SIZE 128 //could not read the maximum size (721) of entries in one call 2751 2752 typedef enum 2753 { 2754 NVSWITCH_NVLINK_NO_ERROR = 0, 2755 2756 //DL RX Fatal Counts 2757 NVSWITCH_NVLINK_ERR_DL_RX_FAULT_DL_PROTOCOL_FATAL = 1000, 2758 NVSWITCH_NVLINK_ERR_DL_RX_FAULT_SUBLINK_CHANGE_FATAL, 2759 2760 //DL RX Correctable Accumulated Counts 2761 NVSWITCH_NVLINK_ERR_DL_RX_FLIT_CRC_CORR, 2762 NVSWITCH_NVLINK_ERR_DL_RX_LANE0_CRC_CORR, 2763 NVSWITCH_NVLINK_ERR_DL_RX_LANE1_CRC_CORR, 2764 NVSWITCH_NVLINK_ERR_DL_RX_LANE2_CRC_CORR, 2765 NVSWITCH_NVLINK_ERR_DL_RX_LANE3_CRC_CORR, 2766 NVSWITCH_NVLINK_ERR_DL_RX_LINK_REPLAY_EVENTS_CORR, 2767 2768 //DL TX Fatal Counts 2769 NVSWITCH_NVLINK_ERR_DL_TX_FAULT_RAM_FATAL, 2770 NVSWITCH_NVLINK_ERR_DL_TX_FAULT_INTERFACE_FATAL, 2771 NVSWITCH_NVLINK_ERR_DL_TX_FAULT_SUBLINK_CHANGE_FATAL, 2772 2773 //DL TX Correctable Accumulated Counts 2774 NVSWITCH_NVLINK_ERR_DL_TX_LINK_REPLAY_EVENTS_CORR, 2775 2776 //DL NA Fatal Counts 2777 NVSWITCH_NVLINK_ERR_DL_LTSSM_FAULT_UP_FATAL, 2778 NVSWITCH_NVLINK_ERR_DL_LTSSM_FAULT_DOWN_FATAL, 2779 2780 //DL NA Correctable Accumulated Counts 2781 NVSWITCH_NVLINK_ERR_DL_LINK_RECOVERY_EVENTS_CORR, 2782 2783 //TLC RX Fatal Counts 2784 NVSWITCH_NVLINK_ERR_TLC_RX_DL_HDR_PARITY_ERR_FATAL = 2000, 2785 NVSWITCH_NVLINK_ERR_TLC_RX_DL_DATA_PARITY_ERR_FATAL, 2786 NVSWITCH_NVLINK_ERR_TLC_RX_DL_CTRL_PARITY_ERR_FATAL, 2787 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_AE_FATAL, 2788 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_BE_FATAL, 2789 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_ADDR_ALIGN_FATAL, 2790 NVSWITCH_NVLINK_ERR_TLC_RX_PKTLEN_ERR_FATAL, 2791 NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL, 2792 NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL, 2793 NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL, 2794 NVSWITCH_NVLINK_ERR_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL, 2795 NVSWITCH_NVLINK_ERR_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL, 2796 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_CR_FATAL, 2797 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL, 2798 NVSWITCH_NVLINK_ERR_TLC_RX_HDR_OVERFLOW_FATAL, 2799 NVSWITCH_NVLINK_ERR_TLC_RX_DATA_OVERFLOW_FATAL, 2800 NVSWITCH_NVLINK_ERR_TLC_RX_STOMP_DETECTED_FATAL, 2801 NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CMD_ENC_FATAL, 2802 NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_DAT_LEN_ENC_FATAL, 2803 NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL, 2804 2805 //TLC RX Non-Fatal Counts 2806 NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL, 2807 NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL, 2808 NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL, 2809 NVSWITCH_NVLINK_ERR_TLC_RX_POISON_NONFATAL, 2810 NVSWITCH_NVLINK_ERR_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL, 2811 NVSWITCH_NVLINK_ERR_TLC_RX_ILLEGAL_PRI_WRITE_NONFATAL, 2812 2813 //TLC RX Fatal Counts addendum 2814 NVSWITCH_NVLINK_ERR_TLC_RX_HDR_RAM_ECC_DBE_FATAL, 2815 NVSWITCH_NVLINK_ERR_TLC_RX_DAT0_RAM_ECC_DBE_FATAL, 2816 NVSWITCH_NVLINK_ERR_TLC_RX_DAT1_RAM_ECC_DBE_FATAL, 2817 2818 //TLC TX Fatal Counts 2819 NVSWITCH_NVLINK_ERR_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL, 2820 NVSWITCH_NVLINK_ERR_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL, 2821 NVSWITCH_NVLINK_ERR_TLC_TX_NCISOC_PARITY_ERR_FATAL, 2822 2823 //TLC TX Non-Fatal Counts 2824 NVSWITCH_NVLINK_ERR_TLC_TX_ILLEGAL_PRI_WRITE_NONFATAL, 2825 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL, 2826 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL, 2827 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL, 2828 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL, 2829 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL, 2830 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL, 2831 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL, 2832 NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL, 2833 NVSWITCH_NVLINK_ERR_TLC_TX_POISON_NONFATAL, 2834 NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_HW_ERR_NONFATAL, 2835 NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_UR_ERR_NONFATAL, 2836 NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_PRIV_ERR_NONFATAL, 2837 NVSWITCH_NVLINK_ERR_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL, 2838 NVSWITCH_NVLINK_ERR_TLC_TX_RSP_DAT_RAM_ECC_DBE_NONFATAL, 2839 NVSWITCH_NVLINK_ERR_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL, 2840 NVSWITCH_NVLINK_ERR_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL, 2841 2842 //NVLIPT Fatal Counts 2843 NVSWITCH_NVLINK_ERR_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL = 3000, 2844 NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL, 2845 NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL, 2846 NVSWITCH_NVLINK_ERR_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL, 2847 NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PLL_TIMEOUT_FATAL, 2848 NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PHYARB_TIMEOUT_FATAL, 2849 2850 //NVLIPT Non-Fatal Counts 2851 NVSWITCH_NVLINK_ERR_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL, 2852 NVSWITCH_NVLINK_ERR_NVLIPT_FAILED_MINION_REQUEST_NONFATAL, 2853 NVSWITCH_NVLINK_ERR_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL, 2854 NVSWITCH_NVLINK_ERR_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL, 2855 NVSWITCH_NVLINK_ERR_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL, 2856 NVSWITCH_NVLINK_ERR_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL, 2857 } NVSWITCH_NVLINK_ERROR_TYPE; 2858 2859 typedef struct 2860 { 2861 NvU8 instance; 2862 NvU32 error; //NVSWITCH_NVLINK_ERROR_TYPE 2863 NvU32 timeStamp; 2864 NvU64 count; 2865 } NVSWITCH_NVLINK_ERROR_ENTRY; 2866 2867 /* 2868 * CTRL_NVSWITCH_GET_NVLINK_ERROR_COUNTS 2869 * 2870 * Control to get the NVLINK errors from inforom cache 2871 * 2872 * Parameters: 2873 * errorIndex [IN/OUT] 2874 * On input: The index of the first NVLink error to retrieve from inforom cache 2875 * On output: The index of the first error to retrieve after the previous call. 2876 * errorCount [OUT] 2877 * Number of errors returned by the call. Currently, errorCount is limited 2878 * by NVSWITCH_NVLINK_ERROR_READ_SIZE. In order to query all the errors, a 2879 * client needs to keep calling the control till errorCount is zero. 2880 * errorLog[] [OUT] 2881 * NVLINK error array 2882 */ 2883 2884 typedef struct 2885 { 2886 NvU32 errorIndex; 2887 NvU32 errorCount; 2888 NVSWITCH_NVLINK_ERROR_ENTRY errorLog[NVSWITCH_NVLINK_ERROR_READ_SIZE]; 2889 } NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS; 2890 2891 #define NVSWITCH_ECC_ERRORS_MAX_READ_COUNT 128 2892 2893 typedef struct 2894 { 2895 NvU32 sxid; 2896 NvU8 linkId; 2897 NvU32 lastErrorTimestamp; 2898 NvBool bAddressValid; 2899 NvU32 address; 2900 NvU32 correctedCount; 2901 NvU32 uncorrectedCount; 2902 } NVSWITCH_ECC_ERROR_ENTRY; 2903 2904 /* 2905 * CTRL_NVSWITCH_GET_ECC_ERROR_COUNTS 2906 * 2907 * Control to get the ECC error counts and logs from inforom 2908 * 2909 * Parameters: 2910 * uncorrectedTotal [out] 2911 * uncorrected ECC errors count 2912 * correctedTotal [out] 2913 * corrected ECC errors count 2914 * errorCount [out] 2915 * recorded error log count in the array 2916 * errorLog[] [OUT] 2917 * ECC errors array 2918 */ 2919 2920 typedef struct 2921 { 2922 NvU64 uncorrectedTotal; 2923 NvU64 correctedTotal; 2924 NvU32 errorCount; 2925 NVSWITCH_ECC_ERROR_ENTRY errorLog[NVSWITCH_ECC_ERRORS_MAX_READ_COUNT]; 2926 } NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS; 2927 2928 #define NVSWITCH_SXID_ENTRIES_NUM 10 2929 2930 typedef struct 2931 { 2932 NvU32 sxid; 2933 NvU32 timestamp; 2934 } NVSWITCH_SXID_ENTRY; 2935 2936 /* 2937 * CTRL_NVSWITCH_GET_SXIDS 2938 * 2939 * Control to get the NVSwitch SXID errors from inforom cache 2940 * 2941 * Parameters: 2942 * sxidCount [OUT] 2943 * The total SXID error number 2944 * sxidFirst [OUT] 2945 * The array of the first NVSWITCH_SXID_ENTRIES_NUM (10) SXIDs 2946 * sxidLast [OUT] 2947 * The array of the last NVSWITCH_SXID_ENTRIES_NUM (10) SXIDs 2948 */ 2949 2950 typedef struct 2951 { 2952 NvU32 sxidCount; 2953 NVSWITCH_SXID_ENTRY sxidFirst[NVSWITCH_SXID_ENTRIES_NUM]; 2954 NVSWITCH_SXID_ENTRY sxidLast[NVSWITCH_SXID_ENTRIES_NUM]; 2955 } NVSWITCH_GET_SXIDS_PARAMS; 2956 2957 /* 2958 * CTRL_NVSWITCH_GET_FOM_VALUES 2959 * This command gives the FOM values to MODS 2960 * 2961 * [in] linkId 2962 * Link number on which the FOM values are requested 2963 * [out] numLanes 2964 * This field specifies the no. of lanes per link 2965 * [out] figureOfMetritValues 2966 * This field contains the FOM values per lane 2967 */ 2968 2969 typedef struct nvswitch_get_fom_values_params 2970 { 2971 NvU32 linkId; 2972 NvU8 numLanes; 2973 NvU16 figureOfMeritValues[NVSWITCH_NVLINK_MAX_LANES]; 2974 } NVSWITCH_GET_FOM_VALUES_PARAMS; 2975 2976 /* 2977 * CTRL_NVSWITCH_SET_RESIDENCY_BINS 2978 * 2979 * Control for setting residency bins. 2980 * 2981 * Parameters: 2982 * [in] table_select 2983 * Which table to return. 2984 * [in] NVSWITCH_RESIDENCY_BIN 2985 * Residency thresholds. The thresholds would be only applied to the 2986 * enabled ports. 2987 * NVSWITCH_GET_INFO can be used to query enabled ports. 2988 */ 2989 2990 typedef struct nvswitch_residency_bin 2991 { 2992 NvU32 lowThreshold; /* in nsec */ 2993 NvU32 hiThreshold; /* in nsec */ 2994 2995 } NVSWITCH_RESIDENCY_THRESHOLDS; 2996 2997 #define NVSWITCH_TABLE_SELECT_MULTICAST 0 2998 #define NVSWITCH_TABLE_SELECT_REDUCTION 1 2999 3000 typedef struct nvswitch_set_residency_bins 3001 { 3002 NvU32 table_select; // NVSWITCH_TABLE_SELECT_MULTICAST/_REDUCTION 3003 NVSWITCH_RESIDENCY_THRESHOLDS bin; 3004 3005 } NVSWITCH_SET_RESIDENCY_BINS; 3006 3007 /* 3008 * CTRL_NVSWITCH_GET_RESIDENCY_BINS 3009 * 3010 * Control for querying multicast & reduction residency histogram. 3011 * 3012 * Parameters: 3013 * [in] linkId 3014 * Link number on which the residency histogram is requested 3015 * [in] table_select 3016 * Which table to return. 3017 * 3018 * [in] bin 3019 * Residency thresholds. 3020 * [out] residency 3021 * Residency data/histogram format. The data will be available for the 3022 * enabled/supported ports returned by NVSWITCH_GET_INFO. 3023 */ 3024 3025 typedef struct nvswitch_residency_bins 3026 { 3027 NV_DECLARE_ALIGNED(NvU64 low, 8); 3028 NV_DECLARE_ALIGNED(NvU64 medium, 8); 3029 NV_DECLARE_ALIGNED(NvU64 high, 8); 3030 } NVSWITCH_RESIDENCY_BINS; 3031 3032 #define NVSWITCH_RESIDENCY_SIZE 128 3033 3034 typedef struct nvswitch_get_residency_bins 3035 { 3036 NvU32 link; 3037 NvU32 table_select; // NVSWITCH_TABLE_SELECT_MULTICAST/_REDUCTION 3038 NVSWITCH_RESIDENCY_THRESHOLDS bin; 3039 NVSWITCH_RESIDENCY_BINS residency[NVSWITCH_RESIDENCY_SIZE]; 3040 } NVSWITCH_GET_RESIDENCY_BINS; 3041 3042 /* 3043 * CTRL_NVSWITCH_GET_RB_STALL_BUSY 3044 * 3045 * Control for querying reduction buffer stall/busy counters. 3046 * 3047 * Parameters: 3048 * [in] linkId 3049 * Link number on which the stall/busy counters are requested 3050 * [in] table_select 3051 * Which table to return. 3052 * 3053 * [out] stall_busy 3054 * Reduction buffer stall/busy counters. The data will be available for the 3055 * enabled/supported ports returned by NVSWITCH_GET_INFO. 3056 */ 3057 3058 typedef struct nvswitch_stall_busy 3059 { 3060 NV_DECLARE_ALIGNED(NvU64 time, 8); // in ns 3061 NV_DECLARE_ALIGNED(NvU64 stall, 8); 3062 NV_DECLARE_ALIGNED(NvU64 busy, 8); 3063 } NVSWITCH_STALL_BUSY; 3064 3065 typedef struct nvswitch_get_rd_stall_busy 3066 { 3067 NvU32 link; 3068 NvU32 table_select; // NVSWITCH_TABLE_SELECT_MULTICAST/_REDUCTION 3069 NVSWITCH_STALL_BUSY vc0; 3070 NVSWITCH_STALL_BUSY vc1; 3071 } NVSWITCH_GET_RB_STALL_BUSY; 3072 3073 /* 3074 * CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR 3075 * 3076 * Control for querying multicast ID error vector 3077 * 3078 * Parameters: 3079 * [in] link 3080 * Link number on which the error vector is requested 3081 * 3082 * [out] error_vector[] 3083 * Bit vector of multicast IDs that are in error. 3084 */ 3085 3086 #define NVSWITCH_MC_ID_ERROR_VECTOR_COUNT 128 3087 3088 typedef struct nvswitch_get_multicast_id_error_vector 3089 { 3090 NvU32 link; 3091 NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / 32]; 3092 } NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR; 3093 3094 /* 3095 * CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR 3096 * 3097 * Control for clearing multicast ID error vector 3098 * 3099 * Parameters: 3100 * [in] link 3101 * Link number on which the error vector clear is requested 3102 * 3103 * [in] error_vector[] 3104 * Bit vector of multicast IDs to clear error. 3105 */ 3106 3107 typedef struct nvswitch_clear_multicast_id_error_vector 3108 { 3109 NvU32 link; 3110 NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / 32]; 3111 } NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR; 3112 3113 /* 3114 * NVSWITCH_NVLINK_ERR_INFO 3115 * Error information per link 3116 * 3117 * Parameters: 3118 * TLErrlog 3119 * Returns the error mask for NVLINK TL errors 3120 * Used in Pascal 3121 * 3122 * TLIntrEn 3123 * Returns the intr enable mask for NVLINK TL errors 3124 * Used in Pascal 3125 * 3126 * TLCTxErrStatus0 3127 * Returns the TLC Tx Error Mask 0 3128 * Used in Volta 3129 * 3130 * TLCRxErrStatus0 3131 * Returns the TLC Rx Error Mask 0 3132 * Used in Volta 3133 * 3134 * TLCRxErrStatus1 3135 * Returns the TLC Rx Error Mask 1 3136 * Used in Volta 3137 * 3138 * TLCTxErrLogEn0 3139 * Returns the TLC Tx Error Log En 0 3140 * Used in Volta 3141 * 3142 * TLCRxErrLogEn0 3143 * Returns the TLC Rx Error Log En 0 3144 * Used in Volta 3145 * 3146 * TLCRxErrLogEn1 3147 * Returns the TLC Rx Error Log En 1 3148 * Used in Volta 3149 * 3150 * MIFTxErrStatus0 3151 * Returns the MIF Rx Error Mask 0 3152 * Used in Volta 3153 * 3154 * MIFRxErrStatus0 3155 * Returns the MIF Tx Error Mask 0 3156 * Used in Volta 3157 * 3158 * DLSpeedStatusTx 3159 * Returns the NVLINK DL speed status for sublink Tx 3160 * 3161 * DLSpeedStatusRx 3162 * Returns the NVLINK DL speed status for sublink Rx 3163 * 3164 * bExcessErrorDL 3165 * Returns true for excessive error rate interrupt from DL 3166 */ 3167 typedef struct 3168 { 3169 NvU32 TLErrlog; 3170 NvU32 TLIntrEn; 3171 NvU32 TLCTxErrStatus0; 3172 NvU32 TLCRxErrStatus0; 3173 NvU32 TLCRxErrStatus1; 3174 NvU32 TLCTxErrLogEn0; 3175 NvU32 TLCRxErrLogEn0; 3176 NvU32 TLCRxErrLogEn1; 3177 NvU32 MIFTxErrStatus0; 3178 NvU32 MIFRxErrStatus0; 3179 NvU32 DLSpeedStatusTx; 3180 NvU32 DLSpeedStatusRx; 3181 NvBool bExcessErrorDL; 3182 } NVSWITCH_NVLINK_ERR_INFO; 3183 3184 /* 3185 * CTRL_NVSWITCH_GET_ERR_INFO 3186 * This command is used to query the NVLINK error information 3187 * 3188 * Possible status values returned are: 3189 * NV_OK 3190 * NV_ERR_NOT_SUPPORTED 3191 */ 3192 3193 /* 3194 * NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS 3195 * 3196 * linkMask 3197 * Returns the mask of links enabled 3198 * 3199 * linkErrInfo 3200 * Returns the error information for all the links 3201 */ 3202 typedef struct 3203 { 3204 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 3205 NVSWITCH_NVLINK_ERR_INFO linkErrInfo[NVSWITCH_NVLINK_MAX_LINKS]; 3206 } NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS; 3207 3208 #define NVSWITCH_INBAND_DATA_SIZE 4096 3209 3210 /* 3211 * CTRL_NVSWITCH_INBAND_SEND_DATA 3212 * 3213 * Control call used for sending data over inband. 3214 * 3215 * Parameters: 3216 * 3217 * dataSize[IN] 3218 * Valid data in the buffer 3219 * 3220 * linkId[IN] 3221 * Link number on which the data needs to be sent 3222 * 3223 * buffer[IN] 3224 * Data which needs to be sent on the other side 3225 * 3226 * dataSent [OUT] 3227 * Bytes of data which were sent to the other side 3228 */ 3229 typedef struct nvswitch_inband_send_data_params 3230 { 3231 /* input parameters */ 3232 NvU32 dataSize; 3233 NvU32 linkId; 3234 NvU8 buffer[NVSWITCH_INBAND_DATA_SIZE]; 3235 3236 /* output parameters */ 3237 NvU32 dataSent; 3238 } NVSWITCH_INBAND_SEND_DATA_PARAMS; 3239 3240 /* 3241 * CTRL_NVSWITCH_INBAND_READ_DATA 3242 * 3243 * Control call used for reading data received over inband 3244 * 3245 * Parameters: 3246 * 3247 * linkId[IN] 3248 * Link number on which the data needs to be read. 3249 * 3250 * dataSize[OUT] 3251 * Valid data in the buffer 3252 * 3253 * buffer[OUT] 3254 * Data which needs to be read from the other side 3255 */ 3256 typedef struct nvswitch_inband_read_data_params 3257 { 3258 /* input parameters */ 3259 NvU32 linkId; 3260 3261 /* output parameters */ 3262 NvU32 dataSize; 3263 NvU8 buffer[NVSWITCH_INBAND_DATA_SIZE]; 3264 } NVSWITCH_INBAND_READ_DATA_PARAMS; 3265 3266 /* 3267 * CTRL_NVSWITCH_INBAND_FLUSH_DATA 3268 * 3269 * Flushing all the pending data for the corresponding link. 3270 * Messages would be stored in a queue. If flush is send all the 3271 * pending messages which are there for that linkId will be deleted. 3272 * 3273 * Parameters: 3274 * 3275 * linkMask[IN] 3276 * Mask of Links on which the data needs to be flushed. 3277 */ 3278 typedef struct nvswitch_inband_flush_data_params 3279 { 3280 /* input parameters */ 3281 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 3282 3283 /* output parameters */ 3284 } NVSWITCH_INBAND_FLUSH_DATA_PARAMS; 3285 3286 /* 3287 * CTRL_NVSWITCH_INBAND_PENDING_DATA_STATS 3288 * 3289 * Control call to check which links have pending data 3290 * 3291 * Parameters: 3292 * 3293 * linkMask[OUT] 3294 * Mask of the links which has data on it. 3295 */ 3296 typedef struct nvswitch_inband_pending_data_stats_params 3297 { 3298 /* output parameters */ 3299 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 3300 } NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS; 3301 3302 /* 3303 * CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 3304 * 3305 * Control for querying the board part number 3306 * 3307 * Parameters: 3308 * [out] data[] 3309 * Byte vector of the board part number. 3310 */ 3311 3312 #define NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES 20 3313 3314 typedef struct nvswitch_get_board_part_number_vector 3315 { 3316 NvU8 data[NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES]; 3317 } NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR; 3318 3319 #define NVSWITCH_GET_SW_INFO_COUNT_MAX 32 3320 3321 typedef enum nvswitch_get_sw_info_index 3322 { 3323 NVSWITCH_GET_SW_INFO_INDEX_INFOROM_NVL_SUPPORTED = 0x0, 3324 NVSWITCH_GET_SW_INFO_INDEX_INFOROM_BBX_SUPPORTED 3325 } NVSWITCH_GET_SW_INFO_INDEX; 3326 3327 typedef struct nvswitch_get_sw_info_params 3328 { 3329 NvU32 count; 3330 NvU32 index[NVSWITCH_GET_SW_INFO_COUNT_MAX]; 3331 NvU32 info[NVSWITCH_GET_SW_INFO_COUNT_MAX]; 3332 } NVSWITCH_GET_SW_INFO_PARAMS; 3333 3334 /* 3335 * CTRL_NVSWITCH_CLEAR_COUNTERS 3336 * This command clears/resets the counters for the specified types. 3337 * 3338 * [in] linkMask 3339 * This parameter specifies for which links we want to clear the 3340 * counters. 3341 * 3342 * [in] counterMask 3343 * This parameter specifies the input mask for desired counters to be 3344 * cleared. Note that all counters cannot be cleared. 3345 * 3346 * NOTE: Bug# 2098529: On Turing all DL errors and LP counters are cleared 3347 * together. They cannot be cleared individually per error type. RM 3348 * would possibly move to a new API on Ampere and beyond 3349 */ 3350 3351 typedef struct 3352 { 3353 NV_DECLARE_ALIGNED(NvU64 linkMask, 8); 3354 NvU32 counterMask; 3355 } NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS; 3356 3357 /* 3358 * NVSWITCH_CTRL_I2C_DEVICE_INFO 3359 * 3360 * This structure describes the basic I2C Device information. 3361 * 3362 * type 3363 * This field return the type of device NVSWITCH_I2C_DEVICE_<xyz> 3364 * i2cAddress 3365 * This field contains the 7 bit/10 bit address of the I2C device. 3366 * i2cLogicalPort 3367 * This field contains the Logical port of the I2C device. 3368 */ 3369 3370 typedef enum 3371 { 3372 NVSWITCH_I2C_PORT_I2CA = 0, 3373 NVSWITCH_I2C_PORT_I2CB, 3374 NVSWITCH_I2C_PORT_I2CC, 3375 NVSWITCH_I2C_PORT_I2CD 3376 } NVSWITCH_I2C_PORT_TYPE; 3377 3378 typedef enum 3379 { 3380 NVSWITCH_I2C_DEVICE_UNKNOWN = 0, 3381 3382 NVSWITCH_I2C_DEVICE_SKIP = 0xFF 3383 3384 } NVSWITCH_I2C_DEVICE_TYPE; 3385 3386 typedef struct 3387 { 3388 NVSWITCH_I2C_DEVICE_TYPE type; 3389 NvU32 i2cAddress; 3390 NVSWITCH_I2C_PORT_TYPE i2cPortLogical; 3391 } NVSWITCH_CTRL_I2C_DEVICE_INFO; 3392 3393 /* Maximum number of I2C devices in DCB */ 3394 #define NVSWITCH_CTRL_I2C_MAX_DEVICES 32 3395 3396 /* 3397 * CTRL_NVSWITCH_I2C_TABLE_GET_DEV_INFO 3398 * 3399 * RM Control to get I2C device info from the DCB I2C Devices Table. 3400 * 3401 * i2cDevCount 3402 * The value of this parameter will give the number of valid 3403 * I2C devices returned in structure. 3404 * 3405 * i2cDevInfo[] 3406 * For each device the control call will report the device info 3407 * 3408 */ 3409 typedef struct 3410 { 3411 NvU8 i2cDevCount; 3412 NVSWITCH_CTRL_I2C_DEVICE_INFO i2cDevInfo[NVSWITCH_CTRL_I2C_MAX_DEVICES]; 3413 } NVSWITCH_CTRL_I2C_GET_DEV_INFO_PARAMS; 3414 3415 //! Maximum size of index. 3416 #define NVSWITCH_CTRL_I2C_INDEX_LENGTH_MAX 4 3417 3418 /*! Set if the command should begin with a START. For a transactional 3419 * interface (highly recommended), this should always be _SEND. 3420 */ 3421 #define NVSWITCH_CTRL_I2C_FLAGS_START 0:0 3422 #define NVSWITCH_CTRL_I2C_FLAGS_START_NONE 0 3423 #define NVSWITCH_CTRL_I2C_FLAGS_START_SEND 1 3424 3425 /*! 3426 * Indicate whether to send a repeated start between the index and 3427 * message phrases. 3428 * 3429 * This flag will send a restart between each index and message. This should 3430 * be set for reads, but rarely (if ever) for writes. 3431 * 3432 * A RESTART is required when switching directions; this is called a combined 3433 * format. These are typically used in indexed read commands, where an index 3434 * is written to the device to indicate what register(s) to read, and then 3435 * the register is read. Almost always, indexed writes do not require a 3436 * restart, though some devices will accept them. However, this flag should 3437 * be used for writes in the rare case where a restart should be sent between 3438 * the last index and the message. 3439 */ 3440 #define NVSWITCH_CTRL_I2C_FLAGS_RESTART 1:1 3441 #define NVSWITCH_CTRL_I2C_FLAGS_RESTART_NONE 0 3442 #define NVSWITCH_CTRL_I2C_FLAGS_RESTART_SEND 1 3443 3444 /*! Set if the command should conclude with a STOP. For a transactional 3445 * interface (highly recommended), this should always be _SEND. 3446 */ 3447 #define NVSWITCH_CTRL_I2C_FLAGS_STOP 2:2 3448 #define NVSWITCH_CTRL_I2C_FLAGS_STOP_NONE 0 3449 #define NVSWITCH_CTRL_I2C_FLAGS_STOP_SEND 1 3450 3451 /*! The slave addressing mode: 7-bit (most common) or 10-bit. It is possible 3452 * but not recommended to send no address at all using _NONE. 3453 */ 3454 #define NVSWITCH_CTRL_I2C_FLAGS_ADDRESS_MODE 4:3 3455 #define NVSWITCH_CTRL_I2C_FLAGS_ADDRESS_MODE_NO_ADDRESS 0 3456 #define NVSWITCH_CTRL_I2C_FLAGS_ADDRESS_MODE_7BIT 1 3457 #define NVSWITCH_CTRL_I2C_FLAGS_ADDRESS_MODE_10BIT 2 3458 3459 //! The length of the index. If length is 0, no index will be sent. 3460 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH 7:5 3461 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH_ZERO 0 3462 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH_ONE 1 3463 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH_TWO 2 3464 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH_THREE 3 3465 #define NVSWITCH_CTRL_I2C_FLAGS_INDEX_LENGTH_MAXIMUM NVSWITCH_CTRL_I2C_INDEX_LENGTH_MAX 3466 3467 /*! The flavor to use: software bit-bang or hardware controller. The hardware 3468 * controller is faster, but is not necessarily available or capable. 3469 */ 3470 #define NVSWITCH_CTRL_I2C_FLAGS_FLAVOR 8:8 3471 #define NVSWITCH_CTRL_I2C_FLAGS_FLAVOR_HW 0 3472 #define NVSWITCH_CTRL_I2C_FLAGS_FLAVOR_SW 1 3473 3474 /*! The target speed at which to drive the transaction at. 3475 * 3476 * Note: The lib reserves the right to lower the speed mode if the I2C master 3477 * implementation cannot handle the speed given. 3478 */ 3479 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE 11:9 3480 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_DEFAULT 0x00000000 3481 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_100KHZ 0x00000003 3482 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_200KHZ 0x00000004 3483 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_300KHZ 0x00000005 3484 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_400KHZ 0x00000006 3485 #define NVSWITCH_CTRL_I2C_FLAGS_SPEED_MODE_1000KHZ 0x00000007 3486 3487 /* 3488 * NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE 3489 * A client uses this field to specify a transaction mode. 3490 * Possible values are: 3491 * NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL 3492 * The default, this value indicates to use the normal I2C transaction 3493 * mode which will involve read/write operations depending on client's 3494 * needs. 3495 * NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING 3496 * This value specifies that the device only needs to be pinged. No need 3497 * of performing a complete read/write transaction. This will address 3498 * the device to be pinged but not send any data. On receiving an ACK, 3499 * we will get a confirmation on the device's availability. 3500 * PING requires that: 3501 * _START = _SEND 3502 * _RESTART = _NONE 3503 * _STOP = _SEND 3504 * _ADDRESS_MODE != _NO_ADDRESS 3505 * _INDEX_LENGTH = _ZERO 3506 * messageLength = 0 3507 */ 3508 #define NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE 12:12 3509 #define NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE_NORMAL (0x00000000) 3510 #define NVSWITCH_CTRL_I2C_FLAGS_TRANSACTION_MODE_PING (0x00000001) 3511 3512 /*! 3513 * Block Reads/Writes: There are two different protocols for reading/writing >2 3514 * byte sets of data to/from a slave device. The SMBus specification section 3515 * 5.5.7 defines "Block Reads/Writes" in which the first byte of the payload 3516 * specifies the size of the data to be read/written s.t. payload_size = 3517 * data_size + 1. However, many other devices depend on the master to already 3518 * know the size of the data being accessed (i.e. SW written with knowledge of 3519 * the device's I2C register spec) and skip this overhead. This second behavior 3520 * is actually the default behavior of all the lib's I2C interfaces. 3521 * 3522 * Setting this bit will enable the block protocol for reads and writes for size 3523 * >2. 3524 */ 3525 #define NVSWITCH_CTRL_I2C_FLAGS_BLOCK_PROTOCOL 17:17 3526 #define NVSWITCH_CTRL_I2C_FLAGS_BLOCK_PROTOCOL_DISABLED 0x00000000 3527 #define NVSWITCH_CTRL_I2C_FLAGS_BLOCK_PROTOCOL_ENABLED 0x00000001 3528 3529 /*! 3530 * NVSWITCH_CTRL_I2C_FLAGS_RESERVED 3531 * A client must leave this field as 0, as it is reserved for future use. 3532 */ 3533 #define NVSWITCH_CTRL_I2C_FLAGS_RESERVED 31:18 3534 3535 #define NVSWITCH_CTRL_I2C_MESSAGE_LENGTH_MAX 256 3536 3537 /* 3538 * CTRL_NVSWITCH_I2C_INDEXED 3539 * 3540 * Perform a basic I2C transaction synchronously. 3541 * 3542 * portId 3543 * This field must be specified by the client to indicate the logical 3544 * port/bus for which the transaction is requested. 3545 * 3546 * bIsRead 3547 * This field must be specified by the client to indicate whether the 3548 * command is a write (FALSE) or a read (TRUE). 3549 * 3550 * flags 3551 * This parameter specifies optional flags used to control certain modal 3552 * features such as target speed and addressing mode. The currently 3553 * defined fields are described previously; see NVSWITCH_CTRL_I2C_FLAGS_*. 3554 * 3555 * acquirer 3556 * The ID of the client that is trying to take control of the I2C module. 3557 * 3558 * address 3559 * The address of the I2C slave. The address should be shifted left by 3560 * one. For example, the I2C address 0x50, often used for reading EDIDs, 3561 * would be stored here as 0xA0. This matches the position within the 3562 * byte sent by the master, as the last bit is reserved to specify the 3563 * read or write direction. 3564 * 3565 * index 3566 * This parameter, required of the client if index is one or more, 3567 * specifies the index to be written. The buffer should be arranged such 3568 * that index[0] will be the first byte sent. 3569 * 3570 * messageLength 3571 * This parameter, required of the client, specifies the number of bytes to 3572 * read or write from the slave after the index is written. 3573 * 3574 * message 3575 * This parameter, required of the client, specifies the data to be written 3576 * to the slave. The buffer should be arranged such that message[0] will 3577 * be the first byte read or written. If the transaction is a read, then 3578 * it will follow the combined format described in the I2C specification. 3579 * If the transaction is a write, the message will immediately follow the 3580 * index without a restart. 3581 * 3582 */ 3583 typedef struct 3584 { 3585 NvU8 port; 3586 NvU8 bIsRead; 3587 NvU16 address; 3588 NvU32 flags; 3589 NvU32 acquirer; 3590 3591 NvU8 index[NVSWITCH_CTRL_I2C_INDEX_LENGTH_MAX]; 3592 3593 NvU32 messageLength; 3594 NvU8 message[NVSWITCH_CTRL_I2C_MESSAGE_LENGTH_MAX]; 3595 } NVSWITCH_CTRL_I2C_INDEXED_PARAMS; 3596 3597 /* 3598 * Structure to store register values required to debug ALI training failures 3599 * 3600 * dlstatMn00 3601 * DLSTAT MN00 register value (subcode and code) 3602 * dlstatUc01 3603 * DLSTAT UC01 register value 3604 * dlstatLinkIntr 3605 * NV_MINION_NVLINK_LINK_INTR (subcode, code and state) 3606 */ 3607 typedef struct nvswitch_minion_ali_debug_registers 3608 { 3609 NvU32 dlstatMn00; 3610 NvU32 dlstatUc01; 3611 NvU32 dlstatLinkIntr; 3612 } NVSWITCH_MINION_ALI_DEBUG_REGISTERS; 3613 3614 /* 3615 * CTRL_NVSWITCH_REGISTER_READ/WRITE 3616 * 3617 * This provides direct access to the MMIO space. 3618 */ 3619 3620 typedef struct 3621 { 3622 NvU32 engine; // REGISTER_RW_ENGINE_* 3623 NvU32 instance; // engine instance 3624 NvU32 offset; // Register offset within device/instance 3625 NvU32 val; // out: register value read 3626 } NVSWITCH_REGISTER_READ; 3627 3628 typedef struct 3629 { 3630 NvU32 engine; // REGISTER_RW_ENGINE_* 3631 NvU32 instance; // engine instance 3632 NvBool bcast; // Unicast or broadcast 3633 NvU32 offset; // Register offset within engine/instance 3634 NvU32 val; // in: register value to write 3635 } NVSWITCH_REGISTER_WRITE; 3636 3637 3638 typedef struct 3639 { 3640 NvU8 thresholdMan; 3641 NvU8 thresholdExp; 3642 NvU8 timescaleMan; 3643 NvU8 timescaleExp; 3644 NvBool bInterruptEn; 3645 NvBool bInterruptTrigerred; 3646 NvU32 flags; 3647 } NVSWITCH_NVLINK_ERROR_THRESHOLD_VALUES; 3648 3649 #define NVSWITCH_NVLINK_ERROR_THRESHOLD_RESET 0x1 3650 3651 /* 3652 * CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD 3653 * 3654 * Set the Nvlink Error Rate Threshold. 3655 * 3656 * Parameters: 3657 * linkMask [IN] 3658 * A valid link mask for which we need to set the Error Threshold 3659 * 3660 * errorThreshold [IN] 3661 * Threshold values, interrupt enable/disable and flags 3662 */ 3663 3664 typedef struct 3665 { 3666 NV_DECLARE_ALIGNED(NvU64 link_mask, 8); 3667 NVSWITCH_NVLINK_ERROR_THRESHOLD_VALUES errorThreshold[NVSWITCH_NVLINK_MAX_LINKS]; 3668 } NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS; 3669 3670 /* 3671 * CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD 3672 * 3673 * Control to query NVLIPT counter configuration. 3674 * 3675 * Parameters: 3676 * linkMask [IN] 3677 * A valid link mask for which we need to get the Error Threshold 3678 * 3679 * errorThreshold [OUT] 3680 * Threshold values, interrupt enable/disable and flags 3681 */ 3682 3683 typedef struct 3684 { 3685 NV_DECLARE_ALIGNED(NvU64 link_mask, 8); 3686 NVSWITCH_NVLINK_ERROR_THRESHOLD_VALUES errorThreshold[NVSWITCH_NVLINK_MAX_LINKS]; 3687 } NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS; 3688 3689 #define REGISTER_RW_ENGINE_RAW 0x00 3690 3691 #define REGISTER_RW_ENGINE_CLKS 0x10 3692 #define REGISTER_RW_ENGINE_FUSE 0x11 3693 #define REGISTER_RW_ENGINE_JTAG 0x12 3694 #define REGISTER_RW_ENGINE_PMGR 0x13 3695 #define REGISTER_RW_ENGINE_SAW 0x14 3696 #define REGISTER_RW_ENGINE_XP3G 0x15 3697 #define REGISTER_RW_ENGINE_XVE 0x16 3698 #define REGISTER_RW_ENGINE_SOE 0x17 3699 #define REGISTER_RW_ENGINE_SMR 0x18 3700 #define REGISTER_RW_ENGINE_SE 0x19 3701 #define REGISTER_RW_ENGINE_CLKS_SYS 0x1A 3702 #define REGISTER_RW_ENGINE_CLKS_SYSB 0x1B 3703 #define REGISTER_RW_ENGINE_CLKS_P0 0x1C 3704 #define REGISTER_RW_ENGINE_XPL 0x1D 3705 #define REGISTER_RW_ENGINE_XTL 0x1E 3706 3707 #define REGISTER_RW_ENGINE_SIOCTRL 0x20 3708 #define REGISTER_RW_ENGINE_MINION 0x21 3709 #define REGISTER_RW_ENGINE_NVLIPT 0x22 3710 #define REGISTER_RW_ENGINE_NVLTLC 0x23 3711 #define REGISTER_RW_ENGINE_NVLTLC_MULTICAST 0x24 3712 #define REGISTER_RW_ENGINE_DLPL 0x25 3713 #define REGISTER_RW_ENGINE_NVLW 0x26 3714 #define REGISTER_RW_ENGINE_NVLIPT_LNK 0x27 3715 #define REGISTER_RW_ENGINE_NVLIPT_LNK_MULTICAST 0x28 3716 #define REGISTER_RW_ENGINE_NVLDL 0x29 3717 #define REGISTER_RW_ENGINE_NVLDL_MULTICAST 0x2a 3718 #define REGISTER_RW_ENGINE_PLL 0x2b 3719 3720 #define REGISTER_RW_ENGINE_NPG 0x30 3721 #define REGISTER_RW_ENGINE_NPORT 0x31 3722 #define REGISTER_RW_ENGINE_NPORT_MULTICAST 0x32 3723 3724 #define REGISTER_RW_ENGINE_SWX 0x40 3725 #define REGISTER_RW_ENGINE_AFS 0x41 3726 #define REGISTER_RW_ENGINE_NXBAR 0x42 3727 #define REGISTER_RW_ENGINE_TILE 0x43 3728 #define REGISTER_RW_ENGINE_TILE_MULTICAST 0x44 3729 #define REGISTER_RW_ENGINE_TILEOUT 0x45 3730 #define REGISTER_RW_ENGINE_TILEOUT_MULTICAST 0x46 3731 3732 /* 3733 * CTRL call command list. 3734 * 3735 * Linux driver supports only 8-bit commands. 3736 * 3737 * See struct control call command modification guidelines at the top 3738 * of this file. 3739 */ 3740 #define CTRL_NVSWITCH_GET_INFO 0x01 3741 #define CTRL_NVSWITCH_SET_SWITCH_PORT_CONFIG 0x02 3742 #define CTRL_NVSWITCH_SET_INGRESS_REQUEST_TABLE 0x03 3743 #define CTRL_NVSWITCH_SET_INGRESS_REQUEST_VALID 0x04 3744 #define CTRL_NVSWITCH_SET_INGRESS_RESPONSE_TABLE 0x05 3745 #define CTRL_NVSWITCH_SET_GANGED_LINK_TABLE 0x06 3746 #define CTRL_NVSWITCH_GET_INTERNAL_LATENCY 0x07 3747 #define CTRL_NVSWITCH_SET_LATENCY_BINS 0x08 3748 #define CTRL_NVSWITCH_GET_NVLIPT_COUNTERS 0x09 3749 #define CTRL_NVSWITCH_SET_NVLIPT_COUNTER_CONFIG 0x0A 3750 #define CTRL_NVSWITCH_GET_NVLIPT_COUNTER_CONFIG 0x0B 3751 #define CTRL_NVSWITCH_GET_ERRORS 0x0C 3752 #define CTRL_NVSWITCH_SET_REMAP_POLICY 0x0D 3753 #define CTRL_NVSWITCH_SET_ROUTING_ID 0x0E 3754 #define CTRL_NVSWITCH_SET_ROUTING_LAN 0x0F 3755 #define CTRL_NVSWITCH_GET_INGRESS_REQUEST_TABLE 0x10 3756 #define CTRL_NVSWITCH_GET_INGRESS_RESPONSE_TABLE 0x11 3757 #define CTRL_NVSWITCH_GET_INGRESS_REQLINKID 0x12 3758 #define CTRL_NVSWITCH_UNREGISTER_LINK 0x13 3759 #define CTRL_NVSWITCH_RESET_AND_DRAIN_LINKS 0x14 3760 #define CTRL_NVSWITCH_GET_ROUTING_LAN 0x15 3761 #define CTRL_NVSWITCH_SET_ROUTING_LAN_VALID 0x16 3762 #define CTRL_NVSWITCH_GET_NVLINK_STATUS 0x17 3763 #define CTRL_NVSWITCH_ACQUIRE_CAPABILITY 0x18 3764 #define CTRL_NVSWITCH_GET_ROUTING_ID 0x19 3765 #define CTRL_NVSWITCH_SET_ROUTING_ID_VALID 0x1A 3766 #define CTRL_NVSWITCH_GET_TEMPERATURE 0x1B 3767 #define CTRL_NVSWITCH_GET_REMAP_POLICY 0x1C 3768 #define CTRL_NVSWITCH_SET_REMAP_POLICY_VALID 0x1D 3769 #define CTRL_NVSWITCH_GET_THROUGHPUT_COUNTERS 0x1E 3770 #define CTRL_NVSWITCH_GET_BIOS_INFO 0x1F 3771 #define CTRL_NVSWITCH_BLACKLIST_DEVICE 0x20 3772 #define CTRL_NVSWITCH_SET_FM_DRIVER_STATE 0x21 3773 #define CTRL_NVSWITCH_SET_DEVICE_FABRIC_STATE 0x22 3774 #define CTRL_NVSWITCH_SET_FM_HEARTBEAT_TIMEOUT 0x23 3775 #define CTRL_NVSWITCH_REGISTER_EVENTS 0x24 3776 #define CTRL_NVSWITCH_UNREGISTER_EVENTS 0x25 3777 #define CTRL_NVSWITCH_SET_TRAINING_ERROR_INFO 0x26 3778 #define CTRL_NVSWITCH_GET_FATAL_ERROR_SCOPE 0x27 3779 #define CTRL_NVSWITCH_SET_MC_RID_TABLE 0x28 3780 #define CTRL_NVSWITCH_GET_MC_RID_TABLE 0x29 3781 #define CTRL_NVSWITCH_GET_COUNTERS 0x2A 3782 #define CTRL_NVSWITCH_GET_NVLINK_ECC_ERRORS 0x2B 3783 #define CTRL_NVSWITCH_I2C_SMBUS_COMMAND 0x2C 3784 #define CTRL_NVSWITCH_GET_TEMPERATURE_LIMIT 0x2D 3785 #define CTRL_NVSWITCH_GET_NVLINK_MAX_ERROR_RATES 0x2E 3786 #define CTRL_NVSWITCH_GET_NVLINK_ERROR_COUNTS 0x2F 3787 #define CTRL_NVSWITCH_GET_ECC_ERROR_COUNTS 0x30 3788 #define CTRL_NVSWITCH_GET_SXIDS 0x31 3789 #define CTRL_NVSWITCH_GET_FOM_VALUES 0x32 3790 #define CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS 0x33 3791 #define CTRL_NVSWITCH_SET_RESIDENCY_BINS 0x34 3792 #define CTRL_NVSWITCH_GET_RESIDENCY_BINS 0x35 3793 #define CTRL_NVSWITCH_GET_RB_STALL_BUSY 0x36 3794 #define CTRL_NVSWITCH_RESERVED_0 0x37 3795 #define CTRL_NVSWITCH_RESERVED_1 0x38 3796 #define CTRL_NVSWITCH_RESERVED_2 0x39 3797 #define CTRL_NVSWITCH_RESERVED_3 0x3A 3798 #define CTRL_NVSWITCH_RESERVED_4 0x3B 3799 #define CTRL_NVSWITCH_RESERVED_5 0x3C 3800 #define CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR 0x3D 3801 #define CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR 0x3E 3802 #define CTRL_NVSWITCH_INBAND_SEND_DATA 0x43 3803 #define CTRL_NVSWITCH_INBAND_READ_DATA 0x44 3804 #define CTRL_NVSWITCH_INBAND_FLUSH_DATA 0x45 3805 #define CTRL_NVSWITCH_INBAND_PENDING_DATA_STATS 0x46 3806 #define CTRL_NVSWITCH_GET_SW_INFO 0x47 3807 #define CTRL_NVSWITCH_RESERVED_6 0x48 3808 #define CTRL_NVSWITCH_RESERVED_7 0x49 3809 #define CTRL_NVSWITCH_RESERVED_8 0x4A 3810 #define CTRL_NVSWITCH_RESERVED_9 0x4B 3811 #define CTRL_NVSWITCH_RESERVED_10 0x4C 3812 #define CTRL_NVSWITCH_REGISTER_READ 0x4D 3813 #define CTRL_NVSWITCH_REGISTER_WRITE 0x4E 3814 #define CTRL_NVSWITCH_GET_INFOROM_VERSION 0x4F 3815 #define CTRL_NVSWITCH_GET_ERR_INFO 0x50 3816 #define CTRL_NVSWITCH_CLEAR_COUNTERS 0x51 3817 #define CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD 0x52 3818 #define CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD 0x53 3819 #define CTRL_NVSWITCH_GET_VOLTAGE 0x54 3820 #define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x55 3821 3822 #ifdef __cplusplus 3823 } 3824 #endif 3825 3826 #endif // _CTRL_DEVICE_NVSWITCH_H_ 3827