1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _LR10_H_ 25 #define _LR10_H_ 26 27 #include "nvlink.h" 28 #include "nvCpuUuid.h" 29 30 #include "export_nvswitch.h" 31 #include "common_nvswitch.h" 32 #include "pmgr_nvswitch.h" 33 #include "rom_nvswitch.h" 34 #include "error_nvswitch.h" 35 36 #include "ctrl_dev_nvswitch.h" 37 38 #include "nvswitch/lr10/dev_nvs_master.h" 39 40 // 41 // Re-direction to use new common link access wrappers 42 // 43 44 #define NVSWITCH_IS_LINK_ENG_VALID_LR10(_d, _eng, _linknum) \ 45 NVSWITCH_IS_LINK_ENG_VALID(_d, _linknum, _eng) 46 47 #define NVSWITCH_LINK_OFFSET_LR10(_d, _physlinknum, _eng, _dev, _reg) \ 48 NVSWITCH_LINK_OFFSET(_d, _physlinknum, _eng, _dev, _reg) 49 50 #define NVSWITCH_LINK_WR32_LR10(_d, _physlinknum, _eng, _dev, _reg, _data) \ 51 NVSWITCH_LINK_WR32(_d, _physlinknum, _eng, _dev, _reg, _data) 52 53 #define NVSWITCH_LINK_RD32_LR10(_d, _physlinknum, _eng, _dev, _reg) \ 54 NVSWITCH_LINK_RD32(_d, _physlinknum, _eng, _dev, _reg) 55 56 #define NVSWITCH_LINK_WR32_IDX_LR10(_d, _physlinknum, _eng, _dev, _reg, _idx, _data) \ 57 NVSWITCH_LINK_WR32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx, _data) 58 59 #define NVSWITCH_LINK_RD32_IDX_LR10(_d, _physlinknum, _eng, _dev, _reg, _idx) \ 60 NVSWITCH_LINK_RD32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx) 61 62 // 63 // NVSWITCH_ENG_* MMIO wrappers are to be used for top level discovered 64 // devices like SAW, FUSE, PMGR, XVE, etc. 65 // 66 67 #define NVSWITCH_ENG_WR32_LR10(_d, _eng, _bcast, _engidx, _dev, _reg, _data) \ 68 NVSWITCH_ENG_WR32(_d, _eng, _bcast, _engidx, _dev, _reg, _data) 69 70 #define NVSWITCH_ENG_RD32_LR10(_d, _eng, _engidx, _dev, _reg) \ 71 NVSWITCH_ENG_RD32(_d, _eng, , _engidx, _dev, _reg) 72 73 #define NVSWITCH_ENG_WR32_IDX_LR10(_d, _eng, _bcast, _engidx, _dev, _reg, _idx, _data) \ 74 NVSWITCH_ENG_WR32_IDX(_d, _eng, _bcast, _engidx, _dev, _reg, _idx, _data) 75 76 #define NVSWITCH_BCAST_WR32_LR10(_d, _eng, _dev, _reg, _data) \ 77 NVSWITCH_ENG_WR32_LR10(_d, _eng, _BCAST, 0, _dev, _reg, _data) 78 79 #define NVSWITCH_BCAST_RD32_LR10(_d, _eng, _dev, _reg) \ 80 NVSWITCH_ENG_RD32(_d, _eng, _BCAST, 0, bc, _dev, _reg) 81 82 #define NVSWITCH_CLK_NVLINK_RD32_LR10(_d, _reg, _idx) \ 83 NVSWITCH_REG_RD32(_d, _PCLOCK, _NVSW_NVLINK##_reg(_idx)) 84 85 #define NVSWITCH_CLK_NVLINK_WR32_LR10(_d, _reg, _idx, _data) \ 86 if (IS_RTLSIM(_d) || IS_FMODEL(_d)) \ 87 { \ 88 NVSWITCH_PRINT(_d, MMIO, \ 89 "%s: Skip write NV_PCLOCK_NVSW_NVLINK%d %s (0x%06x) on FSF\n", \ 90 __FUNCTION__, \ 91 _idx, #_reg, \ 92 NV_PCLOCK_NVSW_NVLINK##_reg(_idx)); \ 93 } \ 94 else \ 95 { \ 96 NVSWITCH_REG_WR32(_d, _PCLOCK, _NVSW_NVLINK##_reg(_idx), _data); \ 97 } 98 99 #define NVSWITCH_ENG_VALID_LR10(_d, _eng, _engidx) \ 100 ( \ 101 ((_engidx < NUM_##_eng##_ENGINE_LR10) && \ 102 (NVSWITCH_GET_CHIP_DEVICE_LR10(_d)->eng##_eng[_engidx].valid)) ? \ 103 NV_TRUE : NV_FALSE \ 104 ) 105 106 #define NVSWITCH_SAW_RD32_LR10(_d, _dev, _reg) \ 107 NVSWITCH_ENG_RD32_LR10(_d, SAW, 0, _dev, _reg) 108 109 #define NVSWITCH_SAW_WR32_LR10(_d, _dev, _reg, _data) \ 110 NVSWITCH_ENG_WR32_LR10(_d, SAW, , 0, _dev, _reg, _data) 111 112 #define NVSWITCH_NPG_RD32_LR10(_d, _engidx, _dev, _reg) \ 113 NVSWITCH_ENG_RD32_LR10(_d, NPG, _engidx, _dev, _reg) 114 115 #define NVSWITCH_NPG_WR32_LR10(_d, _engidx, _dev, _reg, _data) \ 116 NVSWITCH_ENG_WR32_LR10(_d, NPG, , _engidx, _dev, _reg, _data) 117 118 #define NVSWITCH_NPGPERF_WR32_LR10(_d, _engidx, _dev, _reg, _data) \ 119 NVSWITCH_ENG_WR32_LR10(_d, NPG_PERFMON, , _engidx, _dev, _reg, _data) 120 121 #define NVSWITCH_NPORT_RD32_LR10(_d, _engidx, _dev, _reg) \ 122 NVSWITCH_ENG_RD32_LR10(_d, NPORT, _engidx, _dev, _reg) 123 124 #define NVSWITCH_NPORT_WR32_LR10(_d, _engidx, _dev, _reg, _data) \ 125 NVSWITCH_ENG_WR32_LR10(_d, NPORT, , _engidx, _dev, _reg, _data) 126 127 #define NVSWITCH_NPORT_MC_BCAST_WR32_LR10(_d, _dev, _reg, _data) \ 128 NVSWITCH_BCAST_WR32_LR10(_d, NPORT, _dev, _reg, _data) 129 130 #define NVSWITCH_NVLIPT_RD32_LR10(_d, _engidx, _dev, _reg) \ 131 NVSWITCH_ENG_RD32_LR10(_d, NVLIPT, _engidx, _dev, _reg) 132 133 #define NVSWITCH_NVLIPT_WR32_LR10(_d, _engidx, _dev, _reg, _data) \ 134 NVSWITCH_ENG_WR32_LR10(_d, NVLIPT, , _engidx, _dev, _reg, _data) 135 136 typedef struct 137 { 138 NvBool valid; 139 NvU32 initialized; 140 NvU32 version; 141 NvU32 disc_type; 142 union 143 { 144 struct 145 { 146 NvU32 cluster; 147 NvU32 cluster_id; 148 NvU32 discovery; // Used for top level only 149 } top; 150 struct 151 { 152 NvU32 uc_addr; 153 } uc; 154 struct 155 { 156 NvU32 bc_addr; 157 NvU32 mc_addr[3]; 158 } bc; 159 } info; 160 } ENGINE_DESCRIPTOR_TYPE_LR10; 161 162 #define NUM_PTOP_ENGINE_LR10 1 163 #define NUM_CLKS_ENGINE_LR10 1 164 #define NUM_FUSE_ENGINE_LR10 1 165 #define NUM_JTAG_ENGINE_LR10 1 166 #define NUM_PMGR_ENGINE_LR10 1 167 #define NUM_SAW_ENGINE_LR10 1 168 #define NUM_XP3G_ENGINE_LR10 1 169 #define NUM_XVE_ENGINE_LR10 1 170 #define NUM_ROM_ENGINE_LR10 1 171 #define NUM_EXTDEV_ENGINE_LR10 1 172 #define NUM_PRIVMAIN_ENGINE_LR10 1 173 #define NUM_PRIVLOC_ENGINE_LR10 10 174 #define NUM_PTIMER_ENGINE_LR10 1 175 #define NUM_SOE_ENGINE_LR10 1 176 #define NUM_SMR_ENGINE_LR10 2 177 #define NUM_I2C_ENGINE_LR10 1 178 #define NUM_SE_ENGINE_LR10 1 179 #define NUM_THERM_ENGINE_LR10 1 180 181 #define NUM_NPG_ENGINE_LR10 9 182 #define NUM_NPG_BCAST_ENGINE_LR10 1 183 #define NUM_NPG_PERFMON_ENGINE_LR10 9 184 #define NUM_NPG_PERFMON_BCAST_ENGINE_LR10 1 185 #define NUM_NPORT_ENGINE_LR10 36 186 #define NUM_NPORT_BCAST_ENGINE_LR10 4 187 #define NUM_NPORT_MULTICAST_ENGINE_LR10 9 188 #define NUM_NPORT_MULTICAST_BCAST_ENGINE_LR10 1 189 #define NUM_NPORT_PERFMON_ENGINE_LR10 36 190 #define NUM_NPORT_PERFMON_BCAST_ENGINE_LR10 4 191 #define NUM_NPORT_PERFMON_MULTICAST_ENGINE_LR10 9 192 #define NUM_NPORT_PERFMON_MULTICAST_BCAST_ENGINE_LR10 1 193 194 #define NUM_NXBAR_ENGINE_LR10 4 195 #define NUM_NXBAR_BCAST_ENGINE_LR10 1 196 #define NUM_NXBAR_PERFMON_ENGINE_LR10 4 197 #define NUM_NXBAR_PERFMON_BCAST_ENGINE_LR10 1 198 #define NUM_TILE_ENGINE_LR10 16 199 #define NUM_TILE_BCAST_ENGINE_LR10 4 200 #define NUM_TILE_MULTICAST_ENGINE_LR10 4 201 #define NUM_TILE_MULTICAST_BCAST_ENGINE_LR10 1 202 #define NUM_TILE_PERFMON_ENGINE_LR10 16 203 #define NUM_TILE_PERFMON_BCAST_ENGINE_LR10 4 204 #define NUM_TILE_PERFMON_MULTICAST_ENGINE_LR10 4 205 #define NUM_TILE_PERFMON_MULTICAST_BCAST_ENGINE_LR10 1 206 207 // 208 // Tile Column consists of 4 Tile blocks and 9 Tileout blocks. 209 // There are 4 Tile Columns, one per each NXBAR. 210 211 #define NUM_NXBAR_TCS_LR10 NUM_NXBAR_ENGINE_LR10 212 #define NUM_NXBAR_TILEOUTS_PER_TC_LR10 9 213 #define NUM_NXBAR_TILES_PER_TC_LR10 4 214 215 #define TILE_TO_LINK(_device, _tc, _tile) \ 216 ( \ 217 NVSWITCH_ASSERT((_tc < NUM_NXBAR_TCS_LR10)) \ 218 , \ 219 NVSWITCH_ASSERT((_tile < NUM_NXBAR_TILES_PER_TC_LR10)) \ 220 , \ 221 ((_tc) * NUM_NXBAR_TILES_PER_TC_LR10 + (_tile)) \ 222 ) 223 224 #define NV_NXBAR_TC_TILEOUT_ERR_FATAL_INTR_EN(i) (NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN + \ 225 i * (NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN - NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN)) 226 227 #define NV_NXBAR_TC_TILEOUT_ERR_STATUS(i) (NV_NXBAR_TC_TILEOUT0_ERR_STATUS + \ 228 i * (NV_NXBAR_TC_TILEOUT1_ERR_STATUS - NV_NXBAR_TC_TILEOUT0_ERR_STATUS)) 229 230 #define NV_NXBAR_TC_TILEOUT_ERR_FIRST(i) (NV_NXBAR_TC_TILEOUT0_ERR_FIRST + \ 231 i * (NV_NXBAR_TC_TILEOUT1_ERR_FIRST - NV_NXBAR_TC_TILEOUT0_ERR_FIRST)) 232 233 #define NV_NXBAR_TC_TILEOUT_ERR_CYA(i) (NV_NXBAR_TC_TILEOUT0_ERR_CYA + \ 234 i * (NV_NXBAR_TC_TILEOUT1_ERR_CYA - NV_NXBAR_TC_TILEOUT0_ERR_CYA)) 235 236 #define NVSWITCH_NXBAR_RD32_LR10(_d, _engidx, _dev, _reg) \ 237 NVSWITCH_ENG_RD32_LR10(_d, NXBAR, _engidx, _dev, _reg) 238 239 #define NVSWITCH_NXBAR_WR32_LR10(_d, _engidx, _dev, _reg, _data) \ 240 NVSWITCH_ENG_WR32_LR10(_d, NXBAR, , _engidx, _dev, _reg, _data) 241 242 #define NVSWITCH_TILE_RD32_LR10(_d, _engidx, _dev, _reg) \ 243 NVSWITCH_ENG_RD32_LR10(_d, TILE, _engidx, _dev, _reg) 244 245 #define NVSWITCH_TILE_WR32_LR10(_d, _engidx, _dev, _reg, _data) \ 246 NVSWITCH_ENG_WR32_LR10(_d, TILE, , _engidx, _dev, _reg, _data) 247 248 249 #define NV_PPRIV_PRT_PRT_PRIV_ERROR_ADR(i) (NV_PPRIV_PRT_PRT0_PRIV_ERROR_ADR + \ 250 i * (NV_PPRIV_PRT_PRT1_PRIV_ERROR_ADR - NV_PPRIV_PRT_PRT0_PRIV_ERROR_ADR)) 251 252 #define NV_PPRIV_PRT_PRT_PRIV_ERROR_WRDAT(i) (NV_PPRIV_PRT_PRT0_PRIV_ERROR_WRDAT + \ 253 i * (NV_PPRIV_PRT_PRT1_PRIV_ERROR_WRDAT - NV_PPRIV_PRT_PRT0_PRIV_ERROR_WRDAT)) 254 255 #define NV_PPRIV_PRT_PRT_PRIV_ERROR_INFO(i) (NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO + \ 256 i * (NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO - NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO)) 257 258 #define NV_PPRIV_PRT_PRT_PRIV_ERROR_CODE(i) (NV_PPRIV_PRT_PRT0_PRIV_ERROR_CODE + \ 259 i * (NV_PPRIV_PRT_PRT1_PRIV_ERROR_CODE - NV_PPRIV_PRT_PRT0_PRIV_ERROR_CODE)) 260 261 #define NUM_NVLW_ENGINE_LR10 9 262 #define NUM_NVLW_BCAST_ENGINE_LR10 1 263 #define NUM_NVLW_PERFMON_ENGINE_LR10 9 264 #define NUM_NVLW_PERFMON_BCAST_ENGINE_LR10 1 265 #define NUM_MINION_ENGINE_LR10 9 266 #define NUM_MINION_BCAST_ENGINE_LR10 1 267 #define NUM_NVLIPT_ENGINE_LR10 9 268 #define NUM_NVLIPT_BCAST_ENGINE_LR10 1 269 #define NUM_NVLIPT_SYS_PERFMON_ENGINE_LR10 9 270 #define NUM_NVLIPT_SYS_PERFMON_BCAST_ENGINE_LR10 1 271 #define NUM_NVLTLC_ENGINE_LR10 36 272 #define NUM_NVLTLC_BCAST_ENGINE_LR10 4 273 #define NUM_NVLTLC_MULTICAST_ENGINE_LR10 9 274 #define NUM_NVLTLC_MULTICAST_BCAST_ENGINE_LR10 1 275 #define NUM_TX_PERFMON_ENGINE_LR10 36 276 #define NUM_TX_PERFMON_BCAST_ENGINE_LR10 4 277 #define NUM_TX_PERFMON_MULTICAST_ENGINE_LR10 9 278 #define NUM_TX_PERFMON_MULTICAST_BCAST_ENGINE_LR10 1 279 #define NUM_RX_PERFMON_ENGINE_LR10 36 280 #define NUM_RX_PERFMON_BCAST_ENGINE_LR10 4 281 #define NUM_RX_PERFMON_MULTICAST_ENGINE_LR10 9 282 #define NUM_RX_PERFMON_MULTICAST_BCAST_ENGINE_LR10 1 283 #define NUM_PLL_ENGINE_LR10 9 284 #define NUM_PLL_BCAST_ENGINE_LR10 1 285 #define NUM_NVLDL_ENGINE_LR10 36 286 #define NUM_NVLDL_BCAST_ENGINE_LR10 4 287 #define NUM_NVLDL_MULTICAST_ENGINE_LR10 9 288 #define NUM_NVLDL_MULTICAST_BCAST_ENGINE_LR10 1 289 #define NUM_NVLIPT_LNK_ENGINE_LR10 36 290 #define NUM_NVLIPT_LNK_BCAST_ENGINE_LR10 4 291 #define NUM_NVLIPT_LNK_MULTICAST_ENGINE_LR10 9 292 #define NUM_NVLIPT_LNK_MULTICAST_BCAST_ENGINE_LR10 1 293 #define NUM_SYS_PERFMON_ENGINE_LR10 36 294 #define NUM_SYS_PERFMON_BCAST_ENGINE_LR10 4 295 #define NUM_SYS_PERFMON_MULTICAST_ENGINE_LR10 9 296 #define NUM_SYS_PERFMON_MULTICAST_BCAST_ENGINE_LR10 1 297 #define NVSWITCH_NUM_PRIV_PRT_LR10 9 298 299 300 #define NVSWITCH_NPORT_PER_NPG (NUM_NPORT_ENGINE_LR10/NUM_NPG_ENGINE_LR10) 301 #define NPORT_TO_LINK(_device, _npg, _nport) \ 302 ( \ 303 NVSWITCH_ASSERT((_npg < NUM_NPG_ENGINE_LR10)) \ 304 , \ 305 NVSWITCH_ASSERT((_nport < NVSWITCH_NPORT_PER_NPG))\ 306 , \ 307 ((_npg) * NVSWITCH_NPORT_PER_NPG + (_nport)) \ 308 ) 309 #define NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64(_nvlipt_idx) \ 310 (NVBIT64(NVSWITCH_LINKS_PER_NVLIPT) - 1) << (_nvlipt_idx * NVSWITCH_LINKS_PER_NVLIPT); 311 312 #define NVSWITCH_NUM_LINKS_LR10 (NUM_NPORT_ENGINE_LR10) 313 #define NVSWITCH_NUM_LANES_LR10 4 314 315 #define NVSWITCH_LINKS_PER_NVLW (NVSWITCH_NUM_LINKS_LR10/NUM_NVLW_ENGINE_LR10) 316 #define NVSWITCH_LINKS_PER_MINION (NVSWITCH_NUM_LINKS_LR10/NUM_MINION_ENGINE_LR10) 317 #define NVSWITCH_LINKS_PER_NVLIPT (NVSWITCH_NUM_LINKS_LR10/NUM_NVLIPT_ENGINE_LR10) 318 #define NVSWITCH_LINKS_PER_NPG (NVSWITCH_NUM_LINKS_LR10/NUM_NPG_ENGINE_LR10) 319 320 #define NVSWITCH_DECLARE_ENGINE_UC_LR10(_engine) \ 321 ENGINE_DESCRIPTOR_TYPE_LR10 eng##_engine[NUM_##_engine##_ENGINE_LR10]; 322 323 #define NVSWITCH_DECLARE_ENGINE_LR10(_engine) \ 324 ENGINE_DESCRIPTOR_TYPE_LR10 eng##_engine[NUM_##_engine##_ENGINE_LR10]; \ 325 ENGINE_DESCRIPTOR_TYPE_LR10 eng##_engine##_BCAST[NUM_##_engine##_BCAST_ENGINE_LR10]; 326 327 #define NVSWITCH_NVLIPT_GET_PUBLIC_ID_LR10(_physlinknum) \ 328 ((_physlinknum)/NVSWITCH_LINKS_PER_NVLIPT) 329 330 #define NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(_physlinknum) \ 331 ((_physlinknum)%NVSWITCH_LINKS_PER_NVLIPT) 332 333 #define DISCOVERY_TYPE_UNDEFINED 0 334 #define DISCOVERY_TYPE_DISCOVERY 1 335 #define DISCOVERY_TYPE_UNICAST 2 336 #define DISCOVERY_TYPE_BROADCAST 3 337 338 // 339 // These field #defines describe which physical fabric address bits are 340 // relevant to the specific remap table address check/remap operation. 341 // 342 #define NV_INGRESS_REMAP_ADDR_PHYS_LR10 46:36 343 344 #define NV_INGRESS_REMAP_ADR_OFFSET_PHYS_LR10 35:20 345 #define NV_INGRESS_REMAP_ADR_BASE_PHYS_LR10 35:20 346 #define NV_INGRESS_REMAP_ADR_LIMIT_PHYS_LR10 35:20 347 348 typedef NVSWITCH_LINK_TYPE NVSWITCH_LINK_TYPE_LR10; 349 350 // 351 // NPORT Portstat information 352 // 353 354 // 355 // LR10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs. 356 // But DNGRD(1), ATR(2), ATSD(3), and PROBE(4) will be never used as PowerPC ATS support is not a POR for LR10 HW. 357 // 358 #define NVSWITCH_NUM_VCS_LR10 8 359 360 typedef struct 361 { 362 NvU32 count; 363 NvU32 low; 364 NvU32 medium; 365 NvU32 high; 366 NvU32 panic; 367 } 368 NVSWITCH_LATENCY_BINS_LR10; 369 370 typedef struct 371 { 372 NvU32 count; 373 NvU64 start_time_nsec; 374 NvU64 last_read_time_nsec; 375 NVSWITCH_LATENCY_BINS_LR10 accum_latency[NVSWITCH_NUM_LINKS_LR10]; 376 } 377 NVSWITCH_LATENCY_VC_LR10; 378 379 typedef struct 380 { 381 NvU32 sample_interval_msec; 382 NvU64 last_visited_time_nsec; 383 NVSWITCH_LATENCY_VC_LR10 latency[NVSWITCH_NUM_VCS_LR10]; 384 } NVSWITCH_LATENCY_STATS_LR10; 385 386 #define NV_NPORT_PORTSTAT_LR10(_block, _reg, _vc, _index) (NV_NPORT_PORTSTAT ## _block ## _reg ## _0 ## _index + \ 387 _vc * (NV_NPORT_PORTSTAT ## _block ## _reg ## _1 ## _index - NV_NPORT_PORTSTAT ## _block ## _reg ## _0 ## _index)) 388 389 #define NVSWITCH_NPORT_PORTSTAT_RD32_LR10(_d, _engidx, _block, _reg, _vc) \ 390 ( \ 391 NVSWITCH_ASSERT(NVSWITCH_IS_LINK_ENG_VALID_LR10(_d, NPORT, _engidx)) \ 392 , \ 393 NVSWITCH_PRINT(_d, MMIO, \ 394 "%s: MEM_RD NPORT_PORTSTAT[%d]: %s,%s (%06x+%04x)\n", \ 395 __FUNCTION__, \ 396 _engidx, \ 397 #_block, #_reg, \ 398 NVSWITCH_GET_ENG(_d, NPORT, , _engidx), \ 399 NV_NPORT_PORTSTAT_LR10(_block, _reg, _vc, _0)) \ 400 , \ 401 nvswitch_reg_read_32(_d, \ 402 NVSWITCH_GET_ENG(_d, NPORT, , _engidx) + \ 403 NV_NPORT_PORTSTAT_LR10(_block, _reg, _vc, _0)) \ 404 ); \ 405 ((void)(_d)) 406 407 #define NVSWITCH_PORTSTAT_BCAST_WR32_LR10(_d, _block, _reg, _idx, _data) \ 408 { \ 409 NVSWITCH_PRINT(_d, MMIO, \ 410 "%s: BCAST_WR NPORT_PORTSTAT: %s,%s (%06x+%04x) 0x%08x\n", \ 411 __FUNCTION__, \ 412 #_block, #_reg, \ 413 NVSWITCH_GET_ENG(_d, NPORT, _BCAST, 0), \ 414 NV_NPORT_PORTSTAT_LR10(_block, _reg, _idx, ), _data); \ 415 NVSWITCH_OFF_WR32(_d, \ 416 NVSWITCH_GET_ENG(_d, NPORT, _BCAST, 0) + \ 417 NV_NPORT_PORTSTAT_LR10(_block, _reg, _idx, ), _data); \ 418 } 419 420 // 421 // Per-chip device information 422 // 423 424 // 425 // The chip-specific engine list is used to generate the code to collect 426 // discovered unit information and coalesce it into the data structures used by 427 // the common IO library (see io_nvswitch.h). 428 // 429 // The PTOP discovery table presents the information on wrappers and sub-units 430 // in a hierarchical manner. The top level discovery contains information 431 // about top level UNICAST units and IP wrappers like NPG, NVLW, and NXBAR. 432 // Individual units within an IP wrapper are described in discovery sub-tables. 433 // Each IP wrapper may have MULTICAST descriptors to allow addressing sub-units 434 // within a wrapper and a cluster of IP wrappers will also have a BCAST 435 // discovery tables, which have MULTICAST descriptors within them. 436 // In order to collect all the useful unit information into a single container, 437 // we need to pick where to find each piece within the parsed discovery table. 438 // Top level IP wrappers like NPG have a BCAST range to broadcast reads/writes, 439 // but IP sub-units like NPORT have a MULTICAST range within the BCAST IP 440 // wrapper to broadcast to all the sub-units in all the IP wrappers. 441 // So in the lists below top level IP wrappers (NPG, NVLW, and NXBAR) point 442 // to the _BCAST IP wrapper, but sub-unit point to the _MULTICAST range inside 443 // the BCAST unit (_MULTICAST_BCAST). 444 // 445 // All IP-based (0-based register manuals) engines need to be listed here to 446 // generate chip-specific handlers as well as in the global common list of all 447 // engines that have ever existed on *ANY* architecture(s) in order for them 448 // use common IO wrappers. 449 // 450 451 #define NVSWITCH_LIST_LR10_ENGINES(_op) \ 452 _op(XVE, ) \ 453 _op(SAW, ) \ 454 _op(SOE, ) \ 455 _op(SMR, ) \ 456 _op(NPG, _BCAST) \ 457 _op(NPORT, _MULTICAST_BCAST) \ 458 \ 459 _op(NVLW, _BCAST) \ 460 _op(MINION, _BCAST) \ 461 _op(NVLIPT, _BCAST) \ 462 _op(NVLIPT_LNK, _MULTICAST_BCAST) \ 463 _op(NVLTLC, _MULTICAST_BCAST) \ 464 _op(NVLDL, _MULTICAST_BCAST) \ 465 \ 466 _op(NXBAR, _BCAST) \ 467 _op(TILE, _MULTICAST_BCAST) \ 468 \ 469 _op(NPG_PERFMON, _BCAST) \ 470 _op(NPORT_PERFMON, _MULTICAST_BCAST) \ 471 \ 472 _op(NVLW_PERFMON, _BCAST) \ 473 474 typedef struct 475 { 476 struct 477 { 478 NVSWITCH_ENGINE_DESCRIPTOR_TYPE common[NVSWITCH_ENGINE_ID_SIZE]; 479 } io; 480 481 NVSWITCH_DECLARE_ENGINE_UC_LR10(PTOP) 482 NVSWITCH_DECLARE_ENGINE_UC_LR10(CLKS) 483 NVSWITCH_DECLARE_ENGINE_UC_LR10(FUSE) 484 NVSWITCH_DECLARE_ENGINE_UC_LR10(JTAG) 485 NVSWITCH_DECLARE_ENGINE_UC_LR10(PMGR) 486 NVSWITCH_DECLARE_ENGINE_UC_LR10(SAW) 487 NVSWITCH_DECLARE_ENGINE_UC_LR10(XP3G) 488 NVSWITCH_DECLARE_ENGINE_UC_LR10(XVE) 489 NVSWITCH_DECLARE_ENGINE_UC_LR10(ROM) 490 NVSWITCH_DECLARE_ENGINE_UC_LR10(EXTDEV) 491 NVSWITCH_DECLARE_ENGINE_UC_LR10(PRIVMAIN) 492 NVSWITCH_DECLARE_ENGINE_UC_LR10(PRIVLOC) 493 NVSWITCH_DECLARE_ENGINE_UC_LR10(PTIMER) 494 NVSWITCH_DECLARE_ENGINE_UC_LR10(SOE) 495 NVSWITCH_DECLARE_ENGINE_UC_LR10(SMR) 496 NVSWITCH_DECLARE_ENGINE_UC_LR10(I2C) 497 NVSWITCH_DECLARE_ENGINE_UC_LR10(SE) 498 NVSWITCH_DECLARE_ENGINE_UC_LR10(THERM) 499 500 NVSWITCH_DECLARE_ENGINE_LR10(NVLW) 501 NVSWITCH_DECLARE_ENGINE_LR10(NXBAR) 502 NVSWITCH_DECLARE_ENGINE_LR10(NPG) 503 504 NVSWITCH_DECLARE_ENGINE_LR10(MINION) 505 NVSWITCH_DECLARE_ENGINE_LR10(NVLIPT) 506 NVSWITCH_DECLARE_ENGINE_LR10(NVLTLC) 507 NVSWITCH_DECLARE_ENGINE_LR10(NVLTLC_MULTICAST) 508 NVSWITCH_DECLARE_ENGINE_LR10(NVLIPT_SYS_PERFMON) 509 NVSWITCH_DECLARE_ENGINE_LR10(TX_PERFMON) 510 NVSWITCH_DECLARE_ENGINE_LR10(RX_PERFMON) 511 NVSWITCH_DECLARE_ENGINE_LR10(TX_PERFMON_MULTICAST) 512 NVSWITCH_DECLARE_ENGINE_LR10(RX_PERFMON_MULTICAST) 513 NVSWITCH_DECLARE_ENGINE_LR10(PLL) 514 NVSWITCH_DECLARE_ENGINE_LR10(NVLW_PERFMON) 515 NVSWITCH_DECLARE_ENGINE_LR10(NVLDL) 516 NVSWITCH_DECLARE_ENGINE_LR10(NVLDL_MULTICAST) 517 NVSWITCH_DECLARE_ENGINE_LR10(NVLIPT_LNK) 518 NVSWITCH_DECLARE_ENGINE_LR10(NVLIPT_LNK_MULTICAST) 519 NVSWITCH_DECLARE_ENGINE_LR10(SYS_PERFMON) 520 NVSWITCH_DECLARE_ENGINE_LR10(SYS_PERFMON_MULTICAST) 521 522 NVSWITCH_DECLARE_ENGINE_LR10(NPG_PERFMON) 523 NVSWITCH_DECLARE_ENGINE_LR10(NPORT) 524 NVSWITCH_DECLARE_ENGINE_LR10(NPORT_MULTICAST) 525 NVSWITCH_DECLARE_ENGINE_LR10(NPORT_PERFMON) 526 NVSWITCH_DECLARE_ENGINE_LR10(NPORT_PERFMON_MULTICAST) 527 528 NVSWITCH_DECLARE_ENGINE_LR10(NXBAR_PERFMON) 529 NVSWITCH_DECLARE_ENGINE_LR10(TILE) 530 NVSWITCH_DECLARE_ENGINE_LR10(TILE_MULTICAST) 531 NVSWITCH_DECLARE_ENGINE_LR10(TILE_PERFMON) 532 NVSWITCH_DECLARE_ENGINE_LR10(TILE_PERFMON_MULTICAST) 533 534 // VBIOS configuration Data 535 NVSWITCH_BIOS_NVLINK_CONFIG bios_config; 536 537 // GPIO 538 const NVSWITCH_GPIO_INFO *gpio_pin; 539 NvU32 gpio_pin_size; 540 541 // Interrupts 542 NvU32 intr_enable_legacy; 543 NvU32 intr_enable_corr; 544 NvU32 intr_enable_fatal; 545 NvU32 intr_enable_nonfatal; 546 NvU32 intr_minion_dest; 547 548 // 549 // Book-keep interrupt masks to restore them after reset. 550 // Note: There is no need to book-keep interrupt masks for NVLink units like 551 // DL, MINION, TLC etc. because NVLink init routines would setup them. 552 // 553 struct 554 { 555 NVSWITCH_INTERRUPT_MASK route; 556 NVSWITCH_INTERRUPT_MASK ingress; 557 NVSWITCH_INTERRUPT_MASK egress; 558 NVSWITCH_INTERRUPT_MASK tstate; 559 NVSWITCH_INTERRUPT_MASK sourcetrack; 560 NVSWITCH_INTERRUPT_MASK tile; 561 NVSWITCH_INTERRUPT_MASK tileout; 562 } intr_mask; 563 564 // Latency statistics 565 NVSWITCH_LATENCY_STATS_LR10 *latency_stats; 566 567 // External TDIODE info 568 NVSWITCH_TDIODE_INFO_TYPE tdiode; 569 570 // Ganged Link table 571 NvU64 *ganged_link_table; 572 573 // 574 // Mask of links on the LR10 device connected to a disabled 575 // remote link 576 // 577 NvU64 disabledRemoteEndLinkMask; 578 579 // 580 // Bool indicating if disabledRemoteEndLinkMask 581 // has been cached previously 582 // 583 NvBool bDisabledRemoteEndLinkMaskCached; 584 } lr10_device; 585 586 #define NVSWITCH_NUM_DEVICES_PER_DELTA_LR10 6 587 588 typedef struct { 589 NvU32 switchPhysicalId; 590 NvU64 accessLinkMask; 591 NvU64 trunkLinkMask; 592 } lr10_links_connected_to_disabled_remote_end; 593 594 #define NVSWITCH_GET_CHIP_DEVICE_LR10(_device) \ 595 ( \ 596 ((_device)->chip_id == NV_PSMC_BOOT_42_CHIP_ID_LR10) ? \ 597 ((lr10_device *) _device->chip_device) : \ 598 NULL \ 599 ) 600 601 // 602 // Internal function declarations 603 // 604 NvlStatus nvswitch_device_discovery_lr10(nvswitch_device *device, NvU32 discovery_offset); 605 void nvswitch_filter_discovery_lr10(nvswitch_device *device); 606 NvlStatus nvswitch_process_discovery_lr10(nvswitch_device *device); 607 nvswitch_device *nvswitch_get_device_by_pci_info_lr10(nvlink_pci_info *info); 608 NvlStatus nvswitch_ring_master_cmd_lr10(nvswitch_device *device, NvU32 cmd); 609 void nvswitch_initialize_interrupt_tree_lr10(nvswitch_device *device); 610 void nvswitch_lib_enable_interrupts_lr10(nvswitch_device *device); 611 void nvswitch_lib_disable_interrupts_lr10(nvswitch_device *device); 612 NvlStatus nvswitch_lib_service_interrupts_lr10(nvswitch_device *device); 613 NvlStatus nvswitch_lib_check_interrupts_lr10(nvswitch_device *device); 614 void nvswitch_set_ganged_link_table_lr10(nvswitch_device *device, NvU32 firstIndex, NvU64 *ganged_link_table, NvU32 numEntries); 615 NvlStatus nvswitch_pmgr_init_config_lr10(nvswitch_device *device); 616 NvlStatus nvswitch_minion_service_falcon_interrupts_lr10(nvswitch_device *device, NvU32 instance); 617 NvlStatus nvswitch_ctrl_i2c_indexed_lr10(nvswitch_device *device, 618 NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); 619 NvU32 nvswitch_i2c_get_port_info_lr10(nvswitch_device *device, NvU32 port); 620 void nvswitch_translate_error_lr10(NVSWITCH_ERROR_TYPE *error_entry, 621 NVSWITCH_NVLINK_ARCH_ERROR *arch_error, 622 NVSWITCH_NVLINK_HW_ERROR *hw_error); 623 NvlStatus nvswitch_corelib_add_link_lr10(nvlink_link *link); 624 NvlStatus nvswitch_corelib_remove_link_lr10(nvlink_link *link); 625 NvlStatus nvswitch_corelib_set_dl_link_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 626 NvlStatus nvswitch_corelib_get_dl_link_mode_lr10(nvlink_link *link, NvU64 *mode); 627 NvlStatus nvswitch_corelib_set_tl_link_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 628 NvlStatus nvswitch_corelib_get_tl_link_mode_lr10(nvlink_link *link, NvU64 *mode); 629 NvlStatus nvswitch_corelib_set_tx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 630 NvlStatus nvswitch_corelib_get_tx_mode_lr10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); 631 NvlStatus nvswitch_corelib_set_rx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 632 NvlStatus nvswitch_corelib_get_rx_mode_lr10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); 633 NvlStatus nvswitch_corelib_set_rx_detect_lr10(nvlink_link *link, NvU32 flags); 634 NvlStatus nvswitch_corelib_get_rx_detect_lr10(nvlink_link *link); 635 void nvswitch_corelib_training_complete_lr10(nvlink_link *link); 636 NvBool nvswitch_link_lane_reversed_lr10(nvswitch_device *device, NvU32 linkId); 637 NvBool nvswitch_is_link_in_reset_lr10(nvswitch_device *device, nvlink_link *link); 638 NvlStatus nvswitch_wait_for_tl_request_ready_lr10(nvlink_link *link); 639 NvlStatus nvswitch_request_tl_link_state_lr10(nvlink_link *link, NvU32 tlLinkState, NvBool bSync); 640 void nvswitch_execute_unilateral_link_shutdown_lr10(nvlink_link *link); 641 NvlStatus nvswitch_get_link_public_id_lr10(nvswitch_device *device, NvU32 linkId, NvU32 *publicId); 642 NvlStatus nvswitch_get_link_local_idx_lr10(nvswitch_device *device, NvU32 linkId, NvU32 *localLinkIdx); 643 NvlStatus nvswitch_set_training_error_info_lr10(nvswitch_device *device, 644 NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS *pLinkTrainingErrorInfoParams); 645 NvlStatus nvswitch_read_vbios_link_entries_lr10(nvswitch_device *device, NvU32 tblPtr,NvU32 entriesCount,NVLINK_CONFIG_DATA_LINKENTRY *link_entries, NvU32 *identified_entriesCount); 646 NvlStatus nvswitch_ctrl_get_fatal_error_scope_lr10(nvswitch_device *device, NVSWITCH_GET_FATAL_ERROR_SCOPE_PARAMS *pParams); 647 void nvswitch_init_scratch_lr10(nvswitch_device *device); 648 void nvswitch_init_dlpl_interrupts_lr10(nvlink_link *link); 649 NvlStatus nvswitch_init_nport_lr10(nvswitch_device *device); 650 NvlStatus nvswitch_poll_sublink_state_lr10(nvswitch_device *device, nvlink_link *link); 651 void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 linkNumber); 652 void nvswitch_reset_persistent_link_hw_state_lr10(nvswitch_device *device, NvU32 linkNumber); 653 void nvswitch_store_topology_information_lr10(nvswitch_device *device, nvlink_link *link); 654 void nvswitch_init_lpwr_regs_lr10(nvlink_link *link); 655 void nvswitch_program_l1_scratch_reg_lr10(nvswitch_device *device, NvU32 linkNumber); 656 NvlStatus nvswitch_set_training_mode_lr10(nvswitch_device *device); 657 NvBool nvswitch_i2c_is_device_access_allowed_lr10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead); 658 NvU32 nvswitch_get_sublink_width_lr10(nvswitch_device *device,NvU32 linkNumber); 659 NvlStatus nvswitch_parse_bios_image_lr10(nvswitch_device *device); 660 NvlStatus nvswitch_ctrl_get_throughput_counters_lr10(nvswitch_device *device, NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *p); 661 void nvswitch_corelib_get_uphy_load_lr10(nvlink_link *link, NvBool *bUnlocked); 662 void nvswitch_init_buffer_ready_lr10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); 663 NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *params); 664 NvlStatus nvswitch_service_nvldl_fatal_link_lr10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link); 665 NvlStatus nvswitch_ctrl_inband_send_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p); 666 NvlStatus nvswitch_ctrl_inband_read_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p); 667 void nvswitch_send_inband_nack_lr10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId); 668 NvU32 nvswitch_get_max_persistent_message_count_lr10(nvswitch_device *device); 669 NvlStatus nvswitch_launch_ALI_link_training_lr10(nvswitch_device *device, nvlink_link *link, NvBool bSync); 670 NvlStatus nvswitch_service_minion_link_lr10(nvswitch_device *device, NvU32 nvliptInstance); 671 void nvswitch_apply_recal_settings_lr10(nvswitch_device *device, nvlink_link *link); 672 NvlStatus nvswitch_ctrl_get_sw_info_lr10(nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p); 673 void nvswitch_setup_link_system_registers_lr10(nvswitch_device *device, nvlink_link *link); 674 void nvswitch_load_link_disable_settings_lr10(nvswitch_device *device, nvlink_link *link); 675 NvBool nvswitch_is_smbpbi_supported_lr10(nvswitch_device *device); 676 NvlStatus nvswitch_ctrl_get_board_part_number_lr10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p); 677 NvlStatus nvswitch_ctrl_get_link_l1_capability_lr10(nvswitch_device *device, NvU32 linkId, NvBool *isL1Capable); 678 NvlStatus nvswitch_ctrl_get_link_l1_threshold_lr10(nvswitch_device *device, NvU32 linkNum, NvU32 *lpThreshold); 679 NvlStatus nvswitch_ctrl_set_link_l1_threshold_lr10(nvlink_link *link, NvU32 lpEntryThreshold); 680 NvlStatus nvswitch_get_board_id_lr10(nvswitch_device *device, NvU16 *boardId); 681 682 NvlStatus nvswitch_ctrl_get_soe_heartbeat_lr10(nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p); 683 void nvswitch_update_link_state_led_lr10(nvswitch_device *device); 684 void nvswitch_led_shutdown_lr10(nvswitch_device *device); 685 686 NvlStatus nvswitch_ctrl_set_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p); 687 NvlStatus nvswitch_ctrl_get_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p); 688 NvlStatus nvswitch_launch_ALI_lr10(nvswitch_device *device); 689 NvlStatus nvswitch_reset_and_train_link_lr10(nvswitch_device *device, nvlink_link *link); 690 691 NvlStatus nvswitch_ctrl_get_bios_info_lr10(nvswitch_device *device, NVSWITCH_GET_BIOS_INFO_PARAMS *p); 692 NvBool nvswitch_does_link_need_termination_enabled_lr10(nvswitch_device *device, nvlink_link *link); 693 NvlStatus nvswitch_link_termination_setup_lr10(nvswitch_device *device, nvlink_link* link); 694 void nvswitch_fsp_update_cmdq_head_tail_lr10(nvswitch_device *device, NvU32 queueHead, NvU32 queueTail); 695 void nvswitch_fsp_get_cmdq_head_tail_lr10(nvswitch_device *device, NvU32 *pQueueHead, NvU32 *pQueueTail); 696 void nvswitch_fsp_update_msgq_head_tail_lr10(nvswitch_device *device, NvU32 msgqHead, NvU32 msgqTail); 697 void nvswitch_fsp_get_msgq_head_tail_lr10(nvswitch_device *device, NvU32 *pMsgqHead, NvU32 *pMsgqTail); 698 NvU32 nvswitch_fsp_get_channel_size_lr10(nvswitch_device *device); 699 NvU8 nvswitch_fsp_nvdm_to_seid_lr10(nvswitch_device *device, NvU8 nvdmType); 700 NvU32 nvswitch_fsp_create_mctp_header_lr10(nvswitch_device *device, NvU8 som, NvU8 eom, NvU8 seid, NvU8 seq); 701 NvU32 nvswitch_fsp_create_nvdm_header_lr10(nvswitch_device *device, NvU32 nvdmType); 702 NvlStatus nvswitch_fsp_get_packet_info_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size, NvU8 *pPacketState, NvU8 *pTag); 703 NvlStatus nvswitch_fsp_validate_mctp_payload_header_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 704 NvlStatus nvswitch_fsp_process_nvdm_msg_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 705 NvlStatus nvswitch_fsp_process_cmd_response_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 706 NvlStatus nvswitch_fsp_config_ememc_lr10(nvswitch_device *device, NvU32 offset, NvBool bAincw, NvBool bAincr); 707 NvlStatus nvswitch_fsp_write_to_emem_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 708 NvlStatus nvswitch_fsp_read_from_emem_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 709 NvlStatus nvswitch_fsp_error_code_to_nvlstatus_map_lr10(nvswitch_device *device, NvU32 errorCode); 710 NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_lr10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS *params); 711 NvlStatus nvswitch_tnvl_get_attestation_report_lr10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params); 712 NvlStatus nvswitch_tnvl_get_status_lr10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params); 713 #endif //_LR10_H_ 714