1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the Software), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _LS10_H_ 25 #define _LS10_H_ 26 27 28 29 #include "export_nvswitch.h" 30 #include "common_nvswitch.h" 31 32 #include "ctrl_dev_nvswitch.h" 33 34 #include "nvswitch/ls10/dev_master.h" 35 36 #define NVSWITCH_NUM_LINKS_LS10 64 37 #define NVSWITCH_NUM_LANES_LS10 2 38 39 #define NVSWITCH_LINKS_PER_MINION_LS10 4 40 #define NVSWITCH_LINKS_PER_NVLIPT_LS10 4 41 #define NVSWITCH_LINKS_PER_NVLW_LS10 4 42 #define NVSWITCH_LINKS_PER_NPG_LS10 4 43 44 #define NVSWITCH_NPORT_PER_NPG_LS10 NVSWITCH_LINKS_PER_NPG_LS10 45 46 #define NUM_PTOP_ENGINE_LS10 1 47 #define NUM_FUSE_ENGINE_LS10 1 48 #define NUM_GIN_ENGINE_LS10 1 49 #define NUM_JTAG_ENGINE_LS10 1 50 51 #define NUM_PMGR_ENGINE_LS10 1 52 #define NUM_SAW_ENGINE_LS10 1 53 #define NUM_ROM_ENGINE_LS10 1 54 #define NUM_EXTDEV_ENGINE_LS10 1 55 #define NUM_PTIMER_ENGINE_LS10 1 56 #define NUM_SOE_ENGINE_LS10 1 57 #define NUM_SMR_ENGINE_LS10 2 58 #define NUM_SE_ENGINE_LS10 1 59 #define NUM_THERM_ENGINE_LS10 1 60 #define NUM_XAL_ENGINE_LS10 1 61 #define NUM_XAL_FUNC_ENGINE_LS10 1 62 #define NUM_XTL_CONFIG_ENGINE_LS10 1 63 #define NUM_XPL_ENGINE_LS10 1 64 #define NUM_XTL_ENGINE_LS10 1 65 #define NUM_SYSCTRL_ENGINE_LS10 1 66 #define NUM_UXL_ENGINE_LS10 1 67 #define NUM_GPU_PTOP_ENGINE_LS10 1 68 #define NUM_PMC_ENGINE_LS10 1 69 #define NUM_PBUS_ENGINE_LS10 1 70 #define NUM_ROM2_ENGINE_LS10 1 71 #define NUM_GPIO_ENGINE_LS10 1 72 #define NUM_FSP_ENGINE_LS10 1 73 74 #define NUM_CLKS_SYS_ENGINE_LS10 1 75 #define NUM_CLKS_SYSB_ENGINE_LS10 1 76 #define NUM_CLKS_P0_ENGINE_LS10 4 77 #define NUM_CLKS_P0_BCAST_ENGINE_LS10 1 78 #define NUM_SAW_PM_ENGINE_LS10 1 79 #define NUM_PCIE_PM_ENGINE_LS10 1 80 #define NUM_PRT_PRI_HUB_ENGINE_LS10 16 81 #define NUM_PRT_PRI_RS_CTRL_ENGINE_LS10 16 82 #define NUM_PRT_PRI_HUB_BCAST_ENGINE_LS10 1 83 #define NUM_PRT_PRI_RS_CTRL_BCAST_ENGINE_LS10 1 84 #define NUM_SYS_PRI_HUB_ENGINE_LS10 1 85 #define NUM_SYS_PRI_RS_CTRL_ENGINE_LS10 1 86 #define NUM_SYSB_PRI_HUB_ENGINE_LS10 1 87 #define NUM_SYSB_PRI_RS_CTRL_ENGINE_LS10 1 88 #define NUM_PRI_MASTER_RS_ENGINE_LS10 1 89 90 #define NUM_NPG_ENGINE_LS10 16 91 #define NUM_NPG_PERFMON_ENGINE_LS10 NUM_NPG_ENGINE_LS10 92 #define NUM_NPORT_ENGINE_LS10 (NUM_NPG_ENGINE_LS10 * NVSWITCH_NPORT_PER_NPG_LS10) 93 #define NUM_NPORT_MULTICAST_ENGINE_LS10 NUM_NPG_ENGINE_LS10 94 #define NUM_NPORT_PERFMON_ENGINE_LS10 NUM_NPORT_ENGINE_LS10 95 #define NUM_NPORT_PERFMON_MULTICAST_ENGINE_LS10 NUM_NPG_ENGINE_LS10 96 97 #define NUM_NPG_BCAST_ENGINE_LS10 1 98 #define NUM_NPG_PERFMON_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10 99 #define NUM_NPORT_BCAST_ENGINE_LS10 NVSWITCH_NPORT_PER_NPG_LS10 100 #define NUM_NPORT_MULTICAST_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10 101 #define NUM_NPORT_PERFMON_BCAST_ENGINE_LS10 NUM_NPORT_BCAST_ENGINE_LS10 102 #define NUM_NPORT_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10 103 104 #define NUM_NVLW_ENGINE_LS10 16 105 #define NUM_NVLIPT_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 106 #define NUM_MINION_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 107 #define NUM_PLL_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 108 #define NUM_CPR_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 109 #define NUM_NVLW_PERFMON_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 110 #define NUM_NVLIPT_SYS_PERFMON_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 111 #define NUM_NVLDL_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 112 #define NUM_NVLTLC_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 113 #define NUM_NVLIPT_LNK_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 114 #define NUM_SYS_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 115 #define NUM_TX_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 116 #define NUM_RX_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 117 #define NUM_NVLDL_ENGINE_LS10 (NUM_NVLW_ENGINE_LS10 * NVSWITCH_LINKS_PER_NVLIPT_LS10) 118 #define NUM_NVLTLC_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 119 #define NUM_NVLIPT_LNK_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 120 #define NUM_SYS_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 121 #define NUM_TX_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 122 #define NUM_RX_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 123 124 #define NUM_NVLW_BCAST_ENGINE_LS10 1 125 #define NUM_NVLIPT_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 126 #define NUM_MINION_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 127 #define NUM_PLL_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 128 #define NUM_CPR_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 129 #define NUM_NVLW_PERFMON_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 130 #define NUM_NVLIPT_SYS_PERFMON_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 131 #define NUM_NVLDL_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 132 #define NUM_NVLTLC_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 133 #define NUM_NVLIPT_LNK_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 134 #define NUM_SYS_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 135 #define NUM_TX_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 136 #define NUM_RX_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 137 #define NUM_NVLDL_BCAST_ENGINE_LS10 NVSWITCH_LINKS_PER_NVLIPT_LS10 138 #define NUM_NVLTLC_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 139 #define NUM_NVLIPT_LNK_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 140 #define NUM_SYS_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 141 #define NUM_TX_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 142 #define NUM_RX_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 143 144 #define NUM_NXBAR_ENGINE_LS10 3 145 #define NUM_NXBAR_PERFMON_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 146 #define NUM_TILE_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 147 #define NUM_TILE_PERFMON_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 148 #define NUM_TILE_ENGINE_LS10 (12 * NUM_NXBAR_ENGINE_LS10) 149 #define NUM_TILE_PERFMON_ENGINE_LS10 NUM_TILE_ENGINE_LS10 150 #define NUM_TILEOUT_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 151 #define NUM_TILEOUT_PERFMON_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 152 #define NUM_TILEOUT_ENGINE_LS10 NUM_TILE_ENGINE_LS10 153 #define NUM_TILEOUT_PERFMON_ENGINE_LS10 NUM_TILE_ENGINE_LS10 154 155 #define NUM_NXBAR_BCAST_ENGINE_LS10 1 156 #define NUM_NXBAR_PERFMON_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 157 #define NUM_TILE_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 158 #define NUM_TILE_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 159 #define NUM_TILE_BCAST_ENGINE_LS10 12 160 #define NUM_TILE_PERFMON_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10 161 #define NUM_TILEOUT_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 162 #define NUM_TILEOUT_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 163 #define NUM_TILEOUT_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10 164 #define NUM_TILEOUT_PERFMON_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10 165 #define NUM_MAX_MCFLA_SLOTS_LS10 128 166 167 #define NPORT_TO_LINK_LS10(_device, _npg, _nport) \ 168 ( \ 169 NVSWITCH_ASSERT((_npg < NUM_NPG_ENGINE_LS10)) \ 170 , \ 171 NVSWITCH_ASSERT((_nport < NVSWITCH_NPORT_PER_NPG_LS10)) \ 172 , \ 173 ((_npg) * NVSWITCH_NPORT_PER_NPG_LS10 + (_nport)) \ 174 ) 175 176 #define NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10 (NVSWITCH_NUM_LINKS_LS10/NUM_NVLIPT_ENGINE_LS10) 177 178 #define NVSWITCH_NVLIPT_GET_PUBLIC_ID_LS10(_physlinknum) \ 179 ((_physlinknum)/NVSWITCH_LINKS_PER_NVLIPT_LS10) 180 181 #define NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(_physlinknum) \ 182 ((_physlinknum)%NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10) 183 184 #define NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(_nvlipt_idx) \ 185 (NVBIT64(NVSWITCH_LINKS_PER_NVLIPT_LS10) - 1) << (_nvlipt_idx * NVSWITCH_LINKS_PER_NVLIPT_LS10); 186 187 #define DMA_ADDR_WIDTH_LS10 64 188 189 #define SOE_VBIOS_VERSION_MASK 0xFF0000 190 #define SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR 0x370000 191 #define SOE_VBIOS_REVLOCK_ISSUE_INGRESS_STOP 0x440000 192 193 // LS10 Saved LED state 194 #define ACCESS_LINK_LED_STATE CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED 195 196 // Access link LED states on LS10 Systems 197 #define ACCESS_LINK_LED_STATE_FAULT 0U 198 #define ACCESS_LINK_LED_STATE_OFF 1U 199 #define ACCESS_LINK_LED_STATE_INITIALIZE 2U 200 #define ACCESS_LINK_LED_STATE_UP_WARM 3U 201 #define ACCESS_LINK_LED_STATE_UP_ACTIVE 4U 202 #define ACCESS_LINK_NUM_LED_STATES 5U 203 204 // 205 // Helpful IO wrappers 206 // 207 208 #define NVSWITCH_NPORT_WR32_LS10(_d, _engidx, _dev, _reg, _data) \ 209 NVSWITCH_ENG_WR32(_d, NPORT, , _engidx, _dev, _reg, _data) 210 211 #define NVSWITCH_NPORT_RD32_LS10(_d, _engidx, _dev, _reg) \ 212 NVSWITCH_ENG_RD32(_d, NPORT, , _engidx, _dev, _reg) 213 214 #define NVSWITCH_MINION_WR32_LS10(_d, _engidx, _dev, _reg, _data) \ 215 NVSWITCH_ENG_WR32(_d, MINION, , _engidx, _dev, _reg, _data) 216 217 #define NVSWITCH_MINION_RD32_LS10(_d, _engidx, _dev, _reg) \ 218 NVSWITCH_ENG_RD32(_d, MINION, , _engidx, _dev, _reg) 219 220 #define NVSWITCH_MINION_WR32_BCAST_LS10(_d, _dev, _reg, _data) \ 221 NVSWITCH_ENG_WR32(_d, MINION, _BCAST, 0, _dev, _reg, _data) 222 223 #define NVSWITCH_NPG_WR32_LS10(_d, _engidx, _dev, _reg, _data) \ 224 NVSWITCH_ENG_WR32(_d, NPG, , _engidx, _dev, _reg, _data) 225 226 #define NVSWITCH_NPG_RD32_LS10(_d, _engidx, _dev, _reg) \ 227 NVSWITCH_ENG_RD32(_d, NPG, , _engidx, _dev, _reg) 228 229 // 230 // Per-chip device information 231 // 232 233 #define DISCOVERY_TYPE_UNDEFINED 0 234 #define DISCOVERY_TYPE_DISCOVERY 1 235 #define DISCOVERY_TYPE_UNICAST 2 236 #define DISCOVERY_TYPE_BROADCAST 3 237 238 typedef struct 239 { 240 NvBool valid; 241 NvU32 initialized; 242 NvU32 version; 243 NvU32 disc_type; 244 union 245 { 246 struct 247 { 248 NvU32 cluster; 249 NvU32 cluster_id; 250 NvU32 discovery; // Used for top level only 251 } top; 252 struct 253 { 254 NvU32 uc_addr; 255 } uc; 256 struct 257 { 258 NvU32 bc_addr; 259 NvU32 mc_addr[3]; 260 } bc; 261 } info; 262 } ENGINE_DISCOVERY_TYPE_LS10; 263 264 #define NVSWITCH_DECLARE_ENGINE_UC_LS10(_engine) \ 265 ENGINE_DISCOVERY_TYPE_LS10 eng##_engine[NUM_##_engine##_ENGINE_LS10]; 266 267 #define NVSWITCH_DECLARE_ENGINE_LS10(_engine) \ 268 ENGINE_DISCOVERY_TYPE_LS10 eng##_engine[NUM_##_engine##_ENGINE_LS10]; \ 269 ENGINE_DISCOVERY_TYPE_LS10 eng##_engine##_BCAST[NUM_##_engine##_BCAST_ENGINE_LS10]; 270 271 #define NVSWITCH_LIST_LS10_ENGINE_UC(_op) \ 272 _op(PTOP) \ 273 _op(FUSE) \ 274 _op(GIN) \ 275 _op(JTAG) \ 276 _op(PMGR) \ 277 _op(SAW) \ 278 _op(ROM) \ 279 _op(EXTDEV) \ 280 _op(PTIMER) \ 281 _op(SOE) \ 282 _op(SMR) \ 283 _op(SE) \ 284 _op(THERM) \ 285 _op(XAL) \ 286 _op(XAL_FUNC) \ 287 _op(XTL_CONFIG) \ 288 _op(XPL) \ 289 _op(XTL) \ 290 _op(UXL) \ 291 _op(GPU_PTOP) \ 292 _op(PMC) \ 293 _op(PBUS) \ 294 _op(ROM2) \ 295 _op(GPIO) \ 296 _op(FSP) \ 297 _op(CLKS_SYS) \ 298 _op(CLKS_SYSB) \ 299 _op(CLKS_P0) \ 300 _op(CLKS_P0_BCAST) \ 301 _op(SAW_PM) \ 302 _op(PCIE_PM) \ 303 _op(SYS_PRI_HUB) \ 304 _op(SYS_PRI_RS_CTRL) \ 305 _op(SYSB_PRI_HUB) \ 306 _op(SYSB_PRI_RS_CTRL) \ 307 _op(PRI_MASTER_RS) \ 308 309 #define NVSWITCH_LIST_PRI_HUB_LS10_ENGINE(_op) \ 310 _op(PRT_PRI_HUB) \ 311 _op(PRT_PRI_RS_CTRL) \ 312 _op(PRT_PRI_HUB_BCAST) \ 313 _op(PRT_PRI_RS_CTRL_BCAST) \ 314 315 #define NVSWITCH_LIST_NPG_LS10_ENGINE(_op) \ 316 _op(NPG) \ 317 _op(NPG_PERFMON) \ 318 _op(NPORT) \ 319 _op(NPORT_MULTICAST) \ 320 _op(NPORT_PERFMON) \ 321 _op(NPORT_PERFMON_MULTICAST) 322 323 #define NVSWITCH_LIST_NVLW_LS10_ENGINE(_op) \ 324 _op(NVLW) \ 325 _op(NVLIPT) \ 326 _op(MINION) \ 327 _op(CPR) \ 328 _op(NVLW_PERFMON) \ 329 _op(NVLIPT_SYS_PERFMON) \ 330 _op(NVLDL_MULTICAST) \ 331 _op(NVLTLC_MULTICAST) \ 332 _op(NVLIPT_LNK_MULTICAST) \ 333 _op(SYS_PERFMON_MULTICAST) \ 334 _op(TX_PERFMON_MULTICAST) \ 335 _op(RX_PERFMON_MULTICAST) \ 336 _op(NVLDL) \ 337 _op(NVLTLC) \ 338 _op(NVLIPT_LNK) \ 339 _op(SYS_PERFMON) \ 340 _op(TX_PERFMON) \ 341 _op(RX_PERFMON) 342 343 #define NVSWITCH_LIST_NXBAR_LS10_ENGINE(_op) \ 344 _op(NXBAR) \ 345 _op(NXBAR_PERFMON) \ 346 _op(TILE_MULTICAST) \ 347 _op(TILE_PERFMON_MULTICAST) \ 348 _op(TILE) \ 349 _op(TILE_PERFMON) \ 350 _op(TILEOUT_MULTICAST) \ 351 _op(TILEOUT_PERFMON_MULTICAST) \ 352 _op(TILEOUT) \ 353 _op(TILEOUT_PERFMON) 354 355 #define NVSWITCH_LIST_LS10_ENGINE(_op) \ 356 NVSWITCH_LIST_NPG_LS10_ENGINE(_op) \ 357 NVSWITCH_LIST_NVLW_LS10_ENGINE(_op) \ 358 NVSWITCH_LIST_NXBAR_LS10_ENGINE(_op) 359 360 // 361 // The chip-specific engine list is used to generate the code to collect 362 // discovered unit information and coalesce it into the data structures used by 363 // the common IO library (see io_nvswitch.h). 364 // 365 // The PTOP discovery table presents the information on wrappers and sub-units 366 // in a hierarchical manner. The top level discovery contains information 367 // about top level UNICAST units and IP wrappers like NPG, NVLW, and NXBAR. 368 // Individual units within an IP wrapper are described in discovery sub-tables. 369 // Each IP wrapper may have MULTICAST descriptors to allow addressing sub-units 370 // within a wrapper and a cluster of IP wrappers will also have a BCAST 371 // discovery tables, which have MULTICAST descriptors within them. 372 // In order to collect all the useful unit information into a single container, 373 // we need to pick where to find each piece within the parsed discovery table. 374 // Top level IP wrappers like NPG have a BCAST range to broadcast reads/writes, 375 // but IP sub-units like NPORT have a MULTICAST range within the BCAST IP 376 // wrapper to broadcast to all the sub-units in all the IP wrappers. 377 // So in the lists below top level IP wrappers (NPG, NVLW, and NXBAR) point 378 // to the _BCAST IP wrapper, but sub-unit point to the _MULTICAST range inside 379 // the BCAST unit (_MULTICAST_BCAST). 380 // 381 // All IP-based (0-based register manuals) engines need to be listed here to 382 // generate chip-specific handlers as well as in the global common list of all 383 // engines that have ever existed on *ANY* architecture(s) in order for them 384 // use common IO wrappers. 385 // 386 387 #define NVSWITCH_LIST_LS10_ENGINES(_op) \ 388 _op(GIN, ) \ 389 _op(XAL, ) \ 390 _op(XPL, ) \ 391 _op(XTL, ) \ 392 _op(XTL_CONFIG, ) \ 393 _op(SAW, ) \ 394 _op(SOE, ) \ 395 _op(SMR, ) \ 396 \ 397 _op(PRT_PRI_HUB, _BCAST) \ 398 _op(PRT_PRI_RS_CTRL, _BCAST) \ 399 _op(SYS_PRI_HUB, ) \ 400 _op(SYS_PRI_RS_CTRL, ) \ 401 _op(SYSB_PRI_HUB, ) \ 402 _op(SYSB_PRI_RS_CTRL, ) \ 403 _op(PRI_MASTER_RS, ) \ 404 _op(PTIMER, ) \ 405 _op(CLKS_SYS, ) \ 406 _op(CLKS_SYSB, ) \ 407 _op(CLKS_P0, _BCAST) \ 408 \ 409 _op(NPG, _BCAST) \ 410 _op(NPORT, _MULTICAST_BCAST) \ 411 \ 412 _op(NVLW, _BCAST) \ 413 _op(MINION, _BCAST) \ 414 _op(NVLIPT, _BCAST) \ 415 _op(CPR, _BCAST) \ 416 _op(NVLIPT_LNK, _MULTICAST_BCAST) \ 417 _op(NVLTLC, _MULTICAST_BCAST) \ 418 _op(NVLDL, _MULTICAST_BCAST) \ 419 \ 420 _op(NXBAR, _BCAST) \ 421 _op(TILE, _MULTICAST_BCAST) \ 422 _op(TILEOUT, _MULTICAST_BCAST) \ 423 \ 424 _op(NPG_PERFMON, _BCAST) \ 425 _op(NPORT_PERFMON, _MULTICAST_BCAST) \ 426 \ 427 _op(NVLW_PERFMON, _BCAST) \ 428 429 // 430 // These field #defines describe which physical fabric address bits are 431 // relevant to the specific remap table address check/remap operation. 432 // 433 434 #define NV_INGRESS_REMAP_ADDR_PHYS_LS10 51:39 /* LR10: 46:36 */ 435 436 #define NV_INGRESS_REMAP_ADR_OFFSET_PHYS_LS10 38:21 /* LR10: 35:20 */ 437 #define NV_INGRESS_REMAP_ADR_BASE_PHYS_LS10 38:21 /* LR10: 35:20 */ 438 #define NV_INGRESS_REMAP_ADR_LIMIT_PHYS_LS10 38:21 /* LR10: 35:20 */ 439 440 // 441 // Multicast REMAP table is not indexed through the same _RAM_SEL mechanism as 442 // other REMAP tables, but we want to be able to use the same set of APIs for 443 // all the REMAP tables, so define a special RAM_SEL value for MCREMAP that 444 // does not conflict with the existing definitions. 445 // 446 #define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECT_MULTICAST_REMAPRAM (DRF_MASK(NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS) + 1) 447 448 // 449 // NPORT Portstat information 450 // 451 452 // 453 // LS10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs. 454 // But DNGRD(1), ATR(2), ATSD(3), and PROBE(4) will be never used. 455 // 456 #define NVSWITCH_NUM_VCS_LS10 8 457 458 typedef struct 459 { 460 NvU32 count; 461 NvU32 low; 462 NvU32 medium; 463 NvU32 high; 464 NvU32 panic; 465 } 466 NVSWITCH_LATENCY_BINS_LS10; 467 468 typedef struct 469 { 470 NvU32 count; 471 NvU64 start_time_nsec; 472 NvU64 last_read_time_nsec; 473 NVSWITCH_LATENCY_BINS_LS10 accum_latency[NVSWITCH_NUM_LINKS_LS10]; 474 } 475 NVSWITCH_LATENCY_VC_LS10; 476 477 typedef struct 478 { 479 NvU32 sample_interval_msec; 480 NvU64 last_visited_time_nsec; 481 NVSWITCH_LATENCY_VC_LS10 latency[NVSWITCH_NUM_VCS_LS10]; 482 } NVSWITCH_LATENCY_STATS_LS10; 483 484 #define NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo) (NV_NPORT_PORTSTAT ## _block ## _reg ## _0 ## _hi_lo + \ 485 _vc * (NV_NPORT_PORTSTAT ## _block ## _reg ## _1 ## _hi_lo - NV_NPORT_PORTSTAT ## _block ## _reg ## _0 ## _hi_lo)) 486 487 #define NVSWITCH_NPORT_PORTSTAT_RD32_LS10(_d, _engidx, _block, _reg, _hi_lo, _vc) \ 488 ( \ 489 NVSWITCH_ASSERT(NVSWITCH_IS_LINK_ENG_VALID_LS10(_d, NPORT, _engidx)) \ 490 , \ 491 NVSWITCH_PRINT(_d, MMIO, \ 492 "%s: MEM_RD NPORT_PORTSTAT[%d]: %s,%s,_%s,%s (%06x+%04x)\n", \ 493 __FUNCTION__, \ 494 _engidx, \ 495 #_block, #_reg, #_vc, #_hi_lo, \ 496 NVSWITCH_GET_ENG(_d, NPORT, , _engidx), \ 497 NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo)) \ 498 , \ 499 nvswitch_reg_read_32(_d, \ 500 NVSWITCH_GET_ENG(_d, NPORT, , _engidx) + \ 501 NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo)) \ 502 ); \ 503 ((void)(_d)) 504 505 #define NVSWITCH_PORTSTAT_BCAST_WR32_LS10(_d, _block, _reg, _idx, _data) \ 506 { \ 507 NVSWITCH_PRINT(_d, MMIO, \ 508 "%s: BCAST_WR NPORT_PORTSTAT: %s,%s (%06x+%04x) 0x%08x\n", \ 509 __FUNCTION__, \ 510 #_block, #_reg, \ 511 NVSWITCH_GET_ENG(_d, NPORT, _BCAST, 0), \ 512 NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \ 513 NVSWITCH_OFF_WR32(_d, \ 514 NVSWITCH_GET_ENG(_d, NPORT, _BCAST, 0) + \ 515 NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \ 516 } 517 518 #define NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS ((device->bModeContinuousALI ? 12 : 30) *\ 519 NVSWITCH_INTERVAL_1SEC_IN_NS) 520 #define NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS (12 * NVSWITCH_INTERVAL_1MSEC_IN_NS) 521 522 // Struct used for passing around error masks in error handling functions 523 typedef struct 524 { 525 NvBool bPending; 526 NvU32 regData; 527 } MINION_LINK_INTR; 528 529 typedef struct 530 { 531 NvU32 dl; 532 NvU32 tlcRx0; 533 NvU32 tlcRx0Injected; 534 NvU32 tlcRx1; 535 NvU32 tlcRx1Injected; 536 NvU32 liptLnk; 537 NvU32 liptLnkInjected; 538 MINION_LINK_INTR minionLinkIntr; 539 } NVLINK_LINK_ERROR_INFO_ERR_MASKS, *PNVLINK_LINK_ERROR_INFO_ERR_MASKS; 540 541 typedef struct 542 { 543 NvBool bLinkErrorsCallBackEnabled; 544 NvBool bLinkStateCallBackEnabled; 545 NvU64 lastRetrainTime; 546 NvU64 lastLinkUpTime; 547 } NVLINK_LINK_ERROR_REPORTING_STATE; 548 549 typedef struct 550 { 551 NVLINK_LINK_ERROR_INFO_ERR_MASKS fatalIntrMask; 552 NVLINK_LINK_ERROR_INFO_ERR_MASKS nonFatalIntrMask; 553 } NVLINK_LINK_ERROR_REPORTING_DATA; 554 555 typedef struct 556 { 557 NVLINK_LINK_ERROR_REPORTING_STATE state; 558 NVLINK_LINK_ERROR_REPORTING_DATA data; 559 } NVLINK_LINK_ERROR_REPORTING; 560 561 typedef struct 562 { 563 struct 564 { 565 NVSWITCH_ENGINE_DESCRIPTOR_TYPE common[NVSWITCH_ENGINE_ID_SIZE]; 566 } io; 567 568 NVSWITCH_LIST_LS10_ENGINE_UC(NVSWITCH_DECLARE_ENGINE_UC_LS10) 569 NVSWITCH_LIST_PRI_HUB_LS10_ENGINE(NVSWITCH_DECLARE_ENGINE_UC_LS10) 570 NVSWITCH_LIST_LS10_ENGINE(NVSWITCH_DECLARE_ENGINE_LS10) 571 572 // Interrupts 573 NvU32 intr_minion_dest; 574 575 // VBIOS configuration Data 576 NVSWITCH_BIOS_NVLINK_CONFIG bios_config; 577 578 // GPIO 579 const NVSWITCH_GPIO_INFO *gpio_pin; 580 NvU32 gpio_pin_size; 581 582 // Latency statistics 583 NVSWITCH_LATENCY_STATS_LS10 *latency_stats; 584 585 // External TDIODE info 586 NVSWITCH_TDIODE_INFO_TYPE tdiode; 587 588 // 589 // Book-keep interrupt masks to restore them after reset. 590 // Note: There is no need to book-keep interrupt masks for NVLink units like 591 // DL, MINION, TLC etc. because NVLink init routines would setup them. 592 // 593 struct 594 { 595 NVSWITCH_INTERRUPT_MASK route; 596 NVSWITCH_INTERRUPT_MASK ingress[2]; 597 NVSWITCH_INTERRUPT_MASK egress[2]; 598 NVSWITCH_INTERRUPT_MASK tstate; 599 NVSWITCH_INTERRUPT_MASK sourcetrack; 600 NVSWITCH_INTERRUPT_MASK mc_tstate; 601 NVSWITCH_INTERRUPT_MASK red_tstate; 602 NVSWITCH_INTERRUPT_MASK tile; 603 NVSWITCH_INTERRUPT_MASK tileout; 604 } intr_mask; 605 606 // Ganged Link table 607 NvU64 *ganged_link_table; 608 609 //NVSWITCH Minion core 610 NvU32 minionEngArch; 611 612 NvBool riscvManifestBoot; 613 614 // Nvlink error reporting management 615 NVLINK_LINK_ERROR_REPORTING deferredLinkErrors[NVSWITCH_NUM_LINKS_LS10]; 616 617 } ls10_device; 618 619 // 620 // Helpful IO wrappers 621 // 622 623 #define NVSWITCH_GET_CHIP_DEVICE_LS10(_device) \ 624 ( \ 625 ((_device)->chip_id == NV_PMC_BOOT_42_CHIP_ID_LS10) ? \ 626 ((ls10_device *) _device->chip_device) : \ 627 NULL \ 628 ) 629 630 #define NVSWITCH_ENG_VALID_LS10(_d, _eng, _engidx) \ 631 ( \ 632 ((_engidx < NUM_##_eng##_ENGINE_LS10) && \ 633 (NVSWITCH_GET_CHIP_DEVICE_LS10(_d)->eng##_eng[_engidx].valid)) ? \ 634 NV_TRUE : NV_FALSE \ 635 ) 636 637 #define NVSWITCH_ENG_WR32_LS10(_d, _eng, _bcast, _engidx, _dev, _reg, _data) \ 638 NVSWITCH_ENG_WR32(_d, _eng, _bcast, _engidx, _dev, _reg, _data) 639 640 #define NVSWITCH_ENG_RD32_LS10(_d, _eng, _engidx, _dev, _reg) \ 641 NVSWITCH_ENG_RD32(_d, _eng, , _engidx, _dev, _reg) 642 643 #define NVSWITCH_BCAST_WR32_LS10(_d, _eng, _dev, _reg, _data) \ 644 NVSWITCH_ENG_WR32(_d, _eng, _BCAST, 0, _dev, _reg, _data) 645 646 #define NVSWITCH_BCAST_RD32_LS10(_d, _eng, _dev, _reg) \ 647 NVSWITCH_ENG_RD32(_d, _eng, _BCAST, 0, _dev, _reg) 648 649 #define NVSWITCH_SOE_WR32_LS10(_d, _instance, _dev, _reg, _data) \ 650 NVSWITCH_ENG_WR32(_d, SOE, , _instance, _dev, _reg, _data) 651 652 #define NVSWITCH_SOE_RD32_LS10(_d, _instance, _dev, _reg) \ 653 NVSWITCH_ENG_RD32(_d, SOE, , _instance, _dev, _reg) 654 655 #define NVSWITCH_NPORT_BCAST_WR32_LS10(_d, _dev, _reg, _data) \ 656 NVSWITCH_ENG_WR32(_d, NPORT, _BCAST, 0, _dev, _reg, _data) 657 658 #define NVSWITCH_SAW_WR32_LS10(_d, _dev, _reg, _data) \ 659 NVSWITCH_ENG_WR32(_d, SAW, , 0, _dev, _reg, _data) 660 661 #define NVSWITCH_SAW_RD32_LS10(_d, _dev, _reg) \ 662 NVSWITCH_ENG_RD32(_d, SAW, , 0, _dev, _reg) 663 664 #define NVSWITCH_NPORT_MC_BCAST_WR32_LS10(_d, _dev, _reg, _data) \ 665 NVSWITCH_BCAST_WR32_LS10(_d, NPORT, _dev, _reg, _data) 666 667 // 668 // Tile Column consists of 12 Tile blocks and 11 (really 12) Tileout blocks. 669 // 670 671 #define NUM_NXBAR_TILES_PER_TC_LS10 12 672 #define NUM_NXBAR_TILEOUTS_PER_TC_LS10 12 673 674 #define TILE_INDEX_LS10(_device, _nxbar, _tile) \ 675 ( \ 676 NVSWITCH_ASSERT((_nxbar < NUM_NXBAR_ENGINE_LS10)) \ 677 , \ 678 NVSWITCH_ASSERT((_tile < NUM_NXBAR_TILES_PER_TC_LS10)) \ 679 , \ 680 ((_nxbar) * NUM_NXBAR_TILES_PER_TC_LS10 + (_tile)) \ 681 ) 682 683 #define NVSWITCH_TILE_RD32(_d, _engidx, _dev, _reg) \ 684 NVSWITCH_ENG_RD32(_d, TILE, , _engidx, _dev, _reg) 685 686 #define NVSWITCH_TILE_WR32(_d, _engidx, _dev, _reg, _data) \ 687 NVSWITCH_ENG_WR32(_d, TILE, , _engidx, _dev, _reg, _data) 688 689 #define NVSWITCH_TILEOUT_RD32(_d, _engidx, _dev, _reg) \ 690 NVSWITCH_ENG_RD32(_d, TILEOUT, , _engidx, _dev, _reg) 691 692 #define NVSWITCH_TILEOUT_WR32(_d, _engidx, _dev, _reg, _data) \ 693 NVSWITCH_ENG_WR32(_d, TILEOUT, , _engidx, _dev, _reg, _data) 694 695 // 696 // Per link register access routines 697 // LINK_* MMIO wrappers are used to reference per-link engine instances 698 // 699 700 #define NVSWITCH_IS_LINK_ENG_VALID_LS10(_d, _eng, _linknum) \ 701 NVSWITCH_IS_LINK_ENG_VALID(_d, _linknum, _eng) 702 703 #define NVSWITCH_LINK_OFFSET_LS10(_d, _physlinknum, _eng, _dev, _reg) \ 704 NVSWITCH_LINK_OFFSET(_d, _physlinknum, _eng, _dev, _reg) 705 706 #define NVSWITCH_LINK_WR32_LS10(_d, _physlinknum, _eng, _dev, _reg, _data) \ 707 NVSWITCH_LINK_WR32(_d, _physlinknum, _eng, _dev, _reg, _data) 708 709 #define NVSWITCH_LINK_RD32_LS10(_d, _physlinknum, _eng, _dev, _reg) \ 710 NVSWITCH_LINK_RD32(_d, _physlinknum, _eng, _dev, _reg) 711 712 #define NVSWITCH_LINK_WR32_IDX_LS10(_d, _physlinknum, _eng, _dev, _reg, _idx, _data) \ 713 NVSWITCH_LINK_WR32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx, _data) 714 715 #define NVSWITCH_LINK_RD32_IDX_LS10(_d, _physlinknum, _eng, _dev, _reg, _idx) \ 716 NVSWITCH_LINK_RD32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx) 717 718 #define NVSWITCH_MINION_LINK_WR32_LS10(_d, _physlinknum, _dev, _reg, _data) \ 719 NVSWITCH_LINK_WR32(_d, _physlinknum, MINION, _dev, _reg, _data) 720 721 #define NVSWITCH_MINION_LINK_RD32_LS10(_d, _physlinknum, _dev, _reg) \ 722 NVSWITCH_LINK_RD32(_d, _physlinknum, MINION, _dev, _reg) 723 724 // 725 // MINION 726 // 727 728 typedef const struct 729 { 730 NvU32 osCodeOffset; 731 NvU32 osCodeSize; 732 NvU32 osDataOffset; 733 NvU32 osDataSize; 734 NvU32 numApps; 735 NvU32 appCodeStart; 736 NvU32 appDataStart; 737 NvU32 codeOffset; 738 NvU32 codeSize; 739 NvU32 dataOffset; 740 NvU32 dataSize; 741 } FALCON_UCODE_HDR_INFO_LS10, *PFALCON_UCODE_HDR_INFO_LS10; 742 743 typedef const struct 744 { 745 // 746 // Version 1 747 // Version 2 748 // Vesrion 3 = for Partition boot 749 // Vesrion 4 = for eb riscv boot 750 // 751 NvU32 version; // structure version 752 NvU32 bootloaderOffset; 753 NvU32 bootloaderSize; 754 NvU32 bootloaderParamOffset; 755 NvU32 bootloaderParamSize; 756 NvU32 riscvElfOffset; 757 NvU32 riscvElfSize; 758 NvU32 appVersion; // Changelist number associated with the image 759 // 760 // Manifest contains information about Monitor and it is 761 // input to BR 762 // 763 NvU32 manifestOffset; 764 NvU32 manifestSize; 765 // 766 // Monitor Data offset within RISCV image and size 767 // 768 NvU32 monitorDataOffset; 769 NvU32 monitorDataSize; 770 // 771 // Monitor Code offset withtin RISCV image and size 772 // 773 NvU32 monitorCodeOffset; 774 NvU32 monitorCodeSize; 775 NvU32 bIsMonitorEnabled; 776 // 777 // Swbrom Code offset within RISCV image and size 778 // 779 NvU32 swbromCodeOffset; 780 NvU32 swbromCodeSize; 781 // 782 // Swbrom Data offset within RISCV image and size 783 // 784 NvU32 swbromDataOffset; 785 NvU32 swbromDataSize; 786 } RISCV_UCODE_HDR_INFO_LS10, *PRISCV_UCODE_HDR_INFO_LS10; 787 788 // 789 // defines used by internal ls10 functions to get 790 // specific clock status 791 // 792 #define NVSWITCH_PER_LINK_CLOCK_RXCLK 0 793 #define NVSWITCH_PER_LINK_CLOCK_TXCLK 1 794 #define NVSWITCH_PER_LINK_CLOCK_NCISOCCLK 2 795 #define NVSWITCH_PER_LINK_CLOCK_NUM 3 796 #define NVSWITCH_PER_LINK_CLOCK_SET(_name) BIT(NVSWITCH_PER_LINK_CLOCK_##_name) 797 // 798 // HAL functions shared by LR10 and used by LS10 799 // 800 801 #define nvswitch_is_link_valid_ls10 nvswitch_is_link_valid_lr10 802 #define nvswitch_is_link_in_use_ls10 nvswitch_is_link_in_use_lr10 803 804 #define nvswitch_deassert_link_reset_ls10 nvswitch_deassert_link_reset_lr10 805 #define nvswitch_determine_platform_ls10 nvswitch_determine_platform_lr10 806 #define nvswitch_get_swap_clk_default_ls10 nvswitch_get_swap_clk_default_lr10 807 #define nvswitch_post_init_device_setup_ls10 nvswitch_post_init_device_setup_lr10 808 #define nvswitch_set_training_error_info_ls10 nvswitch_set_training_error_info_lr10 809 #define nvswitch_init_scratch_ls10 nvswitch_init_scratch_lr10 810 #define nvswitch_hw_counter_shutdown_ls10 nvswitch_hw_counter_shutdown_lr10 811 #define nvswitch_hw_counter_read_counter_ls10 nvswitch_hw_counter_read_counter_lr10 812 813 #define nvswitch_ecc_writeback_task_ls10 nvswitch_ecc_writeback_task_lr10 814 #define nvswitch_ctrl_get_routing_id_ls10 nvswitch_ctrl_get_routing_id_lr10 815 #define nvswitch_ctrl_set_routing_id_valid_ls10 nvswitch_ctrl_set_routing_id_valid_lr10 816 #define nvswitch_ctrl_set_routing_id_ls10 nvswitch_ctrl_set_routing_id_lr10 817 #define nvswitch_ctrl_set_routing_lan_ls10 nvswitch_ctrl_set_routing_lan_lr10 818 #define nvswitch_ctrl_get_routing_lan_ls10 nvswitch_ctrl_get_routing_lan_lr10 819 #define nvswitch_ctrl_set_routing_lan_valid_ls10 nvswitch_ctrl_set_routing_lan_valid_lr10 820 #define nvswitch_ctrl_set_ingress_request_table_ls10 nvswitch_ctrl_set_ingress_request_table_lr10 821 #define nvswitch_ctrl_get_ingress_request_table_ls10 nvswitch_ctrl_get_ingress_request_table_lr10 822 #define nvswitch_ctrl_set_ingress_request_valid_ls10 nvswitch_ctrl_set_ingress_request_valid_lr10 823 #define nvswitch_ctrl_get_ingress_response_table_ls10 nvswitch_ctrl_get_ingress_response_table_lr10 824 #define nvswitch_ctrl_set_ingress_response_table_ls10 nvswitch_ctrl_set_ingress_response_table_lr10 825 826 #define nvswitch_ctrl_get_info_ls10 nvswitch_ctrl_get_info_lr10 827 828 #define nvswitch_ctrl_set_switch_port_config_ls10 nvswitch_ctrl_set_switch_port_config_lr10 829 #define nvswitch_ctrl_get_throughput_counters_ls10 nvswitch_ctrl_get_throughput_counters_lr10 830 831 #define nvswitch_save_nvlink_seed_data_from_minion_to_inforom_ls10 nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10 832 #define nvswitch_store_seed_data_from_inforom_to_corelib_ls10 nvswitch_store_seed_data_from_inforom_to_corelib_lr10 833 #define nvswitch_corelib_clear_link_state_ls10 nvswitch_corelib_clear_link_state_lr10 834 835 #define nvswitch_read_oob_blacklist_state_ls10 nvswitch_read_oob_blacklist_state_lr10 836 837 #define nvswitch_corelib_add_link_ls10 nvswitch_corelib_add_link_lr10 838 #define nvswitch_corelib_remove_link_ls10 nvswitch_corelib_remove_link_lr10 839 #define nvswitch_corelib_set_tl_link_mode_ls10 nvswitch_corelib_set_tl_link_mode_lr10 840 #define nvswitch_corelib_set_rx_mode_ls10 nvswitch_corelib_set_rx_mode_lr10 841 #define nvswitch_corelib_set_rx_detect_ls10 nvswitch_corelib_set_rx_detect_lr10 842 #define nvswitch_corelib_write_discovery_token_ls10 nvswitch_corelib_write_discovery_token_lr10 843 #define nvswitch_corelib_read_discovery_token_ls10 nvswitch_corelib_read_discovery_token_lr10 844 845 #define nvswitch_inforom_ecc_log_error_event_ls10 nvswitch_inforom_ecc_log_error_event_lr10 846 #define nvswitch_inforom_ecc_get_errors_ls10 nvswitch_inforom_ecc_get_errors_lr10 847 #define nvswitch_inforom_bbx_get_sxid_ls10 nvswitch_inforom_bbx_get_sxid_lr10 848 849 #define nvswitch_vbios_read_structure_ls10 nvswitch_vbios_read_structure_lr10 850 851 #define nvswitch_setup_system_registers_ls10 nvswitch_setup_system_registers_lr10 852 853 #define nvswitch_minion_get_initoptimize_status_ls10 nvswitch_minion_get_initoptimize_status_lr10 854 855 #define nvswitch_poll_sublink_state_ls10 nvswitch_poll_sublink_state_lr10 856 #define nvswitch_setup_link_loopback_mode_ls10 nvswitch_setup_link_loopback_mode_lr10 857 858 #define nvswitch_link_lane_reversed_ls10 nvswitch_link_lane_reversed_lr10 859 860 #define nvswitch_i2c_get_port_info_ls10 nvswitch_i2c_get_port_info_lr10 861 #define nvswitch_i2c_set_hw_speed_mode_ls10 nvswitch_i2c_set_hw_speed_mode_lr10 862 863 #define nvswitch_ctrl_get_err_info_ls10 nvswitch_ctrl_get_err_info_lr10 864 865 NvlStatus nvswitch_ctrl_get_err_info_lr10(nvswitch_device *device, NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS *ret); 866 867 NvBool nvswitch_is_link_valid_lr10(nvswitch_device *device, NvU32 link_id); 868 NvBool nvswitch_is_link_in_use_lr10(nvswitch_device *device, NvU32 link_id); 869 870 NvlStatus nvswitch_initialize_device_state_lr10(nvswitch_device *device); 871 NvlStatus nvswitch_deassert_link_reset_lr10(nvswitch_device *device, nvlink_link *link); 872 void nvswitch_determine_platform_lr10(nvswitch_device *device); 873 NvU32 nvswitch_get_swap_clk_default_lr10(nvswitch_device *device); 874 NvlStatus nvswitch_post_init_device_setup_lr10(nvswitch_device *device); 875 NvlStatus nvswitch_set_training_error_info_lr10(nvswitch_device *device, NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS *pLinkTrainingErrorInfoParams); 876 void nvswitch_init_scratch_lr10(nvswitch_device *device); 877 void nvswitch_hw_counter_shutdown_lr10(nvswitch_device *device); 878 NvU64 nvswitch_hw_counter_read_counter_lr10(nvswitch_device *device); 879 880 void nvswitch_ecc_writeback_task_lr10(nvswitch_device *device); 881 NvlStatus nvswitch_ctrl_get_routing_id_lr10(nvswitch_device *device, NVSWITCH_GET_ROUTING_ID_PARAMS *params); 882 NvlStatus nvswitch_ctrl_set_routing_id_valid_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_ID_VALID *p); 883 NvlStatus nvswitch_ctrl_set_routing_id_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_ID *p); 884 NvlStatus nvswitch_ctrl_set_routing_lan_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_LAN *p); 885 NvlStatus nvswitch_ctrl_get_routing_lan_lr10(nvswitch_device *device, NVSWITCH_GET_ROUTING_LAN_PARAMS *params); 886 NvlStatus nvswitch_ctrl_set_routing_lan_valid_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_LAN_VALID *p); 887 NvlStatus nvswitch_ctrl_set_ingress_request_table_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_REQUEST_TABLE *p); 888 NvlStatus nvswitch_ctrl_get_ingress_request_table_lr10(nvswitch_device *device, NVSWITCH_GET_INGRESS_REQUEST_TABLE_PARAMS *params); 889 NvlStatus nvswitch_ctrl_set_ingress_request_valid_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_REQUEST_VALID *p); 890 NvlStatus nvswitch_ctrl_get_ingress_response_table_lr10(nvswitch_device *device, NVSWITCH_GET_INGRESS_RESPONSE_TABLE_PARAMS *params); 891 NvlStatus nvswitch_ctrl_set_ingress_response_table_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_RESPONSE_TABLE *p); 892 893 NvlStatus nvswitch_ctrl_get_nvlink_status_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret); 894 NvlStatus nvswitch_ctrl_get_nvlink_status_ls10(nvswitch_device *device, NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret); 895 896 NvlStatus nvswitch_ctrl_get_info_lr10(nvswitch_device *device, NVSWITCH_GET_INFO *p); 897 898 NvlStatus nvswitch_ctrl_set_switch_port_config_lr10(nvswitch_device *device, NVSWITCH_SET_SWITCH_PORT_CONFIG *p); 899 NvlStatus nvswitch_ctrl_get_throughput_counters_lr10(nvswitch_device *device, NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *p); 900 void nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10(nvswitch_device *device, NvU32 linkId); 901 void nvswitch_store_seed_data_from_inforom_to_corelib_lr10(nvswitch_device *device); 902 NvlStatus nvswitch_read_oob_blacklist_state_lr10(nvswitch_device *device); 903 904 NvlStatus nvswitch_corelib_add_link_lr10(nvlink_link *link); 905 NvlStatus nvswitch_corelib_remove_link_lr10(nvlink_link *link); 906 NvlStatus nvswitch_corelib_get_dl_link_mode_lr10(nvlink_link *link, NvU64 *mode); 907 NvlStatus nvswitch_corelib_set_tl_link_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 908 NvlStatus nvswitch_corelib_get_tx_mode_lr10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); 909 NvlStatus nvswitch_corelib_set_rx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 910 NvlStatus nvswitch_corelib_get_rx_mode_lr10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); 911 NvlStatus nvswitch_corelib_set_rx_detect_lr10(nvlink_link *link, NvU32 flags); 912 NvlStatus nvswitch_corelib_write_discovery_token_lr10(nvlink_link *link, NvU64 token); 913 NvlStatus nvswitch_corelib_read_discovery_token_lr10(nvlink_link *link, NvU64 *token); 914 NvlStatus nvswitch_corelib_set_dl_link_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 915 NvlStatus nvswitch_corelib_set_tx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); 916 NvlStatus nvswitch_corelib_get_tl_link_mode_lr10(nvlink_link *link, NvU64 *mode); 917 void nvswitch_init_buffer_ready_lr10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); 918 919 NvlStatus nvswitch_inforom_ecc_log_error_event_lr10(nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, INFOROM_NVS_ECC_ERROR_EVENT *err_event); 920 NvlStatus nvswitch_inforom_ecc_get_errors_lr10(nvswitch_device *device, NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS *params); 921 NvlStatus nvswitch_inforom_bbx_get_sxid_lr10(nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *params); 922 923 void nvswitch_init_dlpl_interrupts_lr10(nvlink_link *link); 924 925 NvlStatus nvswitch_vbios_read_structure_lr10(nvswitch_device *device, void *structure, NvU32 offset, NvU32 *ppacked_size, const char *format); 926 927 NvlStatus nvswitch_setup_system_registers_lr10(nvswitch_device *device); 928 929 NvlStatus nvswitch_minion_get_initoptimize_status_lr10(nvswitch_device *device, NvU32 linkId); 930 931 NvlStatus nvswitch_poll_sublink_state_lr10(nvswitch_device *device, nvlink_link *link); 932 void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 linkNumber); 933 934 NvBool nvswitch_link_lane_reversed_lr10(nvswitch_device *device, NvU32 linkId); 935 void nvswitch_store_topology_information_lr10(nvswitch_device *device, nvlink_link *link); 936 937 NvlStatus nvswitch_request_tl_link_state_lr10(nvlink_link *link, NvU32 tlLinkState, NvBool bSync); 938 NvlStatus nvswitch_wait_for_tl_request_ready_lr10(nvlink_link *link); 939 940 NvlStatus nvswitch_parse_bios_image_lr10(nvswitch_device *device); 941 NvU32 nvswitch_i2c_get_port_info_lr10(nvswitch_device *device, NvU32 port); 942 void nvswitch_i2c_set_hw_speed_mode_lr10(nvswitch_device *device, NvU32 port, NvU32 speedMode); 943 NvlStatus nvswitch_ctrl_i2c_indexed_lr10(nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); 944 void nvswitch_corelib_clear_link_state_lr10(nvlink_link *link); 945 946 // 947 // Internal function declarations 948 // 949 950 NvlStatus nvswitch_corelib_set_dl_link_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); 951 NvlStatus nvswitch_corelib_set_tx_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); 952 void nvswitch_init_lpwr_regs_ls10(nvlink_link *link); 953 void nvswitch_program_l1_scratch_reg_ls10(nvswitch_device *device, NvU32 linkNumber); 954 955 NvlStatus nvswitch_minion_service_falcon_interrupts_ls10(nvswitch_device *device, NvU32 instance); 956 957 NvlStatus nvswitch_device_discovery_ls10(nvswitch_device *device, NvU32 discovery_offset); 958 void nvswitch_filter_discovery_ls10(nvswitch_device *device); 959 NvlStatus nvswitch_process_discovery_ls10(nvswitch_device *device); 960 void nvswitch_lib_enable_interrupts_ls10(nvswitch_device *device); 961 void nvswitch_lib_disable_interrupts_ls10(nvswitch_device *device); 962 NvlStatus nvswitch_lib_service_interrupts_ls10(nvswitch_device *device); 963 NvlStatus nvswitch_lib_check_interrupts_ls10(nvswitch_device *device); 964 void nvswitch_initialize_interrupt_tree_ls10(nvswitch_device *device); 965 void nvswitch_corelib_training_complete_ls10(nvlink_link *link); 966 NvlStatus nvswitch_init_nport_ls10(nvswitch_device *device); 967 NvlStatus nvswitch_corelib_get_rx_detect_ls10(nvlink_link *link); 968 void nvswitch_reset_persistent_link_hw_state_ls10(nvswitch_device *device, NvU32 linkNumber); 969 NvlStatus nvswitch_minion_get_rxdet_status_ls10(nvswitch_device *device, NvU32 linkId); 970 NvlStatus nvswitch_minion_restore_seed_data_ls10(nvswitch_device *device, NvU32 linkId, NvU32 *seedData); 971 NvlStatus nvswitch_minion_set_sim_mode_ls10(nvswitch_device *device, nvlink_link *link); 972 NvlStatus nvswitch_minion_set_smf_settings_ls10(nvswitch_device *device, nvlink_link *link); 973 NvlStatus nvswitch_minion_select_uphy_tables_ls10(nvswitch_device *device, nvlink_link *link); 974 NvlStatus nvswitch_set_training_mode_ls10(nvswitch_device *device); 975 NvlStatus nvswitch_corelib_get_tl_link_mode_ls10(nvlink_link *link, NvU64 *mode); 976 NvU32 nvswitch_get_sublink_width_ls10(nvswitch_device *device,NvU32 linkNumber); 977 NvlStatus nvswitch_parse_bios_image_ls10(nvswitch_device *device); 978 NvBool nvswitch_is_link_in_reset_ls10(nvswitch_device *device, nvlink_link *link); 979 void nvswitch_corelib_get_uphy_load_ls10(nvlink_link *link, NvBool *bUnlocked); 980 NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_ls10(nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *params); 981 void nvswitch_init_buffer_ready_ls10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); 982 void nvswitch_apply_recal_settings_ls10(nvswitch_device *device, nvlink_link *link); 983 NvlStatus nvswitch_corelib_get_dl_link_mode_ls10(nvlink_link *link, NvU64 *mode); 984 NvlStatus nvswitch_corelib_get_tx_mode_ls10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); 985 NvlStatus nvswitch_corelib_get_rx_mode_ls10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); 986 NvlStatus nvswitch_ctrl_get_sw_info_ls10(nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p); 987 NvlStatus nvswitch_launch_ALI_link_training_ls10(nvswitch_device *device, nvlink_link *link, NvBool bSync); 988 NvlStatus nvswitch_service_nvldl_fatal_link_ls10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link); 989 NvlStatus nvswitch_ctrl_inband_send_data_ls10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p); 990 NvlStatus nvswitch_ctrl_inband_read_data_ls10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p); 991 void nvswitch_send_inband_nack_ls10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId); 992 NvU32 nvswitch_get_max_persistent_message_count_ls10(nvswitch_device *device); 993 NvlStatus nvswitch_service_minion_link_ls10(nvswitch_device *device, NvU32 nvliptInstance); 994 void nvswitch_apply_recal_settings_ls10(nvswitch_device *device, nvlink_link *link); 995 void nvswitch_store_topology_information_ls10(nvswitch_device *device, nvlink_link *link); 996 NvlStatus nvswitch_ctrl_i2c_indexed_ls10(nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); 997 NvBool nvswitch_i2c_is_device_access_allowed_ls10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead); 998 NvlStatus nvswitch_minion_get_ali_debug_registers_ls10(nvswitch_device *device, nvlink_link *link, NVSWITCH_MINION_ALI_DEBUG_REGISTERS *params); 999 void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link); 1000 void nvswitch_setup_link_system_registers_ls10(nvswitch_device *device, nvlink_link *link); 1001 void nvswitch_load_link_disable_settings_ls10(nvswitch_device *device, nvlink_link *link); 1002 void nvswitch_link_disable_interrupts_ls10(nvswitch_device *device, NvU32 link); 1003 void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link); 1004 void nvswitch_set_dlpl_interrupts_ls10(nvlink_link *link); 1005 void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); 1006 NvlStatus nvswitch_ctrl_get_board_part_number_ls10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p); 1007 void nvswitch_create_deferred_link_state_check_task_ls10(nvswitch_device *device, NvU32 nvlipt_instance, NvU32 link); 1008 NvlStatus nvswitch_request_tl_link_state_ls10(nvlink_link *link, NvU32 tlLinkState, NvBool bSync); 1009 NvlStatus nvswitch_ctrl_get_link_l1_capability_ls10(nvswitch_device *device, NvU32 linkId, NvBool *isL1Capable); 1010 NvlStatus nvswitch_ctrl_get_link_l1_threshold_ls10(nvswitch_device *device, NvU32 linkNum, NvU32 *lpThreshold); 1011 NvlStatus nvswitch_ctrl_set_link_l1_threshold_ls10(nvlink_link *link, NvU32 lpEntryThreshold); 1012 NvlStatus nvswitch_get_board_id_ls10(nvswitch_device *device, NvU16 *boardId); 1013 1014 // 1015 // SU generated functions 1016 // 1017 1018 NvlStatus nvswitch_nvs_top_prod_ls10(nvswitch_device *device); 1019 NvlStatus nvswitch_apply_prod_nvlw_ls10(nvswitch_device *device); 1020 NvlStatus nvswitch_apply_prod_nxbar_ls10(nvswitch_device *device); 1021 1022 NvlStatus nvswitch_launch_ALI_ls10(nvswitch_device *device); 1023 1024 NvlStatus nvswitch_ctrl_set_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p); 1025 NvlStatus nvswitch_ctrl_get_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p); 1026 1027 void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); 1028 1029 NvBool nvswitch_is_inforom_supported_ls10(nvswitch_device *device); 1030 void nvswitch_set_error_rate_threshold_ls10(nvlink_link *link, NvBool bIsDefault); 1031 void nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink_link *link, NvBool bEnable); 1032 NvlStatus nvswitch_reset_and_train_link_ls10(nvswitch_device *device, nvlink_link *link); 1033 NvBool nvswitch_are_link_clocks_on_ls10(nvswitch_device *device, nvlink_link *link, NvU32 clocksMask); 1034 NvBool nvswitch_does_link_need_termination_enabled_ls10(nvswitch_device *device, nvlink_link *link); 1035 NvlStatus nvswitch_link_termination_setup_ls10(nvswitch_device *device, nvlink_link* link); 1036 void nvswitch_get_error_rate_threshold_ls10(nvlink_link *link); 1037 void nvswitch_fsp_update_cmdq_head_tail_ls10(nvswitch_device *device, NvU32 queueHead, NvU32 queueTail); 1038 void nvswitch_fsp_get_cmdq_head_tail_ls10(nvswitch_device *device, NvU32 *pQueueHead, NvU32 *pQueueTail); 1039 void nvswitch_fsp_update_msgq_head_tail_ls10(nvswitch_device *device, NvU32 msgqHead, NvU32 msgqTail); 1040 void nvswitch_fsp_get_msgq_head_tail_ls10(nvswitch_device *device, NvU32 *pMsgqHead, NvU32 *pMsgqTail); 1041 NvU32 nvswitch_fsp_get_channel_size_ls10(nvswitch_device *device); 1042 NvU8 nvswitch_fsp_nvdm_to_seid_ls10(nvswitch_device *device, NvU8 nvdmType); 1043 NvU32 nvswitch_fsp_create_mctp_header_ls10(nvswitch_device *device, NvU8 som, NvU8 eom, NvU8 seid, NvU8 seq); 1044 NvU32 nvswitch_fsp_create_nvdm_header_ls10(nvswitch_device *device, NvU32 nvdmType); 1045 NvlStatus nvswitch_fsp_get_packet_info_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size, NvU8 *pPacketState, NvU8 *pTag); 1046 NvlStatus nvswitch_fsp_validate_mctp_payload_header_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 1047 NvlStatus nvswitch_fsp_process_nvdm_msg_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 1048 NvlStatus nvswitch_fsp_process_cmd_response_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 1049 NvlStatus nvswitch_fsp_config_ememc_ls10(nvswitch_device *device, NvU32 offset, NvBool bAincw, NvBool bAincr); 1050 NvlStatus nvswitch_fsp_write_to_emem_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 1051 NvlStatus nvswitch_fsp_read_from_emem_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); 1052 NvlStatus nvswitch_fsp_error_code_to_nvlstatus_map_ls10(nvswitch_device *device, NvU32 errorCode); 1053 NvlStatus nvswitch_fsprpc_get_caps_ls10(nvswitch_device *device, NVSWITCH_FSPRPC_GET_CAPS_PARAMS *params); 1054 NvlStatus nvswitch_detect_tnvl_mode_ls10(nvswitch_device *device); 1055 NvBool nvswitch_is_tnvl_mode_enabled_ls10(nvswitch_device *device); 1056 NvBool nvswitch_is_tnvl_mode_locked_ls10(nvswitch_device *device); 1057 NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_ls10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS *params); 1058 NvlStatus nvswitch_tnvl_get_attestation_report_ls10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params); 1059 NvlStatus nvswitch_tnvl_send_fsp_lock_config_ls10(nvswitch_device *device); 1060 NvlStatus nvswitch_tnvl_get_status_ls10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params); 1061 1062 NvlStatus nvswitch_ctrl_get_soe_heartbeat_ls10(nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p); 1063 NvlStatus nvswitch_cci_enable_iobist_ls10(nvswitch_device *device, NvU32 linkNumber, NvBool bEnable); 1064 NvlStatus nvswitch_cci_initialization_sequence_ls10(nvswitch_device *device, NvU32 linkNumber); 1065 NvlStatus nvswitch_cci_deinitialization_sequence_ls10(nvswitch_device *device, NvU32 linkNumber); 1066 void nvswitch_update_link_state_led_ls10(nvswitch_device *device); 1067 void nvswitch_led_shutdown_ls10(nvswitch_device *device); 1068 1069 #endif //_LS10_H_ 1070 1071